Fine particle optical transport network overhead processing device and method based on FPGA

Abstract

The invention discloses an overhead processing device of a fine particle optical transport network based on an FPGA (Field Programmable Gate Array), which is characterized in that each bit width conversion module is used for performing bit width conversion on an input fgODUflex signal, each converted fgODUflex signal occupies the same data bus in a time division multiplexing form, and each converted fgODUflex signal occupies the same data bus based on the data bus. The processing of overhead bytes of each fgODUflex signal is realized in a time division multiplexing mode, so that the system resources of the FPGA are saved.

Description

Technical Field

[0001] This application relates to the technical field of fine-grained optical transport networks, and particularly to an overhead processing device and method for a fine-grained optical transport network based on FPGA. Background Art

[0002] The fine-grained optical transport network (fgOTN) is an evolution of the technologies of SDH (ITU-T G.707) and OTN (ITU-G.709). It perfectly inherits the characteristics of SDH and OTN (Optical Transport Network), such as high reliability and deterministic delay, and supports various VBR (Variable Bit Rate) and CBR (Constant Bit Rate) services, such as Ethernet, E1, and SDH. It can provide a secure hard isolation solution based on a rigid hard pipe for quality connections and can be widely applied to carrier government and enterprise dedicated lines, as well as private networks in industries such as power and transportation.

[0003] The fine-grained optical transport network adopts a fixed time slot allocation design with a bandwidth unit of 10 Mb / s to meet the requirements of high-reliability and deterministic delay transmission of small-granularity services with the least amount of resources. There are technical problems in related overhead processing methods, such as more resource usage, low efficiency, and insufficient processing bandwidth. If the bandwidth is to be increased, multiple copies of the circuit need to be replicated, resulting in a huge resource usage of the FPGA and a complex implementation solution. Summary of the Invention

[0004] The purpose of this application is to provide a data mapping device for a fine-grained optical transport network based on FPGA, which uses time-division multiplexing to perform overhead byte down-insertion processing on fgODUflex signals of multiple channels on a single data bus, saving the system resources of the FPGA.

[0005] In a first aspect, this application provides an overhead processing device for a fine-grained optical transport network based on FPGA, the device comprising: Multiple bit-width conversion modules, for each bit-width conversion module, converting a first fgODUflex signal with a first bit-width into a second fgODUflex signal with a second bit-width, and occupying the same data bus in a time-division multiplexing form for each of the second fgODUflex signals, wherein both the first fgODUflex signal and the second fgODUflex signal carry corresponding channel numbers; A framing module, which is used to perform the following processing for each clock cycle of the system clock: obtain the channel number, the second fgODUflex signal, and the frame header indication signal corresponding to the current clock cycle, and perform byte counting on the second fgODUflex signal in response to the frame header indication signal to obtain the column count value and the row count value corresponding to the channel number within the current clock cycle; A multiframe synchronization module, which is used to perform the following processing for each clock cycle of the system clock: obtain the channel number, the second fgODUflex signal, the column count value, and the row count value corresponding to the current clock cycle. When the column count value reaches the maximum column count value and the row count value reaches the maximum row count value, the multiframe count value corresponding to the channel number is incremented by one to obtain the multiframe count value corresponding to the channel number; An overhead processing module, which is used to perform the following processing for each clock cycle of the system clock: obtain the channel number, the second fgODUflex signal, the column count value, the row count value, and the multiframe count value corresponding to the current clock cycle, determine the position of the overhead byte based on the column count value, the row count value, and the multiframe count value, and insert the overhead byte at the position.

[0006] Optionally, the bit width conversion module is specifically used for: Input a 64-bit first fgODUflex signal within each clock cycle, and form a 256-bit second fgODUflex signal from four 64-bit first fgODUflex signals input in four consecutive clock cycles. Among them, when the 64-bit first fgODUflex signal input in the first clock cycle is input, it is determined whether there is an externally input frame header indication. If so, the frame header indication and the 256-bit second fgODUflex signal are output together.

[0007] Optionally, the framing module includes a row counter, a column counter, and a first storage unit. The first storage unit uses each channel number as a storage address, and the storage space corresponding to each storage address stores the column count value and the row count value corresponding to the channel number. Among them, For each channel number, determine the channel number, frame header indication, and second fgODUflex signal within the current clock cycle. The column counter counts the second fgODUflex signal, performs an increment operation on the basis of the stored column count value corresponding to the channel number to obtain a column count value, stores the obtained column count value in the storage space corresponding to the channel number in the first storage unit, and at the next clock cycle corresponding to the channel number, the column counter accumulatively counts on the previously stored column count value, and so on. In response to the column counter reaching 238, the row counter performs an increment operation on the basis of the stored row count value to obtain a row count value, stores the obtained row count value in the storage space corresponding to the channel number in the first storage unit, resets the column counter and starts counting from zero, and so on, until the row count value is 1 and the column count value reaches 238, then reset the column counter and the row counter. Among them, in the case of having a frame header indication, clear the column count value and row count value corresponding to the channel number in the first storage unit.

[0008] Optionally, the multi-frame synchronization module includes a second storage unit. For each channel number, if there is a frame header indication within the current clock cycle, obtain the corresponding channel number and the multi-frame count value of bits 207 to 200 in the second fgODUflex signal, store the obtained multi-frame count value in the storage space corresponding to the channel number in the second storage unit, and within the clock cycle when the column count value is 238 and the row count value is 1, increment the stored multi-frame count value by one as the updated multi-frame count value, and store the updated multi-frame count value in the storage space corresponding to the channel number in the second storage unit.

[0009] Optionally, the overhead processing module includes a BIP overhead processing unit and a third storage unit. Among them, for each channel number, if the column count value of the current clock cycle is the first value and the row count value is 0, or the column count value of the current clock cycle is the first value and the row count value is 1, the BIP overhead processing unit obtains the corresponding channel number and the 144-bit payload signal in the second fgODUflex signal; if the column count value of the current clock cycle is the second value and the row count value is 0, or the column count value of the current clock cycle is the second value and the row count value is 1, the BIP overhead processing unit obtains the corresponding channel number and the second fgODUflex signal; The BIP overhead processing unit performs BIP-8 calculation on the obtained 144-bit payload signals and the second fgODUflex signals to obtain the BIP overhead of the current frame, and stores the BIP overhead of the current frame in the storage space corresponding to the channel number in the third storage unit; If the column count value in the current clock cycle is 0 and the row count value is 1, the BIP overhead processing unit obtains the corresponding channel number and the second fgODUflex signal, and inserts the BIP overhead of the penultimate frame corresponding to the channel number into the corresponding bit position in the second fgODUflex signal. Among them, the third storage unit stores the BIP overhead of the penultimate frame, the BIP overhead of the previous frame, and the BIP overhead of the current frame corresponding to each channel number. The first value is one of the following: 0, 59, 119, 179, and the second value is any value in the range of 0 to 238 except the first value.

[0010] Optionally, the overhead processing module includes a BWR overhead processing unit and a fourth storage unit. For each channel number, When the column value in the current clock cycle is 0 and the row value is 0, the BWR overhead processing unit obtains the corresponding channel number and the first 3-bit data in the second fgODUflex signal at bit positions 143 to 141, and stores the first 3-bit data in the storage space corresponding to the channel number in the third storage unit 144. When the column value in the current clock cycle is 119 and the row value is 0, the BWR overhead processing unit obtains the corresponding channel number and the second 3-bit data in the second fgODUflex signal at bit positions 15 to 13, and stores the second 3-bit data in the storage space corresponding to the channel number in the third storage unit 144. When the column value in the current clock cycle is 0 and the row value is 1, the BWR overhead processing unit obtains the corresponding channel number and the CRC-3 data in the second fgODUflex signal at bit positions 143 to 141, performs CRC-3 calculation on the stored first 3-bit data and the second 3-bit data, checks the calculation result against the obtained CRC-3 data, and outputs a bandwidth adjustment indication if they are consistent.

[0011] Optionally, the overhead processing module includes a feedback overhead processing unit and a fifth storage unit. For each channel number, When the column value in the current clock cycle is 0 and the row count value is 0, the feedback overhead processing unit obtains the channel number corresponding to the current clock cycle, outputs an indication signal to the receiving side, and receives the feedback overhead output from the receiving side. The fifth storage unit stores the feedback overhead in the storage space corresponding to the channel number. The feedback overhead includes PM BDI overhead, TCM2 BDI overhead, TCM1 BDI overhead, PM BEI overhead, TCM2 BEI / BIAE overhead, and TCM1 BEI / BIAE overhead. When the column count value in the current clock cycle is 0 and the row count value is 0, or when the column count value in the current clock cycle is 0 and the row count value is 1, the feedback overhead processing unit obtains the corresponding channel number and the second fgODUflex signal, and inserts the PM BDI overhead, TCM2 BDI overhead, and TCM1 BDI overhead corresponding to the channel number into bit positions 163, 159, and 155 of the second fgODUflex signal respectively; When the column count value in the current clock cycle is 119 and the row count value is 0, or when the column count value in the current clock cycle is 119 and the row count value is 1, the feedback overhead processing unit obtains the corresponding channel number and the second fgODUflex signal, and inserts the PM BDI overhead, TCM2 BDI overhead, and TCM1 BDI overhead corresponding to the channel number into bit positions 35, 31, and 27 of the second fgODUflex signal respectively; When the column count value in the current clock cycle is 0 and the row count value is 1, the feedback overhead processing unit obtains the corresponding channel number and the second fgODUflex signal, and inserts the PM BEI overhead, TCM2 BEI / BIAE overhead, and TCM1 BEI / BIAE overhead corresponding to the channel number into bit positions 167 - 164, 215 - 212, and 191 - 188 of the second fgODUflex signal respectively.

[0012] Optionally, the cancellation processing module includes a TTI overhead processing unit and a sixth storage unit. The sixth storage unit uses the channel number, the lowest two bits of the multiframe indication, and the position sequence number as the storage address. The storage space corresponding to each storage address is used to store the corresponding TTI overhead. The position sequence number is used to indicate the position sequence of the TTI overhead in the fgODUflex frame structure, and the position sequence number is 00, 01, 10, 11. The TTI overhead includes PM TTI overhead, TCM2 TTI overhead, and TCM1 TTI overhead. Among them, For each channel number, when the column count value in the current clock cycle is 59 and the row count value is 0, the TTI overhead processing unit obtains the corresponding channel number and the second fgODUflex signal, uses the channel number, the lowest two bits of the multiframe indication, and 00 as the storage address of the sixth storage unit, and inserts the obtained PM TTI overhead, TCM2 TTI overhead, and TCM1 TTI overhead into bit positions 95 - 80, 79 - 64, and 63 - 48 of the second fgODUflex signal respectively; When the column count value in the current clock cycle is 179 and the row count value is 0, the TTI overhead processing unit obtains the corresponding channel number and the second fgODUflex signal. Using the channel number, the lowest two bits of the multiframe indication, and 01 as the storage address of the sixth storage unit, the obtained PM TTI overhead, TCM2 TTI overhead, and TCM1 TTI overhead are inserted into bit positions 223 to 208, 207 to 192, and 191 to 176 of the second fgODUflex signal respectively; When the column count value in the current clock cycle is 59 and the row count value is 1, the TTI overhead processing unit obtains the corresponding channel number and the second fgODUflex signal. Using the channel number, the lowest two bits of the multiframe indication, and 10 as the storage address of the sixth storage unit, the obtained PM TTI overhead, TCM2 TTI overhead, and TCM1 TTI overhead are inserted into bit positions 95 to 80, 79 to 64, and 63 to 48 of the second fgODUflex signal respectively; When the column count value in the current clock cycle is 179 and the row count value is 1, the TTI overhead processing unit obtains the corresponding channel number and the second fgODUflex signal. Using the channel number, the lowest two bits of the multiframe indication, and 11 as the storage address of the sixth storage unit, the obtained PM TTI overhead, TCM2 TTI overhead, and TCM1 TTI overhead are inserted into bit positions 223 to 208, 207 to 192, and 191 to 176 of the second fgODUflex signal respectively.

[0013] Optionally, the overhead processing module includes a STAT overhead processing unit 1 and a seventh storage unit. The seventh storage unit uses the channel number as the storage address, and the storage space corresponding to each storage address is used to store the corresponding STAT overhead. The STAT overhead includes PM STAT overhead, TCM2 STAT overhead, and TCM1 STAT overhead. Among them, For each channel number, when the column count value in the current clock cycle is 0 and the row count value is 0, or when the column count value in the current clock cycle is 0 and the row count value is 1, the STAT overhead processing unit obtains the corresponding channel number and the second fgODUflex signal, and inserts the PM STAT overhead, TCM2 STAT overhead, and TCM1 STAT overhead corresponding to the channel number into bit positions 162 to 160, 158 to 156, and 154 to 152 of the second fgODUflex signal respectively; When the column count value in the current clock cycle is 119 and the row count value is 0, or when the column count value in the current clock cycle is 119 and the row count value is 1, the STAT overhead processing unit obtains the corresponding channel number and the second fgODUflex signal, and inserts the PM STAT overhead, TCM2 STAT overhead, and TCM1 STAT overhead corresponding to the channel number into bit positions 34-32, 30-28, and 26-24 of the second fgODUflex signal respectively.

[0014] Optionally, the overhead processing module includes an APS overhead processing unit and an eighth storage unit. The eighth storage unit uses the channel number as the storage address, and the storage space corresponding to each storage address is used to store the corresponding APS overhead. The APS overhead includes PM ASP overhead, TCM2 ASP overhead, and TCM1 ASP overhead. Among them, For each channel number, when the column count value in the current clock cycle is 119 and the row count value is 1, the APS overhead processing unit obtains the corresponding channel number and the second fgODUflex signal, and inserts the PM ASP overhead, TCM2 ASP overhead, and TCM1 ASP overhead corresponding to the channel number into bit positions 63-48, 95-80, and 79-64 of the second fgODUflex signal respectively.

[0015] In a second aspect, the present application provides an overhead processing method for a fine-grained optical transport network based on FPGA. The method includes: Converting a first fgODUflex signal with a first bit width into a second fgODUflex signal with a second bit width, and multiplexing each second fgODUflex signal in a time-division manner to occupy the same data bus. Among them, both the first fgODUflex signal and the second fgODUflex signal carry the corresponding channel number; For each clock cycle of the system clock, perform the following processing: Obtain the channel number, the second fgODUflex signal, and the frame header indication signal corresponding to the current clock cycle, and in response to the frame header indication signal, perform byte counting on the second fgODUflex signal to obtain the column count value and the row count value corresponding to the channel number in the current clock cycle; Obtain the channel number, the second fgODUflex signal, the column count value, and the row count value corresponding to the current clock cycle. When the column count value reaches the maximum column count value and the row count value reaches the maximum row count value, the multiplex frame count value corresponding to the channel number is incremented by one to obtain the multiplex frame count value corresponding to the channel number; Obtain the channel number corresponding to the current clock cycle, the second fgODUflex signal, the column count value, the row count value, and the multiframe count value. Determine the position of the overhead byte based on the column count value, the row count value, and the multiframe count value, and perform the insertion of the overhead byte at the position.

[0016] In this application, each bit-width conversion module performs bit-width conversion on the input fgODUflex signal, and the converted fgODUflex signals occupy the same data bus in a time-division multiplexing manner. Based on this data bus, the processing of the overhead bytes of each fgODUflex signal is realized through time-division multiplexing, which can realize the overhead processing of high-bandwidth fgoduflex data. This solution can be flexibly configured, can save the system resources of the FPGA, can support service flows with any number of entries, and users can make any configuration according to actual needs. Brief Description of the Drawings

[0017] Figure 1 It is the system block diagram of the overhead processing device of the fine-grained optical transport network based on FPGA provided by the embodiment of this application; Figure 2 It is the schematic diagram of the fgODUflex standard frame structure provided by the first embodiment of this application; Figure 3 It is the timing diagram of the bit-width conversion module provided by the embodiment of this application; Figure 4 It is the output data summary timing diagram of four bit-width conversion modules provided by the embodiment of this application; Figure 5 It is the schematic diagram of the framing module structure provided by the embodiment of this application; Figure 6 It is the timing diagram of the row and column counting of a single data stream provided by the embodiment of this application; Figure 7 It is the timing diagram of the row and column counting of multiple data streams provided by the embodiment of this application; Figure 8 It is the schematic diagram of the multiframe synchronization module structure provided by the embodiment of this application; Figure 9 It is the multiframe counting timing diagram provided by the embodiment of this application; Figure 10 It is the schematic diagram of the overhead processing module structure provided by the embodiment of this application; Figure 11 It is the timing diagram of the BIP overhead processing provided by the embodiment of this application; Figure 12 It is the flowchart of the overhead processing method of the fine-grained optical transport network based on FPGA provided by the embodiment of this application; Figure 13System block diagram of the communication device provided by the embodiment of the present application. Detailed implementation manners

[0018] The present application will be described in detail below in conjunction with the specific implementation manners shown in the accompanying drawings. However, these implementation manners do not limit the present application, and any structural, method, or functional transformation made by those of ordinary skill in the art based on these implementation manners is included within the protection scope of the present application.

[0019] As Figure 1As shown in the figure, the data mapping device based on FPGA for the fine-grained optical transport network provided by an embodiment of the present application includes a plurality of bit-width conversion modules 11, a framing module 12, a multiframe synchronization module 13, and an overhead processing module 14. For each bit-width conversion module 11, a first fgODUflex (Fine Grain Optical Data Unit Flex) signal with a first bit-width is converted into a second fgODUflex signal with a second bit-width, and each second fgODUflex signal occupies the same data bus in a time-division multiplexing manner, where both the first fgODUflex signal and the second fgODUflex signal carry corresponding channel numbers. The framing module 12 performs the following processing for each clock cycle of the system clock: obtains the channel number, the second fgODUflex signal, and the frame header indication signal corresponding to the current clock cycle, and performs byte counting on the second fgODUflex signal in response to the frame header indication signal to obtain the column count value and the row count value corresponding to the channel number within the current clock cycle. The multiframe synchronization module 13 performs the following processing for each clock cycle of the system clock: obtains the channel number, the second fgODUflex signal, the column count value, and the row count value corresponding to the current clock cycle. When the column count value reaches the maximum column count value and the row count value reaches the maximum row count value, the previous multiframe count value corresponding to the channel number is incremented by one to obtain the multiframe count value corresponding to the channel number. The overhead processing module 14 performs the following processing for each clock cycle of the system clock: obtains the channel number, the second fgODUflex signal, the column count value, the row count value, and the multiframe count value corresponding to the current clock cycle, determines the position of the overhead byte based on the column count value, the row count value, and the multiframe count value, and inserts the overhead byte at this position, where the overhead byte includes BIP (Bit Interleaved Parity) overhead, BWR (Bandwidth Size Adjustment) overhead, backward defect indication (BDI) overhead, backward error indication (BEI) overhead, backward input alignment error (BIAE) overhead, TTI (Trail Trace Identifier) overhead, STAT (channel status overhead), and APS (Automatic Protection Switching) overhead.

[0020] In this embodiment, each bit-width conversion module 11 performs bit-width conversion on the input fgODUflex signal, and the converted fgODUflex signals occupy the same data bus in a time-division multiplexing manner. Based on this data bus, the processing of the overhead bytes of each fgODUflex signal is realized through time-division multiplexing, which can realize the overhead processing of large-bandwidth fgoduflex data. This solution can be flexibly configured, can save the system resources of the FPGA, can support service flows with any number of entries, and users can make arbitrary configurations according to actual needs.

[0021] As Figure 2 shown in the fgODUflex standard frame structure, bytes 1-16 are the overhead byte area, bytes 17-1904 are the payload area, bytes 1905-1920 are the overhead byte area, and bytes 1921-3824 are the payload area. Therefore, based on the byte positions of each overhead byte, the function of inserting the overhead byte is realized. The frame alignment signal of fgODUflex includes 8 bytes of FAS, which are sequentially marked as FAS0~FAS0, and are respectively located in the 1st to 4th byte columns of the 1st to 4th rows and the 1905th to 1908th columns.

[0022] In an embodiment of the present application, the first bit-width is set to 64 bits, and the second bit-width is set to 256 bits. For each bit-width conversion module 11, a 64-bit first fgODUflex signal is input in each clock cycle, and a 256-bit second fgODUflex signal composed of 64-bit first fgODUflex signals input in four consecutive clock cycles is output. Among them, when the 64-bit first fgODUflex signal is input in the first clock cycle, it is determined whether there is an externally input frame header indication. If so, the frame header indication and the 256-bit second fgODUflex signal are output together.

[0023] Exemplarily, the first fgODUflex signal can be understood that the payload area part in the frame structure has been filled with data, and the overhead area part is 0, and the overhead bytes are filled based on the solution of the present application.

[0024] The protocol stipulates that the frame length of the fgODUflex signal is 4*3824 bytes, which can be just divided into 478 256-bit data blocks. Therefore, the bit-width conversion module 11 performs preliminary processing on the input first fgODUflex signal, expands the input data stream, and expands the 64-bit data stream to a 256-bit data stream.

[0025] Exemplarily, as Figure 3Timing diagram of the bit-width conversion module 11 shown. The input data of the bit-width conversion module 11 is a 64-bit first fgODUflex signal. The first 64-bit first fgODUflex signal input first is the high 64 bits of the 256-bit second fgODUflex signal. As shown in the figure, the first 64-bit first fgODUflex signal input in the first clock cycle is a, corresponding to bits [255:192] of the 256-bit second fgODUflex signal, and the second fgODUflex signal in this clock cycle is 000a; the second 64-bit first fgODUflex signal input in the second clock cycle is b, corresponding to bits [191:128] of the 256-bit second fgODUflex signal, and the second fgODUflex signal in this clock cycle is 00ab; the third 64-bit first fgODUflex signal input in the third clock cycle is c, corresponding to bits [127:64] of the 256-bit second fgODUflex signal, and the second fgODUflex signal in this clock cycle is 0abc; the fourth 64-bit first fgODUflex signal input in the fourth clock cycle is d, corresponding to bits [63:0] of the 256-bit second fgODUflex signal, and the second fgODUflex signal in this clock cycle is abcd. A 64-bit first fgODUflex signal is input in each clock cycle, and the first fgODUflex signals input in four consecutive clock cycles. The output data signal remains unchanged for four beats, stored as a 256-bit second fgODUflex signal, and the second fgODUflex signal is output once every four beats, and the clock data is updated and changed once every four beats.

[0026] Exemplarily, the input data of the bit-width conversion module 11 further includes the channel number corresponding to the first fgODUflex signal, such as Figure 3 the channel number shown. This channel number is 0, indicating that the channel number of the first fgODUflex signal input to the bit-width conversion module 11 is 0, and the bit-width conversion module 11 processes the fgODUflex signal with the channel number 0. It can be understood that the channel number of the first fgODUflex signal processed by the bit-width conversion module 11 can be different each time. The first fgODUflex signals input by the bit-width conversion module 11 in four clock cycles are generally of the same channel number. The channel numbers of the first fgODUflex signals processed by each bit-width conversion module 11 can be the same or different.

[0027] Exemplarily, when a 64-bit first fgODUflex signal is input in the first clock cycle, it is necessary to determine whether the 64-bit first fgODUflex signal is a frame header through an externally input frame header indication. If there is a frame header indication, the frame header indication is temporarily stored, and after all four clock-beat first fgODUflex signals are received, the frame header indication and the 256-bit second fgODUflex signal are output together. The frame header indication may generally be input together with the first 64-bit first fgODUflex signal input by the bit width conversion module 11, but not every first 64-bit first fgODUflex signal will be input together. Therefore, when outputting the 256-bit second fgODUflex signal, it is not necessarily output together with the frame header indication. Figure 3 As shown, the frame header indication is a high level indicating that the corresponding first fgODUflex signal is a frame header, which is subsequently output together with the first fgODUflex signal.

[0028] For example, four bit width conversion modules 11 can be supported, each bit width conversion module 11 supports 10G bandwidth, and a total of 40G bandwidth can be supported, and any number of service flows can be supported. Figure 4 The output data summary timing diagram of the four bit width conversion modules shown in the figure, the channel number 0 of the first bit width conversion module 11 corresponds to p0, and the output second fgODUflex signal 0 corresponds to a; the channel number 1 of the second bit width conversion module 11 corresponds to p1, and the output second fgODUflex signal 1 corresponds to b; the channel number 2 of the third bit width conversion module 11 corresponds to p2, and the output second fgODUflex signal 2 corresponds to c; the channel number 3 of the fourth bit width conversion module 11 corresponds to p3, and the output second fgODUflex signal 3 corresponds to d. The channel numbers of the four bit width conversion modules 11 occupy the same data bus in the form of time division multiplexing, as shown in FIG. Figure 4 The output channel numbers shown are p0, p1, p2, and p3, and the second fgODUflex signals of the four bit width conversion modules 11 occupy the same data bus in a time division multiplexing form, such as Figure 4 The output second fgODUflex signals shown are a, b, c, and d.

[0029] Exemplarily, the second fgODUflex signal output by each bit width conversion module 11 is valid for four beats, so the signals output by the four bit width conversion modules 11 occupy the same data bus, so it is only necessary to take the data output by one bit width conversion module 11 in turn every beat, such as Figure 4As shown, the data output by each bit-width conversion module 11 is selected through a clock tick counting signal. The clock tick counting signal counts up to four ticks in total. When the clock tick counting signal is 0 (i.e., the first clock tick), the second fgODUflex signal output by the first bit-width conversion module 11 is selected. Since the second fgODUflex signals output by the first bit-width conversion module 11 are all valid for four ticks, the second fgODUflex signal at the first clock tick is selected as above, and the second fgODUflex signals at the remaining 2nd - 4th clock ticks of the first bit-width conversion module 11 are used as invalid data. Similarly, when the clock tick counting signal is 1 (i.e., the second clock tick), the second fgODUflex signal output by the second bit-width conversion module 11 is selected. Since the second fgODUflex signals output by the second bit-width conversion module 11 are all valid for four ticks, the second fgODUflex signal at the second clock tick is selected as above, and the second fgODUflex signals at the first, third, and fourth clock ticks of the second bit-width conversion module 11 are used as invalid data. And so on, the second fgODUflex signals output by the four bit-width conversion modules 11 are integrated onto a single data bus to ensure that no data is discarded.

[0030] As Figure 2 shown in the fgODUflex standard frame structure, there are 4 rows and 3824 columns in each row. Based on the above description, it can be known that the bit-width conversion module 11 outputs 256-bit data. 4 * 3824 * 8 / 256 = 2 * 239. Therefore, for the convenience of processing, the data of 4 * 3824 columns is converted into a data block of 2 rows and 239 columns, and each column data block is 256 bits. The row and column counts are performed on the second fgODUflex signal output by the bit-width conversion module 11. Subsequently, based on the obtained row count value and column count value, the byte position of the overhead byte can be determined, thereby realizing the function of inserting the overhead byte.

[0031] An embodiment of the present application, as Figure 5As shown in the figure, the framing module 12 includes a row counter 121, a column counter 122, and a first storage unit 123. The first storage unit 123 uses each channel number as a storage address, and the storage space corresponding to each storage address stores the column count value and the row count value corresponding to the channel number. The column counter 121 and the row counter 122 use the time-division multiplexing method to perform column counting and row counting on the second fgODUflex signal of each channel number. The time-division multiplexing method includes: for each channel number, determining the channel number, frame header indication, and second fgODUflex signal within the current clock cycle. The column counter 121 performs counting on the second fgODUflex signal, performs an increment operation on the basis of the stored column count value to obtain the column count value, stores the obtained column count value in the storage space corresponding to the channel number in the first storage unit 123, and at the next clock cycle corresponding to the channel number, the column counter 121 accumulates and counts on the previously stored column count value, and so on. In response to the column counter 121 reaching 238, the row counter 122 performs an increment operation on the basis of the stored row count value to obtain the row count value, stores the obtained row count value in the storage space corresponding to the channel number in the first storage unit 123, resets the column counter 121 and starts counting from zero, and so on, until the row count value is 1 and the column count value reaches 238, then resets the column counter 121 and the row counter 122. Among them, in the case of a frame header indication, the column count value and the row count value corresponding to the channel number in the first storage unit 123 are cleared.

[0032] In this embodiment, if a frame header indication is received, it indicates that the second fgODUflex signal is frame header data, and the row count value and the column count value stored last time in the first storage unit 123 are cleared, and the signal is counted again; if no frame header indication is received, counting is performed on the basis of the row count value and the column count value stored last time in the first storage unit 123. This can avoid the data being in an incorrect state after an exception occurs. For example, in the case of an exception such as losing a data block or incorrect frame header indication, there may be a situation where the row and column count values in the first storage unit 123 are inconsistent with the count values of the actual data stream. Therefore, through the above error correction mechanism of clearing with frame header indication, the stored row and column count values can be matched with the actual data stream, and the signal is continuously being sent. Even if an error occurs in the initial stage, it can be immediately rematched.

[0033] Exemplarily, such as Figure 6The timing diagram of row and column counting shown below represents the timing schematic diagram of row and column counting for a single data stream. As can be seen from the figure, the channel number corresponding to the current clock cycle is 0, and the second fgODUflex signal of channel number 0 is counted. The frame header indication is at a high level, indicating that the second fgODUflex signal is frame header data. The column counter 121 and the row counter 122 restart counting, and count the second fgODUflex signal (a). The column counter 121 starts counting to obtain a column count value of 0 (the count value in this embodiment is 0 to 238), and the row counter 122 has a row count value of 0. The column count value 0 and the row count value 0 are stored in the storage space corresponding to the storage address of channel number 0 in the first storage unit 123, that is, the storage address is 0, the written column count value is 0, and the written row count value is 0. In the next clock cycle corresponding to channel number 0, the second fgODUflex signal (b) is counted. The column counter 121 adds 1 to the previously stored column count value of 0 to obtain a column count value of 1, and the row count value is 0. Similarly, the column count value 1 and the row count value 0 are written into the storage space corresponding to the storage address 0, and so on. When the column count value of the column counter 121 reaches 238, the row counter 122 adds 1 to the row count value of 0 to obtain a row count value of 1, the column counter 121 is cleared, and the column counter 121 starts counting from 0. At the same time, the row count value and the column count value are updated in the storage address 0. Until the row count value is 1 and the column count value reaches 238, the counting of a complete fgODUflex frame structure is completed, and the column counter 121 and the row counter 122 are reset, and the above-described implementation manner is repeated.

[0034] Exemplarily, as Figure 7 The timing diagram of row and column counting shown below represents the timing schematic diagram of row and column counting for multiple data streams. As can be seen from the figure, in the first clock cycle, the second fgODUflex signal (a) of channel number 0 is subjected to row counting and column counting, and the obtained row count value 0 and column count value 0 are stored in the storage space with the storage address 0 in the first storage unit 123. In the second clock cycle, the second fgODUflex signal (b) of channel number 1 is subjected to row counting and column counting, and the obtained row count value 0 and column count value 0 are stored in the storage space with the storage address 1 in the first storage unit 123, and so on. In each clock cycle, the second fgODUflex signal of the corresponding channel number is subjected to row and column counting, thereby implementing the time-division multiplexing technical solution without replicating the counting circuit for each channel number, saving the system resources of the FPGA.

[0035] As can be seen from the fgODUflex standard frame structure, the 1-byte multiplex frame indication MFAS is located in the 7th column of the 1st row. MFAS increments based on the fgODUflex frame, with a value range of 0 to 255, and is used to indicate 256-frame multiplex frames. MFAS is located in the 7th byte of the frame header position. Based on the description of the bit width conversion module 11 in the above embodiment, the 1st to 8th bytes of the fgODUflex signal are sent first. Therefore, the bit positions of MFAS in the second fgODUflex signal of 256 bits are 207 to 200. When the frame header indication appears, obtain the MFAS value of bits 207 to 200 in the second fgODUflex signal, write the obtained MFAS value into the memory, and perform multiplex frame counting based on this MFAS value to ensure self-correction when an abnormal situation causes an incorrect multiplex frame count. Since the processing of each overhead byte is related to the multiplex frame comparison, the multiplex frame count value obtained by each count is updated and stored for subsequent processing of the overhead bytes.

[0036] An embodiment of the present application, as Figure 8 shown, the multiplex frame synchronization module 13 includes a second storage unit 132. The second storage unit 132 uses each channel number as the storage address. For each channel number, if there is a frame header indication in the current clock cycle, obtain the corresponding channel number and the multiplex frame count value of bits 207 to 200 in the second fgODUflex signal, store the obtained multiplex frame count value in the storage space corresponding to this channel number in the second storage unit 132, and in the clock cycle when the column count value is 238 and the row count value is 1, add one to the stored multiplex frame count value as the updated multiplex frame count value, and store the updated multiplex frame count value in the storage space corresponding to this channel number in the second storage unit 132.

[0037] Exemplarily, as Figure 9 shown in the multiplex frame counting timing diagram, the channel number corresponding to the current clock cycle is 0. Obtain the multiplex frame count value of bits 207 to 200 in the second fgODUflex signal as ax, write ax to the storage address 0 corresponding to the channel number 0. When the column count value is 238 and the row count value is 1, add one to the obtained multiplex frame count value ax as the updated multiplex frame count value ax + 1, and write ax + 1 to the storage address 0 corresponding to the channel number 0.

[0038] As can be seen from the fgODUflex standard frame structure, the fgODUflex overhead information is used for maintenance and operation functions to support fgODUflex connections. The fgODUflex overhead includes path monitoring PM, tandem connection monitoring TCM1 and TCM2. The fgODUflex path monitoring overhead is generated and terminated at the source and sink ends of the fgODUflex channel respectively. The fgODUflex tandem connection monitoring overhead is generated and terminated at the source and sink ends of the corresponding tandem connection respectively. The PM, TCM1, and TCM2 overhead fields include the following: path trace identifier (TTI), bit parity check (BIP-8), backward defect indication (BDI), backward error indication (BEI), backward input alignment error (BIAE), status indication (STAT) for maintaining the signal, delay measurement (DM), and automatic protection switching (APS). Bit-interleaved parity (BIP) is defined in the fgODUflex overhead. For PM (path monitoring), BIP is located in the 11th byte column of the 3rd row; for TCM1 (tandem connection monitoring), BIP is located in the 8th byte column of the 3rd row; for TCM2 (tandem connection monitoring), BIP is located in the 5th byte column of the 3rd row.

[0039] The protocol stipulates that the BIP calculation is based on the 15th - 1904th byte column and the 1919th - 3824th byte column of the fgoduflex area of each frame. The BIP calculation result is generated in the (i - 2)th frame and inserted into the BIP overhead position in the i-th frame of fgODUflex. Therefore, it is necessary to store the BIP of the (i - 2)th frame, the BIP of the (i - 1)th frame, and the BIP of the i-th frame. When inserting the BIP overhead of the current frame (i.e., the i-th frame), the stored BIP of the (i - 2)th frame is inserted into the corresponding overhead byte position.

[0040] As can be seen from the above embodiments, the received second fgODUflex signal is a 256-bit signal. The situation of this 256-bit signal may be all payload, or may be overhead and payload. Therefore, when calculating BIP, for the second fgODUflex signal that is all payload, the complete second fgODUflex signal is calculated. For the second fgODUflex signal that contains overhead, 128 bits of the payload need to be calculated. Based on the positions of each overhead byte in the fgODUflex standard frame structure and the bit position distribution of 256 bits, the column count values corresponding to each overhead byte can be determined, and then the calculation of BIP can be realized. That is, when the column count value is 0, 59, 119, 179, the corresponding second fgODUflex signal contains the overhead area, and for the remaining column count values, the corresponding second fgODUflex signal is all payload data.

[0041] An embodiment of the present application, such as Figure 10As shown in the figure, the overhead processing module 14 includes a BIP overhead processing unit 141 and a third storage unit 142. For each channel number, if the column count value in the current clock cycle is the first value and the row count value is 0, or the column count value is the first value and the row count value is 1, obtain the channel number corresponding to this clock cycle and the 144-bit payload signal in the second fgODUflex signal. If the column count value in the current clock cycle is the second value and the row count value is 0, or the column count value is the second value and the row count value is 1, obtain the channel number corresponding to this clock cycle and the second fgODUflex signal. Perform BIP-8 calculation on the obtained 144-bit payload signals and the second fgODUflex signals respectively to obtain the BIP overhead of the current frame, and store the BIP overhead of the current frame in the storage space corresponding to this channel number in the third storage unit 142. If the column count value in the current clock cycle is 0 and the row count value is 1, obtain the channel number corresponding to this clock cycle and the second fgODUflex signal, and insert the BIP overhead of the previous previous frame corresponding to this channel number into the corresponding bit position in the second fgODUflex signal. Among them, the third storage unit 142 stores the BIP overhead of the previous previous frame, the BIP overhead of the previous frame, and the BIP overhead of the current frame corresponding to each channel number. The first value is one of the following: 0, 59, 119, 179. The second value is any value in the range of 0 to 238 except the first value. The position of the BIP overhead byte is determined based on the column count value. If the first value is 0 or 179, obtain the lower 144-bit signal in the second fgODUflex signal as the 144-bit payload signal. If the first value is 59 or 119, obtain the higher 128-bit signal and the lower 16 bits in the second fgODUflex signal as the 144-bit payload signal. It should be noted that as can be seen from the above, the calculation of BIP is based on the columns of bytes 15 - 1904 and bytes 1919 - 3824 in the fgoduflex area of each frame. From the structure of the fgoduflex frame, the 144-bit payload signal described in this embodiment refers to the 16-bit mapping signal including bytes 15 - 16 in the frame structure and the 128-bit (bytes 17 - 24) pure payload signal, or the 16-bit mapping signal including bytes 1919 - 1920 in the frame structure and the 128-bit (bytes 1921 - 1928) pure payload signal.

[0042] Exemplarily, as Figure 11The timing schematic diagram of BIP overhead processing shown. The channel number (rx_tpid) corresponding to the current clock cycle is 0. The calculated bip8 calculated value of the i-th frame is written into the storage space at storage address 0 of the third storage unit 142. The previous bip8 calculated values of the (i - 1)-th frame and the (i - 2)-th frame have been stored in the storage space at storage address 0 of the third storage unit 142. Storage address 0 stores the bip8 calculated value of the (i - 2)-th frame, the bip8 calculated value of the (i - 1)-th frame, and the bip8 calculated value of the i-th frame. When performing BIP overhead processing on the fgoduflex signal of the current frame (the i-th frame), the bip8 calculated value of the (i - 2)-th frame is inserted into the corresponding bit position in the second fgoduflex signal.

[0043] When packet services are mapped to the fgodu flex frame, there is BWR overhead in the mapping overhead area for bandwidth lossless adjustment. From the fgodu flex standard frame structure, it can be seen that the BWR overhead is located in columns 15 of rows 1 to 3, and consists of BWR_IND (1 bit), NCS (1 bit), and CRC-3 (3 bits), for a total of 9 bits. BWR_IND is the bandwidth lossless adjustment indication, and BWR_IND is located in the first bit of row 1 and the first bit of row 2. The 3-bit CRC is used as the error check code for bits 1 to 3 of rows 1 and 2 in the fgodu flex frame. When receiving the data of bits 1 to 3 of the first row and the data of bits 1 to 3 of the first row, these 6-bit data are stored, and CRC-3 calculation is performed on these 6-bit data. The result of the calculation is compared with the CRC-3 data received in the third row. If the verification is consistent, it indicates that the BWR_IND indication is valid, and BWR_IND is obtained for bandwidth lossless adjustment of the fgodu flex signal.

[0044] An embodiment of the present application, such as Figure 11As shown, the overhead processing module 14 includes a BWR overhead processing unit 143 and a fourth storage unit 144. The BWR processing unit 143 is configured to: for each channel number, if the column value in the current clock cycle is 0 and the row value is 0, obtain the corresponding channel number and the first 3-bit data in the second fgODUflex signal with bit positions 143 to 141, and store the first 3-bit data in the storage space corresponding to the channel number in the third storage unit 144; if the column value in the current clock cycle is 119 and the row value is 0, obtain the corresponding channel number and the second 3-bit data in the second fgODUflex signal with bit positions 15 to 13, and store the second 3-bit data in the storage space corresponding to the channel number in the third storage unit 144; if the column value in the current clock cycle is 0 and the row value is 1, obtain the corresponding channel number and the CRC-3 data in the second fgODUflex signal with bit positions 143 to 141, perform CRC-3 calculation on the stored first 3-bit data and the second 3-bit data, check the calculation result against the obtained CRC-3 data, and if they are consistent, output a bandwidth adjustment indication.

[0045] The BDI (Backward Defect Indication) overhead in the fgODUflex frame structure is used to transmit a signal fault status indication to the source end when a signal fault is detected at the path or tandem connection sink end. The BDI is set to "1" to indicate a backward defect indication for fgODUflex, otherwise it is set to "0". For PM, the BDI is located at the 5th bit in the 12th byte column of each row; for TCM1, the BDI overhead is located at the 5th bit in the 13th byte column of each row; for TCM2, the BDI overhead is located at the 1st bit in the 13th byte column of each row. For PM, 4-bit BEI (Backward Error Indication) overhead is defined in bits 1 - 4 in the 12th byte column of the 3rd row. For TCM1 and TCM2, 4-bit BEI / BIAE (Backward Error Indication and Backward Input Alignment Error) overhead is defined for each level of TCM, located in bits 1 - 4 in the 9th byte column of the 3rd row and bits 1 - 4 in the 6th byte column of the 3rd row respectively.

[0046] An embodiment of the present application, such as Figure 10As shown, the overhead processing module 14 includes a feedback overhead processing unit 145 and a fifth storage unit 146. For each channel number, when the column value in the current clock cycle is 0 and the row count value is 0, the feedback overhead processing unit 145 obtains the channel number corresponding to this clock cycle, outputs an indication signal to the receiving side, and receives the feedback overhead output from the receiving side. The fifth storage unit 146 stores the feedback overhead in the storage space corresponding to this channel number. The feedback overhead includes PM BDI overhead, TCM2 BDI overhead, TCM1 BDI overhead, PM BEI overhead, TCM2 BEI / BIAE overhead, and TCM1 BEI / BIAE overhead. When the column count value in the current clock cycle is 0 and the row count value is 0, obtain the channel number corresponding to this clock cycle and the second fgODUflex signal, and insert the PM BDI overhead, TCM2 BDI overhead, and TCM1 BDI overhead corresponding to this channel number into bit positions 163, 159, and 155 of the second fgODUflex signal respectively. When the column count value in the current clock cycle is 119 and the row count value is 0, obtain the channel number corresponding to this clock cycle and the second fgODUflex signal, and insert the PM BDI overhead, TCM2 BDI overhead, and TCM1 BDI overhead corresponding to this channel number into bit positions 35, 31, and 27 of the second fgODUflex signal respectively. When the column count value in the current clock cycle is 0 and the row count value is 1, obtain the channel number corresponding to this clock cycle and the second fgODUflex signal, and insert the PM BDI overhead, TCM2 BDI overhead, and TCM1 BDI overhead corresponding to this channel number into bit positions 163, 159, and 155 of the second fgODUflex signal respectively. When the column count value in the current clock cycle is 119 and the row count value is 1, obtain the channel number corresponding to this clock cycle and the second fgODUflex signal, and insert the PM BDI overhead, TCM2 BDI overhead, and TCM1 BDI overhead corresponding to this channel number into bit positions 35, 31, and 27 of the second fgODUflex signal respectively. When the column count value in the current clock cycle is 0 and the row count value is 1, obtain the channel number corresponding to this clock cycle and the second fgODUflex signal, and insert the PM BEI overhead, TCM2 BEI / BIAE overhead, and TCM1 BEI / BIAE overhead corresponding to this channel number into bit positions 167 - 164, 215 - 212, and 191 - 188 of the second fgODUflex signal respectively. The mapping processing of BDI overhead, BEI overhead, and BIAE overhead is related to the receiving side. When processing these overhead bytes, the sending side outputs an indication signal to notify the receiving side that mapping processing of these overhead bytes is required. The receiving side receives this indication signal and sends the relevant overhead bytes to the sending side so that the sending side can perform the processing of the overhead bytes.

[0047] The overhead in fgODUflex also includes configuration overhead, which is configured by an external interface, such as TTI (Path Trace Identifier) overhead, STAT (Status Indication of Maintenance Signal) overhead, APS (Automatic Protection Switching) overhead, etc. For TTI overhead, for PM, an 8-byte TTI field is defined in the 1909-1910 byte columns of the first to fourth rows; for TCM1, an 8-byte TTI field is defined in the 1913-1914 byte columns of the first to fourth rows; for TCM2, an 8-byte TTI field is defined in the 1911-1912 byte columns of the first to fourth rows. A complete 32-byte path trace identifier information transmission for PM, TCM1, or TCM2 is completed every four frames, indicated by MFAS[7,8].

[0048] An embodiment of the present application, such as Figure 10As shown in the figure, the overhead processing module 14 includes a TTI overhead processing unit 147 and a sixth storage unit 148. The sixth storage unit 148 is used to store the configured TTI overhead. The sixth storage unit 148 uses the channel number + the lowest two bits of the multiframe indication + the position sequence number as the storage address. The storage space corresponding to each storage address is used to store the corresponding TTI overhead. The position sequence number is used to indicate the position sequence of the TTI overhead in the fgODUflex frame structure, and the position sequence numbers are 00, 01, 10, and 11. For each channel number, when the column count value in the current clock cycle is 59 and the row count value is 0, the TTI overhead processing unit 147 obtains the corresponding channel number and the second fgODUflex signal, and uses the channel number + the lowest two bits of the multiframe indication + 00 as the storage address of the sixth storage unit 148, and inserts the obtained PM TTI overhead, TCM2 TTI overhead, and TCM1 TTI overhead into bit positions 95-80, 79-64, and 63-48 of the second fgODUflex signal respectively; when the column count value in the current clock cycle is 179 and the row count value is 0, the TTI overhead processing unit 147 obtains the corresponding channel number and the second fgODUflex signal, and uses the channel number + the lowest two bits of the multiframe indication + 01 as the storage address of the sixth storage unit 148, and inserts the obtained PM TTI overhead, TCM2 TTI overhead, and TCM1 TTI overhead into bit positions 223-208, 207-192, and 191-176 of the second fgODUflex signal respectively; when the column count value in the current clock cycle is 59 and the row count value is 1, the TTI overhead processing unit 147 obtains the corresponding channel number and the second fgODUflex signal, and uses the channel number + the lowest two bits of the multiframe indication + 10 as the storage address of the sixth storage unit 148, and inserts the obtained PM TTI overhead, TCM2 TTI overhead, and TCM1 TTI overhead into bit positions 95-80, 79-64, and 63-48 of the second fgODUflex signal respectively; when the column count value in the current clock cycle is 179 and the row count value is 1, the TTI overhead processing unit 147 obtains the corresponding channel number and the second fgODUflex signal, and uses the channel number + the lowest two bits of the multiframe indication + 11 as the storage address of the sixth storage unit 148, and inserts the obtained PM TTI overhead, TCM2 TTI overhead, and TCM1 TTI overhead into bit positions 223-208, 207-192, and 191-176 of the second fgODUflex signal respectively. The TTI overhead includes PM TTI overhead, TCM2 TTI overhead, and TCM1 TTI overhead. The insertion of the TTI overhead bytes is realized.

[0049] In the STAT (status indication for maintenance signals) overhead, for PM, a 3-bit status overhead (PM STAT) is defined, located at bits 6 - 8 in the 12th byte column of each row, for maintenance signal indication; for each TCM, a 3-bit status overhead (TCM1 STAT and TSM2 STAT) is also defined. TCM1 STAT is located at bits 6 - 8 in the 13th byte column of each row. TCM2STAT is located at bits 2 - 4 in the 13th byte column of each row.

[0050] An embodiment of the present application is as Figure 10 shown. The overhead processing module 14 includes a STAT overhead processing unit 149 and a seventh storage unit 14A. The seventh storage unit 14A is used to store the configured STAT overhead. The seventh storage unit 14A uses the channel number as the storage address, and the storage space corresponding to each storage address is used to store the corresponding STAT overhead. The STAT overhead includes PM STAT overhead, TCM2 STAT overhead, and TCM1 STAT overhead. For each channel number, if the column count value in the current clock cycle is 0 and the row count value is 0, the STAT overhead processing unit 149 obtains the channel number and the second fgODUflex signal corresponding to this clock cycle, and inserts the PM STAT overhead, TCM2 STAT overhead, and TCM1 STAT overhead corresponding to this channel number into bit positions 162 - 160, 158 - 156, and 154 - 152 of the second fgODUflex signal respectively; if the column count value in the current clock cycle is 119 and the row count value is 0, it obtains the channel number and the second fgODUflex signal corresponding to this clock cycle, and inserts the PM STAT overhead, TCM2 STAT overhead, and TCM1 STAT overhead corresponding to this channel number into bit positions 34 - 32, 30 - 28, and 26 - 24 of the second fgODUflex signal respectively; if the column count value in the current clock cycle is 0 and the row count value is 1, the STAT overhead processing unit 149 obtains the channel number and the second fgODUflex signal corresponding to this clock cycle, and inserts the PMSTAT overhead, TCM2 STAT overhead, and TCM1 STAT overhead corresponding to this channel number into bit positions 162 - 160, 158 - 156, and 154 - 152 of the second fgODUflex signal respectively; if the column count value in the current clock cycle is 119 and the row count value is 1, it obtains the channel number and the second fgODUflex signal corresponding to this clock cycle, and inserts the PM STAT overhead, TCM2 STAT overhead, and TCM1 STAT overhead corresponding to this channel number into bit positions 34 - 32, 30 - 28, and 26 - 24 of the second fgODUflex signal respectively, so as to achieve the insertion of STAT overhead.

[0051] In the fgODUflex frame structure, a 2-byte PM APS (Automatic Protection Switching) automatic protection switching overhead field is defined in the 9th - 10th byte column of the 4th row; a 2-byte TCM1 APS overhead field is defined in the 7th - 8th byte column of the 4th row; and a 2-byte TCM2 APS overhead field is defined in the 5th - 6th byte column of the 4th row.

[0052] An embodiment of the present application, as Figure 10 shown, the overhead processing module 14 includes an APS overhead processing unit 14B and an eighth storage unit 14C. The eighth storage unit 14C is used to store the configured APS overhead. The eighth storage unit 14C uses the channel number as the storage address, and the storage space corresponding to each storage address is used to store the corresponding APS overhead. The APS overhead includes PM ASP overhead, TCM2 ASP overhead, and TCM1 ASP overhead. For each channel number, if the column count value in the current clock cycle is 119 and the row count value is 1, the APS overhead processing unit 14B obtains the channel number and the second fgODUflex signal corresponding to this clock cycle, and inserts the PM ASP overhead, TCM2 ASP overhead, and TCM1 ASP overhead corresponding to this channel number into the bit positions 63 - 48, 95 - 80, and 79 - 64 of the second fgODUflex signal respectively, so as to achieve the insertion of APS overhead bytes.

[0053] Based on the same inventive concept, an embodiment of the present application also provides a method for processing overhead of a fine-grained optical transport network based on FPGA. The implementation solution provided by this method to solve the problem is similar to the implementation solution described in the above device. Therefore, the specific limitations in one or more embodiments of the method for processing overhead of a fine-grained optical transport network based on FPGA provided below can refer to the limitations on the device for processing overhead of a fine-grained optical transport network based on FPGA in the above text, and will not be elaborated here.

[0054] Please refer to Figure 12 , the present application provides a method for processing overhead of a fine-grained optical transport network based on FPGA, and this method includes: S1201, convert a first fgODUflex signal with a first bit width into a second fgODUflex signal with a second bit width, and multiplex each second fgODUflex signal in a time-division multiplexing manner to occupy the same data bus, where both the first fgODUflex signal and the second fgODUflex signal carry corresponding channel numbers; S1202. For each clock cycle of the system clock, perform the following processing: Obtain the channel number, the second fgODUflex signal, and the frame header indication signal corresponding to the current clock cycle, and perform byte counting on the second fgODUflex signal in response to the frame header indication signal to obtain the column count value and the row count value corresponding to the channel number within the current clock cycle; S1203. Obtain the channel number, the second fgODUflex signal, the column count value, and the row count value corresponding to the current clock cycle. When the column count value reaches the maximum column count and the row count value reaches the maximum row count, increment the multiframe count value corresponding to the channel number by one to obtain the multiframe count value corresponding to the channel number; S1204. Obtain the channel number, the second fgODUflex signal, the column count value, the row count value, and the multiframe count value corresponding to the current clock cycle. Determine the position of the overhead byte based on the column count value, the row count value, and the multiframe count value, and perform down-insertion of the overhead byte at the position.

[0055] As an example, please refer to Figure 13, which shows a schematic structural diagram of a communication device provided by an embodiment of the present application. The network device includes an overhead processing device 1301 of a fine-grained optical transport network based on FPGA, a communication interface 1302, a processor 1303, a memory 1304, and a bus 1305. The processor 1303, the memory 1304, the communication interface 1302, and the overhead processing device 1301 of the fine-grained optical transport network based on FPGA are communicatively connected to each other through the bus 1305. The memory 1304 can be used to store computer programs, and the computer programs can include instructions and data. In the embodiment of the present application, the memory 1304 can be various types of storage media, such as random access memory, static random access memory, non-volatile RAM, DDR, etc. The memory 1304 can include a hard disk and / or internal memory. The processor 1303 can be a general-purpose processor, and the general-purpose processor can be a processor that executes specific steps and / or operations by reading and executing the computer programs stored in a memory (such as the memory 1304), and the general-purpose processor is used to process the data output by the overhead processing device 1301 of the fine-grained optical transport network based on FPGA. The general-purpose processor can be, for example but not limited to, a central processing unit. In addition, the processor 1303 can also be a dedicated processor, and the dedicated processor can be a processor specifically designed to execute specific steps and / or operations. The dedicated processor can be, for example but not limited to, ASIC and FPGA, etc. In addition, the processor 1303 can also be a combination of multiple processors, such as a multi-core processor. The communication interface 1302 can include input / output interfaces, physical interfaces, and logical interfaces, etc., which are used to implement the interconnection of devices inside the network device, and interfaces for implementing the interconnection of the network device with other devices (such as network devices). The physical interface can be a gigabit Ethernet interface, which can be used to implement the interconnection of the network device with other devices, and the logical interface is an interface inside the network device, which can be used to implement the interconnection of devices inside the network device. The bus 1305 can be of any type and is used to implement the communication bus for interconnecting the processor 1303, the memory 1304, the communication interface 1302, and the overhead processing device 1301 of the fine-grained optical transport network based on FPGA, such as a system bus. The structure of the overhead processing device 1301 of the fine-grained optical transport network based on FPGA can refer to Figure 1 the illustrated embodiment shown, and will not be elaborated here. The interconnection of any one of the processor 1303, the memory 1304, and the communication interface 1302 with the overhead processing device 1301 of the fine-grained optical transport network based on FPGA can specifically refer to the interconnection of this any one device with the devices in the overhead processing device 1301 of the fine-grained optical transport network based on FPGA.

[0056] The embodiments disclosed in this application also provide a computer-readable storage medium. Instructions are stored in the computer-readable storage medium. When it runs on a computer, the computer is caused to execute the overhead processing method of the fine-grained optical transport network based on FPGA described in any one of the above embodiments.

[0057] Although the preferred embodiments of this application have been disclosed for illustrative purposes, those of ordinary skill in the art will recognize that various improvements, additions, and substitutions are possible without departing from the scope and spirit of the application disclosed by the appended claims.

Claims

1. An overhead processing device for a fine-grained optical transport network based on FPGA, characterized in that, The device includes: A plurality of bit-width conversion modules, for each bit-width conversion module, converting a first fgODUflex signal with a first bit-width into a second fgODUflex signal with a second bit-width, and multiplexing the respective second fgODUflex signals in a time-division multiplexing manner to occupy the same data bus, wherein both the first fgODUflex signal and the second fgODUflex signal carry corresponding channel numbers; A framing module, for each clock cycle of the system clock, performing the following processing: obtaining the channel number, the second fgODUflex signal, and the frame header indication signal corresponding to the current clock cycle, and in response to the frame header indication signal, performing byte counting on the second fgODUflex signal to obtain the column count value and the row count value corresponding to the channel number within the current clock cycle; A multi-frame synchronization module, for each clock cycle of the system clock, performing the following processing: obtaining the channel number, the second fgODUflex signal, the column count value, and the row count value corresponding to the current clock cycle, and when the column count value reaches the column count maximum value and the row count value reaches the row count maximum value, incrementing the multi-frame count value corresponding to the channel number by one to obtain the multi-frame count value corresponding to the channel number; An overhead processing module, for each clock cycle of the system clock, performing the following processing: obtaining the channel number, the second fgODUflex signal, the column count value, the row count value, and the multi-frame count value corresponding to the current clock cycle, determining the position of the overhead byte based on the column count value, the row count value, and the multi-frame count value, and inserting the overhead byte at the position; 2. The device according to claim 1, wherein The bit-width conversion module is specifically configured to: Input a 64-bit first fgODUflex signal within each clock cycle, and form a 256-bit second fgODUflex signal by combining four 64-bit first fgODUflex signals input in four consecutive clock cycles. When inputting the 64-bit first fgODUflex signal in the first clock cycle, determine whether there is an externally input frame header indication. If so, output the frame header indication and the 256-bit second fgODUflex signal together.

3. The device according to claim 2, characterized in that, The framing module includes a row counter, a column counter, and a first storage unit. The first storage unit uses each channel number as a storage address, and the storage space corresponding to each storage address stores the column count value and the row count value corresponding to each channel number, wherein, For each channel number, determine the channel number, frame header indication, and second fgODUflex signal within the current clock cycle. The column counter counts the second fgODUflex signal, performs an increment operation on the basis of the stored column count value corresponding to the channel number to obtain a column count value, stores the obtained column count value in the storage space corresponding to the channel number in the first storage unit, and in the next clock cycle corresponding to the channel number, the column counter accumulatively counts on the previously stored column count value, and so on. In response to the column counter reaching 238, the row counter performs an increment operation on the basis of the stored row count value to obtain a row count value, stores the obtained row count value in the storage space corresponding to the channel number in the first storage unit, resets the column counter and starts counting from zero, and so on, until the row count value is 1 and the column count value reaches 238, then reset the column counter and the row counter, wherein, in the case of having a frame header indication, clear the column count value and row count value corresponding to the channel number in the first storage unit.

4. The device according to claim 2, characterized in that The multiframe synchronization module includes a second storage unit. For each channel number, if there is a frame header indication within the current clock cycle, obtain the corresponding channel number and the multiframe count value of bits 207 to 200 in the second fgODUflex signal, store the obtained multiframe count value in the storage space corresponding to the channel number in the second storage unit, and in the clock cycle when the column count value is 238 and the row count value is 1, increment the stored multiframe count value by one as the updated multiframe count value, and store the updated multiframe count value in the storage space corresponding to the channel number in the second storage unit.

5. The device according to claim 2, characterized in that, The overhead processing module includes a BIP overhead processing unit and a third storage unit, wherein, for each channel number, if the column count value of the current clock cycle is the first value and the row count value is 0, or the column count value of the current clock cycle is the first value and the row count value is 1, the BIP overhead processing unit obtains the corresponding channel number and the 144-bit payload signal in the second fgODUflex signal; if the column count value of the current clock cycle is the second value and the row count value is 0, or the column count value of the current clock cycle is the second value and the row count value is 1, the BIP overhead processing unit obtains the corresponding channel number and the second fgODUflex signal; The BIP overhead processing unit performs BIP-8 calculation on the obtained 144-bit payload signals and the second fgODUflex signals respectively to obtain the BIP overhead of the current frame, and stores the BIP overhead of the current frame in the storage space corresponding to the channel number in the third storage unit; If the column count value in the current clock cycle is 0 and the row count value is 1, the BIP overhead processing unit obtains the corresponding channel number and the second fgODUflex signal, and inserts the BIP overhead of the penultimate frame corresponding to the channel number into the corresponding bit position in the second fgODUflex signal. Among them, the third storage unit stores the BIP overhead of the penultimate frame, the BIP overhead of the previous frame, and the BIP overhead of the current frame corresponding to each channel number. The first value is one of the following: 0, 59, 119, 179, and the second value is any value other than the first value in the range of 0 to 238.

6. The device according to claim 2, wherein The overhead processing module includes a BWR overhead processing unit and a fourth storage unit. For each channel number, When the column value in the current clock cycle is 0 and the row value is 0, the BWR overhead processing unit obtains the corresponding channel number and the first 3-bit data with bit positions 143 to 141 in the second fgODUflex signal, and stores the first 3-bit data in the storage space corresponding to the channel number in the third storage unit 144. When the column value in the current clock cycle is 119 and the row value is 0, the BWR overhead processing unit obtains the corresponding channel number and the second 3-bit data with bit positions 15 to 13 in the second fgODUflex signal, and stores the second 3-bit data in the storage space corresponding to the channel number in the third storage unit 144. When the column value in the current clock cycle is 0 and the row value is 1, the BWR overhead processing unit obtains the corresponding channel number and the CRC-3 data with bit positions 143 to 141 in the second fgODUflex signal, performs CRC-3 calculation on the stored first 3-bit data and the second 3-bit data, checks the calculation result with the obtained CRC-3 data. If they are consistent, a bandwidth adjustment indication is output.

7. The device according to claim 2, characterized in that, The overhead processing module includes a feedback overhead processing unit and a fifth storage unit. For each channel number, When the column value in the current clock cycle is 0 and the row count value is 0, the feedback overhead processing unit obtains the channel number corresponding to this clock cycle, outputs an indication signal to the receiving side, and receives the feedback overhead output from the receiving side. The fifth storage unit stores the feedback overhead in the storage space corresponding to the channel number. Among them, the feedback overhead includes PM BDI overhead, TCM2 BDI overhead, TCM1 BDI overhead, PM BEI overhead, TCM2 BEI / BIAE overhead, and TCM1 BEI / BIAE overhead. When the column count value in the current clock cycle is 0 and the row count value is 0, or when the column count value in the current clock cycle is 0 and the row count value is 1, the feedback overhead processing unit obtains the corresponding channel number and the second fgODUflex signal, and inserts the PM BDI overhead, TCM2 BDI overhead, and TCM1 BDI overhead corresponding to the channel number into bit positions 163, 159, and 155 of the second fgODUflex signal respectively. When the column count value in the current clock cycle is 119 and the row count value is 0, or when the column count value in the current clock cycle is 119 and the row count value is 1, the feedback overhead processing unit obtains the corresponding channel number and the second fgODUflex signal, and inserts the PM BDI overhead, TCM2 BDI overhead, and TCM1 BDI overhead corresponding to the channel number into bit positions 35, 31, and 27 of the second fgODUflex signal respectively; When the column count value in the current clock cycle is 0 and the row count value is 1, the feedback overhead processing unit obtains the corresponding channel number and the second fgODUflex signal, and inserts the PM BEI overhead, TCM2 BEI / BIAE overhead, and TCM1 BEI / BIAE overhead corresponding to the channel number into bit positions 167 - 164, 215 - 212, and 191 - 188 of the second fgODUflex signal respectively.

8. The device according to claim 2, characterized in that, The cancellation processing module includes a TTI overhead processing unit and a sixth storage unit. The sixth storage unit uses the channel number, the lowest two bits of the multiframe indication, and the position sequence number as the storage address. The storage space corresponding to each storage address is used to store the corresponding TTI overhead. The position sequence number is used to indicate the position sequence of the TTI overhead in the fgODUflex frame structure. The position sequence numbers are 00, 01, 10, and 11. The TTI overhead includes PM TTI overhead, TCM2 TTI overhead, and TCM1 TTI overhead. Among them, For each channel number, when the column count value in the current clock cycle is 59 and the row count value is 0, the TTI overhead processing unit obtains the corresponding channel number and the second fgODUflex signal, uses the channel number, the lowest two bits of the multiframe indication, and 00 as the storage address of the sixth storage unit, and inserts the obtained PM TTI overhead, TCM2 TTI overhead, and TCM1 TTI overhead into bit positions 95 - 80, 79 - 64, and 63 - 48 of the second fgODUflex signal respectively; When the column count value in the current clock cycle is 179 and the row count value is 0, the TTI overhead processing unit obtains the corresponding channel number and the second fgODUflex signal, uses the channel number, the lowest two bits of the multiframe indication, and 01 as the storage address of the sixth storage unit, and inserts the obtained PM TTI overhead, TCM2 TTI overhead, and TCM1 TTI overhead into bit positions 223 - 208, 207 - 192, and 191 - 176 of the second fgODUflex signal respectively. When the column count value in the current clock cycle is 59 and the row count value is 1, the TTI overhead processing unit obtains the corresponding channel number and the second fgODUflex signal, uses the channel number, the lowest two bits of the multiframe indication, and 10 as the storage address of the sixth storage unit, and inserts the obtained PM TTI overhead, TCM2 TTI overhead, and TCM1 TTI overhead into bit positions 95 - 80, 79 - 64, and 63 - 48 of the second fgODUflex signal respectively; When the column count value in the current clock cycle is 179 and the row count value is 1, the TTI overhead processing unit obtains the corresponding channel number and the second fgODUflex signal, uses the channel number, the lowest two bits of the multiframe indication, and 11 as the storage address of the sixth storage unit, and inserts the obtained PM TTI overhead, TCM2 TTI overhead, and TCM1 TTI overhead into bit positions 223 - 208, 207 - 192, and 191 - 176 of the second fgODUflex signal respectively.

9. The device according to claim 2, characterized in that, The overhead processing module includes a STAT overhead processing unit 1 and a seventh storage unit. The seventh storage unit uses the channel number as the storage address, and the storage space corresponding to each storage address is used to store the corresponding STAT overhead. The STAT overhead includes PM STAT overhead, TCM2 STAT overhead, and TCM1 STAT overhead. Among them, For each channel number, when the column count value in the current clock cycle is 0 and the row count value is 0, or when the column count value in the current clock cycle is 0 and the row count value is 1, the STAT overhead processing unit obtains the corresponding channel number and the second fgODUflex signal, and inserts the PM STAT overhead, TCM2 STAT overhead, and TCM1 STAT overhead corresponding to the channel number into bit positions 162 - 160, 158 - 156, and 154 - 152 of the second fgODUflex signal respectively; When the column count value in the current clock cycle is 119 and the row count value is 0, or when the column count value in the current clock cycle is 119 and the row count value is 1, the STAT overhead processing unit obtains the corresponding channel number and the second fgODUflex signal, and inserts the PM STAT overhead, TCM2 STAT overhead, and TCM1 STAT overhead corresponding to the channel number into bit positions 34 - 32, 30 - 28, and 26 - 24 of the second fgODUflex signal respectively.

10. The device according to claim 2, characterized in that, The overhead processing module includes an APS overhead processing unit and an eighth storage unit. The eighth storage unit uses the channel number as the storage address, and the storage space corresponding to each storage address is used to store the corresponding APS overhead. The APS overhead includes PM ASP overhead, TCM2 ASP overhead, and TCM1 ASP overhead. Among them, For each channel number, if the column count value in the current clock cycle is 119 and the row count value is 1, the APS overhead processing unit obtains the corresponding channel number and the second fgODUflex signal, and inserts the PM ASP overhead, TCM2ASP overhead, and TCM1 ASP overhead corresponding to the channel number into bit positions 63-48, 95-80, and 79-64 of the second fgODUflex signal, respectively.

11. An overhead processing method for a fine-grained optical transport network based on FPGA, characterized in that, The method includes: Converting a first fgODUflex signal with a first bit width into a second fgODUflex signal with a second bit width, and multiplexing each second fgODUflex signal in a time-division multiplexing manner to occupy the same data bus, where both the first fgODUflex signal and the second fgODUflex signal carry corresponding channel numbers; For each clock cycle of the system clock, perform the following processing: Obtain the channel number, the second fgODUflex signal, and the frame header indication signal corresponding to the current clock cycle, and in response to the frame header indication signal, perform byte counting on the second fgODUflex signal to obtain the column count value and the row count value corresponding to the channel number in the current clock cycle; Obtain the channel number, the second fgODUflex signal, the column count value, and the row count value corresponding to the current clock cycle. When the column count value reaches the column count maximum value and the row count value reaches the row count maximum value, the multiplex frame count value corresponding to the channel number is incremented by one to obtain the multiplex frame count value corresponding to the channel number; Obtain the channel number, the second fgODUflex signal, the column count value, the row count value, and the multiplex frame count value corresponding to the current clock cycle, determine the position of the overhead byte based on the column count value, the row count value, and the multiplex frame count value, and perform down-insertion of the overhead byte at the position.

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