Static random access memory and manufacturing method thereof
By using multiple patterning processes in the static random access memory to define the lower contact position and shape and design a misaligned upper contact structure, the problem of insufficient SRAM production process is solved, and the reliability and electrical connection quality of the miniaturization process are improved.
Patent Information
- Application Number
- CN202410075393.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-01-04
- Filing Date
- 2024-01-18
- Publication Date
- 2025-07-08
AI Technical Summary
The existing static random access memory (SRAM) has the problem of insufficient production process in the miniaturization process, resulting in product abnormalities.
Multi-patterning production process is used to define the position and shape of the lower contact, and design misalignment between the lower contact and the upper contact to form a stacked contact structure, improving layout elasticity and avoiding the defect of insufficient upper contact spacing after miniaturization of dimensions.
By improving the bottleneck of the miniaturization production process, the production process margin of static random access memory is improved, ensuring the quality and reliability of electrical connections.
Smart Images
Figure CN120282441A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a static random access memory (SRAM), and more particularly to a static random access memory having a contact structure with a double-layer structure. Background Art
[0002] A static random access memory (SRAM) belongs to a volatile memory. Under normal power supply, the storage cell can always retain the data it should store. When the power supply disappears, the storage cell will lose the data it stores. The static random access memory has the characteristics of fast access speed and can be compatible with the manufacturing process of logic elements. Therefore, it is commonly used as an embedded memory of a processor to provide a speed buffer between the processor and the main memory. With the evolution of the manufacturing process generation, the design of SRAM elements is becoming more and more dense, and a slight manufacturing process deviation may lead to product abnormalities. How to improve the manufacturing process margin of SRAM to maintain product quality is an important issue in the current field. Summary of the Invention
[0003] One of the objectives of the present invention is to provide a static random access memory and its manufacturing method, in which the contact structure of the active region is jointly constituted by a stacked lower contact and an upper contact. The present invention defines the position and shape of the lower contact through a multiple patterning manufacturing process, and designs a misalignment between the lower contact and the upper contact, which can improve the bottleneck of the miniaturization manufacturing process and increase the manufacturing process margin.
[0004] A static random access memory according to an embodiment of the present invention includes a substrate, including a first active region and a second active region that are parallel to each other. A first gate structure straddles the first active region and the second active region. A first lower contact and a second lower contact are respectively located on the first active region and the second active region on one side of the first gate structure. A third lower contact and a fourth lower contact are respectively located on the first active region and the second active region on the other side of the first gate structure. In a plan view, the first lower contact, the second lower contact, the third lower contact, and the fourth lower contact respectively include a first edge between the first active region and the second active region, and a second edge relative to the first edge. The first edges of the first lower contact and the third lower contact are aligned with each other, the first edges of the second lower contact and the fourth lower contact are aligned with each other, the second edges of the first lower contact and the third lower contact are not aligned, and the second edges of the second lower contact and the fourth lower contact are not aligned.
[0005] A manufacturing method of a static random access memory according to another embodiment includes the following steps. First, a substrate is provided, including a plurality of active regions parallel to each other. Then, a lower dielectric layer is formed on the substrate, and a plurality of gate structures located in the lower dielectric layer, spanning the plurality of active regions, and parallel to each other are formed. Next, a first mask layer is formed on the lower dielectric layer, which includes a plurality of notch patterns corresponding to the plurality of active regions respectively. Then, a second mask layer is formed on the first mask layer, which includes a plurality of strip patterns corresponding to the plurality of gate structures respectively. After that, using the first mask layer and the second mask layer as masks, the lower dielectric layer is etched to form a plurality of lower contact openings, respectively exposing parts of the plurality of active regions, and then a plurality of lower contacts are formed in the plurality of lower contact openings. BRIEF DESCRIPTION OF THE DRAWINGS
[0006] Figure 1 The circuit diagram of a storage unit (bit cell) of a static random access memory according to an embodiment of the present invention;
[0007] Figure 2 The plan view of a storage unit (bit cell) of a static random access memory according to an embodiment of the present invention;
[0008] Figure 3 is the cross-sectional view along Figure 2 the AA' tangent line shown;
[0009] Figure 4 is the cross-sectional view along Figure 2 the BB' tangent line shown;
[0010] Figures 5 to 14 Shown is the schematic diagram of the steps of the manufacturing method of a static random access memory according to an embodiment of the present invention, where Figure 5 , Figure 7 , Figure 8 , Figure 11 and Figure 13 are plan views, Figure 6 , Figure 9 , Figure 10 , Figure 12 and Figure 14 are cross-sectional views along the FF' tangent line in the plan view.
[0011] SYMBOL DESCRIPTION
[0012] 10: Active region
[0013] 11: First active region
[0014] 12: Second active region
[0015] 13: Third active region
[0016] 14: Fourth active region
[0017] 20: Gate structure
[0018] 21: First gate structure
[0019] 22: Second gate structure
[0020] 23: First access gate structure
[0021] 24: Fourth gate structure
[0022] 22a: Gate dielectric layer
[0023] 24a: Work function metal layer
[0024] 26a: Low-resistance metal layer
[0025] 28a: Cover layer
[0026] 30: Lower contact
[0027] 31: First lower contact
[0028] 32: Second lower contact
[0029] 33: Third lower contact
[0030] 34: Fourth lower contact
[0031] 35: Fifth lower contact
[0032] 36: Sixth lower contact
[0033] 37: Seventh lower contact
[0034] 40: Upper contact
[0035] 41: First upper contact
[0036] 42: Second upper contact
[0037] 43: Third upper contact
[0038] 44: Fourth upper contact
[0039] 45: Fifth upper contact
[0040] 104: Isolation structure
[0041] 112: Lower dielectric layer
[0042] 114: Buffer layer
[0043] 116: First mask layer
[0044] 118: Second mask layer
[0045] 122: Etch stop layer
[0046] 124: Upper dielectric layer
[0047] 10A: Substrate
[0048] 116a: Notch pattern
[0049] 118a: Strip pattern
[0050] 118b: Strip pattern
[0051] 30a: Barrier layer
[0052] 30b: Conductive material
[0053] 31a: First edge
[0054] 31b: Second edge
[0055] 32a: First edge
[0056] 32b: Second edge
[0057] 33a: First edge
[0058] 33b: Second edge
[0059] 34a: First edge
[0060] 34b: Second edge
[0061] 36a: Third edge
[0062] 36b: Fourth edge
[0063] 37a: Third edge
[0064] 37b: Fourth edge
[0065] 40a: Barrier layer
[0066] 40b: Conductive material
[0067] A1: Region
[0068] BL: Bit line
[0069] BLB: Bit line
[0070] AA': Tangent line
[0071] BB': Tangent line
[0072] CC': Tangent line
[0073] DD': Tangent line
[0074] EE': Tangent line
[0075] FF': Tangent
[0076] C1: Odd rows
[0077] C2: Even rows
[0078] GL: Interface layer
[0079] OP: Lower contact opening
[0080] PD1: First pull-down transistor
[0081] PD2: Second pull-down transistor
[0082] PG1: First access transistor
[0083] PG2: Second access transistor
[0084] PL1: First pull-up transistor
[0085] PL2: Second pull-up transistor
[0086] R1: Odd columns
[0087] R2: Even columns
[0088] SN1: Storage node
[0089] SN2: Storage node
[0090] SP: Sidewall structure
[0091] ST1: First step portion
[0092] ST2: Second step portion
[0093] ST3: Third step portion
[0094] ST4: Fourth step portion
[0095] ST5: Fifth step portion
[0096] ST6: Sixth step portion
[0097] Vcc: Power supply voltage
[0098] Vss: Ground voltage
[0099] W1: Width
[0100] W2: Width
[0101] W3: Width
[0102] W4: Width
[0103] WL: Word line
[0104] X: First direction
[0105] Y: Second direction
[0106] Z: Third direction Detailed implementation manners
[0107] To enable those of ordinary skill in the art to which the present invention pertains to further understand the present invention, the preferred embodiments of the present invention are specifically enumerated below, and in conjunction with the accompanying drawings, the composition and the desired effects of the present invention are described in detail.
[0108] For the convenience of description, the drawings of the present invention are only schematic for easier understanding of the present invention, and their detailed proportions can be adjusted according to the design requirements. Regarding the up-and-down relationship of the relative components in the figures described in the text, those skilled in the art should understand that it refers to the relative positions of the objects, so they can all be flipped to present the same components, and this should all fall within the scope disclosed in this specification. It should be noted that the following embodiments can, without departing from the spirit of the present invention, replace, recombine, and mix the features in several different embodiments to complete other embodiments.
[0109] Please refer to Figure 1, is the circuit diagram of a storage cell (bitcell) of a static random access memory (SRAM) according to an embodiment of the present invention. Each storage cell of the static random access memory of the present invention includes 6 transistors, and thus can also be referred to as a six-transistor static random access memory (6T-SRAM). Specifically, each storage cell includes a first pull-up transistor PL1, a second pull-up transistor PL2, a first pull-down transistor PD1, a second pull-down transistor PD2, a first access transistor PG1, and a second access transistor PG2. The conductivity types of the first pull-up transistor PL1 and the second pull-up transistor PL2 are opposite to those of the first pull-down transistor PD1 and the second pull-down transistor PD2. The source terminal of the first pull-up transistor PL1 is electrically connected to the supply voltage (Vcc), the drain terminal of the first pull-up transistor PL1 is electrically connected to the drain terminal of the first pull-down transistor PD1, the source terminal of the first pull-down transistor PD1 is electrically connected to the ground voltage (Vss), and the gate terminals of the first pull-up transistor PL1 and the first pull-down transistor PD1 are electrically connected to form an inverter. Similarly, the source terminal of the second pull-up transistor PL2 is electrically connected to the supply voltage (Vcc), the drain terminal of the second pull-up transistor PL2 is electrically connected to the drain terminal of the second pull-down transistor PD2, the source terminal of the second pull-down transistor PD2 is electrically connected to the ground voltage (Vss), and the gate terminals of the second pull-up transistor PL2 and the second pull-down transistor PD2 are electrically connected to form another inverter. By cross-coupling the above two inverters, for example, coupling the gate terminals of the first pull-up transistor PL1 and the first pull-down transistor PD1 to the drain terminals of the second pull-up transistor PL2 and the second pull-down transistor PD2, and coupling the gate terminals of the second pull-up transistor PL2 and the second pull-down transistor PD2 to the drain terminals of the first pull-up transistor PL1 and the first pull-down transistor PD1 to form a latch circuit, data can be latched in the storage nodes SN1 or SN2. The first access transistor PG1 and the second access transistor PG2 are used to control the writing and reading of data in the storage cell. Specifically, the first access transistor PG1 is connected between the storage node SN1 and the bit line BL, the second access transistor PG2 is connected between the storage node SN2 and the bit line BLB, and the gates of the first access transistor PG1 and the second access transistor PG2 are electrically connected to the word line WL, and the conduction (on) or cutoff (off) of the first access transistor PG1 and the second access transistor PG2 is controlled by the word line WL. When the first access transistor PG1 and the second access transistor PG2 are conducting (on), data can be written or read from the bit line BL and the bit line BLB.
[0110] Please refer to Figure 2 andFigure 13 。 Figure 13 A partial plan view of a static random access memory according to an embodiment of the present invention. Figure 2 is Figure 13 An enlarged view of the area A1 shown, showing a plan view of a memory cell (bitcell) that constitutes a static random access memory. The first direction X and the second direction Y shown in the figure are directions parallel to the surface of the substrate 10A of the static random access memory. The first direction X and the second direction Y are perpendicular to each other. The third direction Z is perpendicular to the surface of the substrate 10A. The AA' tangent and the BB' tangent are parallel to the second direction Y. The CC' tangent, the DD' tangent, the EE' tangent, and the FF' tangent are parallel to the first direction X.
[0111] The static random access memory is composed of Figure 2 The six-transistor memory cell (bit cell) arrangement shown, including a substrate 10A, a plurality of active regions 10 provided on the substrate 10A, extending along the first direction X and arranged parallel to each other along the second direction Y. A plurality of gate structures 20 are provided on the substrate 10A, extending along the second direction Y across the active regions 10 and arranged parallel to each other along the first direction X. A plurality of lower contacts 30 are arranged on the substrate 10A and cross the active regions 10. A plurality of upper contacts 40 are respectively provided on the lower contacts 30.
[0112] Locally, as Figure 2 shown, the static random access memory includes a first active region 11, a second active region 12, a third active region 13, and a fourth active region 14 arranged adjacent to each other, where the second active region 12 is provided between the first active region 11 and the third active region 13, and the third active region 13 is provided between the second active region 12 and the fourth active region 14. The first gate structure 21 and the second gate structure 22 are arranged adjacent to each other and staggered, where the first gate structure 21 extends across the first active region 11 and the second active region 12 to form a first pull-down transistor PD1 and a first pull-up transistor PL1, and the second gate structure 22 extends across the third active region 13 and the fourth active region 14 to form a second pull-down transistor PD2 and a second pull-up transistor PL2. According to an embodiment of the present invention, the first pull-up transistor PL1 and the second pull-up transistor PL2 are P-type metal oxide semiconductor (PMOS) transistors, and the first pull-down transistor PD1 and the second pull-down transistor PD2 are N-type metal oxide semiconductor (NMOS) transistors.
[0113] The first lower contact 31 is disposed on the first active region 11 on one side of the first gate structure 21, and the first upper contact 41 is disposed on the first lower contact 31. The two are used to electrically connect the source terminal of the first pull-down transistor PD1 to the ground voltage Vss. The second lower contact 32 is disposed on the second active region 12 on the same side as the first lower contact 31, and the second upper contact 42 is disposed on the second lower contact 32. The two are used to electrically connect the source terminal of the first pull-up transistor PL1 to the power supply voltage Vcc.
[0114] The third lower contact 33 and the fourth lower contact 34 are respectively disposed on the first active region 11 and the second active region 12 on the other side of the first gate structure 21. The third upper contact 43 is disposed on the third lower contact 33 and the fourth lower contact 43 and is electrically connected to the third lower contact 33 and the fourth lower contact 34 to achieve electrical connection between the drain terminal of the first pull-up transistor PL1 and the drain terminal of the first pull-down transistor PD1.
[0115] The fifth lower contact 35 and the sixth lower contact 36 are disposed on the side of the second gate structure 22 adjacent to the first gate structure 21, and are respectively disposed on the third active region 13 and the fourth active region 14. The fourth upper contact 44 is disposed on the fifth lower contact 35 and the sixth lower contact 36 and is electrically connected to the fifth lower contact 35 and the sixth lower contact 36 to achieve electrical connection between the drain terminal of the second pull-up transistor PL2 and the drain terminal of the second pull-down transistor PD2.
[0116] The end of the first gate structure 21 can extend to overlap and be electrically connected to the end of the third active region 13, and the end of the second gate structure 22 can extend to overlap and be electrically connected to the end of the second active region 12, thereby realizing cross-coupling between the inverter formed by the first pull-up transistor PL1 and the first pull-down transistor PD1 and the inverter formed by the second pull-up transistor PL2 and the second pull-down transistor PD2, so as to form a latch circuit.
[0117] The first access gate structure 23 is aligned with the second gate structure 22 along the second direction Y, spanning the first active region 11 to form a first access transistor PG1. The second access gate structure 24 is aligned with the first gate structure 21 along the second direction Y, spanning the fourth active region 14 to form a second access transistor PG2. According to an embodiment of the present invention, the first access transistor PG1 and the second access transistor PG2 are N-type metal oxide semiconductor (NMOS) transistors. As Figure 2 shown, the fourth active region 14 can be provided with a seventh lower contact 37 and a fifth upper contact 45 on the side of the second access transistor PG2 relative to the sixth lower contact 36 to electrically connect the second access transistor PG2 to the bit line BLB (refer to Figure 1)。Similarly, on one side of the first access transistor PG1 relative to the third lower contact 33, the first active region 11 may be provided with another contact structure (not shown in the figure) to electrically connect the first access transistor PG1 and the bit line BL.
[0118] In the present invention, the contact structure is designed to be composed of a lower contact and an upper contact, which can improve the layout flexibility. Moreover, by means of the misalignment design between the lower contact and the upper contact, defects (such as short-circuit leakage) caused by insufficient spacing of the upper contact after size reduction can be avoided, and the manufacturing process margin can be improved. In addition, the contact structure is fabricated by the multiple patterning manufacturing process described below, which helps to obtain the desired position and shape of the lower contact.
[0119] Figures 5 to 14 The figure shows a schematic diagram of the steps of a manufacturing method of a static random access memory according to an embodiment of the present invention, where Figure 5 、 Figure 7 、 Figure 8 、 Figure 11 and Figure 13 are plan views, Figure 6 、 Figure 9 、 Figure 10 、 Figure 12 and Figure 14 are cross-sectional views along the tangent FF' of the plan view. For the sake of simplicity, some elements may be omitted in the plan view and the cross-sectional view and not shown.
[0120] Please refer to Figure 5 and Figure 6, first, a substrate 10A is provided, which includes a plurality of active regions 10 parallel to each other, extending along a first direction X and arranged in parallel along a second direction Y, and separated from each other by isolation structures 104. The substrate 10A can be a silicon substrate, a silicon-on-insulator (SOI) substrate, or a III-V semiconductor substrate, but is not limited thereto. The active regions 10 can be fin structures formed by patterning the substrate 10A or selectively epitaxially grown on the substrate 10A, but are not limited thereto. The isolation structure 104 is, for example, a shallow trench isolation structure (STI), but is not limited thereto. Then, a lower dielectric layer 112 and gate structures 20 located in the lower dielectric layer 112 are formed on the substrate 10A, and then a buffer layer 114 is formed to comprehensively cover the lower dielectric layer 112 and the gate structures 20. The gate structures 20 extend along the second direction Y across the active regions 10 respectively and are arranged in parallel and staggered along the first direction X. The gate structures 20 can be metal gates, including a gate dielectric layer 22a from bottom to top, a work function metal layer 24a located on the gate dielectric layer 22a, a low-resistance metal layer 26a located on the work function metal layer 24a, and a capping layer 28a located on the low-resistance metal layer 26a, wherein the top surface of the capping layer 28a is substantially flush with the top surface of the lower dielectric layer 112. In some embodiments, an interface layer GL can be provided between the bottom of the gate structure 20 and the substrate 10A, and a sidewall structure SP can be provided between the sidewalls and the lower dielectric layer 112, wherein the top surface of the sidewall structure SP is substantially flush with the top surface of the lower dielectric layer 112. In some embodiments, an etch stop layer or a stress layer (not shown in the figure) can be included between the lower dielectric layer 112 and the substrate 10A. For the convenience of subsequent description, R1 and R2 marked in the plan view respectively represent the active regions 10 in odd-numbered columns and even-numbered columns, and C1 and C2 marked in the plan view respectively represent the gate structures 20 in odd-numbered rows and even-numbered rows.
[0121] Please refer to Figure 7 . Then, a first mask layer 116 is formed on the buffer layer 114, and then a patterning process is performed on the first mask layer 116 to define a plurality of notch patterns 116a extending along the first direction and corresponding to the active regions 10 respectively in the first mask layer 116. According to an embodiment of the present invention, the notch patterns 116a are formed by a double patterning process, including first performing a photolithography and etching process using a first photomask (not shown in the figure) to define the notch patterns 116a corresponding to the active regions 10 in the odd-numbered column R1 in the first mask layer 116, and then performing another photolithography and etching process using a second photomask (not shown in the figure) to define the notch patterns 116a corresponding to the active regions 10 in the even-numbered column R2 in the first mask layer 116. As Figure 7 shown, the notch patterns 116a at different positions can have different shapes and sizes. In contrast Figure 2Referring to FIG. 0, the first lower contact 31 and the third lower contact 33 are defined by the same T-shaped notch pattern 116a, the second lower contact 32 and the fourth lower contact 34 are defined by the same T-shaped notch pattern 116a, and the sixth lower contact 36 and the seventh lower contact 37 are defined by the same linear notch pattern 116a. The widths W1 and W2 of the notch pattern 116a corresponding to the portions of the first lower contact 31 and the second lower contact 32 are respectively greater than the widths W3 and W4 of the portions corresponding to the third lower contact 33 and the fourth lower contact 34. In some embodiments, the width W1 is equal to the width W2, and the width W3 is equal to the width W4. In some embodiments, the widths of the portions of the notch pattern 116a corresponding to the fifth lower contact 35, the sixth lower contact 36, and the seventh lower contact 37 may be equal to the width W3 or the width W4. According to an embodiment of the present invention, the material of the first mask layer 116 is titanium nitride (TiN), but it is not limited thereto.
[0122] Please refer to Figure 8 and Figure 9 . Then, a second mask layer 118 is formed on the first mask layer 116, which includes elongated patterns 118a and elongated patterns 118b that are alternately arranged at equal intervals along the first direction X and are parallel to each other, respectively corresponding to the gate structures 20. According to an embodiment of the present invention, the elongated patterns 118a and the elongated patterns 118b are made of different materials. The manufacturing steps may include, for example, first forming a first material layer (not shown in the figure) on the first mask layer 116, and then using a third photomask (not shown in the figure) to perform a photolithography and etching manufacturing process to pattern the first material layer into the elongated patterns 118a corresponding to the gate structures 20 in the odd rows C1. Then, a second material layer (not shown in the figure) is formed to cover the first mask layer 116 and the elongated patterns 118a, and then another photolithography and etching manufacturing process is performed using a fourth photomask (not shown in the figure) to pattern the second material layer into the elongated patterns 118b corresponding to the gate structures 20 in the even rows C2. According to an embodiment of the present invention, the material of the elongated pattern 118a is silicon nitride (SiN), and the material of the elongated pattern 118b is photoresist, but it is not limited thereto.
[0123] Please refer to Figure 10 . Then, using the first mask layer 116 and the second mask layer 118 as masks, the portions of the buffer layer 114 and the lower dielectric layer 112 that are exposed from the gaps between the notch pattern 116a, the elongated pattern 118a, and the elongated pattern 118b are etched away, thereby forming a plurality of lower contact openings OP, respectively exposing portions of the active region 10.
[0124] Please refer to Figure 11 and Figure 12After removing the first mask layer 116 and the second mask layer 118, a barrier layer 30a is then formed along the sidewalls and the bottom surface of the lower contact opening OP, and then a conductive material 30b is formed to fill the lower contact opening OP. Then, the barrier layer 30a, the conductive material 30b, and the buffer layer 114 outside the lower contact opening OP are removed by a planarization process (such as chemical mechanical polishing) until the top surface of the gate structure 20 (i.e., the covering layer 28a) is exposed, thereby obtaining the lower contact 30. As Figure 12 shown, the top surfaces of the respective lower contacts 30 are substantially flush with the top surface of the gate structure 20.
[0125] Please refer to Figure 13 and Figure 14 Next, an etch stop layer 122 and an upper dielectric layer 124 are formed on the lower dielectric layer 112, and then a patterning process is performed to form a plurality of upper contact openings (not shown in the figure) passing through the upper dielectric layer 124 and the etch stop layer 122. Then, an upper contact 40 is formed in the upper contact openings. As Figure 14 shown, the upper contact 40 includes a barrier layer 40a and a conductive material 40b. During the patterning process of the upper contact openings, gate contact openings (not shown in the figure) can be defined in the etch stop layer 122 and the upper dielectric layer 124 at the same time, and a gate contact structure (not shown in the figure) is formed in the gate contact openings synchronously when the upper contact 40 is fabricated subsequently.
[0126] With the fabrication process completed thus far, the static random access memory of the present invention is obtained. Please return to Figure 2 and simultaneously refer to Figure 3 and Figure 4 . Figure 3 is a schematic cross-sectional view along the AA' tangent shown in Figure 2 . Figure 4 is a schematic cross-sectional view along the BB' tangent shown in Figure 2 . As Figure 2 shown, the first lower contact 31, the second lower contact 32, the third lower contact 33, and the fourth lower contact 34 respectively include first edges 31a, 32a, 33a, 34a between the first active region 11 and the second active region 12, and second edges 31b, 32b, 33b, 34b relative to the first edges. The sixth lower contact 36 and the seventh lower contact 37 respectively include third edges 36a, 37a between the third active region 13 and the fourth active region 14, and fourth edges 36b, 37b relative to the third edges.
[0127] As described above, the first lower contact 31 and the third lower contact 33 are defined by the same T-shaped notch pattern 116a, where the first edge 31a and the first edge 33a are defined by the straight edges of the notch pattern 116a, the second edge 31b is defined by the convex edge of the T-shaped protrusion, and the second edge 33b is defined by the flat edges on both sides of the T-shaped protrusion. Therefore, the first edge 31a and the first edge 33a are flush with each other along the first direction X (for example Figure 2 shown flush on the DD' tangent line), while the second edge 31b and the second edge 33b are not flush in the first direction X. The second lower contact 32 and the fourth lower contact 34 are defined by another T-shaped notch pattern 116a, where the first edge 32a and the first edge 34a are defined by the straight edges of the notch pattern 116a, the second edge 32b is defined by the convex edge of the T-shaped protrusion, and the second edge 34b is defined by the flat edges on both sides of the T-shaped protrusion. Therefore, the first edge 32a and the first edge 34a are flush with each other along the first direction X (for example Figure 2 shown flush on the CC' tangent line), while the second edge 32b and the second edge 34b are not flush in the first direction X. The distance between the first edge 31a and the second edge 31b of the first lower contact 31 is greater than the distance between the first edge 33a and the second edge 33b of the third lower contact 33. The distance between the first edge 32a and the second edge 32b of the second lower contact 32 is greater than the distance between the first edge 34a and the second edge 34b of the fourth lower contact 34.
[0128] The sixth lower contact 36 and the seventh lower contact 37 are defined by the same line segment-shaped notch pattern 116a, where the third edge 36a and the third edge 37a are defined by the straight edges of the notch pattern 116a. Therefore, the third edge 36a and the third edge 37a are flush with each other along the first direction X (for example Figure 2 shown flush on the EE' tangent line). It should be understood that the fourth edge 36b and the fourth edge 37b are also defined by another straight edge of the notch pattern 116a, and the two are flush with each other along the first direction X.
[0129] The first upper contact 41 is disposed on the first lower contact 31 and is misaligned along the direction away from the first edge 31a of the first lower contact 31. The second upper contact 42 is disposed on the second lower contact 32 and is misaligned along the direction away from the first edge 32a of the second lower contact 32. As Figure 3 shown, the side wall of the first upper contact 41 and the top surface of the first lower contact 31 form a first stepped portion ST1, and the side wall of the second upper contact 42 and the top surface of the second lower contact 32 form a second stepped portion ST2, and the first stepped portion ST1 faces the second stepped portion ST2.
[0130] In some embodiments, the ends of the third upper contact 43 and the fourth upper contact 44 can be retracted, and the distance between the two can be increased to improve the process margin of the manufacturing process. Therefore, as Figure 4 shown, one side wall of the third upper contact 43 and the top surface of the third lower contact 33 form a third stepped portion ST3, and the other side wall of the third upper contact 43 and the top surface of the fourth lower contact 34 form a fourth stepped portion ST4. Similarly, the side wall of the fourth upper contact 44 and the top surface of the fifth lower contact 35 form a fifth stepped portion ST5, and the other side wall of the fourth upper contact 44 and the top surface of the sixth lower contact 36 form a sixth stepped portion ST6. The widths of the stepped surfaces of the first stepped portion ST1, the second stepped portion ST2, the third stepped portion ST3, the fourth stepped portion ST4, the fifth stepped portion ST5, and the sixth stepped portion ST6 (i.e., the widths of the top surfaces of the lower contacts exposed from the upper contacts) can be adjusted according to design requirements. The present invention uses the T-shaped notch pattern 116a to define the first lower contact 31 and the second lower contact 32 to increase the lengths of the first lower contact 31 and the second lower contact 32 in the second direction Y, and can maintain sufficient contact areas between the first lower contact 31 and the first upper contact 41 and between the second lower contact 32 and the second upper contact 42 in the case of having the first stepped portion ST1 and the second stepped portion ST2, ensuring the electrical connection quality.
[0131] In summary, for the static random access memory and its manufacturing method provided by the present invention, the contact structure is jointly formed by stacked lower contacts and upper contacts, which can improve the layout flexibility, overcome the bottleneck of the miniaturization manufacturing process, and improve the process margin of the manufacturing process.
[0132] The above are only the preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope covered by the present invention.
Claims
1. A static random access memory, comprising: a substrate including a first active region and a second active region that are parallel to each other; a first gate structure spanning the first active region and the second active region; a first lower contact and a second lower contact respectively located on the first active region and the second active region on one side of the first gate structure; and a third lower contact and a fourth lower contact respectively located on the first active region and the second active region on the other side of the first gate structure, wherein in a plan view, the first lower contact, the second lower contact, the third lower contact, and the fourth lower contact respectively include a first edge between the first active region and the second active region, and a second edge relative to the first edge, the first edges of the first lower contact and the third lower contact are aligned with each other, the first edges of the second lower contact and the fourth lower contact are aligned with each other, the second edges of the first lower contact and the third lower contact are not aligned, and the second edges of the second lower contact and the fourth lower contact are not aligned.
2. The static random access memory according to claim 1, wherein the top surfaces of the first lower contact, the second lower contact, the third lower contact, and the fourth lower contact are respectively flush with the top surface of the first gate structure.
3. The static random access memory according to claim 1, further comprising: a first upper contact disposed on the first lower contact and misaligned along a direction away from the first edge of the first lower contact; and a second upper contact disposed on the second lower contact and misaligned along a direction away from the first edge of the second lower contact.
4. The static random access memory according to claim 3, wherein in a cross-sectional view, a sidewall of the first upper contact and the top surface of the first lower contact form a first stepped portion, a sidewall of the second upper contact and the top surface of the second lower contact form a second stepped portion, and the first stepped portion faces the second stepped portion.
5. The static random access memory according to claim 1, further comprising a third upper contact disposed on the third lower contact and the fourth lower contact and electrically connecting the third lower contact and the fourth lower contact.
6. The static random access memory according to claim 5, wherein in a cross-sectional view, a sidewall of the third upper contact and the top surface of the third lower contact form a third stepped portion, and another sidewall of the third upper contact and the top surface of the fourth lower contact form a fourth stepped portion.
7. The static random access memory according to claim 1, further comprising: a third active region and a fourth active region respectively parallel to the second active region, and the third active region is between the second active region and the fourth active region; a second gate structure spanning the third active region and the fourth active region; a fifth lower contact and a sixth lower contact located on a side of the second gate structure close to the first gate structure and respectively located on the third active region and the fourth active region; and a fourth upper contact disposed on the fifth lower contact and the sixth lower contact and electrically connecting the fifth lower contact and the sixth lower contact.
8. The static random access memory as claimed in claim 7, wherein in a cross-sectional view, sidewalls of the fourth upper contact and a top surface of the fifth lower contact form a fifth stepped portion, and sidewalls of the fourth upper contact and a top surface of the sixth lower contact form a sixth stepped portion.
9. The static random access memory as claimed in claim 7, further comprising: a third gate structure aligned with the first gate structure and spanning the fourth active region, wherein the sixth lower contact is located between the second gate structure and the third gate structure; and a seventh lower contact located on the fourth active region and on opposite sides of the third gate structure from the sixth lower contact, wherein the sixth lower contact and the seventh lower contact respectively include a third edge between the third active region and the fourth active region and a fourth edge relative to the third edge, and the third edge and the fourth edge of the sixth lower contact are respectively aligned with the third edge and the fourth edge of the seventh lower contact.
10. The static random access memory as claimed in claim 1, wherein a distance between the first edge and the second edge of the first lower contact is greater than a distance between the first edge and the second edge of the third lower contact, and a distance between the first edge and the second edge of the second lower contact is greater than a distance between the first edge and the second edge of the fourth lower contact.
11. A method of manufacturing a static random access memory, comprising: providing a substrate including a plurality of active regions parallel to each other; forming a lower dielectric layer on the substrate and a plurality of gate structures located in the lower dielectric layer, spanning the plurality of active regions, and parallel to each other; forming a first mask layer on the lower dielectric layer, the first mask layer including a plurality of notch patterns respectively corresponding to the plurality of active regions; forming a second mask layer on the first mask layer, the second mask layer including a plurality of strip patterns respectively corresponding to the plurality of gate structures; etching the lower dielectric layer using the first mask layer and the second mask layer as masks to form a plurality of lower contact openings respectively exposing portions of the plurality of active regions; and forming a plurality of lower contacts in the plurality of lower contact openings.
12. The method of manufacturing a static random access memory as claimed in claim 11, wherein top surfaces of the plurality of lower contacts are flush with top surfaces of the plurality of gate structures.
13. The method of manufacturing a static random access memory as claimed in claim 11, wherein the plurality of notch patterns have different shapes.
14. The method of manufacturing a static random access memory as claimed in claim 11, wherein the plurality of notch patterns have different sizes.
15. The method of manufacturing a static random access memory as claimed in claim 11, wherein the step of forming the first mask layer includes: defining the plurality of notch patterns in odd columns using a first photomask; and defining the plurality of notch patterns in even columns using a second photomask.
16. The method of manufacturing a static random access memory as claimed in claim 11, wherein the step of forming the second mask layer includes: defining the plurality of strip patterns in odd rows using a third photomask; and Define the plurality of strip patterns for the even rows using a fourth photomask.
17. The method of manufacturing a static random access memory according to claim 16, wherein the plurality of strip patterns for the odd rows and the plurality of strip patterns for the even rows are made of different materials.
18. The method of manufacturing a static random access memory according to claim 11, wherein the first mask and the second mask are made of different materials.
19. The method of manufacturing a static random access memory according to claim 11, further comprising: Forming an upper dielectric layer on the lower dielectric layer; and Forming a plurality of upper contacts in the upper dielectric layer, respectively located on the plurality of lower contacts.
20. The method of manufacturing a static random access memory according to claim 11, wherein a stepped portion is formed between some of the plurality of upper structures and the plurality of lower structures.