Nonvolatile two-end memory cell, manufacturing method thereof, memory and electronic equipment

Abstract

The invention discloses a nonvolatile two-end storage unit, a manufacturing method thereof, a memory and electronic equipment. The nonvolatile two-end storage unit comprises at least two lower-layer metal connecting wires which are arranged at intervals; the laminated structure comprises at least two lower electrode layers arranged at intervals and conversion layers stacked on the lower electrode layers, and the lower electrode layers and the lower metal connecting wires are arranged in a one-to-one correspondence mode and electrically connected; the upper electrode layers are arranged in one-to-one correspondence with the laminated structures and cover the laminated structures; an upper layer metal wire; and the upper electrode metal connecting wire is arranged on the upper electrode layer and is used for electrically connecting the upper electrode layer to the upper layer metal connecting wire. Through the scheme of the embodiment of the invention, the process window of the preparation process of the upper electrode metal connecting wire can be expanded, the production difficulty is reduced, the product quality problem caused by the process operation problem is further reduced, and the reliability of the product performance is ensured.

Description

Technical Field

[0001] This disclosure generally relates to the field of semiconductor technology. More specifically, this disclosure relates to a non-volatile two-terminal memory cell, a method for manufacturing a non-volatile two-terminal memory cell, a memory, and an electronic device. Background Art

[0002] In the prior art, new memories are usually disposed between the back-end copper interconnect structures, where the bottom electrode (BE) is connected to the surface of the lower metal wire through a bottom electrode via, the top electrode (TE) is connected to the interconnect structure through a top electrode via, and a conversion layer is disposed between the top and bottom electrodes. The memory cells usually adopt a columnar structure and are distributed in an array manner.

[0003] With the rapid development of artificial intelligence technology, especially large language models, the demand for the capacity and performance of memories has further increased. In order to adapt to devices with high computing performance, some existing solutions expand the storage capacity of new memories by increasing the number of memory cells in the new memories, so as to meet the stringent requirements for storage capacity and read / write performance of devices such as servers and intelligent terminals.

[0004] However, with the increase in the number of memory cells, within the limited layout space, the available space of a single memory cell is greatly reduced, and the improvement of the miniaturization degree of the memory cell also places higher requirements on the process precision of the manufacturing process of the memory cell. The increase in process difficulty will increase the abnormal risk caused by process operation problems, thereby affecting the product yield.

[0005] In view of this, there is an urgent need to provide a non-volatile two-terminal storage solution to reduce the process difficulty during production and ensure the stability of the product quality and the product yield of non-volatile two-terminal memory cells. Summary of the Invention

[0006] In order to solve at least one or more of the above-mentioned technical problems, this disclosure proposes a non-volatile two-terminal storage solution in multiple aspects.

[0007] In a first aspect, this disclosure provides a non-volatile two-terminal memory cell including: at least two spaced-apart lower metal wires; a stacked structure including at least two spaced-apart lower electrode layers and a conversion layer stacked on the lower electrode layers, the lower electrode layers being disposed in one-to-one correspondence with and electrically connected to the lower metal wires; an upper electrode layer disposed in one-to-one correspondence with the stacked structure and covering the stacked structure; an upper metal wire; and an upper electrode metal wire disposed on the upper electrode layer and electrically connecting the upper electrode layer to the upper metal wire.

[0008] In a second aspect, the present disclosure provides a method for manufacturing a non-volatile two-terminal storage cell, comprising: preparing at least two lower metal interconnects arranged at intervals; preparing, on each of the lower metal interconnects, a lower electrode layer electrically connected thereto; depositing a conversion layer on the lower electrode layer to form a stacked structure, the stacked structure comprising at least two lower electrode layers arranged at intervals and a conversion layer stacked on the lower electrode layer; depositing an upper electrode layer on each of the stacked structures; preparing, on the upper electrode layer, an upper electrode metal interconnect electrically connected thereto; and preparing an upper metal interconnect electrically connected to the upper electrode metal interconnect.

[0009] In a third aspect, the present disclosure provides a memory having the non-volatile two-terminal storage cell as in the first aspect.

[0010] In a fourth aspect, the present disclosure provides an electronic device having the memory as in the third aspect.

[0011] With the non-volatile two-terminal storage cell provided as above, in the embodiments of the present disclosure, by using an upper electrode layer to cover a stacked structure, a plurality of conversion layers can share one upper electrode layer. Compared with the non-volatile two-terminal storage cell with non-shared upper electrode layers, the non-volatile two-terminal storage cell provided in the embodiments of the present disclosure can provide a larger upper electrode layer, thereby providing a larger process window for the preparation of the upper electrode metal interconnect, facilitating the implementation of a via preparation process with higher precision, and reducing the negative impact on the process implementation due to an overly small process window. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] By reading the following detailed description with reference to the accompanying drawings, the above and other objects, features, and advantages of the exemplary embodiments of the present disclosure will become readily understood. In the drawings, several embodiments of the present disclosure are shown by way of illustration and not limitation, and like or corresponding reference numerals represent like or corresponding parts, wherein:

[0013] Figure 1 An exemplary structural diagram of a non-volatile two-terminal storage cell according to some embodiments of the present disclosure is shown;

[0014] Figure 2 An exemplary structural diagram of a stacked structure according to some embodiments of the present disclosure is shown;

[0015] Figure 3 An exemplary structural diagram of a stacked structure according to some embodiments of the present disclosure is shown;

[0016] Figure 4 An exemplary structural diagram of a stacked structure according to some embodiments of the present disclosure is shown;

[0017] Figure 5 An exemplary structural diagram of a non-volatile two-terminal storage cell according to some embodiments of the present disclosure is shown;

[0018] Figure 6 Shows an exemplary structural diagram of a non-volatile two-terminal storage cell according to some embodiments of the present disclosure;

[0019] Figure 7 Shows an exemplary structural diagram of a non-volatile two-terminal storage cell according to some embodiments of the present disclosure;

[0020] Figure 8 Shows an exemplary structural diagram of a non-volatile two-terminal storage cell according to some embodiments of the present disclosure;

[0021] Figure 9 Shows an exemplary structural diagram of a non-volatile two-terminal storage cell according to some embodiments of the present disclosure

[0022] Figure 10 Shows an exemplary structural diagram of a non-volatile two-terminal storage cell according to some embodiments of the present disclosure;

[0023] Figure 11 Shows an exemplary structural diagram of a non-volatile two-terminal storage cell according to some embodiments of the present disclosure;

[0024] Figure 12 Shows an exemplary structural diagram of a non-volatile two-terminal storage cell according to some embodiments of the present disclosure;

[0025] Figure 13 Shows an exemplary structural diagram of a non-volatile two-terminal storage cell according to some embodiments of the present disclosure;

[0026] Figure 14 Shows an exemplary structural diagram of a non-volatile two-terminal storage cell according to some embodiments of the present disclosure;

[0027] Figure 15 Shows an exemplary structural diagram of a non-volatile two-terminal storage cell according to some embodiments of the present disclosure;

[0028] Figure 16 Shows an exemplary structural diagram of a non-volatile two-terminal storage cell according to some embodiments of the present disclosure;

[0029] Figure 17 Shows an exemplary flowchart of a manufacturing method of a non-volatile two-terminal storage cell according to some embodiments of the present disclosure;

[0030] Figure 18 Shows an exemplary flowchart of a manufacturing method of a non-volatile two-terminal storage cell according to some embodiments of the present disclosure;

[0031] Figure 19 Shows an exemplary flowchart of a manufacturing method of a non-volatile two-terminal storage cell according to some embodiments of the present disclosure;

[0032] Figure 20 An exemplary flowchart showing a method of manufacturing a non-volatile two-terminal memory cell according to some embodiments of the present disclosure;

[0033] Figure 21 An exemplary flowchart showing a method of manufacturing a non-volatile two-terminal memory cell according to some embodiments of the present disclosure;

[0034] Figure 22 A schematic diagram showing the manufacturing process of a non-volatile two-terminal memory cell according to some embodiments of the present disclosure. Detailed implementation manners

[0035] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present disclosure without creative efforts shall fall within the protection scope of the present disclosure.

[0036] It should be understood that the terms "including" and "comprising" used in the specification and claims of the present disclosure indicate the presence of the described features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their combinations.

[0037] It should also be understood that the terms used in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used in the specification and claims of the present disclosure, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include the plural forms. It should be further understood that the term "and / or" used in the specification and claims of the present disclosure refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0038] As used in this specification and the claims, the term "if" can be interpreted as "when" or "once" or "in response to a determination" or "in response to a detection" depending on the context. Similarly, the phrase "if a determination" or "if a [described condition or event] is detected" can be interpreted as meaning "once a determination" or "in response to a determination" or "once a [described condition or event] is detected" or "in response to a detection of a [described condition or event]" depending on the context.

[0039] The following will describe in detail the specific implementation manners of the present disclosure with reference to the accompanying drawings.

[0040] Exemplary application scenarios

[0041] In order to adapt to the performance requirements of memories for rapidly developing technologies such as artificial intelligence, some existing solutions expand the storage capacity of new memories by increasing the number of memory cells in the new memories, so as to meet the stringent requirements for storage capacity and read / write performance of devices such as servers and intelligent terminals.

[0042] However, with the increase in the number of memory cells, the volume of the new memory also increases, which is not conducive to the application of the new memory in scenarios such as edge computing and the Internet of Things. Such scenarios usually require integrating more functions in a limited space, thus posing certain requirements for the miniaturization and performance of the new memory. The miniaturization requirement will in turn impose higher requirements on the process precision in the production process, resulting in an increase in production difficulty.

[0043] Exemplary application solutions

[0044] In view of this, the embodiments of the present disclosure provide a non-volatile two-terminal storage solution, which provides a larger process window for the preparation process of the upper electrode metal connection by sharing one upper electrode layer among multiple conversion layers, thereby reducing the device preparation difficulty and reducing device performance problems caused by improper process operations.

[0045] For the sake of easy understanding, first, the basic storage structure that plays a storage function in the non-volatile two-terminal memory cell is described. In the non-volatile two-terminal memory cell, the lower electrode layer, the conversion layer, and the upper electrode layer stacked in sequence constitute the basic storage structure. By applying a voltage between the upper electrode layer and the lower electrode layer, the formation of conductive filaments in the conversion layer can be controlled, thereby realizing the switching between the high-resistance state and the low-resistance state, and further achieving the purpose of storing different data. In the non-volatile two-terminal memory cell, the voltage applied between the upper electrode layer and the lower electrode layer comes from the upper metal connection electrically connected to the upper electrode layer and the lower metal connection electrically connected to the lower electrode layer.

[0046] In some embodiments, the electrical connection between the upper electrode layer and the upper metal connection is completed through the upper electrode metal connection. The upper electrode metal connection can be formed through the following processes: first, a through hole connecting the upper electrode layer and the upper metal connection is formed through a through hole preparation process such as a dual damascene process, a tungsten plug process, and / or a self-aligned via process, and then, the through hole is filled with metal to form the upper electrode metal connection.

[0047] Due to the wide application of artificial intelligence technology in various industries, higher requirements are put forward for the capacity and performance of memories. Some existing memory solutions choose to increase the number of memory cells in a single memory to achieve high-integration and high-density memories. Since the volume of a single memory is limited, the increase in the number of memory cells will inevitably lead to a reduction in the area available for a single memory cell, which in turn causes a reduction in the process window for the via preparation process that can be used in the upper electrode layer. This undoubtedly increases the production difficulty and also has a certain impact on the product yield of the memory.

[0048] In addition, the reduction in the area available for a single memory cell will also lead to a reduction in the available space of the basic memory structure in the non-volatile two-terminal memory cell. The contact areas of the lower electrode layer, the conversion layer, and the upper electrode layer are limited, resulting in a certain impact on the stability of the basic memory structure, and further affecting the stability of the performance of the entire non-volatile two-terminal memory cell, thereby having a certain impact on the product yield of the memory.

[0049] To address the problems caused by the reduction in the process window for the via preparation process, some embodiments of the present disclosure propose a non-volatile two-terminal memory cell. Figure 1 The exemplary structural diagram of the non-volatile two-terminal memory cell according to some embodiments of the present disclosure is shown.

[0050] As Figure 1 shown, the non-volatile two-terminal memory cell includes: at least two lower metal interconnects 2 arranged at intervals, a stacked structure 4, an upper electrode layer 8, an upper metal interconnect 11, and an upper electrode metal interconnect 10.

[0051] Among them, the stacked structure 4 refers to a composite layer structure formed by stacking a lower electrode layer 41 and a conversion layer 42. The stacked structure 4 in the embodiments of the present disclosure has at least two lower electrode layers 41 arranged at intervals. These lower electrode layers 41 are arranged in one-to-one correspondence with the lower metal interconnects 2 and are electrically connected. Moreover, different lower electrode layers 41 are electrically isolated from each other to ensure that they can work independently. Further, different lower electrode layers 41 can be electrically isolated by an insulating material. Furthermore, the upper electrode layer 8 and the lower electrode layer 41 can also be electrically isolated by an insulating material to prevent device short circuits.

[0052] The stacked structure in the embodiments of the present disclosure further includes a conversion layer 42 stacked on the lower electrode layer 41. As Figure 1 shown, in some embodiments, the stacked structure 4 may include: a conversion layer 42 that simultaneously covers each lower electrode layer 41. In other words, there is one and only one conversion layer 42 in each stacked structure 4, and this conversion layer 42 simultaneously covers all the lower electrode layers 41 in the current stacked structure 4.

[0053] In some other embodiments, the stacked structure 4 may include: at least two conversion layers 42 arranged at intervals, and the conversion layers 42 are arranged in one-to-one correspondence with the lower electrode layers 41. One conversion layer 42 is arranged on each lower electrode layer 41, and different conversion layers 42 are electrically isolated from each other to ensure that they can work independently. At this time, the stacked structure is as shown in Figure 2 shown in Figure 2 FIG. shows an exemplary structural diagram of the stacked structure according to some embodiments of the present disclosure.

[0054] In still some other embodiments, the stacked structure 4 may also include: at least two conversion layers 42 arranged at intervals, wherein at least one conversion layer 42 covers a plurality of lower electrode layers 41, for example, 2 or more lower electrode layers. In other words, in this embodiment, there are a plurality of conversion layers 42 in the stacked structure 4. In one case, a part of the conversion layers 42 may each cover one lower electrode layer 41, while another part of the conversion layers 42 may each cover a plurality of lower electrode layers 41 at the same time. There is no strict limit on the number of the above two parts of conversion layers. At this time, the stacked structure is as shown in Figure 3 shown in Figure 3 FIG. shows an exemplary structural diagram of the stacked structure according to some embodiments of the present disclosure. In another case, a plurality of conversion layers 42 may each cover a plurality of lower electrode layers 41 at the same time. At this time, the stacked structure is as shown in Figure 4 shown in Figure 4 FIG. shows an exemplary structural diagram of the stacked structure according to some embodiments of the present disclosure.

[0055] In the embodiments of the present disclosure, on any of the stacked structures described above in combination with Figure 2 , Figure 3 or Figure 4 , an upper electrode layer is covered, and the upper electrode layer is arranged in one-to-one correspondence with the stacked structure. In other words, for a stacked structure, regardless of whether the number of conversion layers it contains is one or more, the conversion layers are all covered by the same upper electrode layer.

[0056] It can be understood that in the embodiments of the present disclosure, for a stacked structure, a plurality of lower electrode layers arranged at intervals may share one conversion layer or use a plurality of conversion layers. When using a plurality of conversion layers, some lower electrode layers may share one conversion layer and some lower electrode layers may use separate conversion layers, or all conversion layers may be shared by a plurality of lower electrode layers. In addition, for a stacked structure, the lower electrode layer and the conversion layer therein share the same upper electrode layer. At this time, compared with the non-volatile two-terminal storage unit with a non-shared upper electrode layer, the embodiments of the present disclosure can provide a larger upper electrode layer, thereby providing a larger process window for the preparation of the upper electrode metal connection.

[0057] Based on the process window provided by the upper electrode layer, in the embodiments of the present disclosure, an upper electrode metal wire electrically connected thereto can be formed on the upper electrode layer.

[0058] In some embodiments, as Figure 1 shown, since the lower electrode layer 41 and the conversion layer 42 in the stacked structure 4 share an upper electrode layer 8, an upper electrode metal wire 10 electrically connected thereto can be provided for each upper electrode layer 8, and is electrically connected to the upper layer metal wire 11 through the upper electrode metal wire 10. This embodiment allows a relatively large via hole to be prepared and then filled with metal to form the upper electrode metal wire, with relatively low process precision requirements and high product yield.

[0059] In other embodiments, Figure 5 An exemplary structural diagram of a non-volatile two-terminal storage cell according to some embodiments of the present disclosure is shown, as Figure 5 shown, multiple upper electrode metal wires 10 electrically connected thereto can also be provided on the upper electrode layer 8, and the upper electrode metal wires 10 are arranged in one-to-one correspondence with the lower electrode layer 41 or the conversion layer 42 in the stacked structure 4. This embodiment provides a relatively large process window, which is beneficial to performing a via hole preparation process with higher precision and reducing the negative impact on process execution caused by an overly small process window.

[0060] It should be noted that the above embodiments are described for one stacked structure in the non-volatile two-terminal storage cell. For the non-volatile two-terminal storage cell, the number of stacked structures included therein is one or more.

[0061] It can be understood that when the number of stacked structures included in the non-volatile two-terminal storage cell is one, all the lower electrode layers and conversion layers in the non-volatile two-terminal storage cell share an upper electrode layer. When the number of stacked structures included in the non-volatile two-terminal storage cell is multiple, all the lower electrode layers in the non-volatile two-terminal storage cell can be divided into several groups, and each group of lower electrode layers shares an upper electrode layer. Further, regardless of whether the number of stacked structures is one or multiple, the lower electrode layers can share a conversion layer, or some of the lower electrode layers share a conversion layer and some of the lower electrode layers are each covered with a corresponding conversion layer, or each lower electrode layer is covered with a separately corresponding conversion layer.

[0062] Regarding the problem caused by the limited contact area of the lower electrode layer, the conversion layer, and the upper electrode layer, some embodiments of the present disclosure also propose a non-volatile two-terminal storage cell, Figure 6 An exemplary structural diagram of a non-volatile two-terminal storage cell according to some embodiments of the present disclosure is shown.

[0063] As Figure 6As shown, the non-volatile two-terminal memory cell includes: a lower metal wire 2, a lower electrode layer 41, a conversion layer 42, and an upper electrode layer 8 stacked in sequence, wherein the upper electrode layer 8 is isolated from the lower electrode layer 41 to prevent device short-circuit. Further, in some embodiments, electrical isolation can also be achieved between the upper electrode layer 8 and the lower electrode layer 41 through an insulating material.

[0064] In Figure 6 In the non-volatile two-terminal memory cell shown, the conversion layer 42 contacts at least two surfaces of the lower electrode layer 41, wherein the surface of the lower electrode layer 41 covered by the conversion layer 42 includes: the top surface of the lower electrode layer 41. Further, the lower electrode layer 41 includes: a top surface and side walls connected to each other, and the conversion layer 42 includes: a first part and a second part, wherein the first part of the conversion layer 42 covers the top surface of the lower electrode layer 41, and the second part of the conversion layer 42 at least partially contacts the side walls of the lower electrode layer 41.

[0065] It can be understood that the side wall of the lower electrode layer contacted by the second part of the conversion layer mentioned above is one of the at least two surfaces of the lower electrode layer contacted by the conversion layer.

[0066] The lower electrode layer 41 includes a top surface, a bottom surface, and side walls connecting the two. It should be noted that the lower electrode layer can be in the shape of a square column, a cylinder, or other shapes. The square-column-shaped lower electrode layer 41 includes four planar side walls, and the cylinder-shaped lower electrode layer 41 includes a curved side wall. The number and shape of the side walls of the lower electrode layer are not limited in this embodiment. Among them, the bottom surface of the lower electrode layer 41 is in direct electrical connection or indirect electrical connection with the lower metal wire 2, the top surface of the lower electrode layer 41 is completely covered by the conversion layer 42, and at least part of the side walls of the lower electrode layer 41 are covered by the conversion layer 42. For the RRAM in the prior art solution, the contact area between the lower electrode layer and the conversion layer is only the surface area S1 of the top surface of the lower electrode layer. In the non-volatile two-terminal memory cell shown in this embodiment, the contact area between the lower electrode layer and the conversion layer, in addition to the surface area of the top surface of the lower electrode layer, also includes the surface area of at least part of the side walls of the lower electrode layer. In other words, in the non-volatile two-terminal memory cell shown in this embodiment, the contact area S between the lower electrode layer 41 and the conversion layer 42 = S1 + S2, where S1 represents the surface area of the top surface of the lower electrode layer, and S2 represents the surface area of part of the side walls of the lower electrode layer. Compared with the prior art solution with a contact area of S1, a larger contact area is formed between the lower electrode layer 41 and the conversion layer 42 in this embodiment.

[0067] Assume that the lower electrode layer 41 is in the shape of a square column, which includes four side walls, and the second part of the conversion layer 42 can contact one or more of the side walls. Figure 7 Shows an exemplary structural diagram of a non-volatile two-terminal memory cell according to some embodiments of the present disclosure, such as Figure 7As shown, when the second part of the conversion layer 42 contacts the four side walls of the lower electrode layer 41, the conversion layer 42 will completely cover the exposed surface of the lower electrode layer 41, and the conversion layer 42 will isolate the lower electrode layer 41 from the upper electrode layer 8.

[0068] It can be understood that the covering state of the conversion layer on the lower electrode layer includes the following two types: the first is that the second part of the conversion layer contacts part of the side walls of the lower electrode layer, and the second is that the second part of the conversion layer contacts all the side walls of the lower electrode layer.

[0069] Similarly to the conversion layer 42 and the lower electrode layer 41, the upper electrode layer 8 contacts at least two surfaces of the conversion layer 42. Among them, the surfaces of the conversion layer 42 covered by the upper electrode layer 8 include: the top surface of the conversion layer 42. Further, the upper electrode layer 8 includes: a third part and a fourth part. Among them, the third part of the upper electrode layer 8 covers the first part of the conversion layer 42, and the fourth part of the upper electrode layer 8 at least partially contacts the second part of the conversion layer 42.

[0070] It can be understood that the side wall of the conversion layer contacted by the fourth part of the upper electrode layer is one of the at least two surfaces of the conversion layer contacted by the upper electrode layer.

[0071] The conversion layer 42 also includes a top surface, a bottom surface, and side walls connecting the two. The number and shape of the side walls of the conversion layer 42 are also not limited. Among them, the bottom surface of the conversion layer 42 is in direct contact with the lower electrode layer 41, the top surface of the conversion layer 42 is covered by the upper electrode layer 8, and at least part of the side walls of the conversion layer 42 are covered by the upper electrode layer 8. For the RRAM in the prior art solution, the contact area between the upper electrode layer and the conversion layer is only the surface area S3 of the top surface of the conversion layer. In the non-volatile two-terminal storage unit shown in this embodiment, the contact area between the upper electrode layer and the conversion layer, in addition to the surface area of the top surface of the conversion layer, also includes the surface area of at least part of the side walls of the conversion layer. In other words, in the non-volatile two-terminal storage unit shown in this embodiment, the contact area S' between the upper electrode layer and the conversion layer = S3 + S4, where S3 represents the surface area of the top surface of the conversion layer, and S4 represents the surface area of part of the side walls of the conversion layer. Compared with the prior art solution with a contact area of S3, a larger contact surface area is formed between the upper electrode layer 8 and the conversion layer 42 in this embodiment.

[0072] By extending the contact surface between the lower electrode layer and the conversion layer from the top surface of the lower electrode layer to the side wall of the lower electrode layer, the longitudinal surface can be effectively utilized. Without increasing the lateral occupation area of the lower electrode layer, the contact area between the lower electrode layer and the conversion layer can be increased. Similarly, by extending the contact surface between the upper electrode layer and the conversion layer from the top surface of the conversion layer to the side wall of the conversion layer, the contact area between the upper electrode layer and the conversion layer can be increased without increasing the lateral occupation area of the conversion layer. Thus, the contact area between adjacent structural layers in the RRAM can be increased as a whole to provide a larger area for the formation of the conductive filament.

[0073] Assume that the conversion layer 42 is in the shape of a square column and includes four side walls. The fourth part of the upper electrode layer 8 can contact one or more side walls of the conversion layer 42. As Figure 7 shown, when the fourth part of the upper electrode layer 8 contacts the four side walls of the conversion layer 42, the upper electrode layer 8 will completely cover the exposed surface of the conversion layer 42. In other words, the upper electrode layer 8 and the lower electrode layer 41 will completely enclose the conversion layer 42.

[0074] It can be understood that the covering state of the upper electrode layer on the conversion layer also includes the following two types: one is that the fourth part of the upper electrode layer contacts part of the side walls of the conversion layer, and the other is that the second part of the upper electrode layer contacts all the side walls of the conversion layer.

[0075] It should be noted that when the fourth part of the upper electrode layer contacts part of the side walls of the conversion layer, the covering state of the conversion layer on the lower electrode layer can be the first covering state described in the previous embodiments or the second covering state described in the previous embodiments. Similarly, when the second part of the electrode layer contacts all the side walls of the conversion layer, the covering state of the conversion layer on the lower electrode layer can be the first covering state described in the previous embodiments or the second covering state described in the previous embodiments.

[0076] Since the conversion layer not only covers the top surface of the lower electrode layer but also at least covers part of the side walls of the lower electrode layer, the contact area between the conversion layer and the lower electrode layer is increased while the bottom area of the lower electrode layer remains the same. The bottom area of the lower electrode layer can be reduced while maintaining the original contact area. Similarly, the contact area between the upper electrode layer and the conversion layer is also increased, which is beneficial to integrating more memory cells in a limited space while taking into account the reliability of device performance, and achieving higher storage density and storage capacity.

[0077] In the above non-volatile two-terminal memory cell, the lower metal wire 2 includes a conductive material, so that the driving voltage applied to the lower metal wire 2 can be transmitted to the lower electrode layer 41, and the formation of the conductive filament in the conversion layer 42 is controlled in combination with the driving voltage received by the upper electrode layer 8.

[0078] According to the diffusion characteristics of the conductive material, the conductive material can be divided into a first type of conductive material that is easy to diffuse and a second type of conductive material that is not easy to diffuse.

[0079] In some embodiments, for the first type of conductive material that is easy to diffuse, for example, one or more of the following materials: copper, silver, aluminum, the non-volatile two-terminal storage unit further includes: a diffusion barrier layer 3. Figure 8 An exemplary structural diagram of a non-volatile two-terminal storage unit according to some embodiments of the present disclosure is shown, as Figure 8 shown, the diffusion barrier layer 3 and the lower electrode layer 41 are sequentially stacked on the top surface of the lower metal wire 2, which is used to prevent the diffusion of the conductive material in the lower metal wire 2, avoid problems such as the deterioration of the interface quality between the lower metal wire 2 and the lower electrode layer 41 and the accelerated aging of the device, and ensure that the formation process of the conductive filament in the conversion layer 42 is not affected.

[0080] In other embodiments, for the second type of conductive material that is not easy to diffuse, for example, one or more of the following materials: tungsten, titanium, titanium nitride, ruthenium, the top surface of the lower metal wire 2 in the non-volatile two-terminal storage unit is as Figure 7 shown, which is in direct contact with the bottom surface of the lower electrode layer 41.

[0081] It should be noted that in actual applications, even if the conductive material has the characteristic of not being easy to diffuse, a diffusion barrier layer can be directly provided between the lower metal wire 2 and the lower electrode layer 41 to ensure that the device performance is not affected.

[0082] It should also be noted that in the embodiments described in combination with Figures 1 to 5 it can also be determined whether to provide the diffusion barrier layer 3 according to the diffusion characteristics of the conductive material used in the lower metal wire 2. Or, regardless of which conductive material the lower metal wire 2 uses, a diffusion barrier layer 3 is provided between the lower metal wire 2 and the lower electrode layer 41 to prevent the negative impact caused by metal diffusion.

[0083] The above embodiments describe the structural design made for the problem that the conductive material in the lower metal wire diffuses to the lower electrode layer. In actual applications, the conductive material in the lower metal wire may also diffuse to other structural layers, for example, the logic unit or other dielectric layers in the device. Considering this problem, some embodiments of the present disclosure also design the structure of the non-volatile two-terminal storage unit based on the relative sizes of the lower electrode layer and the lower metal wire and the diffusion characteristics of the conductive material used in the lower metal wire.

[0084] If the lower metal interconnect satisfies one or more of the following conditions: the conductive material of the lower metal interconnect is copper, silver, and / or aluminum and the width of the lower metal interconnect is greater than the width of the lower electrode layer, then there is a possibility that the conductive material in the lower metal interconnect diffuses into other structural layers, thereby affecting the device performance. In view of this situation, some embodiments of the present disclosure provide a non-volatile two-terminal memory cell. Figure 9 FIG. shows an exemplary structural diagram of a non-volatile two-terminal memory cell according to some embodiments of the present disclosure. Figure 9 As shown, the non-volatile two-terminal memory cell further includes an etch stop layer 6 and a lower metal interlayer dielectric layer 1. Among them, the lower metal interconnect 2 is disposed inside the lower metal interlayer dielectric layer 1, and the top surface of the lower metal interconnect 2 is flush with the top surface of the lower metal interlayer dielectric layer 1. The etch stop layer 6 covers the top surface of the lower metal interlayer dielectric layer 1 and / or a part of the top surface of the lower metal interconnect 2.

[0085] As an example, if the conductive material of the lower metal interconnect 2 is copper, silver, and / or aluminum, it indicates that the conductive material in the lower metal interconnect 2 is prone to diffusion. At this time, the lower electrode layer 41 is electrically connected to the lower metal interconnect 2 through a diffusion barrier layer 3. Assuming that the width of the lower metal interconnect 2 is less than or equal to the width of the lower electrode layer 41, as Figure 9 shown, at this time, the conductive material is likely to diffuse into the logic area of the device, affecting the operation of the logic components in the logic area. By providing the etch stop layer 6, this problem can be effectively avoided.

[0086] As another example, Figure 10 FIG. shows an exemplary structural diagram of a non-volatile two-terminal memory cell according to some embodiments of the present disclosure. Figure 10 As shown, assuming that the conductive material of the lower metal interconnect is copper, silver, and / or aluminum, at this time, the lower electrode layer 41 is electrically connected to the lower metal interconnect 2 through a diffusion barrier layer 3, and moreover, the width of the lower metal interconnect 2 is greater than the width of the lower electrode layer 41. Then, the conductive material is not only likely to diffuse into the logic area of the device, but also may diffuse into the structural layers around the lower electrode layer 41. By providing the etch stop layer 6, this problem can also be effectively avoided.

[0087] As yet another example, Figure 11 FIG. shows an exemplary structural diagram of a non-volatile two-terminal memory cell according to some embodiments of the present disclosure. Figure 11As shown, assuming that the width of the lower metal interconnect 2 is greater than the width of the lower electrode layer 41 and the conductive material of the lower metal interconnect 2 is not prone to diffusion, the lower electrode layer 41 can be in direct contact with the lower metal interconnect 2. At this time, the lower metal interconnect 2 not covered by the lower electrode layer 41 is likely to form a conductive path with the conversion layer 42 and the upper electrode layer 8, thus affecting the formation of the conductive path of the lower electrode layer - conversion layer - upper electrode layer. By providing an etch stop layer 6, the formation of the conductive path of the lower metal interconnect - conversion layer - upper electrode layer can be effectively restricted.

[0088] Furthermore, in some embodiments, the thickness of the etch stop layer 6 is greater than 150 Å to ensure that it has sufficient anti-diffusion ability.

[0089] In contrast to the above situation, if the lower metal interconnect satisfies the following conditions: the conductive material of the lower metal interconnect is tungsten, titanium, titanium nitride, and / or ruthenium and the width of the lower metal interconnect is less than or equal to the width of the lower electrode layer, it can be considered that the possibility of the conductive material in the lower metal interconnect 2 diffusing into other structural layers and affecting the device performance is relatively small, and thus the structure layer of the etch stop layer 6 can be simplified. At this time, the non-volatile two-terminal memory cell includes: an insulating dielectric layer 9 and a lower metal interlayer dielectric layer 1. The lower metal interconnect 2 is disposed inside the lower metal interlayer dielectric layer 1, and the top surface of the lower metal interconnect 2 is flush with the top surface of the lower metal interlayer dielectric layer 1. The bottom surface of the insulating dielectric layer 9 is in direct contact with and covers the top surface of the lower metal interlayer dielectric layer 1.

[0090] Since the conductive material of the lower metal interconnect 2 is a material such as tungsten, titanium, titanium nitride, and / or ruthenium that is not prone to diffusion, in this non-volatile two-terminal memory cell, the lower electrode layer 41 is in direct contact with the lower metal interconnect 2.

[0091] It should be noted that if the lower metal interconnect satisfies the following conditions: the conductive material of the lower metal interconnect is tungsten, titanium, titanium nitride, and / or ruthenium and the width of the lower metal interconnect is less than or equal to the width of the lower electrode layer, both the etch stop layer 6 and the diffusion barrier layer 3 are optional structural layers. In other words, if the lower metal interconnect satisfies the following conditions: the conductive material of the lower metal interconnect is tungsten, titanium, titanium nitride, and / or ruthenium and the width of the lower metal interconnect is less than or equal to the width of the lower electrode layer, an etch stop layer can be provided on the top surface of the insulating dielectric layer 9 and / or the lower metal interlayer dielectric layer 1, or it can be not provided, and no excessive restrictions are made here. Additionally, if the lower metal interconnect satisfies the following conditions: the conductive material of the lower metal interconnect is tungsten, titanium, titanium nitride, and / or ruthenium and the width of the lower metal interconnect is less than or equal to the width of the lower electrode layer, a diffusion barrier layer can be provided between the lower electrode layer and the lower metal interconnect, or it can be not provided, and no excessive restrictions are made here either.

[0092] It should be noted that in the embodiments described in conjunction with Figures 1 to 5 whether to provide an etch stop layer can also be determined according to the diffusion characteristics of the conductive material and the relative widths of the lower electrode layer and the lower metal interconnects. Alternatively, regardless of the conductive material used for the lower metal interconnects, an etch stop layer is provided between the lower metal interconnects and the lower electrode layer to prevent the negative impacts caused by metal diffusion.

[0093] It should also be noted that in the non-volatile two-terminal memory cell provided with the etch stop layer 6, the etch stop layer 6 and the upper metal interconnect 11 can also be filled with an insulating dielectric layer 9 to form an insulating region, so as to avoid unnecessary electrical connections between the conductive structural layers and cause problems such as device short circuits.

[0094] Furthermore, the structural design for the problem of too small process window and the structural design for the problem of limited contact area can be combined to improve the product yield in the production process from multiple dimensions. In other words, the structures of various non-volatile two-terminal memory cells shown in the foregoing embodiments can be combined in multiple selections according to actual situations to form a new structure of the non-volatile two-terminal memory cell.

[0095] Taking Figure 1 the non-volatile two-terminal memory cell shown as an example, the conversion layer therein can contact at least two surfaces of the lower electrode layer, and one surface is the top surface of the lower electrode layer. For the sake of understanding, Figure 12 an exemplary structural diagram of the non-volatile two-terminal memory cell of some embodiments of the present disclosure is shown. As Figure 12 shown, a conversion layer 42 covers both the top surface and the sidewalls of a plurality of lower electrode layers 41 in the stacked structure 4 at the same time, thereby increasing the contact area between the lower electrode layer 41 and the conversion layer 42. An upper electrode layer 8 covers both the top surface and the sidewalls of the conversion layer 42 at the same time, thereby increasing the contact area between the upper electrode layer 8 and the conversion layer 42 and expanding the process window of the upper electrode metal interconnect 10 corresponding to the stacked structure 4.

[0096] Furthermore, the lower electrode layer 41 includes a top surface and sidewalls, and the conversion layer 42 includes a first part and a second part. Among them, the first part of the conversion layer 42 covers the top surface of the lower electrode layer 41, and the second part of the conversion layer 42 can cover a part or all of the sidewalls of the lower electrode layer 41. The upper electrode layer 8 includes a third part and a fourth part. The third part of the upper electrode layer 8 covers the first part of the conversion layer 42, and the fourth part of the upper electrode layer 8 can partially or completely cover the second part of the conversion layer 42. For the sake of understanding, Figure 13 an exemplary structural diagram of the non-volatile two-terminal memory cell of some embodiments of the present disclosure is shown. In Figure 13In the non-volatile two-terminal memory cell shown, the second portion of the conversion layer 42 covers a portion of the sidewalls of the lower electrode layer 41, and the fourth portion of the upper electrode layer 8 partially or completely covers the second portion of the conversion layer 42.

[0097] It should be noted that the above structure is only an exemplary structure of the non-volatile two-terminal memory cell. In actual applications, one of the sidewalls of the lower electrode layer 41 and the second portion of the conversion layer 42 can also be completely covered, and the other can be partially covered.

[0098] The above embodiments introduce the case where only one conversion layer is included in the stacked structure. In some other embodiments, the stacked structure can be as Figure 2 and Figure 3 shown, which includes at least two conversion layers arranged at intervals.

[0099] In Figure 2 、 Figure 3 or Figure 4 Based on the non-volatile two-terminal memory cell shown, the conversion layer 42 contacts at least two surfaces of the lower electrode layer 41 including the top surface, and the upper electrode layer 8 contacts at least two surfaces of the conversion layer 42 including the top surface. For ease of understanding, taking the non-volatile two-terminal memory cell shown in Figure 2 as an example, based on this non-volatile two-terminal memory cell, Figure 14 shows an exemplary structural diagram of the non-volatile two-terminal memory cell of some embodiments of the present disclosure. In the non-volatile two-terminal memory cell shown in Figure 14 , one conversion layer 42 is provided on each lower electrode layer 41. These conversion layers 42 are electrically isolated from each other and at least partially cover the sidewalls of the lower electrode layer 41. The top surfaces and at least part of the sidewalls of these conversion layers 42 are covered by an upper electrode layer 8.

[0100] It should be noted that similar to the non-volatile two-terminal memory cell shown in Figure 12 , the sidewalls of the lower electrode layer 41 can also be completely covered by the conversion layer 42, and / or the sidewalls of the conversion layer 42 can also be completely covered by an upper electrode layer 8. Details will not be elaborated here.

[0101] Although Figure 12 、 Figure 13 and Figure 14 In the non-volatile two-terminal memory cell shown, the upper electrode layer 8 is connected to the upper layer metal wire 11 through an upper electrode metal wire 10. However, in actual applications, multiple upper electrode metal wires 10 electrically connected to the upper electrode layer 8 can also be provided. The upper electrode metal wires 10 are arranged in one-to-one correspondence with the lower electrode layer 41 or the conversion layer 42 in the stacked structure 4. At this time, an optional structure of the non-volatile two-terminal memory cell can be as Figure 15 shown, Figure 15An exemplary structural diagram of a non-volatile two-terminal memory cell according to some embodiments of the present disclosure is shown. In Figure 15 In the non-volatile two-terminal memory cell shown, the stacked structure 4 includes a plurality of conversion layers 42. Among them, a part of the conversion layers 42 each cover a lower electrode layer 41 and at least partially cover the sidewalls of the lower electrode layer 41, while another part of the conversion layers 42 can each cover a plurality of lower electrode layers 41 simultaneously and at least partially cover the sidewalls of these lower electrode layers 41. In addition, the shared upper electrode layer 8 also at least partially covers the second part of the conversion layer 42.

[0102] Furthermore, considering the diffusion characteristics of the conductive material of the lower metal wire 2, a diffusion barrier layer 3 can be specifically provided between the lower metal wire 2 and the lower electrode layer 41. The setting method of the diffusion barrier layer 3 can refer to the description in the previous embodiments and will not be elaborated here.

[0103] Even further, considering the diffusion characteristics of the conductive material and the relative width sizes of the lower electrode layer and the lower metal wire, an etching stop layer 6 can be specifically provided in the non-volatile two-terminal memory cell. The setting method of the etching stop layer 6 can refer to the description in the previous embodiments. Figure 16 An exemplary structural diagram of a non-volatile two-terminal memory cell according to some embodiments of the present disclosure is shown. As Figure 16 shown, assuming that the lower metal wire uses a conductive material with easy diffusion characteristics and the width of the lower metal wire is greater than the width of the lower electrode layer, the diffusion barrier layer and the lower electrode layer are stacked in sequence on the top surface of the lower metal wire, and the top surface of the lower metal wire not covered by the diffusion barrier layer is covered by the etching stop layer to avoid the negative impact of metal diffusion on the device performance.

[0104] Based on the non-volatile two-terminal memory cell provided in any of the previous embodiments, some embodiments of the present disclosure further provide a memory having the non-volatile two-terminal memory cell.

[0105] Furthermore, some embodiments of the present disclosure further provide an electronic device having the above memory.

[0106] In order to obtain the non-volatile two-terminal memory cell described above in combination with Figures 1 - 5 the description, some embodiments of the present disclosure provide a preparation method as Figure 17 shown. Figure 17 An exemplary flowchart of a manufacturing method 1700 of a non-volatile two-terminal memory cell according to some embodiments of the present disclosure is shown.

[0107] Referring to Figure 17 , in step S1701, a lower metal wire is prepared;

[0108] In step S1702, one lower electrode layer electrically connected thereto is fabricated on each of the lower metal interconnects.

[0109] In step S1703, a conversion layer is deposited on the lower electrode layer to form a stacked structure.

[0110] In step S1704, an upper electrode layer is deposited on each of the stacked structures.

[0111] In step S1705, upper electrode metal interconnects electrically connected thereto are fabricated on the upper electrode layer.

[0112] In step S1706, upper metal interconnects electrically connected to the upper electrode metal interconnects are fabricated.

[0113] In some embodiments, the number of the lower metal interconnects fabricated in step S1701 is at least two, and the at least two lower metal interconnects are spaced apart. Further, when fabricating the lower metal interconnects, a conductive material may be selected and fabricated to form conductive lower metal interconnects, so as to form an electrical connection with the subsequently fabricated lower electrode layer.

[0114] In some embodiments, the lower electrode layer may also be fabricated using a conductive material in step S1702 to form an electrical connection with the lower metal interconnects.

[0115] Further, the lower electrode layer and the lower metal interconnects may form an electrical connection by direct contact, or the lower electrode layer and the lower metal interconnects may also form an electrical connection indirectly. As an example, when the conductive material used for the lower metal interconnects is one or more of the following materials: tungsten, titanium, titanium nitride, ruthenium, the lower electrode layer and the lower metal interconnects may form an electrical connection by direct contact. At this time, step S1702 may be performed as follows: fabricate a lower electrode layer in direct contact with the lower metal interconnects. As another example, when the conductive material used for the lower metal interconnects is one or more of the following materials: copper, silver, aluminum, the lower electrode layer and the lower metal interconnects may indirectly achieve an electrical connection through a diffusion barrier layer. At this time, step S1702 may be performed as follows: sequentially fabricate a diffusion barrier layer and a lower electrode layer on the lower metal interconnects.

[0116] Further, in some embodiments, the diffusion barrier layer and / or the lower electrode layer may be formed by a deposition process and an etching process. After forming a film structure on the lower metal interconnect by the deposition process, a part of the diffusion barrier layer and / or the lower electrode layer is removed by the etching process, thereby reducing the bottom area of the lower electrode layer and forming a columnar conductive structure. Further still, before removing a part of the diffusion barrier layer and / or the lower electrode layer by the etching process, an etching hard mask layer, such as a silicon oxide layer or a silicon nitride layer, etc., may be deposited on the lower electrode layer, and the etching hard mask layer at a specific position is cured by a photolithography process to protect the lower electrode layer and / or the diffusion barrier layer therebelow. After the etching process is implemented, the protected lower electrode layer and / or the diffusion barrier layer are retained to form a columnar conductive structure.

[0117] It can be understood that when the conductive material used for the lower metal interconnect is one or more of the following materials: tungsten, titanium, titanium nitride, ruthenium, the columnar conductive structure includes the lower electrode that is not removed. When the conductive material used for the lower metal interconnect is one or more of the following materials: copper, silver, aluminum, the columnar conductive structure includes the lower electrode layer and the diffusion barrier layer that are not removed.

[0118] In the embodiments of the present disclosure, the stacked structure includes at least two spaced-apart lower electrode layers and a conversion layer stacked on the lower electrode layer. In actual applications, there are various situations regarding the covering pattern and quantity of the conversion layer with respect to the lower electrode layer: Firstly, as Figure 1 shown, the number of conversion layers is 1, and this conversion layer simultaneously covers each lower electrode layer; Secondly, as Figure 2 shown, the number of conversion layers is at least 2, and one conversion layer corresponding thereto is provided on each lower electrode layer; Thirdly, as Figure 3 shown, the number of conversion layers is at least 2, wherein, a part of the conversion layers may each cover one lower electrode layer, and another part of the conversion layers may each simultaneously cover multiple lower electrode layers; Fourthly, as Figure 4 shown, the number of conversion layers is at least 2, and each conversion layer simultaneously covers multiple lower electrode layers respectively.

[0119] For the first situation described above, the specific implementation process of step S1703 is as follows: Deposit a conversion layer on the lower electrode layer to cover each lower electrode layer.

[0120] For the second to fourth situations described above, the specific implementation process of step S1703 is as follows: Deposit a conversion layer on the lower electrode layer, and then, etch away a part of the conversion layer to retain at least two spaced-apart conversion layers. For the second situation, the conversion layers are arranged in one-to-one correspondence with the lower electrode layers. For the third and fourth situations, at least one conversion layer covers multiple lower electrode layers, where the multiple herein means 2 or more.

[0121] It should be noted that the number of stacked structures formed in step S1703 can be one or more. Whether the number of stacked structures is one or more, only one upper electrode layer is deposited on each stacked structure. Further, in some embodiments, after the upper electrode layer is deposited, part of the upper electrode layer can be removed by an etching process, for example, the upper electrode layer located in the edge region of the device.

[0122] Since the conversion layers belonging to the same stacked structure share one upper electrode layer, for a stacked structure, the area of the formed upper electrode layer is thus provided, providing a larger process window for the preparation of the upper electrode metal connection. In other words, the execution difficulty of step S1705 in the embodiments of the present disclosure will be lower than the preparation step of the upper electrode metal connection in the prior art.

[0123] It should be noted that when performing step S1705, one upper electrode metal connection electrically connected thereto can be prepared on each upper electrode layer, or multiple upper electrode metal connections electrically connected thereto can also be prepared on each upper electrode layer, and the multiple upper electrode metal connections can be arranged in one-to-one correspondence with the lower electrode layer or the conversion layer in the stacked structure.

[0124] In some embodiments, the upper electrode metal connection and the upper layer metal connection can be sequentially formed in two processes with a sequential execution order. In other embodiments, the upper electrode metal connection and the upper layer metal connection can also be formed in the same process, for example, directly forming a complete connection structure including the upper electrode metal connection and the upper layer metal connection through a damascene process.

[0125] According to the embodiments described in combination with the foregoing Figures 9 - 11 The relative size of the lower electrode layer and the lower layer metal connection and the diffusion characteristics of the conductive material used for the lower layer metal connection will affect the stability and reliability of the device performance. To solve this problem, some embodiments of the present disclosure selectively add an etching barrier layer structure in the non-volatile two-terminal memory cell. Based on this, some embodiments of the present disclosure also provide a manufacturing method for a non-volatile two-terminal memory cell. Figure 18 FIG. 1800 shows an exemplary flowchart of a manufacturing method for a non-volatile two-terminal memory cell according to some embodiments of the present disclosure.

[0126] As Figure 18 shown, in step S1801, at least two spaced lower layer metal connections are prepared in the lower layer metal interlayer dielectric layer;

[0127] In step S1802, one lower electrode layer electrically connected thereto is prepared on each lower layer metal connection;

[0128] In step S1803, an etch stop layer is prepared through a deposition process and a photolithography process to cover the top surface of the lower metal interlayer dielectric layer and the top surface of the exposed lower metal interconnect line;

[0129] In step S1804, a conversion layer is deposited on the lower electrode layer to form a stacked structure;

[0130] In step S1805, an upper electrode layer is deposited on each stacked structure;

[0131] In step S1806, an upper electrode metal interconnect line electrically connected thereto is prepared on the upper electrode layer;

[0132] In step S1807, an upper metal interconnect line electrically connected to the upper electrode metal interconnect line is prepared.

[0133] In this embodiment, in step S1801, at least two grooves spaced apart from each other can be prepared in the lower metal interlayer dielectric layer through an etching process, and then the lower metal interconnect lines are formed by depositing a conductive material in the grooves. Further, in order to make the top surface of the lower metal interconnect line flush with the top surface of the lower metal interlayer dielectric layer, after the deposition process is completed, redundant conductive material can be removed through processes such as chemical mechanical polishing (CMP, Chemical Mechanical Polish), and finally at least two lower metal interconnect lines spaced apart from each other are formed.

[0134] When performing step S1803, a preliminary etch stop layer can be formed on the top surface of the lower metal interlayer dielectric layer, the top surface of the lower metal interconnect line, the top surface of the columnar conductive structure, and the side walls of the columnar conductive structure through a deposition process. Then, a photoresist is coated on the preliminary etch stop layer. The photoresist can use an organic spin-on material, for example, spin-on carbon (SOC, Spin-On-Carbon), bottom anti-reflective coating (BARC, Bottom Anti-Reflective Coatings), or top anti-reflective coating (TARC, Top Anti-Reflective Coating), etc. Then, the photoresist in the area around the columnar conductive structure is cured through a developing process, and the uncured photoresist and the part of the etch stop layer covered thereby are removed by combining a re-etching process and a resist stripping process to obtain the final etch stop layer. Further, in order to ensure the anti-diffusion effect of the etch stop layer, in some embodiments, the thickness of the finally obtained etch stop layer is greater than 150 Å.

[0135] It should be noted that, depending on the conductive material used for the lower metal interconnects, the structure of the columnar conductive structure is also different. When the conductive material used for the lower metal interconnects is one or more of the following materials: tungsten, titanium, titanium nitride, ruthenium, the columnar conductive structure includes the unremoved lower electrode. When the conductive material used for the lower metal interconnects is one or more of the following materials: copper, silver, aluminum, the columnar conductive structure includes the unremoved lower electrode layer and the diffusion barrier layer.

[0136] In some embodiments, in order to protect the lower electrode layer in the columnar conductive structure from being damaged during the etch-back process, the etch hard mask layer deposited during the preparation of the columnar conductive structure can be used to protect the lower electrode layer. The etch hard mask layer can be removed synchronously with the cured organic spin-on material during the degluing process or removed separately after the degluing process is completed, and no excessive limitation is imposed here.

[0137] It should be noted that the specific implementation manners of steps S1801, S1802, S1804 to S1807 can refer to the embodiments described above in combination with Figure 17 and will not be elaborated here.

[0138] The manufacturing method of the non-volatile two-terminal memory cell has been introduced above when the lower metal interconnects satisfy one or more of the following conditions: the conductive material of the lower metal interconnects is copper, silver, and / or aluminum and the width of the lower metal interconnects is greater than the width of the lower electrode layer. In other embodiments, if the lower metal interconnects satisfy the following conditions: the conductive material of the lower metal interconnects is tungsten, titanium, titanium nitride, and / or ruthenium, and the width of the lower metal interconnects is less than or equal to the width of the lower electrode layer, the structure of the above-mentioned etch barrier layer can be simplified.

[0139] Based on this, some embodiments of the present disclosure also provide another manufacturing method of a non-volatile two-terminal memory cell, Figure 19 which shows an exemplary flowchart of the manufacturing method 1900 of the non-volatile two-terminal memory cell according to some embodiments of the present disclosure.

[0140] As Figure 19 shown, in step S1901, at least two spaced-apart lower metal interconnects are formed in the lower metal interlayer dielectric layer;

[0141] In step S1902, a lower electrode layer electrically connected thereto is formed on each lower metal interconnect;

[0142] In step S1903, an insulating dielectric layer is deposited to cover the top surface of the lower metal interlayer dielectric layer;

[0143] In step S1904, a conversion layer is deposited on the lower electrode layer to form a stacked structure;

[0144] In step S1905, an upper electrode layer is deposited on each stack structure;

[0145] In step S1906, an upper electrode metal wire electrically connected thereto is fabricated on the upper electrode layer;

[0146] In step S1907, an upper layer metal wire electrically connected to the upper electrode metal wire is fabricated.

[0147] It should be noted that Figure 19 The difference between the manufacturing method of the non-volatile two-terminal memory cell shown and Figure 18 the manufacturing method of the non-volatile two-terminal memory cell shown is that: the structure layers deposited in step S1903 and step S1803 for covering the lower metal interlayer dielectric layer are different, and the execution manners of other steps are the same, which will not be elaborated here.

[0148] It should also be noted that in Figure 18 or Figure 19 In the manufacturing method shown, the space between the etch stop layer and the upper layer metal wire or the space between the lower metal interlayer dielectric layer and the upper layer metal wire can be filled with an insulating dielectric layer to form an insulating region, so as to avoid unnecessary electrical connections between the conductive structure layers and cause problems such as device short circuits. Based on this, in some embodiments, before step S1806 and / or step S1906 is executed, an insulating dielectric layer is deposited above the upper electrode layer, and then, step S1807 and / or step S1907 is executed to form the upper electrode metal wire and the upper layer metal wire in the insulating dielectric layer.

[0149] By executing Figures 17 - 19 any one of the manufacturing methods shown, a relatively large process window can be provided for the preparation process of the upper electrode metal wire in the non-volatile two-terminal memory cell, thereby reducing the preparation difficulty of the upper electrode metal wire, reducing device abnormalities introduced by the preparation process, and further improving the product yield.

[0150] In addition to solving the product yield problem from the aspect of the process window size, some embodiments of the present disclosure also start from the contact area of each structure layer of the RRAM and provide a non-volatile two-terminal memory cell as shown in Figures 6 - 16 To obtain this non-volatile two-terminal memory cell, some embodiments of the present disclosure provide a preparation method as shown in Figure 20 which Figure 20 shows an exemplary flowchart of the manufacturing method 2000 of the non-volatile two-terminal memory cell according to some embodiments of the present disclosure.

[0151] As shown in Figure 20 in step S2001, a lower layer metal wire is fabricated using a conductive material;

[0152] In step S2002, a lower electrode layer is prepared on the lower metal wire.

[0153] In step S2003, a conversion layer is deposited on the lower electrode layer.

[0154] In step S2004, an upper electrode layer is deposited on the conversion layer.

[0155] In combination with the foregoing Figure 17 Similar to step S1701 in the embodiment described above, the conductive material used for the lower metal wire can be one or more of the following materials: tungsten, titanium, titanium nitride, ruthenium, or the conductive material used for the lower metal wire is one or more of the following materials: copper, silver, aluminum.

[0156] In this embodiment, the implementation manner of step S2002 can refer to step S1702 in the embodiment described above in combination with the foregoing. Figure 17 According to the different diffusion characteristics of different conductive materials, when the conductive material used for the lower metal wire is one or more of the following materials: tungsten, titanium, titanium nitride, ruthenium, an electrical connection can be formed between the lower electrode layer and the lower metal wire through direct contact. At this time, step S2002 can be executed as follows: A lower electrode layer in direct contact therewith is prepared on the lower metal wire, and then, part of the lower electrode layer is etched away to form a columnar conductive structure, where the columnar conductive structure includes: the remaining lower electrode layer. As another example, when the conductive material used for the lower metal wire is one or more of the following materials: copper, silver, aluminum, an electrical connection can be indirectly achieved between the lower electrode layer and the lower metal wire through a diffusion barrier layer. At this time, step S2002 can be executed as follows: A diffusion barrier layer and a lower electrode layer are sequentially deposited on the lower metal wire, and then, part of the lower electrode layer and part of the diffusion barrier layer are etched away to form a columnar conductive structure, where the columnar conductive structure includes: the remaining lower electrode layer and the diffusion barrier layer.

[0157] During the process of etching to form the columnar conductive structure, an etching hard mask layer can be used to protect the lower electrode layer and / or the diffusion barrier layer that need to be retained. The specific etching process can refer to the description of step S1702 in the foregoing embodiment, and will not be elaborated here.

[0158] In addition to the conductive material used for the lower metal wire, the relative width between the lower metal wire and the lower electrode layer will also affect the performance of the non-volatile two-terminal memory cell. Considering these two factors, some embodiments of this disclosure provide Figures 9 - 11 the non-volatile two-terminal memory cell as shown.

[0159] In order to fabricate such as Figures 9 - 11The structure of the non-volatile two-terminal storage cell shown. In some embodiments of the present disclosure, when performing step S2001, a lower metal interconnect is fabricated in the lower metal interlayer dielectric layer, wherein the top surface of the lower metal interconnect is flush with the top surface of the lower metal interlayer dielectric layer.

[0160] It should be noted that the specific implementation process of fabricating the lower metal interconnect in the lower metal interlayer dielectric layer can refer to step S1801 of the embodiment described above in conjunction with Figure 18 and will not be elaborated here.

[0161] Furthermore, for conductive materials with different diffusion characteristics and different relative width sizes, in some embodiments of the present disclosure, after step S2002 is completed, different structural layers are selectively deposited to cover the top surface of the lower metal interconnect and / or the lower metal interlayer dielectric layer.

[0162] Refer to step S1803 and step S1903 in the embodiment described above in conjunction with Figure 18 and Figure 19 In some embodiments, when the lower metal interconnect satisfies one or more of the following conditions: the conductive material of the lower metal interconnect is copper, silver, and / or aluminum, and the width of the lower metal interconnect is greater than the width of the lower electrode layer, after step S2002 is completed, an etch stop layer is fabricated through a deposition process and a lithography process to cover the top surface of the lower metal interlayer dielectric layer and the exposed top surface of the lower metal interconnect.

[0163] To ensure the anti-diffusion effect of the etch stop layer, the thickness of the etch stop layer is greater than 150 Å.

[0164] The etch stop layer can be fabricated through a deposition process, spin-coating an organic spin-on material, a re-etch process, and a stripping process. The specific fabrication process can refer to the description of step S1803 in the foregoing embodiments and will not be elaborated here.

[0165] In other embodiments, when the lower metal interconnect satisfies the following conditions: the conductive material of the lower metal interconnect is tungsten, titanium, titanium nitride, and / or ruthenium, and the width of the lower metal interconnect is less than or equal to the width of the lower electrode layer, after step S2002 is completed, an insulating dielectric layer is deposited to cover the top surface of the lower metal interlayer dielectric layer.

[0166] In conjunction with Figure 20In the described embodiments, in order to increase the contact area between the conversion layer and the lower electrode layer, the conversion layer obtained after performing step S2003 covers at least two surfaces of the lower electrode layer. Further, step S2003 may be performed as follows: deposit the conversion layer to cover the lower electrode layer, where the lower electrode layer includes a top surface and sidewalls that are interconnected, and then, etch the conversion layer to retain a first portion and a second portion of the conversion layer, where the first portion covers the top surface of the lower electrode layer and the second portion at least partially contacts the sidewalls of the lower electrode layer.

[0167] In the present embodiment, in order to increase the contact area between the conversion layer and the upper electrode layer, the upper electrode layer obtained after performing step S2004 covers at least two surfaces of the conversion layer, and in order to prevent device short - circuiting, the upper electrode layer is isolated from the lower electrode layer. Further, step S2004 may be performed as follows: deposit the upper electrode layer to cover the conversion layer, and then, etch the upper electrode layer to retain a third portion and a fourth portion of the upper electrode layer, where the third portion covers the first portion and the fourth portion at least partially contacts the second portion.

[0168] In some embodiments, the deposition process and the etching process for the conversion layer and the upper electrode layer can be performed layer - by - layer, that is, after performing the deposition process and the etching process on the conversion layer first, then perform the deposition process and the etching process on the upper electrode layer. In other embodiments, the etching process for the conversion layer and the upper electrode layer can be performed synchronously. For example, first deposit the conversion layer on the lower electrode layer, then deposit the upper electrode layer on the conversion layer, and then, perform one etching process to synchronously remove a portion of the conversion layer and the upper electrode layer, such as the conversion layer and the upper electrode layer in the edge region of the device.

[0169] Further, before removing a portion of the diffusion barrier layer and / or the lower electrode layer through the etching process, an etching hard mask layer can also be deposited on the lower electrode layer, and the etching hard mask layer at specific positions can be solidified through a photolithography process to protect the lower electrode layer and / or the diffusion barrier layer below it. After performing the etching process, the protected lower electrode layer and / or diffusion barrier layer are retained to form a columnar conductive structure.

[0170] Even further, in order to protect the lower electrode layer in the columnar conductive structure from being damaged during the back - etching process, when preparing the etching stop layer using the back - etching process, the etching hard mask layer deposited during the preparation of the columnar conductive structure can be used to protect the lower electrode layer.

[0171] In some embodiments, Figure 20 The manufacturing method of the non - volatile two - terminal memory cell shown can be combined with Figures 17 - 19 any one of the methods shown in Figures 12 - 16Any non-volatile two-terminal memory cell, thereby increasing the contact area between the structural layers in the RRAM while expanding the process window of the upper electrode metal wiring, thereby improving the product yield in multiple dimensions.

[0172] Taking Figure 17 the method shown as an example, on the basis of this method, combined with Figure 20 the method shown, a manufacturing method of the following non-volatile two-terminal memory cell can be formed. Figure 21 FIG. 2100 shows an exemplary flowchart of a manufacturing method of a non-volatile two-terminal memory cell according to some embodiments of the present disclosure.

[0173] As Figure 21 shown, in step S2101, a lower metal wiring is prepared.

[0174] In step S2102, a lower electrode layer electrically connected to each lower metal wiring is prepared on each lower metal wiring.

[0175] In step S2103, a conversion layer covering at least two surfaces thereof is deposited on the lower electrode layer to form a stacked structure.

[0176] In step S2104, an upper electrode layer covering at least a part of the sidewall of the conversion layer is deposited on each stacked structure.

[0177] In step S2105, an upper electrode metal wiring electrically connected to the upper electrode layer is prepared on the upper electrode layer.

[0178] In step S2106, an upper metal wiring electrically connected to the upper electrode metal wiring is prepared.

[0179] In this embodiment, the specific implementation manner of step S2101 may refer to step S1701, step S1801, step S1901, or step S2001 in the previous embodiment, and will not be elaborated here.

[0180] In this embodiment, step S2102 may selectively prepare a diffusion barrier layer on the lower metal wiring according to the conductive material used for the lower metal wiring, and then prepare the lower electrode layer on the diffusion barrier layer to complete the indirect connection between the lower metal wiring and the lower electrode layer through the diffusion barrier layer. When the conductive material used for the lower metal wiring meets certain conditions, the lower electrode layer can also directly contact the lower metal wiring and form an electrical connection.

[0181] It should be noted that whether to prepare a diffusion barrier layer in step S2102 may refer to the description of step S1702, step S1802, step S1902, or step S2002 in the previous embodiment, and will not be elaborated here.

[0182] In this embodiment, the first part of the conversion layer prepared in step S2103 covers the top surface of the lower electrode layer, and the second part of the conversion layer also at least partially contacts the sidewall of the lower electrode layer. Further, the conversion layer can first completely cover the lower electrode layer through a deposition process, and then the conversion layer on the top surface of the lower electrode layer and the conversion layer on part or all of the sidewalls of the lower electrode layer are retained through an etching process. Furthermore, through the etching process, the single conversion layer obtained by deposition can also be cut into several spaced-apart conversion layers, and the corresponding relationship between these conversion layers and the lower electrode layer can refer to the embodiments described above in combination with Figures 2 - 4 the embodiments described.

[0183] In this embodiment, the third part of the upper electrode layer prepared in step S2104 covers the first part of the conversion layer, and the fourth part of the upper electrode layer at least partially contacts the second part of the conversion layer. Similar to the conversion layer, the upper electrode layer can first completely cover the lower electrode layer through a deposition process, and then the conversion layer on the top surface of the lower electrode layer and the conversion layer on part or all of the sidewalls of the lower electrode layer are retained through an etching process. It should be noted that when etching the upper electrode layer in this embodiment, it is necessary to maintain the upper electrode layer as a complete and connected structural layer. In other words, for a stacked structure, the single upper electrode layer formed through the deposition process still presents as a single upper electrode layer after the etching process is performed, so that a stacked structure shares one upper electrode layer, achieving the effect of expanding the process window of the upper electrode metal connection.

[0184] To more intuitively illustrate the manufacturing method of the non-volatile two-terminal memory cell, Figure 22 FIGs. show schematic diagrams of the manufacturing process of the non-volatile two-terminal memory cell according to some embodiments of the present disclosure, such as Figure 22As shown, first, a diffusion barrier layer 3, a lower electrode layer 41, and an etch hard mask layer 5 are sequentially deposited on a substrate including a lower metal interconnect 2 and an interlayer dielectric layer 1 of the lower metal layer; then, a part of the etch hard mask layer 5 is cured using a developing process, and several columnar conductive structures corresponding one-to-one to the lower metal interconnects 2 are formed in combination with a photolithography process. Here, the columnar conductive structures include the diffusion barrier layer 3 and the lower electrode layer 41; in order to protect the lower electrode layer 41 from damage, the cured etch hard mask layer 5 can be temporarily retained, and an etch stop layer 6 is directly deposited; in order to etch and remove the unnecessary etch stop layer 6, an organic spin-on material 7 is spin-coated on the etch stop layer 6; the organic spin-on material 7 in a specific area is developed and cured to expose the etch stop layer 6 on the top surface of the lower electrode layer 41 and the etch hard mask layer 5; then, the exposed etch stop layer 6 is removed using a back-etch process; the residual organic spin-on material 7 and the etch hard mask layer 5 are removed through a stripping process, obtaining a columnar conductive structure above the lower metal interconnect 2 and an etch stop layer 6 located around the columnar conductive structure and covering the top surface of the remaining lower metal interconnect 2 and the top surface of the interlayer dielectric layer 1 of the lower metal layer; a conversion layer 42 and an upper electrode layer 8 are sequentially deposited, such that both cover multiple surfaces of the structural layers below them; the conversion layer 42 and the upper electrode layer 8 in the edge region are etched and removed; an insulating dielectric layer 9 is deposited to wrap the upper electrode layer 8 and the conversion layer 42 therein, preventing short circuits between conductive structural layers; finally, upper electrode metal interconnects 10 and upper metal interconnects 11 are formed in the insulating dielectric layer 9 through a preparation method such as a damascene process.

[0185] It should be noted that the above manufacturing process is an exemplary solution provided by this disclosure. In actual applications, the types of structural layers prepared, the preparation sequence of each structural layer, and the processes used can be adjusted and reduced according to actual requirements. For example, if the lower metal interconnect uses a conductive material that is not prone to diffusion, the diffusion barrier layer can be simplified as a structural layer, that is, only the lower electrode layer and the etch hard mask layer need to be sequentially deposited on the substrate. Another example is that if the lower metal interconnect uses a conductive material that is not prone to diffusion and the width of the lower metal interconnect is less than or equal to the width of the lower electrode layer, the etch stop layer can be simplified as a structural layer. After forming the columnar conductive structure, an insulating dielectric layer is deposited to replace the etch stop layer, or after forming the columnar conductive structure, the conversion layer and the upper electrode layer are sequentially deposited, and then the insulating dielectric layer is deposited subsequently.

[0186] In summary, some embodiments of this disclosure provide a non-volatile two-terminal memory cell, which expands the process window of the upper electrode metal interconnect through the design of sharing one upper electrode layer by multiple conversion layers, thereby reducing the preparation difficulty of the upper electrode metal interconnect, reducing the adverse effects on device performance caused by improper process operations, and thus being conducive to improving the yield of the product.

[0187] Some embodiments of the present disclosure also provide a non-volatile two-terminal storage cell, which contacts multiple surfaces of the lower electrode layer through a conversion layer, and the upper electrode layer contacts multiple surfaces of the conversion layer. On the premise of achieving the same contact area, the bottom occupation area of the lower electrode layer is reduced, and more basic storage structures can be integrated on the lower-layer metal wiring with the same area. On the premise of maintaining the original performance level, the storage capacity can be effectively improved, and the problem of increased occupied space of the new memory caused by the increase in the number of storage cells is avoided. Thus, the requirements of miniaturization, storage capacity, and performance are taken into account, and the product yield is further improved.

[0188] Some embodiments of the present disclosure also provide a manufacturing method for manufacturing the above non-volatile two-terminal storage cell to meet the stringent requirements of storage capacity and read / write performance of storage devices for servers, intelligent terminals, and other devices.

[0189] Although multiple embodiments of the present disclosure have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Many variations, changes, and alternative forms may occur to those skilled in the art without departing from the spirit and scope of the present disclosure. It should be understood that various alternative embodiments of the present disclosure described herein may be employed in practicing the present disclosure. The appended claims are intended to define the scope of protection of the present disclosure and thus cover equivalents or alternative forms within the scope of these claims.

[0190] The collection and acquisition of various data in the present disclosure comply with relevant laws and regulations and are authorized by the data providers. Any organization or individual that needs to obtain external data shall obtain authorization according to law and ensure data security, and shall not illegally collect, use, process, or transmit unauthorized or unprotected data, nor illegally buy, sell, provide, or disclose unauthorized or unprotected data.

Claims

1. A non-volatile two-terminal memory cell, characterized in that, Comprising: At least two lower metal interconnects (2) spaced apart; A stacked structure (4) including at least two lower electrode layers (41) spaced apart and a conversion layer (42) stacked on the lower electrode layer (41), wherein the lower electrode layer (41) is provided in one-to-one correspondence with the lower metal interconnect (2) and electrically connected thereto; An upper electrode layer (8) provided in one-to-one correspondence with the stacked structure (4) and covering the stacked structure (4); An upper metal interconnect (11); And An upper electrode metal interconnect (10) provided on the upper electrode layer (8) and electrically connecting the upper electrode layer (8) to the upper metal interconnect (11).

2. The non-volatile two-terminal memory cell according to claim 1, characterized in that, The stacked structure (4) includes: at least two conversion layers (42) spaced apart; Wherein, the conversion layer (42) is provided in one-to-one correspondence with the lower electrode layer (41), or at least one conversion layer (42) covers a plurality of lower electrode layers (41).

3. The non-volatile two-terminal memory cell according to claim 1, wherein The stacked structure (4) includes: a conversion layer (42) that simultaneously covers each lower electrode layer.

4. The non-volatile two-terminal memory cell according to claim 1, characterized in that, The number of the stacked structures (4) is one or more.

5. The non-volatile two-terminal memory cell according to claim 1, wherein The conversion layer (42) covers the top surface of the lower electrode layer (41) and a part of the sidewall connected thereto; The upper electrode layer (8) covers the top surface of the conversion layer (42) and a part of the sidewall connected thereto, and the upper electrode layer (8) is isolated from the lower electrode layer (41).

6. The non-volatile two-terminal memory cell according to claim 5, characterized in that, The conversion layer (42) includes: a first part and a second part, the first part covers the top surface of the lower electrode layer (41), and the second part at least partially contacts the sidewall of the lower electrode layer (41).

7. The non-volatile two-terminal memory cell according to claim 6, wherein, The upper electrode layer (8) includes: a third part and a fourth part, the third part covers the first part, and the fourth part at least partially contacts the second part.

8. The non-volatile two-terminal memory cell according to claim 1, wherein The conductive material used for the lower metal interconnect is one or more of the following materials: copper, silver, aluminum; The non-volatile two-terminal memory cell further includes: a diffusion barrier layer (3), and the diffusion barrier layer (3) and the lower electrode layer (41) are sequentially stacked on the top surface of the lower metal interconnect (2).

9. The non-volatile two-terminal memory cell according to claim 1, wherein The conductive material used for the lower metal interconnect is one or more of the following materials: tungsten, titanium, titanium nitride, ruthenium; The top surface of the lower metal interconnect (2) is in direct contact with the bottom surface of the lower electrode layer (41).

10. The non-volatile two-terminal memory cell according to claim 1, characterized in that, The lower metal interconnect satisfies one or more of the following conditions: the conductive material used for the lower metal interconnect is copper, silver and / or aluminum, and the width of the lower metal interconnect is greater than the width of the lower electrode layer; The non-volatile two-terminal memory cell further includes: an etch stop layer (6) and a lower metal interlayer dielectric layer (1); Wherein, the lower metal interconnect (2) is disposed inside the lower metal interlayer dielectric layer (1), and the top surface of the lower metal interconnect (2) is flush with the top surface of the lower metal interlayer dielectric layer (1), and the etch stop layer (6) covers the top surface of the lower metal interlayer dielectric layer (1) and / or a part of the top surface of the lower metal interconnect (2).

11. The non-volatile two-terminal memory cell according to claim 10, characterized in that, The thickness of the etch stop layer (6) is greater than 150 Å.

12. The non-volatile two-terminal memory cell according to claim 1, wherein The lower metal interconnects satisfy the following conditions: the conductive material of the lower metal interconnects is tungsten, titanium, titanium nitride, and / or ruthenium, and the width of the lower metal interconnects is less than or equal to the width of the lower electrode layer; The non-volatile two-terminal memory cell further includes: an insulating dielectric layer (9) and a lower metal interlayer dielectric layer (1); Wherein, the lower metal interconnects (2) are disposed inside the lower metal interlayer dielectric layer (1), and the top surface of the lower metal interconnects (2) is flush with the top surface of the lower metal interlayer dielectric layer (1), and the bottom surface of the insulating dielectric layer (9) directly contacts and covers the top surface of the lower metal interlayer dielectric layer (1).

13. A manufacturing method of a non-volatile two-terminal storage cell, characterized in that, Including: Fabricating at least two spaced-apart lower metal interconnects; Fabricating a lower electrode layer electrically connected to each lower metal interconnect on each lower metal interconnect; Depositing a conversion layer on the lower electrode layer to form a stacked structure, the stacked structure including at least two spaced-apart lower electrode layers and a conversion layer stacked on the lower electrode layer; Depositing an upper electrode layer on each stacked structure; Fabricating an upper electrode metal interconnect electrically connected to the upper electrode layer on the upper electrode layer; Fabricating an upper metal interconnect electrically connected to the upper electrode metal interconnect.

14. The method according to claim 13, wherein Depositing a conversion layer on the lower electrode layer includes: Depositing a conversion layer on the lower electrode layer; Etching away a part of the conversion layer to retain at least two spaced-apart conversion layers; Wherein, the conversion layers are arranged in one-to-one correspondence with the lower electrode layers, or at least one conversion layer covers a plurality of lower electrode layers.

15. The method according to claim 13, wherein Depositing a conversion layer on the lower electrode layer includes: Depositing a conversion layer on the lower electrode layer to cover each lower electrode layer.

16. The method according to claim 13, wherein Depositing a conversion layer on the lower electrode layer includes: Depositing a conversion layer to cover the top surface of the lower electrode layer and a part of the sidewall connected thereto; Depositing an upper electrode layer to cover the top surface of the lower electrode layer and a part of the sidewall connected thereto, and the upper electrode layer is isolated from the lower electrode layer.

17. The method according to claim 16, wherein Depositing a conversion layer includes: Depositing a conversion layer to cover the lower electrode layer; Etching the conversion layer to retain a first part and a second part of the conversion layer, the first part covering the top surface of the lower electrode layer, and the second part at least partially contacting the sidewall of the lower electrode layer.

18. The method according to claim 17, wherein Depositing an upper electrode layer includes: Depositing an upper electrode layer to cover the conversion layer; Etching the upper electrode layer to retain a third part and a fourth part of the upper electrode layer, the third part covering the first part, and the fourth part at least partially contacting the second part.

19. The method according to claim 13, characterized in that, If the conductive material used for the lower metal interconnects is one or more of the following materials: copper, silver, aluminum, then fabricating a lower electrode layer electrically connected to each lower metal interconnect on each lower metal interconnect includes: Sequentially fabricating a diffusion barrier layer and a lower electrode layer on the lower metal interconnect.

20. The method according to claim 13, wherein If the conductive material used for the lower metal interconnects is one or more of the following materials: tungsten, titanium, titanium nitride, ruthenium, then fabricating a lower electrode layer electrically connected to each lower metal interconnect on each lower metal interconnect includes: Fabricating a lower electrode layer in direct contact with the lower metal interconnect on the lower metal interconnect.

21. The method according to claim 13, characterized in that If the lower metal interconnect satisfies one or more of the following conditions: the conductive material of the lower metal interconnect is copper, silver, and / or aluminum, and the width of the lower metal interconnect is greater than the width of the lower electrode layer, then: Preparing at least two spaced-apart lower metal interconnects includes: preparing at least two spaced-apart lower metal interconnects in a lower metal interlayer dielectric layer, and the top surface of the lower metal interconnect is flush with the top surface of the lower metal interlayer dielectric layer; After preparing one lower electrode layer electrically connected to each lower metal interconnect, the method further includes: preparing an etch stop layer by a deposition process and a lithography process to cover the top surface of the lower metal interlayer dielectric layer and the top surface of the exposed lower metal interconnect.

22. The method according to claim 21, characterized in that The thickness of the etch stop layer is greater than 150 Å.

23. The method according to claim 13, characterized in that, If the lower metal interconnect satisfies the following conditions: the conductive material of the lower metal interconnect is tungsten, titanium, titanium nitride, and / or ruthenium, and the width of the lower metal interconnect is less than or equal to the width of the lower electrode layer, then: Preparing at least two spaced-apart lower metal interconnects includes: preparing at least two spaced-apart lower metal interconnects in a lower metal interlayer dielectric layer, and the top surface of the lower metal interconnect is flush with the top surface of the lower metal interlayer dielectric layer; After preparing one lower electrode layer electrically connected to each lower metal interconnect, the method further includes: depositing an insulating dielectric layer to cover the top surface of the lower metal interlayer dielectric layer.

24. A memory, characterized in that, It has a non-volatile two-terminal memory cell as described in any one of claims 1-12.

25. An electronic device, characterized in that, It has a memory as described in claim 24.

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