Nonvolatile two-end memory cell, manufacturing method thereof, memory and electronic equipment

Abstract

The invention discloses a nonvolatile two-end storage unit, a manufacturing method thereof, a memory and electronic equipment. The nonvolatile two-end storage unit comprises a lower-layer metal connecting wire, a lower electrode layer, a conversion layer and an upper electrode layer which are stacked in sequence, wherein the upper electrode layer and the lower electrode layer are arranged in an isolated manner; the conversion layer contacts at least two surfaces of the lower electrode layer, the surfaces of the lower electrode layer covered by the conversion layer including: a top surface of the lower electrode layer; the upper electrode layer contacts at least two surfaces of the conversion layer, the surfaces of the conversion layer covered by the upper electrode layer including: a top surface of the conversion layer; the lower-layer metal wire comprises a conductive material, and the top surface of the lower-layer metal wire is communicated with the bottom surface of the lower electrode layer. Through the scheme of the embodiment of the invention, the bottom occupied area of the lower electrode layer can be reduced on the premise of realizing the same contact area, and more storage units can be integrated, so that the requirements of miniaturization, storage capacity and performance are considered.

Description

Technical Field

[0001] This disclosure generally relates to the field of semiconductor technology. More specifically, this disclosure relates to a non-volatile two-terminal storage cell, a method for manufacturing a non-volatile two-terminal storage cell, a memory, and an electronic device. Background Art

[0002] In the prior art, new memories are usually arranged between the back-end copper interconnect structures. Among them, the bottom electrode (BE) is connected to the surface of the lower metal wire through the bottom electrode via hole (BE Via), the top electrode (TE) is connected to the interconnect structure through the top electrode via hole (TE Via), and a conversion layer is arranged between the top and bottom electrodes. The storage cells usually adopt a columnar structure and are distributed in an array manner.

[0003] With the rapid development of artificial intelligence technology, especially large language models, the demand for the capacity and performance of memories has further increased. In order to adapt to devices with high computing performance, some existing solutions expand the storage capacity of new memories by increasing the number of storage cells in the new memories, so as to meet the stringent requirements for storage capacity and read / write performance of devices such as servers and intelligent terminals.

[0004] However, with the increase in the number of storage cells, the volume of the new memory also increases, which is not conducive to the application of the new memory in scenarios such as edge computing and the Internet of Things. Such scenarios usually require integrating more functions in a limited space, thus posing certain requirements for the miniaturization and performance of the new memory.

[0005] In view of this, there is an urgent need to provide a non-volatile two-terminal storage cell and related products to improve the integration density of the non-volatile two-terminal storage cell in the new memory and balance the requirements of miniaturization, storage capacity, and performance. Summary of the Invention

[0006] In order to solve at least one or more of the above-mentioned technical problems, this disclosure proposes a non-volatile two-terminal storage solution in multiple aspects.

[0007] In a first aspect, this disclosure provides a non-volatile two-terminal storage cell including: a lower metal wire, a lower electrode layer, a conversion layer, and an upper electrode layer stacked in sequence; wherein, the upper electrode layer and the lower electrode layer are isolated; the conversion layer contacts at least two surfaces of the lower electrode layer, and the surfaces of the lower electrode layer covered by the conversion layer include: the top surface of the lower electrode layer; the upper electrode layer contacts at least two surfaces of the conversion layer, and the surfaces of the conversion layer covered by the upper electrode layer include: the top surface of the conversion layer; the lower metal wire includes a conductive material, and the top surface of the lower metal wire is communicated with the bottom surface of the lower electrode layer.

[0008] In a second aspect, the present disclosure provides a method for manufacturing a non-volatile two-terminal storage cell, including: preparing a lower metal wire using a conductive material; preparing a lower electrode layer on the lower metal wire; depositing a conversion layer on the lower electrode layer, the conversion layer covering at least two surfaces of the lower electrode layer; depositing an upper electrode layer on the conversion layer, the upper electrode layer covering at least two surfaces of the conversion layer and being isolated from the lower electrode layer.

[0009] In a third aspect, the present disclosure provides a memory having the non-volatile two-terminal storage cell as in the first aspect.

[0010] In a fourth aspect, the present disclosure provides an electronic device having the memory as in the third aspect.

[0011] With the non-volatile two-terminal storage cell provided as above, the embodiments of the present disclosure adopt a structural design in which the conversion layer covers multiple surfaces of the lower electrode layer and the upper electrode layer covers multiple surfaces of the conversion layer, increasing the contact area between the lower electrode layer, the conversion layer, and the upper electrode layer. Thus, on the premise of achieving the same contact area, the bottom occupied area of the lower electrode layer in the embodiments of the present disclosure is reduced, and more basic storage structures (i.e., the lower electrode layer, the conversion layer, and the upper electrode layer) can be integrated on the lower metal wire of the same area. On the premise of maintaining the original performance level, the storage capacity can be effectively improved, and the problem of increased occupied space of the new memory caused by the increase in the number of storage cells is avoided, thus taking into account the requirements of miniaturization, storage capacity, and performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] By reading the following detailed description with reference to the accompanying drawings, the above and other objects, features, and advantages of the exemplary embodiments of the present disclosure will become readily understood. In the drawings, several embodiments of the present disclosure are shown in an exemplary rather than restrictive manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0013] Figure 1 An exemplary structural diagram of a non-volatile two-terminal storage cell according to some embodiments of the present disclosure is shown;

[0014] Figure 2 An exemplary structural diagram of a stacked structure according to some embodiments of the present disclosure is shown;

[0015] Figure 3 An exemplary structural diagram of a stacked structure according to some embodiments of the present disclosure is shown;

[0016] Figure 4 An exemplary structural diagram of a stacked structure according to some embodiments of the present disclosure is shown;

[0017] Figure 5 An exemplary structural diagram of a non-volatile two-terminal storage cell according to some embodiments of the present disclosure is shown;

[0018] Figure 6 Shows an exemplary structural diagram of a non-volatile two-terminal storage cell according to some embodiments of the present disclosure;

[0019] Figure 7 Shows an exemplary structural diagram of a non-volatile two-terminal storage cell according to some embodiments of the present disclosure;

[0020] Figure 8 Shows an exemplary structural diagram of a non-volatile two-terminal storage cell according to some embodiments of the present disclosure;

[0021] Figure 9 Shows an exemplary structural diagram of a non-volatile two-terminal storage cell according to some embodiments of the present disclosure

[0022] Figure 10 Shows an exemplary structural diagram of a non-volatile two-terminal storage cell according to some embodiments of the present disclosure;

[0023] Figure 11 Shows an exemplary structural diagram of a non-volatile two-terminal storage cell according to some embodiments of the present disclosure;

[0024] Figure 12 Shows an exemplary structural diagram of a non-volatile two-terminal storage cell according to some embodiments of the present disclosure;

[0025] Figure 13 Shows an exemplary structural diagram of a non-volatile two-terminal storage cell according to some embodiments of the present disclosure;

[0026] Figure 14 Shows an exemplary structural diagram of a non-volatile two-terminal storage cell according to some embodiments of the present disclosure;

[0027] Figure 15 Shows an exemplary structural diagram of a non-volatile two-terminal storage cell according to some embodiments of the present disclosure;

[0028] Figure 16 Shows an exemplary structural diagram of a non-volatile two-terminal storage cell according to some embodiments of the present disclosure;

[0029] Figure 17 Shows an exemplary flowchart of a manufacturing method of a non-volatile two-terminal storage cell according to some embodiments of the present disclosure;

[0030] Figure 18 Shows an exemplary flowchart of a manufacturing method of a non-volatile two-terminal storage cell according to some embodiments of the present disclosure;

[0031] Figure 19 Shows an exemplary flowchart of a manufacturing method of a non-volatile two-terminal storage cell according to some embodiments of the present disclosure;

[0032] Figure 20 An exemplary flowchart showing a method of manufacturing a non-volatile two-terminal memory cell according to some embodiments of the present disclosure;

[0033] Figure 21 An exemplary flowchart showing a method of manufacturing a non-volatile two-terminal memory cell according to some embodiments of the present disclosure;

[0034] Figure 22 A schematic diagram showing the manufacturing process of a non-volatile two-terminal memory cell according to some embodiments of the present disclosure. Detailed Description of Specific Embodiments

[0035] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present disclosure without creative efforts shall fall within the protection scope of the present disclosure.

[0036] It should be understood that the terms "comprising" and "including" as used in the specification and claims of the present disclosure indicate the presence of the described features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their combinations.

[0037] It should also be understood that the terms used in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used in the specification and claims of the present disclosure, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms. It should also be further understood that the term " / and / " as used in the specification and claims of the present disclosure refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0038] As used in this specification and the claims, the term "if" can be interpreted as "when", "once", "in response to determining", or "in response to detecting" depending on the context. Similarly, the phrase "if determined" or "if detected [the described condition or event]" can be interpreted as meaning "once determined", "in response to determining", "once detected [the described condition or event]", or "in response to detecting [the described condition or event]" depending on the context.

[0039] The specific embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0040] Exemplary Application Scenarios

[0041] In order to adapt to the performance requirements of memories for rapidly developing technologies such as artificial intelligence, some existing solutions expand the storage capacity of new memories by increasing the number of storage units in the new memories, so as to meet the stringent requirements of devices such as servers and intelligent terminals for storage capacity and read / write performance.

[0042] However, with the increase in the number of storage units, the volume of the new memory also increases, which is not conducive to the application of the new memory in scenarios such as edge computing and the Internet of Things. Such scenarios usually require integrating more functions in a limited space, thus posing certain requirements for the miniaturization and performance of the new memory.

[0043] Exemplary application solutions

[0044] In view of this, the embodiments of the present disclosure provide a non-volatile two-terminal storage solution, which can balance the storage capacity and performance of storage units through a special stacking design of a lower electrode layer, a conversion layer, and an upper electrode layer.

[0045] For ease of understanding, first, the basic storage structure that performs the storage function in the non-volatile two-terminal storage unit is described. In the non-volatile two-terminal storage unit, the sequentially stacked lower electrode layer, conversion layer, and upper electrode layer constitute the basic storage structure. By applying a voltage between the upper electrode layer and the lower electrode layer, the formation of a conductive filament in the conversion layer can be controlled, so as to realize the switching between a high-resistance state and a low-resistance state, and further achieve the purpose of storing different data. In the non-volatile two-terminal storage unit, the voltage applied between the upper electrode layer and the lower electrode layer comes from an upper metal wire electrically connected to the upper electrode layer and a lower metal wire electrically connected to the lower electrode layer.

[0046] In some embodiments, the electrical connection between the upper electrode layer and the upper metal wire is completed through an upper electrode metal wire. The upper electrode metal wire can be formed through the following processes: first, a via preparation process such as a dual-damascene process, a tungsten plug process, and / or a self-aligned via process is used to form a via connecting the upper electrode layer and the upper metal wire. Then, a metal is filled in the via to form the upper electrode metal wire.

[0047] Due to the wide application of artificial intelligence technology in various industries, higher requirements are put forward for the capacity and performance of memories. Some existing memory solutions choose to increase the number of storage units in a single memory to achieve a high-integration and high-density memory. Since the volume of a single memory is limited, the increase in the number of storage units will inevitably lead to a reduction in the area available for a single storage unit, and further result in a reduction in the process window of the upper electrode layer available for performing the via preparation process, which undoubtedly increases the production difficulty and also has a certain impact on the product yield of the memory.

[0048] In addition, the reduction in the area occupied by a single memory cell will also lead to a reduction in the available space of the basic memory structure in the non-volatile two-terminal memory cell, and the contact areas of the lower electrode layer, the conversion layer, and the upper electrode layer are limited, resulting in a certain impact on the stability of the basic memory structure, and further affecting the stability of the performance of the entire non-volatile two-terminal memory cell, thus having a certain impact on the product yield of the memory.

[0049] In view of the problems caused by the reduction of the process window of the via preparation process, some embodiments of the present disclosure propose a non-volatile two-terminal memory cell, Figure 1 showing an exemplary structural diagram of a non-volatile two-terminal memory cell according to some embodiments of the present disclosure.

[0050] As Figure 1 shown, the non-volatile two-terminal memory cell includes: at least two spaced lower metal interconnects 2, a stacked structure 4, an upper electrode layer 8, an upper metal interconnect 11, and an upper electrode metal interconnect 10.

[0051] Among them, the stacked structure 4 refers to a composite layer structure formed by stacking a lower electrode layer 41 and a conversion layer 42. The stacked structure 4 in the embodiments of the present disclosure has at least two spaced lower electrode layers 41, and these lower electrode layers 41 are arranged in one-to-one correspondence with the lower metal interconnects 2 and are electrically connected. Moreover, different lower electrode layers 41 are electrically isolated from each other to ensure that they can work independently. Further, different lower electrode layers 41 can be electrically isolated by an insulating material. Furthermore, the upper electrode layer 8 and the lower electrode layer 41 can also be electrically isolated by an insulating material to prevent device short circuits.

[0052] The stacked structure in the embodiments of the present disclosure further includes a conversion layer 42 stacked on the lower electrode layer 41. As Figure 1 shown, in some embodiments, the stacked structure 4 may include: a conversion layer 42 that simultaneously covers each lower electrode layer 41. In other words, there is one and only one conversion layer 42 in each stacked structure 4, and this conversion layer 42 simultaneously covers all the lower electrode layers 41 in the current stacked structure 4.

[0053] In other embodiments, the stacked structure 4 may include: at least two spaced conversion layers 42, and the conversion layers 42 are arranged in one-to-one correspondence with the lower electrode layers 41, and one conversion layer 42 is provided on each lower electrode layer 41 and different conversion layers 42 are electrically isolated from each other to ensure that they can work independently. At this time, the stacked structure is as Figure 2 shown, Figure 2 showing an exemplary structural diagram of the stacked structure according to some embodiments of the present disclosure.

[0054] In still other embodiments, the stacked structure 4 may similarly include: at least two conversion layers 42 disposed at intervals, where at least one conversion layer 42 covers a plurality of lower electrode layers 41, for example, 2 or more lower electrode layers. In other words, in this embodiment, there are multiple conversion layers 42 in the stacked structure 4. In one case, a part of the conversion layers 42 may each cover one lower electrode layer 41, while another part of the conversion layers 42 may each cover a plurality of lower electrode layers 41 at the same time. There is no strict limit on the number of the above two parts of conversion layers. At this time, the stacked structure is as Figure 3 shown, Figure 3 which shows an exemplary structural diagram of the stacked structure of some embodiments of the present disclosure. In another case, multiple conversion layers 42 may each cover a plurality of lower electrode layers 41 at the same time. At this time, the stacked structure is as Figure 4 shown, Figure 4 which shows an exemplary structural diagram of the stacked structure of some embodiments of the present disclosure.

[0055] In the embodiments of the present disclosure, the foregoing is combined with Figure 2 , Figure 3 or Figure 4 Any of the stacked structures described is covered with an upper electrode layer, and the upper electrode layer is disposed corresponding to the stacked structure one by one. In other words, for a stacked structure, regardless of whether the number of conversion layers it contains is one or multiple, the conversion layers are all covered by the same upper electrode layer.

[0056] It can be understood that in the embodiments of the present disclosure, for a stacked structure, a plurality of lower electrode layers disposed at intervals may share one conversion layer or use multiple conversion layers. When using multiple conversion layers, some lower electrode layers may share one conversion layer and some lower electrode layers may use separate conversion layers, or all conversion layers may be shared by multiple lower electrode layers. In addition, for a stacked structure, the lower electrode layer and the conversion layer therein share one upper electrode layer. At this time, compared with the non-volatile two-terminal storage unit with a non-shared upper electrode layer, the embodiments of the present disclosure can provide a larger upper electrode layer, thereby providing a larger process window for the preparation of the upper electrode metal connection.

[0057] Based on the process window provided by the upper electrode layer, the embodiments of the present disclosure can form an upper electrode metal connection electrically connected thereto on the upper electrode layer.

[0058] In some embodiments, as Figure 1As shown, since the lower electrode layer 41 and the conversion layer 42 in the stacked structure 4 share an upper electrode layer 8, an upper electrode metal connection line 10 electrically connected thereto can be provided for each upper electrode layer 8, and is electrically connected to the upper layer metal connection line 11 through the upper electrode metal connection line 10. This embodiment allows for metal filling to form the upper electrode metal connection line after preparing a relatively large via hole, with relatively low process precision requirements and high product yield.

[0059] In some other embodiments, Figure 5 An exemplary structural diagram of a non-volatile two-terminal storage cell according to some embodiments of the present disclosure is shown, as Figure 5 shown, multiple upper electrode metal connection lines 10 electrically connected thereto can also be provided on the upper electrode layer 8, and the upper electrode metal connection lines 10 are arranged in one-to-one correspondence with the lower electrode layer 41 or the conversion layer 42 in the stacked structure 4. This embodiment provides a relatively large process window, which is beneficial for performing a via hole preparation process with relatively high precision and reducing the negative impact on process execution caused by an overly small process window.

[0060] It should be noted that the above embodiments are described for one stacked structure in the non-volatile two-terminal storage cell. For a non-volatile two-terminal storage cell, the number of stacked structures it includes is one or more.

[0061] It can be understood that when the number of stacked structures included in the non-volatile two-terminal storage cell is one, all the lower electrode layers and conversion layers in the non-volatile two-terminal storage cell share an upper electrode layer. When the number of stacked structures included in the non-volatile two-terminal storage cell is multiple, all the lower electrode layers in the non-volatile two-terminal storage cell can be divided into several groups, and each group of lower electrode layers shares an upper electrode layer. Further, regardless of whether the number of stacked structures is one or multiple, the lower electrode layers can share a conversion layer, or some of the lower electrode layers share a conversion layer and some of the lower electrode layers are each covered with a corresponding conversion layer, or each lower electrode layer is covered with a corresponding conversion layer alone.

[0062] Regarding the problem caused by the limited contact area of the lower electrode layer, the conversion layer, and the upper electrode layer, some embodiments of the present disclosure also propose a non-volatile two-terminal storage cell, Figure 6 An exemplary structural diagram of a non-volatile two-terminal storage cell according to some embodiments of the present disclosure is shown.

[0063] As Figure 6 shown, the non-volatile two-terminal storage cell includes: a lower layer metal connection line 2, a lower electrode layer 41, a conversion layer 42, and an upper electrode layer 8 stacked in sequence, wherein the upper electrode layer 8 is isolated from the lower electrode layer 41 to prevent device short circuit. Further, in some embodiments, electrical isolation can also be performed between the upper electrode layer 8 and the lower electrode layer 41 through an insulating material.

[0064] In Figure 6 In the non-volatile two-terminal memory cell shown, the conversion layer 42 contacts at least two surfaces of the lower electrode layer 41. Among them, the surface of the lower electrode layer 41 covered by the conversion layer 42 includes: the top surface of the lower electrode layer 41. Further, the lower electrode layer 41 includes: a top surface and a side wall connected to each other, and the conversion layer 42 includes: a first part and a second part. Among them, the first part of the conversion layer 42 covers the top surface of the lower electrode layer 41, and the second part of the conversion layer 42 at least partially contacts the side wall of the lower electrode layer 41.

[0065] It can be understood that the side wall of the lower electrode layer contacted by the second part of the conversion layer described above is one of the at least two surfaces of the lower electrode layer contacted by the conversion layer.

[0066] The lower electrode layer 41 includes a top surface, a bottom surface, and a side wall connecting the two. It should be noted that the lower electrode layer can be in the shape of a square column, a cylinder, or other shapes. The lower electrode layer 41 in the shape of a square column includes four planar side walls, and the lower electrode layer 41 in the shape of a cylinder includes a curved side wall. The number and shape of the side walls of the lower electrode layer are not limited in this embodiment. Among them, the bottom surface of the lower electrode layer 41 is in direct or indirect electrical connection with the lower layer metal connection 2. The top surface of the lower electrode layer 41 is completely covered by the conversion layer 42, and at least part of the side wall of the lower electrode layer 41 is covered by the conversion layer 42. For the RRAM in the prior art solution, the contact area between the lower electrode layer and the conversion layer is only the surface area S1 of the top surface of the lower electrode layer. In the non-volatile two-terminal memory cell shown in this embodiment, the contact area between the lower electrode layer and the conversion layer includes, in addition to the surface area of the top surface of the lower electrode layer, at least part of the surface area of the side wall of the lower electrode layer. In other words, in the non-volatile two-terminal memory cell shown in this embodiment, the contact area S between the lower electrode layer and the conversion layer = S1 + S2, where S1 represents the surface area of the top surface of the lower electrode layer, and S2 represents the surface area of part of the side wall of the lower electrode layer. Compared with the prior art solution with a contact area of S1, a larger contact surface area is formed between the lower electrode layer 41 and the conversion layer 42 in this embodiment.

[0067] Assume that the lower electrode layer 41 is in the shape of a square column and includes four side walls. The second part of the conversion layer 42 can contact one or more of the side walls. Figure 7 An exemplary structural diagram of a non-volatile two-terminal memory cell according to some embodiments of the present disclosure is shown, as Figure 7 shown. When the second part of the conversion layer 42 contacts the four side walls of the lower electrode layer 41, the conversion layer 42 will completely cover the exposed surface of the lower electrode layer 41, and the conversion layer 42 will isolate the lower electrode layer 41 from the upper electrode layer 8.

[0068] It can be understood that the covering state of the conversion layer on the lower electrode layer includes the following two cases: the first is that the second part of the conversion layer contacts a part of the side wall of the lower electrode layer, and the second is that the second part of the conversion layer contacts the entire side wall of the lower electrode layer.

[0069] Similar to the conversion layer 42 and the lower electrode layer 41, the upper electrode layer 8 contacts at least two surfaces of the conversion layer 42. Among them, the surfaces of the conversion layer 42 covered by the upper electrode layer 8 include: the top surface of the conversion layer 42. Further, the upper electrode layer 8 includes: a third part and a fourth part, where the third part of the upper electrode layer 8 covers the first part of the conversion layer 42, and the fourth part of the upper electrode layer 8 at least partially contacts the second part of the conversion layer 42.

[0070] It can be understood that the side wall of the conversion layer contacted by the fourth part of the upper electrode layer is one of the at least two surfaces of the conversion layer contacted by the upper electrode layer.

[0071] The conversion layer 42 also includes a top surface, a bottom surface, and side walls connecting the two. The number and shape of the side walls of the conversion layer 42 are also not limited. Among them, the bottom surface of the conversion layer 42 is in direct contact with the lower electrode layer 41, the top surface of the conversion layer 42 is covered by the upper electrode layer 8, and at least part of the side walls of the conversion layer 42 are covered by the upper electrode layer 8. For the RRAM in the prior art solution, the contact area between the upper electrode layer and the conversion layer is only the surface area S3 of the top surface of the conversion layer. In the non-volatile two-terminal storage unit shown in this embodiment, the contact area between the upper electrode layer and the conversion layer, in addition to the surface area of the top surface of the conversion layer, also includes the surface area of at least part of the side walls of the conversion layer. In other words, in the non-volatile two-terminal storage unit shown in this embodiment, the contact area S' between the upper electrode layer and the conversion layer = S3 + S4, where S3 represents the surface area of the top surface of the conversion layer, and S4 represents the surface area of part of the side walls of the conversion layer. Compared with the prior art solution with a contact area of S3, a larger contact area is formed between the upper electrode layer 8 and the conversion layer 42 in this embodiment.

[0072] By extending the contact surface between the lower electrode layer and the conversion layer from the top surface of the lower electrode layer to the side wall of the lower electrode layer, the longitudinal surface can be effectively utilized, and the contact area between the lower electrode layer and the conversion layer can be increased without increasing the lateral occupied area of the lower electrode layer. Similarly, by extending the contact surface between the upper electrode layer and the conversion layer from the top surface of the conversion layer to the side wall of the conversion layer, the contact area between the upper electrode layer and the conversion layer can be increased without increasing the lateral occupied area of the conversion layer, thereby increasing the contact area between adjacent structural layers in the RRAM as a whole to provide a larger area for the formation of the conductive filament.

[0073] Assume that the conversion layer 42 is in the shape of a square column and includes four side walls. The fourth part of the upper electrode layer 8 can contact one or more of the side walls of the conversion layer 42. AsFigure 7 As shown, when the fourth part of the upper electrode layer 8 contacts the four sidewalls of the switching layer 42, the upper electrode layer 8 completely covers the exposed surface of the switching layer 42. In other words, the upper electrode layer 8 and the lower electrode layer 41 completely enclose the switching layer 42 within them.

[0074] It can be understood that the covering state of the upper electrode layer on the switching layer also includes the following two cases: one is that the fourth part of the upper electrode layer contacts part of the sidewalls of the switching layer, and the other is that the second part of the upper electrode layer contacts all the sidewalls of the switching layer.

[0075] It should be noted that when the fourth part of the upper electrode layer contacts part of the sidewalls of the switching layer, the covering state of the switching layer on the lower electrode layer can be the first covering state described in the previous embodiments or the second covering state described in the previous embodiments. Similarly, when the second part of the electrode layer contacts all the sidewalls of the switching layer, the covering state of the switching layer on the lower electrode layer can be the first covering state described in the previous embodiments or the second covering state described in the previous embodiments.

[0076] Since the switching layer not only covers the top surface of the lower electrode layer but also at least part of the sidewalls of the lower electrode layer, with the lower electrode layer maintaining its original bottom area, the contact area between the switching layer and the lower electrode layer is increased. And when maintaining the original contact area, the bottom area of the lower electrode layer can be reduced. Similarly, the contact area between the upper electrode layer and the switching layer is also increased, which is beneficial to integrating more memory cells in a limited space while taking into account the reliability of device performance, achieving higher storage density and storage capacity.

[0077] In the above non-volatile two-terminal memory cell, the lower metal wire 2 includes a conductive material, so that the driving voltage applied to the lower metal wire 2 can be transmitted to the lower electrode layer 41, and in combination with the driving voltage received by the upper electrode layer 8, the formation of conductive filaments in the switching layer 42 is controlled.

[0078] According to the diffusion characteristics of the conductive material, the conductive material can be divided into a first type of conductive material that is easily diffusible and a second type of conductive material that is not easily diffusible.

[0079] In some embodiments, for the first type of conductive material that is easily diffusible, for example, one or more of the following materials: copper, silver, aluminum, the non-volatile two-terminal memory cell further includes: a diffusion barrier layer 3. Figure 8 Shows an exemplary structural diagram of a non-volatile two-terminal memory cell according to some embodiments of the present disclosure, as Figure 8As shown, the diffusion barrier layer 3 and the lower electrode layer 41 are stacked in sequence on the top surface of the lower metal interconnect 2, which is used to prevent the diffusion of the conductive material in the lower metal interconnect 2, avoid problems such as the deterioration of the interface quality between the lower metal interconnect 2 and the lower electrode layer 41 and the accelerated aging of the device, and ensure that the formation process of the conductive filaments in the conversion layer 42 is not affected.

[0080] In some other embodiments, for the second type of conductive material that is not prone to diffusion, for example, one or more of the following materials: tungsten, titanium, titanium nitride, ruthenium, the top surface of the lower metal interconnect 2 in the non-volatile two-terminal memory cell is as Figure 7 shown, which is in direct contact with the bottom surface of the lower electrode layer 41.

[0081] It should be noted that in practical applications, even if the conductive material has the property of not being prone to diffusion, a diffusion barrier layer can be directly provided between the lower metal interconnect 2 and the lower electrode layer 41 to ensure that the device performance is not affected.

[0082] It should also be noted that in the embodiments described in combination with Figures 1 to 5 it can also be determined whether to provide the diffusion barrier layer 3 according to the diffusion characteristics of the conductive material used in the lower metal interconnect 2, or, regardless of which conductive material is used in the lower metal interconnect 2, a diffusion barrier layer 3 is provided between the lower metal interconnect 2 and the lower electrode layer 41 to prevent the negative impact caused by metal diffusion.

[0083] The above embodiments describe the structural design made for the problem that the conductive material in the lower metal interconnect diffuses to the lower electrode layer. In practical applications, the conductive material in the lower metal interconnect may also diffuse to other structural layers, for example, the logic unit or other dielectric layers in the device. Considering this problem, some embodiments of the present disclosure also design the structure of the non-volatile two-terminal memory cell based on the relative sizes of the lower electrode layer and the lower metal interconnect and the diffusion characteristics of the conductive material used in the lower metal interconnect.

[0084] If the lower metal interconnect satisfies one or more of the following conditions: the conductive material of the lower metal interconnect is copper, silver, and / or aluminum and the width of the lower metal interconnect is greater than the width of the lower electrode layer, there is a possibility that the conductive material in the lower metal interconnect diffuses to other structural layers, thereby affecting the device performance. In response to this situation, some embodiments of the present disclosure provide a non-volatile two-terminal memory cell, Figure 9 shows an exemplary structural diagram of the non-volatile two-terminal memory cell of some embodiments of the present disclosure, as Figure 9As shown, the non-volatile two-terminal memory cell further includes an etch stop layer 6 and an interlayer dielectric layer 1 of the lower metal layer. Among them, the lower metal interconnect 2 is disposed inside the interlayer dielectric layer 1 of the lower metal layer, and the top surface of the lower metal interconnect 2 is flush with the top surface of the interlayer dielectric layer 1 of the lower metal layer. The etch stop layer 6 covers the top surface of the interlayer dielectric layer 1 of the lower metal layer and / or a part of the top surface of the lower metal interconnect 2.

[0085] As an example, if the conductive material of the lower metal interconnect 2 is copper, silver, and / or aluminum, it indicates that the conductive material in the lower metal interconnect 2 is prone to diffusion. At this time, the lower electrode layer 41 is electrically connected to the lower metal interconnect 2 through the diffusion barrier layer 3. Assume that the width of the lower metal interconnect 2 is less than or equal to the width of the lower electrode layer 41. As Figure 9 shown, at this time, the conductive material is prone to diffuse into the logic region of the device, affecting the operation of the logic components in the logic region. By providing the etch stop layer 6, this problem can be effectively avoided.

[0086] As another example, Figure 10 shows an exemplary structural diagram of a non-volatile two-terminal memory cell according to some embodiments of the present disclosure. As Figure 10 shown, assume that the conductive material of the lower metal interconnect is copper, silver, and / or aluminum. At this time, the lower electrode layer 41 is electrically connected to the lower metal interconnect 2 through the diffusion barrier layer 3. Moreover, the width of the lower metal interconnect 2 is greater than the width of the lower electrode layer 41. Then, the conductive material is not only prone to diffuse into the logic region of the device but also may diffuse into the structural layer around the lower electrode layer 41. By providing the etch stop layer 6, this problem can also be effectively avoided.

[0087] As yet another example, Figure 11 shows an exemplary structural diagram of a non-volatile two-terminal memory cell according to some embodiments of the present disclosure. As Figure 11 shown, assume that the width of the lower metal interconnect 2 is greater than the width of the lower electrode layer 41, and the conductive material of the lower metal interconnect 2 is not prone to diffusion. Then, the lower electrode layer 41 can be in direct contact with the lower metal interconnect 2. At this time, the lower metal interconnect 2 not covered by the lower electrode layer 41 is prone to form a conductive path with the conversion layer 42 and the upper electrode layer 8, thus affecting the formation of the conductive path of the lower electrode layer - conversion layer - upper electrode layer. By providing the etch stop layer 6, the formation of the conductive path of the lower metal interconnect - conversion layer - upper electrode layer can be effectively restricted.

[0088] Furthermore, in some embodiments, the thickness of the etch stop layer 6 is greater than 150 Å to ensure that it has sufficient anti-diffusion ability.

[0089] In contrast to the above situation, if the following conditions are met for the lower metal interconnect: the conductive material of the lower metal interconnect is tungsten, titanium, titanium nitride, and / or ruthenium and the width of the lower metal interconnect is less than or equal to the width of the lower electrode layer, it can be considered that the possibility of the conductive material in the lower metal interconnect 2 diffusing into other structural layers and affecting the device performance is relatively small, and thus the etching stop layer 6 can be simplified. At this time, the non-volatile two-terminal memory cell includes: an insulating dielectric layer 9 and a lower metal interlayer dielectric layer 1. The lower metal interconnect 2 is disposed inside the lower metal interlayer dielectric layer 1, and the top surface of the lower metal interconnect 2 is flush with the top surface of the lower metal interlayer dielectric layer 1. The bottom surface of the insulating dielectric layer 9 directly contacts and covers the top surface of the lower metal interlayer dielectric layer 1.

[0090] Since the conductive material of the lower metal interconnect 2 is a material that is not easily diffusible such as tungsten, titanium, titanium nitride, and / or ruthenium, in this non-volatile two-terminal memory cell, the lower electrode layer 41 directly contacts the lower metal interconnect 2.

[0091] It should be noted that if the following conditions are met for the lower metal interconnect: the conductive material of the lower metal interconnect is tungsten, titanium, titanium nitride, and / or ruthenium and the width of the lower metal interconnect is less than or equal to the width of the lower electrode layer, both the etching stop layer 6 and the diffusion barrier layer 3 are optional structural layers. In other words, if the following conditions are met for the lower metal interconnect: the conductive material of the lower metal interconnect is tungsten, titanium, titanium nitride, and / or ruthenium and the width of the lower metal interconnect is less than or equal to the width of the lower electrode layer, an etching stop layer can be provided on the top surface of the insulating dielectric layer 9 and / or the lower metal interlayer dielectric layer 1, or it can be not provided, and there is no excessive limitation here. In addition, if the following conditions are met for the lower metal interconnect: the conductive material of the lower metal interconnect is tungsten, titanium, titanium nitride, and / or ruthenium and the width of the lower metal interconnect is less than or equal to the width of the lower electrode layer, a diffusion barrier layer can be provided between the lower electrode layer and the lower metal interconnect, or it can be not provided, and there is also no excessive limitation here.

[0092] It should be noted that in the embodiments described in combination with Figures 1 to 5 it is also possible to determine whether to provide an etching stop layer based on the diffusion characteristics of the conductive material and the relative widths of the lower electrode layer and the lower metal interconnect. Or, regardless of which conductive material the lower metal interconnect uses, an etching stop layer is provided between the lower metal interconnect and the lower electrode layer to prevent the negative impacts caused by metal diffusion.

[0093] It should also be noted that in the non-volatile two-terminal memory cell provided with the etching stop layer 6, the etching stop layer 6 and the upper metal interconnect 11 can also be filled with the insulating dielectric layer 9 to form an insulating region to avoid unnecessary electrical connections between conductive structural layers and cause problems such as device short circuits.

[0094] Furthermore, the structural design for addressing the problem of an overly small process window and the structural design for addressing the problem of limited contact area can be combined to improve the product yield during the production process from multiple dimensions. In other words, multiple structures of the non-volatile two-terminal memory cells shown in the foregoing embodiments can be selectively combined according to actual circumstances to form a new structure of the non-volatile two-terminal memory cells.

[0095] Taking Figure 1 the non-volatile two-terminal memory cell shown as an example, the conversion layer therein can contact at least two surfaces of the lower electrode layer, one of which is the top surface of the lower electrode layer. For ease of understanding, Figure 12 FIG. shows an exemplary structural diagram of the non-volatile two-terminal memory cell according to some embodiments of the present disclosure. As Figure 12 shown, a conversion layer 42 simultaneously covers the top surfaces and sidewalls of a plurality of lower electrode layers 41 in the stacked structure 4, thereby increasing the contact area between the lower electrode layer 41 and the conversion layer 42. An upper electrode layer 8 simultaneously covers the top surface and sidewalls of the conversion layer 42, thereby increasing the contact area between the upper electrode layer 8 and the conversion layer 42, and expanding the process window of the upper electrode metal connection 10 corresponding to the stacked structure 4.

[0096] Furthermore, the lower electrode layer 41 includes a top surface and sidewalls, and the conversion layer 42 includes a first part and a second part. Among them, the first part of the conversion layer 42 covers the top surface of the lower electrode layer 41, and the second part of the conversion layer 42 can cover part or all of the sidewalls of the lower electrode layer 41. The upper electrode layer 8 includes a third part and a fourth part. The third part of the upper electrode layer 8 covers the first part of the conversion layer 42, and the fourth part of the upper electrode layer 8 can partially or completely cover the second part of the conversion layer 42. For ease of understanding, Figure 13 FIG. shows an exemplary structural diagram of the non-volatile two-terminal memory cell according to some embodiments of the present disclosure. In the Figure 13 non-volatile two-terminal memory cell shown, the second part of the conversion layer 42 covers part of the sidewalls of the lower electrode layer 41, and the fourth part of the upper electrode layer 8 partially or completely covers the second part of the conversion layer 42.

[0097] It should be noted that the above structure is only an exemplary structure of the non-volatile two-terminal memory cell. In actual applications, one of the sidewalls of the lower electrode layer 41 and the second part of the conversion layer 42 can also be completely covered, and the other can be partially covered.

[0098] The above embodiments introduce the case where only one conversion layer is included in the stacked structure. In some other embodiments, the stacked structure can be as Figure 2 and Figure 3 shown, which includes at least two conversion layers arranged at intervals.

[0099] On the basis of the non-volatile two-terminal memory cell shown in Figure 2 , Figure 3 or Figure 4 , the conversion layer 42 contacts at least two surfaces including the top surface in the lower electrode layer 41, and the upper electrode layer 8 contacts at least two surfaces including the top surface in the conversion layer 42. For the sake of easy understanding, taking the non-volatile two-terminal memory cell shown in Figure 2 as an example, based on this non-volatile two-terminal memory cell, Figure 14 shows an exemplary structural diagram of the non-volatile two-terminal memory cell according to some embodiments of the present disclosure. In the non-volatile two-terminal memory cell shown in Figure 14 , one conversion layer 42 is provided on each lower electrode layer 41. These conversion layers 42 are electrically isolated from each other and at least partially cover the side walls of the lower electrode layer 41. The top surfaces and at least part of the side walls of these conversion layers 42 are covered by an upper electrode layer 8.

[0100] It should be noted that, similar to the non-volatile two-terminal memory cell shown in Figure 12 , the side walls of the lower electrode layer 41 can also be completely covered by the conversion layer 42, and / or the side walls of the conversion layer 42 can also be completely covered by an upper electrode layer 8, which will not be elaborated here.

[0101] Although Figure 12 , Figure 13 and Figure 14 the upper electrode layer 8 in the non-volatile two-terminal memory cell shown is connected to the upper layer metal wire 11 through an upper electrode metal wire 10, in actual application, a plurality of upper electrode metal wires 10 electrically connected thereto can also be provided on the upper electrode layer 8. The upper electrode metal wires 10 are arranged in one-to-one correspondence with the lower electrode layer 41 or the conversion layer 42 in the stacked structure 4. At this time, an optional structure of the non-volatile two-terminal memory cell can be as shown in Figure 15 , Figure 15 shows an exemplary structural diagram of the non-volatile two-terminal memory cell according to some embodiments of the present disclosure. In the non-volatile two-terminal memory cell shown in Figure 15 , the stacked structure 4 includes a plurality of conversion layers 42. Among them, a part of the conversion layers 42 each cover one lower electrode layer 41 and at least partially cover the side walls of this lower electrode layer 41, while another part of the conversion layers 42 can each cover a plurality of lower electrode layers 41 at the same time and at least partially cover the side walls of these lower electrode layers 41. In addition, the shared upper electrode layer 8 also at least partially covers the second part of the conversion layer 42.

[0102] Furthermore, considering the diffusion characteristics of the conductive material of the lower layer metal wire 2, a diffusion barrier layer 3 can be specifically provided between the lower layer metal wire 2 and the lower electrode layer 41. The setting method of the diffusion barrier layer 3 can refer to the description in the previous embodiments and will not be elaborated here.

[0103] Further, considering the diffusion characteristics of the conductive material and the relative widths of the lower electrode layer and the lower metal wiring layer, an etching barrier layer 6 can be specifically provided in the non-volatile two-terminal memory cell, and the setting manner of the etching barrier layer 6 can be referred to the description in the foregoing embodiments. Figure 16 FIG. shows an exemplary structural diagram of a non-volatile two-terminal memory cell according to some embodiments of the present disclosure, as Figure 16 shown. Assuming that the lower metal wiring layer uses a conductive material with easy diffusion characteristics and the width of the lower metal wiring layer is greater than that of the lower electrode layer, the diffusion barrier layer and the lower electrode layer are stacked in sequence on the top surface of the lower metal wiring layer, and the top surface of the lower metal wiring layer not covered by the diffusion barrier layer is covered by the etching barrier layer to avoid the negative impact of metal diffusion on the device performance.

[0104] Based on the non-volatile two-terminal memory cell provided in any of the foregoing embodiments, some embodiments of the present disclosure further provide a memory having the non-volatile two-terminal memory cell.

[0105] Furthermore, some embodiments of the present disclosure further provide an electronic device having the above-mentioned memory.

[0106] To obtain the non-volatile two-terminal memory cell described above in connection with Figures 1 - 5 the description, some embodiments of the present disclosure provide a preparation method as Figure 17 shown, Figure 17 FIG. shows an exemplary flowchart of a manufacturing method 1700 of a non-volatile two-terminal memory cell according to some embodiments of the present disclosure.

[0107] Referring to Figure 17 , in step S1701, a lower metal wiring layer is prepared;

[0108] In step S1702, a lower electrode layer electrically connected thereto is prepared on each lower metal wiring layer;

[0109] In step S1703, a conversion layer is deposited on the lower electrode layer to form a stacked structure;

[0110] In step S1704, an upper electrode layer is deposited on each stacked structure;

[0111] In step S1705, an upper electrode metal wiring layer electrically connected thereto is prepared on the upper electrode layer;

[0112] In step S1706, an upper metal wiring layer electrically connected to the upper electrode metal wiring layer is prepared.

[0113] In some embodiments, the number of the lower metal interconnects prepared in step S1701 is at least two, and the at least two lower metal interconnects are spaced apart. Further, when preparing the lower metal interconnects, a conductive material can be selected for preparation to form a conductive lower metal interconnect, so as to form an electrical connection with the lower electrode layer prepared subsequently.

[0114] In some embodiments, step S1702 can also use a conductive material to prepare the lower electrode layer to form an electrical connection with the lower metal interconnect.

[0115] Further, the lower electrode layer and the lower metal interconnect can form an electrical connection through direct contact, or the lower electrode layer and the lower metal interconnect can also form an electrical connection indirectly. As an example, when the conductive material used for the lower metal interconnect is one or more of the following materials: tungsten, titanium, titanium nitride, ruthenium, the lower electrode layer and the lower metal interconnect can form an electrical connection through direct contact. At this time, step S1702 can be performed as follows: prepare the lower electrode layer in direct contact with the lower metal interconnect. As another example, when the conductive material used for the lower metal interconnect is one or more of the following materials: copper, silver, aluminum, the lower electrode layer and the lower metal interconnect can be indirectly electrically connected through a diffusion barrier layer. At this time, step S1702 can be performed as follows: sequentially prepare a diffusion barrier layer and a lower electrode layer on the lower metal interconnect.

[0116] Further, in some embodiments, the diffusion barrier layer and / or the lower electrode layer can be prepared by a deposition process and an etching process. After forming a film structure on the lower metal interconnect by the deposition process, part of the diffusion barrier layer and / or the lower electrode layer is removed by the etching process, so as to reduce the bottom area of the lower electrode layer and form a columnar conductive structure. Further still, before removing part of the diffusion barrier layer and / or the lower electrode layer by the etching process, an etching hard mask layer, such as a silicon oxide layer or a silicon nitride layer, can be deposited on the lower electrode layer, and the etching hard mask layer at a specific position is solidified by a photolithography process to protect the lower electrode layer and / or the diffusion barrier layer below it. After the etching process is performed, the protected lower electrode layer and / or the diffusion barrier layer are retained to form a columnar conductive structure.

[0117] It can be understood that when the conductive material used for the lower metal interconnect is one or more of the following materials: tungsten, titanium, titanium nitride, ruthenium, the columnar conductive structure includes the unremoved lower electrode. When the conductive material used for the lower metal interconnect is one or more of the following materials: copper, silver, aluminum, the columnar conductive structure includes the unremoved lower electrode layer and the diffusion barrier layer.

[0118] In the embodiments of the present disclosure, the stacked structure includes at least two lower electrode layers disposed at intervals and a conversion layer stacked on the lower electrode layer. In practical applications, there are various situations regarding the covering form and quantity of the conversion layer with respect to the lower electrode layer: First, as Figure 1 shown, the number of conversion layers is 1, and this conversion layer simultaneously covers each lower electrode layer; Second, as Figure 2 shown, the number of conversion layers is at least 2, and one conversion layer corresponding to each is provided on each lower electrode layer; Third, as Figure 3 shown, the number of conversion layers is at least 2, where a part of the conversion layers can each cover one lower electrode layer, and another part of the conversion layers can each simultaneously cover multiple lower electrode layers; Fourth, as Figure 4 shown, the number of conversion layers is at least 2, and each conversion layer simultaneously covers multiple lower electrode layers.

[0119] For the first situation described above, the specific execution process of step S1703 is as follows: Deposit a conversion layer on the lower electrode layer to cover each lower electrode layer.

[0120] For the second to fourth situations described above, the specific execution process of step S1703 is as follows: Deposit a conversion layer on the lower electrode layer, and then, etch away part of the conversion layer to retain at least two conversion layers disposed at intervals. For the second situation, the conversion layers are arranged in one-to-one correspondence with the lower electrode layers. For the third and fourth situations, at least one conversion layer covers multiple lower electrode layers, where multiple means 2 or more.

[0121] It should be noted that the number of stacked structures formed in step S1703 can be one or more. Whether the number of stacked structures is one or more, only one upper electrode layer is deposited on each stacked structure. Further, in some embodiments, part of the upper electrode layer can also be removed by an etching process after the upper electrode layer is deposited, for example, the upper electrode layer located in the edge region of the device.

[0122] Since the conversion layers belonging to the same stacked structure share one upper electrode layer, therefore, for one stacked structure, the area of the formed upper electrode layer, thus providing a larger process window for the preparation of the upper electrode metal connection. In other words, the execution difficulty of step S1705 in the embodiments of the present disclosure will be lower than the preparation step of the upper electrode metal connection in the prior art.

[0123] It should be noted that when executing step S1705, one upper electrode metal connection electrically connected thereto can be prepared on each upper electrode layer, or, alternatively, multiple upper electrode metal connections electrically connected thereto can also be prepared on each upper electrode layer, and the multiple upper electrode metal connections can be arranged in one-to-one correspondence with the lower electrode layer or the conversion layer in the stacked structure.

[0124] In some embodiments, the upper electrode metal connection and the upper layer metal connection may be sequentially formed in two processes with a sequential execution order. In other embodiments, the upper electrode metal connection and the upper layer metal connection may also be formed in the same process. For example, a complete connection structure including the upper electrode metal connection and the upper layer metal connection is directly formed by a damascene process.

[0125] According to the embodiments described above in conjunction with Figures 9 - 11 the relative sizes of the lower electrode layer and the lower layer metal connection and the diffusion characteristics of the conductive material used in the lower layer metal connection will affect the stability and reliability of the device performance. To solve this problem, some embodiments of the present disclosure selectively add an etching stop layer structure in the non-volatile two-terminal memory cell. Based on this, some embodiments of the present disclosure also provide a method for manufacturing a non-volatile two-terminal memory cell, Figure 18 FIG. shows an exemplary flowchart of a method 1800 for manufacturing a non-volatile two-terminal memory cell according to some embodiments of the present disclosure.

[0126] As Figure 18 shown, in step S1801, at least two spaced-apart lower layer metal connections are fabricated in the lower layer metal interlayer dielectric layer;

[0127] In step S1802, a lower electrode layer electrically connected to each lower layer metal connection is fabricated on each lower layer metal connection;

[0128] In step S1803, an etching stop layer is fabricated by a deposition process and a lithography process to cover the top surface of the lower layer metal interlayer dielectric layer and the top surface of the exposed lower layer metal connections;

[0129] In step S1804, a conversion layer is deposited on the lower electrode layer to form a stacked structure;

[0130] In step S1805, an upper electrode layer is deposited on each stacked structure;

[0131] In step S1806, an upper electrode metal connection electrically connected to the upper electrode layer is fabricated on the upper electrode layer;

[0132] In step S1807, an upper layer metal connection electrically connected to the upper electrode metal connection is fabricated.

[0133] In this embodiment, in step S1801, at least two grooves spaced apart from each other may be prepared in the lower metal interlayer dielectric layer by an etching process, and then a lower metal interconnect is formed by depositing a conductive material in the grooves. Further, in order to make the top surface of the lower metal interconnect flush with the top surface of the lower metal interlayer dielectric layer, after the deposition process is completed, redundant conductive material may be removed by processes such as chemical mechanical polishing (CMP), and finally at least two lower metal interconnects spaced apart from each other are formed.

[0134] When performing step S1803, a preliminary etch stop layer may be formed on the top surface of the lower metal interlayer dielectric layer, the top surface of the lower metal interconnect, the top surface of the columnar conductive structure, and the sidewalls of the columnar conductive structure by a deposition process. Then, a photoresist is coated on the preliminary etch stop layer. The photoresist may be an organic spin-on material, for example, spin-on carbon (SOC), bottom anti-reflective coating (BARC), or top anti-reflective coating (TARC), etc. Then, the photoresist in the area around the columnar conductive structure is cured by a development process, and the uncured photoresist and the part of the etch stop layer covered thereby are removed by combining an etch-back process and a stripping process to obtain a final etch stop layer. Further, in order to ensure the anti-diffusion effect of the etch stop layer, in some embodiments, the thickness of the finally obtained etch stop layer is greater than 150 Å.

[0135] It should be noted that according to the different conductive materials used for the lower metal interconnects, the structures of the columnar conductive structures are also different. When the conductive material used for the lower metal interconnects is one or more of the following materials: tungsten, titanium, titanium nitride, ruthenium, the columnar conductive structure includes the unremoved lower electrode. When the conductive material used for the lower metal interconnects is one or more of the following materials: copper, silver, aluminum, the columnar conductive structure includes the unremoved lower electrode layer and a diffusion barrier layer.

[0136] In some embodiments, in order to protect the lower electrode layer in the columnar conductive structure from being damaged during the etch-back process, the etch hard mask layer deposited during the preparation of the columnar conductive structure may be used to protect the lower electrode layer. The etch hard mask layer may be removed synchronously with the cured organic spin-on material in the stripping process or removed separately after the stripping process is completed, and no excessive limitation is imposed here.

[0137] It should be noted that the specific implementation manners of step S1801, step S1802, step S1804 to step S1807 may refer to the embodiments described above in conjunction with Figure 17 and will not be elaborated here.

[0138] The manufacturing method of the non-volatile two-terminal memory cell has been described above when the lower metal interconnect meets one or more of the following conditions: the conductive material of the lower metal interconnect is copper, silver, and / or aluminum and the width of the lower metal interconnect is greater than the width of the lower electrode layer. In some other embodiments, if the lower metal interconnect meets the following conditions: the conductive material of the lower metal interconnect is tungsten, titanium, titanium nitride, and / or ruthenium, and the width of the lower metal interconnect is less than or equal to the width of the lower electrode layer, the structure of the above etching stop layer can be simplified.

[0139] Based on this, some embodiments of the present disclosure also provide another manufacturing method of a non-volatile two-terminal memory cell. Figure 19 FIG. shows an exemplary flowchart of a manufacturing method 1900 of a non-volatile two-terminal memory cell according to some embodiments of the present disclosure.

[0140] As Figure 19 shown, in step S1901, at least two spaced-apart lower metal interconnects are formed in the lower metal interlayer dielectric layer;

[0141] In step S1902, a lower electrode layer electrically connected thereto is formed on each lower metal interconnect;

[0142] In step S1903, an insulating dielectric layer is deposited to cover the top surface of the lower metal interlayer dielectric layer;

[0143] In step S1904, a conversion layer is deposited on the lower electrode layer to form a stacked structure;

[0144] In step S1905, an upper electrode layer is deposited on each stacked structure;

[0145] In step S1906, an upper electrode metal interconnect electrically connected thereto is formed on the upper electrode layer;

[0146] In step S1907, an upper metal interconnect electrically connected to the upper electrode metal interconnect is formed.

[0147] It should be noted that Figure 19 the difference between the manufacturing method of the non-volatile two-terminal memory cell shown and Figure 18 the manufacturing method of the non-volatile two-terminal memory cell shown is that the structural layer deposited in step S1903 to cover the lower metal interlayer dielectric layer is different from that in step S1803, and the execution manners of other steps are the same, which will not be elaborated here.

[0148] It should also be noted that in Figure 18 or Figure 19In the manufacturing method shown, the space between the etch stop layer and the upper metal interconnect or the space between the lower inter-metal dielectric layer and the upper metal interconnect can be filled with an insulating dielectric layer to form an insulating region, avoiding unnecessary electrical connections between the conductive structural layers and preventing problems such as device short circuits. Based on this, in some embodiments, before performing step S1806 and / or step S1906, an insulating dielectric layer is deposited above the upper electrode layer, and then step S1807 and / or step S1907 are performed to form the upper electrode metal interconnect and the upper metal interconnect within the insulating dielectric layer.

[0149] By performing Figures 17 - 19 any of the manufacturing methods shown, a relatively large process window can be provided for the preparation process of the upper electrode metal interconnect in the non-volatile two-terminal memory cell, thereby reducing the preparation difficulty of the upper electrode metal interconnect, reducing device anomalies introduced by the preparation process, and improving the product yield.

[0150] In addition to solving the product yield problem from the aspect of the process window size, some embodiments of the present disclosure also start from the aspect of the contact area of each structural layer of the RRAM and provide a non-volatile two-terminal memory cell as Figures 6 - 16 shown. To obtain this non-volatile two-terminal memory cell, some embodiments of the present disclosure provide a preparation method as Figure 20 shown. Figure 20 FIG. shows an exemplary flowchart of the manufacturing method 2000 of the non-volatile two-terminal memory cell according to some embodiments of the present disclosure.

[0151] As Figure 20 shown, in step S2001, a lower metal interconnect is prepared using a conductive material;

[0152] In step S2002, a lower electrode layer is prepared on the lower metal interconnect;

[0153] In step S2003, a conversion layer is deposited on the lower electrode layer;

[0154] In step S2004, an upper electrode layer is deposited on the conversion layer.

[0155] Similar to step S1701 in the embodiment described in combination with the foregoing Figure 17 the conductive material used for the lower metal interconnect can be one or more of the following materials: tungsten, titanium, titanium nitride, ruthenium, or the conductive material used for the lower metal interconnect is one or more of the following materials: copper, silver, aluminum.

[0156] In this embodiment, the execution manner of step S2002 can refer to the foregoing in combination with Figure 17In step S1702 of the described embodiments, according to the different diffusion characteristics of different conductive materials, when the conductive material used for the lower metal wire is one or more of the following materials: tungsten, titanium, titanium nitride, ruthenium, an electrical connection can be formed between the lower electrode layer and the lower metal wire through direct contact. At this time, step S2002 can be performed as follows: Prepare a lower electrode layer in direct contact with the lower metal wire, and then, etch away part of the lower electrode layer to form a columnar conductive structure, where the columnar conductive structure includes: the unetched lower electrode layer. As another example, when the conductive material used for the lower metal wire is one or more of the following materials: copper, silver, aluminum, an electrical connection can be indirectly achieved between the lower electrode layer and the lower metal wire through a diffusion barrier layer. At this time, step S2002 can be performed as follows: Deposit a diffusion barrier layer and a lower electrode layer on the lower metal wire in sequence, and then, etch away part of the lower electrode layer and part of the diffusion barrier layer to form a columnar conductive structure, where the columnar conductive structure includes: the unetched lower electrode layer and the diffusion barrier layer.

[0157] During the process of etching to form the columnar conductive structure, a hard mask layer for etching can be used to protect the lower electrode layer and / or the diffusion barrier layer that need to be retained. For the specific etching process, reference can be made to the description of step S1702 in the previous embodiments, which will not be elaborated here.

[0158] In addition to the conductive material used for the lower metal wire, the relative width between the lower metal wire and the lower electrode layer will also affect the performance of the non-volatile two-terminal memory cell. Considering these two factors, some embodiments of the present disclosure provide a non-volatile two-terminal memory cell as Figures 9 - 11 shown.

[0159] To fabricate the structure of the non-volatile two-terminal memory cell as Figures 9 - 11 shown, in some embodiments of the present disclosure, when performing step S2001, a lower metal wire is fabricated in the lower metal interlayer dielectric layer, where the top surface of the lower metal wire is flush with the top surface of the lower metal interlayer dielectric layer.

[0160] It should be noted that the specific implementation process of fabricating the lower metal wire in the lower metal interlayer dielectric layer can refer to step S1801 of the embodiments described above in combination with Figure 18 which will not be elaborated here.

[0161] Furthermore, for conductive materials with different diffusion characteristics and different relative width sizes, in some embodiments of the present disclosure, after step S2002 is completed, different structural layers are selectively deposited to cover the top surface of the lower metal wire and / or the lower metal interlayer dielectric layer.

[0162] Refer to the previous combination with Figure 18 andFigure 19 In the steps S1803 and S1903 in the described embodiments, in some embodiments, when the lower metal interconnect satisfies one or more of the following conditions: the conductive material of the lower metal interconnect is copper, silver, and / or aluminum, and the width of the lower metal interconnect is greater than the width of the lower electrode layer, after step S2002 is completed, an etch stop layer is prepared by a deposition process and a lithography process to cover the top surface of the lower metal interlayer dielectric layer and the top surface of the exposed lower metal interconnect.

[0163] To ensure the anti-diffusion effect of the etch stop layer, the thickness of the etch stop layer is greater than 150 Å.

[0164] The etch stop layer can be formed by a deposition process, spin-coating an organic spin-on material, a re-etch process, and a stripping process. For the specific preparation process, reference can be made to the description of step S1803 in the previous embodiments, which will not be elaborated here.

[0165] In other embodiments, when the lower metal interconnect satisfies the following conditions: the conductive material of the lower metal interconnect is tungsten, titanium, titanium nitride, and / or ruthenium, and the width of the lower metal interconnect is less than or equal to the width of the lower electrode layer, after step S2002 is completed, an insulating dielectric layer is deposited to cover the top surface of the lower metal interlayer dielectric layer.

[0166] In combination Figure 20 In the described embodiments, to increase the contact area between the conversion layer and the lower electrode layer, the conversion layer obtained after performing step S2003 covers at least two surfaces of the lower electrode layer. Further, step S2003 can be performed as follows: deposit a conversion layer to cover the lower electrode layer, where the lower electrode layer includes a top surface and sidewalls connected to each other, and then, etch the conversion layer to retain a first portion and a second portion of the conversion layer, where the first portion covers the top surface of the lower electrode layer and the second portion at least partially contacts the sidewalls of the lower electrode layer.

[0167] In this embodiment, to increase the contact area between the upper electrode layer and the conversion layer, the upper electrode layer obtained after performing step S2004 covers at least two surfaces of the conversion layer, and to prevent device short-circuiting, the upper electrode layer is isolated from the lower electrode layer. Further, step S2004 can be performed as follows: deposit an upper electrode layer to cover the conversion layer, and then, etch the upper electrode layer to retain a third portion and a fourth portion of the upper electrode layer, where the third portion covers the first portion and the fourth portion at least partially contacts the second portion.

[0168] In some embodiments, the deposition process and the etching process for the conversion layer and the upper electrode layer can be performed in a layered manner. That is, after the deposition process and the etching process are performed on the conversion layer first, the deposition process and the etching process are then performed on the upper electrode layer. In other embodiments, the etching process for the conversion layer and the upper electrode layer can be performed synchronously. For example, the conversion layer is deposited on the lower electrode layer first, and then the upper electrode layer is deposited on the conversion layer. After that, an etching process is performed to synchronously remove a part of the conversion layer and the upper electrode layer, such as the conversion layer and the upper electrode layer in the edge region of the device.

[0169] Further, before removing a part of the diffusion barrier layer and / or the lower electrode layer through the etching process, an etching hard mask layer can also be deposited on the lower electrode layer, and the etching hard mask layer at a specific position is cured through a photolithography process to protect the lower electrode layer and / or the diffusion barrier layer below it. After the etching process is performed, the protected lower electrode layer and / or diffusion barrier layer are retained to form a columnar conductive structure.

[0170] Even further, in order to protect the lower electrode layer in the columnar conductive structure from being damaged during the back-etch process, when preparing the etching stop layer using the back-etch process, the etching hard mask layer deposited during the preparation of the columnar conductive structure can be used to protect the lower electrode layer.

[0171] In some embodiments, Figure 20 the manufacturing method of the non-volatile two-terminal memory cell shown can be combined with Figures 17 - 19 any of the methods shown in Figures 12 - 16 to prepare and form any of the non-volatile two-terminal memory cells shown, so as to increase the contact area between the structural layers in the RRAM while expanding the process window of the upper electrode metal connection, thereby improving the product yield in multiple dimensions.

[0172] Taking Figure 17 the method shown as an example, on the basis of this method, combining Figure 20 the method shown can form the following manufacturing method of the non-volatile two-terminal memory cell. Figure 21 FIG. shows an exemplary flowchart of the manufacturing method 2100 of the non-volatile two-terminal memory cell according to some embodiments of the present disclosure.

[0173] As Figure 21 shown, in step S2101, a lower layer metal connection is prepared;

[0174] In step S2102, a lower electrode layer electrically connected thereto is prepared on each lower layer metal connection;

[0175] In step S2103, a conversion layer covering at least two surfaces thereof is deposited on the lower electrode layer to form a stacked structure;

[0176] In step S2104, an upper electrode layer covering at least the sidewalls of the conversion layer portion is deposited on each stacked structure;

[0177] In step S2105, an upper electrode metal connection line electrically connected thereto is fabricated on the upper electrode layer;

[0178] In step S2106, an upper layer metal connection line electrically connected to the upper electrode metal connection line is fabricated.

[0179] In this embodiment, the specific implementation manner of step S2101 may refer to step S1701, step S1801, step S1901, or step S2001 in the previous embodiments, and will not be elaborated here.

[0180] In this embodiment, in step S2102, a diffusion barrier layer may be selectively fabricated on the lower layer metal connection line first according to the conductive material used for the lower layer metal connection line, and then the lower electrode layer is fabricated on the diffusion barrier layer to complete the indirect connection between the lower layer metal connection line and the lower electrode layer through the diffusion barrier layer. When the conductive material used for the lower layer metal connection line meets certain conditions, the lower electrode layer may also be in direct contact with the lower layer metal connection line to form an electrical connection.

[0181] It should be noted that whether to fabricate a diffusion barrier layer in step S2102 may refer to the descriptions in step S1702, step S1802, step S1902, or step S2002 in the previous embodiments, and will not be elaborated here.

[0182] In this embodiment, the first portion of the conversion layer fabricated in step S2103 covers the top surface of the lower electrode layer, and the second portion of the conversion layer also at least partially contacts the sidewalls of the lower electrode layer. Further, the conversion layer may first completely cover the lower electrode layer through a deposition process, and then the conversion layer on the top surface of the lower electrode layer and the conversion layer on part or all of the sidewalls of the lower electrode layer are retained through an etching process. Further still, through the etching process, the single conversion layer obtained by deposition may also be cut into several spaced-apart conversion layers, and the corresponding relationship between these conversion layers and the lower electrode layer may refer to the embodiments described in combination with the previous Figures 2 - 4 description.

[0183] In this embodiment, the third part of the upper electrode layer prepared in step S2104 covers the first part of the conversion layer, and the fourth part of the upper electrode layer at least partially contacts the second part of the conversion layer. Similarly to the conversion layer, the upper electrode layer can first completely cover the lower electrode layer through a deposition process, and then retain the conversion layer on the top surface of the lower electrode layer and the conversion layer on part or all of the sidewalls of the lower electrode layer through an etching process. It should be noted that when etching the upper electrode layer in this embodiment, it is necessary to maintain the upper electrode layer as a complete and connected structural layer. In other words, for a stacked structure, the single upper electrode layer formed through the deposition process still presents as a single upper electrode layer after the etching process is executed, so that a stacked structure shares a single upper electrode layer, achieving the effect of expanding the process window of the upper electrode metal connection.

[0184] To more intuitively illustrate the manufacturing method of the non-volatile two-terminal memory cell, Figure 22 FIG. shows a schematic diagram of the manufacturing process of the non-volatile two-terminal memory cell according to some embodiments of the present disclosure. As Figure 22 shown, first, a diffusion barrier layer 3, a lower electrode layer 41, and an etching hard mask layer 5 are sequentially deposited on a substrate including a lower metal connection 2 and a lower metal interlayer dielectric layer 1; then, a part of the etching hard mask layer 5 is cured by a development process, and several columnar conductive structures corresponding to the lower metal connections 2 one by one are formed by combining a photolithography process. Here, the columnar conductive structure includes the diffusion barrier layer 3 and the lower electrode layer 41; in order to protect the lower electrode layer 41 from damage, the cured etching hard mask layer 5 can be temporarily retained, and an etching stop layer 6 is directly deposited; in order to etch and remove the unnecessary etching stop layer 6, an organic spin-on material 7 is spin-coated on the etching stop layer 6; the organic spin-on material 7 in a specific area is developed and cured to expose the etching stop layer 6 on the top surface of the lower electrode layer 41 and the etching hard mask layer 5; then, the exposed etching stop layer 6 is removed by a back-etching process; the residual organic spin-on material 7 and the etching hard mask layer 5 are removed by a degluing process, obtaining a columnar conductive structure above the lower metal connection 2 and an etching stop layer 6 located around the columnar conductive structure and covering the top surface of the remaining lower metal connection 2 and the top surface of the lower metal interlayer dielectric layer 1; a conversion layer 42 and an upper electrode layer 8 are sequentially deposited so that both cover multiple surfaces of the structural layer below them; the conversion layer 42 and the upper electrode layer 8 in the edge region are etched and removed; an insulating dielectric layer 9 is deposited to wrap the upper electrode layer 8 and the conversion layer 42 therein to prevent short circuits between the conductive structural layers; finally, upper electrode metal connections 10 and upper metal connections 11 are formed in the insulating dielectric layer 9 through a preparation method such as a damascene process.

[0185] It should be noted that the above manufacturing process is an exemplary solution provided by this disclosure. In actual applications, the type of the prepared structural layer, the preparation sequence of each structural layer, and the adopted process can be adjusted and deleted according to actual requirements. For example, if the lower metal wiring uses a conductive material that is not prone to diffusion, the diffusion barrier layer can be simplified, that is, only the lower electrode layer and the hard mask layer for etching need to be sequentially deposited on the substrate. Another example is that if the lower metal wiring uses a conductive material that is not prone to diffusion and the width of the lower metal wiring is less than or equal to the width of the lower electrode layer, the etching stop layer can be simplified. After forming the columnar conductive structure, an insulating dielectric layer can be deposited to replace the etching stop layer, or after forming the columnar conductive structure, a conversion layer and an upper electrode layer can be sequentially deposited, and then an insulating dielectric layer can be deposited later.

[0186] In summary, some embodiments of this disclosure provide a non-volatile two-terminal memory cell, which expands the process window of the upper electrode metal wiring by designing that multiple conversion layers share one upper electrode layer, thereby reducing the preparation difficulty of the upper electrode metal wiring, reducing the adverse effects on the device performance caused by improper process operations, and thus being conducive to improving the yield of the product.

[0187] Some embodiments of this disclosure also provide a non-volatile two-terminal memory cell, which contacts multiple surfaces of the lower electrode layer through the conversion layer and contacts multiple surfaces of the conversion layer through the upper electrode layer. On the premise of achieving the same contact area, the bottom occupied area of the lower electrode layer is reduced, and more basic memory structures can be integrated on the lower metal wiring with the same area. On the premise of maintaining the original performance level, the storage capacity can be effectively improved, and the problem of increased occupied space of the new memory caused by the increase in the number of memory cells is avoided, thus taking into account the requirements of miniaturization, storage capacity, and performance, and further improving the product yield.

[0188] Some embodiments of this disclosure also provide a manufacturing method for preparing the above non-volatile two-terminal memory cell to manufacture storage devices that meet the stringent requirements of storage capacity and read / write performance for devices such as servers and intelligent terminals.

[0189] Although multiple embodiments of this disclosure have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Many changes, alterations, and alternative ways may occur to those skilled in the art without departing from the spirit and scope of this disclosure. It should be understood that various alternative solutions to the embodiments of this disclosure described herein may be adopted in the practice of this disclosure. The appended claims are intended to define the scope of protection of this disclosure and thus cover equivalents or alternative solutions within the scope of these claims.

[0190] The collection and acquisition of various data in this disclosure comply with relevant laws and regulations and are authorized by the data providers. Any organization or individual that needs to obtain external data shall obtain authorization in accordance with the law and ensure data security, and shall not illegally collect, use, process, or transmit unauthorized or unprotected data, nor illegally buy, sell, provide, or disclose unauthorized or unprotected data.

Claims

1. A non-volatile two-terminal memory cell, characterized in that, Comprising: A lower metal interconnect (2), a lower electrode layer (41), a conversion layer (42), and an upper electrode layer (8) stacked in sequence; wherein, The upper electrode layer (8) is isolated from the lower electrode layer (41); The conversion layer (42) contacts at least two surfaces of the lower electrode layer (41), and the surfaces of the lower electrode layer (41) covered by the conversion layer (42) include: the top surface of the lower electrode layer (41); The upper electrode layer (8) contacts at least two surfaces of the conversion layer (42), and the surfaces of the conversion layer (42) covered by the upper electrode layer (8) include: the top surface of the conversion layer (42); The lower metal interconnect (2) includes a conductive material, and the top surface of the lower metal interconnect (2) is in communication with the bottom surface of the lower electrode layer (41).

2. The non-volatile two-terminal storage unit according to claim 1, wherein The lower electrode layer (41) includes: a top surface and a side wall connected to each other; The conversion layer (42) includes: a first part and a second part, the first part covers the top surface of the lower electrode layer, and the second part at least partially contacts the side wall of the lower electrode layer.

3. The non-volatile two-terminal storage unit according to claim 2, wherein The upper electrode layer (8) includes: a third part and a fourth part, the third part covers the first part, and the fourth part at least partially contacts the second part.

4. The non-volatile two-terminal memory cell according to claim 1, wherein The conductive material is one or more of the following materials: copper, silver, aluminum; The non-volatile two-terminal storage unit further includes: a diffusion barrier layer (3), and the diffusion barrier layer (3) and the lower electrode layer (41) are stacked in sequence on the top surface of the lower metal interconnect (2).

5. The non-volatile two-terminal memory cell according to claim 1, wherein The conductive material is one or more of the following materials: tungsten, titanium, titanium nitride, ruthenium; The top surface of the lower metal interconnect (2) is in direct contact with the bottom surface of the lower electrode layer (41).

6. The non-volatile two-terminal memory cell according to claim 1, wherein The lower metal interconnect satisfies one or more of the following conditions: the conductive material of the lower metal interconnect is copper, silver, and / or aluminum, and the width of the lower metal interconnect is greater than the width of the lower electrode layer; The non-volatile two-terminal storage unit further includes: an etch stop layer (6) and a lower metal interlayer dielectric layer (1); Wherein, the lower metal interconnect (2) is disposed inside the lower metal interlayer dielectric layer (1), and the top surface of the lower metal interconnect (2) is flush with the top surface of the lower metal interlayer dielectric layer (1), and the etch stop layer (6) covers the top surface of the lower metal interlayer dielectric layer (1) and / or a part of the top surface of the lower metal interconnect (2).

7. The non-volatile two-terminal memory cell according to claim 6, wherein The thickness of the etch stop layer (6) is greater than 150 Å.

8. The non-volatile two-terminal memory cell according to claim 1, wherein The lower metal interconnect satisfies the following conditions: the conductive material of the lower metal interconnect is tungsten, titanium, titanium nitride, and / or ruthenium, and the width of the lower metal interconnect is less than or equal to the width of the lower electrode layer; The non-volatile two-terminal storage unit further includes: an insulating dielectric layer (9) and a lower metal interlayer dielectric layer (1); Wherein, the lower metal interconnect (2) is disposed inside the lower metal interlayer dielectric layer (1), and the top surface of the lower metal interconnect (2) is flush with the top surface of the lower metal interlayer dielectric layer (1). The bottom surface of the insulating dielectric layer (9) directly contacts and covers the top surface of the lower metal interlayer dielectric layer (1).

9. A manufacturing method of a non-volatile two-terminal storage cell, characterized in that, Comprising: Preparing a lower metal interconnect using a conductive material; Preparing a lower electrode layer on the lower metal interconnect; Depositing a conversion layer on the lower electrode layer, the conversion layer covering at least two surfaces of the lower electrode layer; Depositing an upper electrode layer on the conversion layer, the upper electrode layer covering at least two surfaces of the conversion layer and being isolated from the lower electrode layer.

10. The method according to claim 9, wherein Depositing a conversion layer on the lower electrode layer includes: Depositing a conversion layer to cover the lower electrode layer, the lower electrode layer including a top surface and sidewalls connected to each other; Etching the conversion layer to retain a first part and a second part of the conversion layer, the first part covering the top surface of the lower electrode layer, and the second part at least partially contacting the sidewalls of the lower electrode layer.

11. The method according to claim 10, wherein Depositing an upper electrode layer on the conversion layer includes: Depositing an upper electrode layer to cover the conversion layer; Etching the upper electrode layer to retain a third part and a fourth part of the upper electrode layer, the third part covering the first part, and the fourth part at least partially contacting the second part.

12. The method according to claim 9, characterized in that, If the conductive material is one or more of the following materials: copper, silver, aluminum, then preparing a lower electrode layer on the lower metal interconnect includes: Sequentially depositing a diffusion barrier layer and a lower electrode layer on the lower metal interconnect; Etching away a part of the lower electrode layer and a part of the diffusion barrier layer to form a columnar conductive structure, the columnar conductive structure including: the unremoved lower electrode layer and diffusion barrier layer.

13. The method according to claim 9, characterized in that, If the conductive material is one or more of the following materials: tungsten, titanium, titanium nitride, ruthenium, then preparing a lower electrode layer on the lower metal interconnect includes: Depositing a lower electrode layer in direct contact with the lower metal interconnect; Etching away a part of the lower electrode layer to form a columnar conductive structure, the columnar conductive structure including: the unremoved lower electrode layer.

14. The method according to claim 9, wherein If the lower metal interconnect satisfies one or more of the following conditions: the conductive material of the lower metal interconnect is copper, silver, and / or aluminum, and the width of the lower metal interconnect is greater than the width of the lower electrode layer, then: Preparing a lower metal interconnect using a conductive material includes: preparing a lower metal interconnect in a lower metal interlayer dielectric layer, the top surface of the lower metal interconnect being flush with the top surface of the lower metal interlayer dielectric layer; After preparing a lower electrode layer on the lower metal interconnect, the method further includes: preparing an etch stop layer by a deposition process and a photolithography process to cover the top surface of the lower metal interlayer dielectric layer and the top surface of the exposed lower metal interconnect.

15. The method according to claim 14, wherein The thickness of the etch stop layer is greater than 150 Å.

16. The method according to claim 11, wherein If the lower metal interconnect satisfies the following conditions: the conductive material of the lower metal interconnect is tungsten, titanium, titanium nitride, and / or ruthenium, and the width of the lower metal interconnect is less than or equal to the width of the lower electrode layer, then: Preparing the lower metal interconnect using the conductive material includes: preparing the lower metal interconnect in the lower metal interlayer dielectric layer, and the top surface of the lower metal interconnect is flush with the top surface of the lower metal interlayer dielectric layer; After preparing the lower electrode layer on the lower metal interconnect, the method further includes: depositing an insulating dielectric layer to cover the top surface of the lower metal interlayer dielectric layer.

17. A memory, characterized in that, It has the non-volatile two-terminal storage cell according to any one of claims 1-8.

18. An electronic device, characterized in that, It has the memory according to claim 17.

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