Semiconductor device and power conversion device

Abstract

The invention provides a semiconductor device with high cutoff tolerance, which can suppress local current electric field concentration and current concentration at a chip terminal part caused by electric field deviation between IGBT units due to shape deviation and impurity deviation during manufacturing. The present invention is characterized by being provided with: an emitter electrode formed on the surface of a semiconductor substrate via an interlayer insulating film; a collector electrode formed on the back surface of the semiconductor substrate; a first semiconductor layer of a first conductivity type, which is in contact with the collector electrode, and which is formed on the back surface of the semiconductor substrate; a second semiconductor layer of a second conductivity type formed on the inner side of the first semiconductor layer; a central region unit disposed along the surface of the semiconductor substrate; and an outer peripheral region unit that is positioned further to the outside than the central region unit in the planar direction of the semiconductor substrate, and that is disposed between the central region unit and a chip termination guard ring region.

Description

[0001] This application is a divisional application of the patent application with the filing date of April 22, 2020, application number 202080061875.6, and invention title "Semiconductor Device and Power Conversion Device". Technical Field

[0002] The present invention relates to the structure of a semiconductor device, and particularly to a technique effective for an insulated gate bipolar transistor (IGBT) applied to a power conversion device. Background Art

[0003] An IGBT module (Insulated Gate Bipolar Transistor: hereinafter simply referred to as IGBT), which is a main component of a power converter such as an inverter, is required to be low-cost and miniaturized. Similarly, power device chips in a power module are also required to be low-cost and miniaturized, and new technologies for achieving a high output current density of an IGBT chip are required.

[0004] If the output current density becomes high, the loss per unit chip area of the power device increases, and the chip temperature rises. Therefore, in an IGBT chip, it is necessary to expand the reverse bias safe operating area (hereinafter also referred to as RBSOA) at the time of turn-off under a high output current. That is, it is necessary that the IGBT is not damaged even at higher currents, voltages, and temperatures, and has sufficient current cut-off tolerance.

[0005] Against this background, as a technique for improving the current cut-off ability, for example, Patent Document 1 proposes a technique of reducing the hole injection of the p-type collector layer in the peripheral guard ring portion of an IGBT chip and suppressing the current concentration in the unit portion that functions as an active region. Thereby, it is possible to suppress the parasitic bipolar transistor operation of the IGBT unit caused by current concentration and improve the current cut-off ability.

[0006] In addition, Patent Document 2 proposes the following structure: by deleting the trench structure in the terminal region of the IGBT chip and making the opening area of the contact hole in the terminal region equal to or smaller than that in the central portion, the avalanche tolerance of the terminal region is higher than that of the IGBT unit. Thereby, it is possible to suppress the electric field concentration in the terminal portion, and even when a high surge voltage is generated, the element is not damaged, and the RBSOA can be improved.

[0007] In addition, Patent Document 3 proposes the following technique: an electric field concentration region formed by a PN junction is provided at the center between the trenches of the IGBT unit, and electron injection based on impact ionization at the time of turn-off is generated evenly between the units, suppressing current concentration and improving the cut-off tolerance.

[0008] Prior Art Documents

[0009] Patent document

[0010] Patent document 1: Japanese Unexamined Patent Application Publication No. 2003-133556

[0011] Patent document 2: Japanese Unexamined Patent Application Publication No. 2011-100877

[0012] Patent document 3: Japanese Unexamined Patent Application Publication No. 2016-012581 Summary of the invention

[0013] Problems to be solved by the invention

[0014] However, in the prior arts of Patent Document 1 and Patent Document 2, when there is an electric field deviation between multiple IGBT units caused by shape deviation and impurity deviation during the manufacturing of the IGBT units, there is a case where current electric field concentration occurs in the unit with a strong electric field, resulting in a decrease in the breakdown withstand voltage.

[0015] In addition, in the prior art of Patent Document 3, hole current from the chip terminal part is concentrated in the chip peripheral unit and the unit at the chip corner, sometimes preventing the improvement of the breakdown withstand voltage.

[0016] Therefore, an object of the present invention is to provide a semiconductor device with a high breakdown withstand voltage that can suppress local current electric field concentration and current concentration at the chip terminal part caused by electric field deviation between IGBT units due to shape deviation and impurity deviation during manufacturing, and a power conversion device using the semiconductor device.

[0017] Means for solving the problems

[0018] To solve the above problems, a semiconductor device according to the present invention includes: an emitter electrode formed on the surface of a semiconductor substrate via an interlayer insulating film; a collector formed on the back surface of the semiconductor substrate; a first semiconductor layer of a first conductivity type, which is in contact with the collector and formed on the back surface of the semiconductor substrate; a second semiconductor layer of a second conductivity type, which is formed closer to the inside than the first semiconductor layer; a central region unit disposed along the surface of the semiconductor substrate; and an outer peripheral region unit, which is located outside the central region unit in the planar direction of the semiconductor substrate and disposed between the central region unit and a chip terminal protection ring region. The central region unit includes: a trench formed between the emitter electrode and the semiconductor substrate; a gate electrode formed inside the trench via a gate insulating film and insulated from the emitter electrode via the interlayer insulating film; a third semiconductor layer of the second conductivity type, which is formed in contact with the gate insulating film and has a higher impurity concentration than the semiconductor substrate; a fourth semiconductor layer of the first conductivity type, which is formed in contact with the semiconductor substrate side of the emitter electrode via an emitter contact portion and has a higher impurity concentration than the first semiconductor layer; a fifth semiconductor layer of the first conductivity type, which is in contact with the gate insulating film and formed on the semiconductor substrate side of the second semiconductor layer and has a lower impurity concentration than the fourth semiconductor layer; a sixth semiconductor layer of the first conductivity type, which is in contact with the surface of the semiconductor substrate side of the fourth semiconductor layer and is formed to protrude from the fifth semiconductor layer toward the semiconductor substrate side and has a lower carrier concentration than the fourth semiconductor layer; and a seventh semiconductor layer of the second conductivity type, which is formed in contact with the collector side surface of the sixth semiconductor layer and has a higher impurity concentration than the semiconductor substrate. The outer peripheral region unit has the trench, the gate electrode, the fourth semiconductor layer, the fifth semiconductor layer, and the sixth semiconductor layer, and the outer peripheral region unit does not have at least one of the third semiconductor layer and the seventh semiconductor layer.

[0019] In addition, the present invention is a power conversion device including: a pair of DC terminals; AC terminals having the same number as the number of phases of an alternating current; a switch bridge arm connected between the pair of DC terminals and connecting in series a parallel circuit of two diodes with opposite polarities of switching elements, and mutual connection points of the parallel circuits constituting power conversion units having the same number as the number of phases of the alternating current connected to different AC terminals, characterized in that the switching element is the semiconductor device described above.

[0020] Advantages of the Invention

[0021] According to the present invention, it is possible to realize a semiconductor device with a high breakdown withstand voltage that can suppress local current and electric field concentration caused by electric field deviation between IGBT cells due to shape deviation and impurity deviation during manufacturing, and a power conversion device using the semiconductor device.

[0022] Thereby, it is possible to achieve a high current density of the IGBT chip, which can contribute to the miniaturization of the power conversion device equipped with the IGBT chip.

[0023] The problems, structures, and effects other than those described above will become clear through the following description of the embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1A It is a top view of the IGBT semiconductor chip according to Embodiment 1 of the present invention.

[0025] Figure 1B It is Figure 1A an enlarged view of the cell terminal region 105 of

[0026] Figure 2 It is Figure 1B a cross-sectional view of the A-A' portion of

[0027] Figure 3 It is a cross-sectional view of an existing IGBT semiconductor chip.

[0028] Figure 4 It is a diagram showing the manufacturing process of the IGBT semiconductor chip according to Embodiment 1 of the present invention.

[0029] Figure 5 It is a diagram showing the turn-off waveform (normal waveform) of the IGBT semiconductor chip.

[0030] Figure 6 It is a schematic diagram showing the internal state during turn-off of an existing IGBT semiconductor chip.

[0031] Figure 7 It is a schematic diagram showing the internal state during turn-off of an existing IGBT semiconductor chip.

[0032] Figure 8 It is a diagram showing the change in the impact ionization coefficient α and the electric field during turn-off of the IGBT semiconductor chip.

[0033] Figure 9 It is a schematic diagram showing the internal state during turn-off of the IGBT semiconductor chip according to Embodiment 1 of the present invention.

[0034] Figure 10 It is a cross-sectional view of the IGBT semiconductor chip according to Embodiment 2 of the present invention.

[0035] Figure 11 It is a cross-sectional view of the IGBT semiconductor chip related to Embodiment 3 of the present invention.

[0036] Figure 12 It is a cross-sectional view of the IGBT semiconductor chip related to Embodiment 4 of the present invention.

[0037] Figure 13 It is a cross-sectional view of the IGBT semiconductor chip related to Embodiment 5 of the present invention.

[0038] Figure 14 It is a top view of the cell terminal region of the IGBT semiconductor chip related to Embodiment 6 of the present invention.

[0039] Figure 15 It is a bird's-eye view of the IGBT semiconductor chip related to Embodiment 6 of the present invention.

[0040] Figure 16 It is a bird's-eye view of the IGBT semiconductor chip related to Embodiment 7 of the present invention.

[0041] Figure 17 It is a bird's-eye view of the IGBT semiconductor chip related to Embodiment 8 of the present invention.

[0042] Figure 18 It is a top view of the cell terminal region of the IGBT semiconductor chip related to Embodiment 9 of the present invention.

[0043] Figure 19 It is a bird's-eye view of the IGBT semiconductor chip related to Embodiment 9 of the present invention.

[0044] Figure 20 It is a circuit block diagram of the power conversion device related to Embodiment 10 of the present invention. Detailed Embodiments

[0045] Hereinafter, the embodiments of the present invention will be described in detail with reference to the drawings. In addition, in each figure, elements with the same reference numerals represent the same components or components having similar functions. Further, p-, p, p+ indicate that the conductivity type of the semiconductor layer is p-type, and the relative impurity concentrations increase in this order. Moreover, n-, n, n+ indicate that the conductivity type of the semiconductor layer is n-type, and the relative impurity concentrations increase in this order.

[0046] Embodiment 1

[0047] Refer to Figures 1A to 9 , the semiconductor device and its manufacturing method according to Embodiment 1 of the present invention will be described. In addition, Figure 3 , Figure 6 , Figure 7This is a diagram showing an existing IGBT semiconductor chip presented as a comparative example for easy understanding of the present invention.

[0048] Figure 1A This is a top view of the IGBT semiconductor chip 101. A cell region 103 where a unit cell having a plurality of IGBTs is arranged is provided at the center of the chip. In addition, a gate electrode PAD 104 for applying the gate voltage of the IGBT is provided. Further, a chip terminal protection ring region 102 is provided on the outer periphery of the IGBT semiconductor chip 101.

[0049] Figure 1B This is an enlarged view of the cell terminal region 105 of the IGBT semiconductor chip 101 and is a schematic diagram showing the surface structure without an emitter electrode. A plurality of unit cells having trench gates 204 arranged periodically are arranged in the cell region 103, and an emitter contact portion 203 is provided at the center portion of the unit cell. A central region cell 201 and a peripheral region cell 202 of the IGBT semiconductor chip 101 are provided on the unit cell. The peripheral region cell 202 is located on the outer side in the planar direction of the IGBT semiconductor chip 101 with respect to the central region cell 201 and is located between the chip terminal protection ring region 102.

[0050] Figure 2 This is Figure 1B a cross-sectional view of the A-A' portion of. The central region cell 201 is formed to include: a trench (the Figure 4Symbol 501), which is formed between the emitter electrode 301 and the semiconductor substrate 308; a gate electrode (trench gate 204), which is formed inside the trench and insulated from the emitter electrode 301 via an insulating layer (interlayer insulating film 302); a gate insulating film 310, which is formed in the trench; a third semiconductor layer (n+ source layer) 303 of the second conductivity type, which is formed to be in contact with the gate insulating film 310 and has a higher impurity concentration than the semiconductor substrate 308; a fourth semiconductor layer (shallow p+ layer) 304 of the first conductivity type, which is formed to be in contact with the surface of the emitter electrode 301 on the semiconductor substrate 308 side via the emitter contact portion 203 and has a higher impurity concentration than the first semiconductor layer (p-type collector layer) 312; a fifth semiconductor layer (p-base layer) 305 of the first conductivity type, which is in contact with the gate insulating film 310 and is formed on the semiconductor substrate 308 side of the second semiconductor layer (n-type buffer layer) 311, and has a lower impurity concentration than the fourth semiconductor layer (shallow p+ layer) 304; a sixth semiconductor layer (deep p+ layer) 306 of the first conductivity type, which is formed to be in contact with the surface of the fourth semiconductor layer (shallow p+ layer) 304 on the semiconductor substrate 308 side and protrudes from the fifth semiconductor layer (p-base layer) 305 toward the semiconductor substrate 308 side, and has a lower carrier concentration than the fourth semiconductor substrate (shallow p+ layer) 304; a seventh semiconductor layer (deep n layer) 307 of the second conductivity type, which is formed to be in contact with the surface of the sixth semiconductor layer (deep p+ layer) 306 on the collector 313 side, and has a higher impurity concentration than the semiconductor substrate 308.

[0051] An outer peripheral region unit 202 outside the central region unit 201 in the planar direction of the IGBT semiconductor chip 101 is formed with: a trench (the following Figure 4A symbol 501) is formed between the emitter electrode 301 and the semiconductor substrate 308; a gate electrode (trench gate 204) is formed inside the trench and insulated from the emitter electrode 301 via an insulating layer (interlayer insulating film 302); a gate insulating film 310 is formed in the trench; a third semiconductor layer of the second conductivity type (n+ source layer) 303 is formed to be in contact with the gate insulating film 310 and has a higher impurity concentration than the semiconductor substrate 308; a fourth semiconductor layer of the first conductivity type (shallow p+ layer) 304 is formed to be in contact with the surface of the semiconductor substrate 308 on the side of the emitter electrode 301 and has a higher impurity concentration than the first semiconductor layer (p-type collector layer) 312; a fifth semiconductor layer of the first conductivity type (p-base layer) 305 is in contact with the gate insulating film 310 and is formed on the side of the semiconductor substrate 308 of the third semiconductor layer (n+ source layer) 303, and has a lower impurity concentration than the fourth semiconductor layer (shallow p+ layer) 304; a sixth semiconductor layer of the first conductivity type (deep p+ layer) 306 is formed to be in contact with the surface of the fourth semiconductor layer (shallow p+ layer) on the side of the semiconductor substrate 308 and protrudes from the fifth semiconductor layer (p-base layer) 305 toward the semiconductor substrate 308, and has a lower carrier concentration than the fourth semiconductor layer (shallow p+ layer) 304.

[0052] Figure 4 is a diagram showing the manufacturing process of the IGBT semiconductor chip 101 of the present embodiment ( Figure 2 ).

[0053] "(a) Trench gate formation"

[0054] First, an n- semiconductor substrate 308 (such as a semiconductor wafer like an Si wafer) is prepared.

[0055] Next, an insulating film (such as SiO2) formed on the n- semiconductor substrate 308 is patterned by photolithography for trench formation.

[0056] Next, using the patterned insulating film as a mask, a trench 501 is formed by anisotropic etching.

[0057] "(b) p-base layer, n+ source layer formation"

[0058] Next, a gate insulating film is formed, a polysilicon film is deposited, and after exposure by photolithography, the trench gate 204 is formed by processing.

[0059] Next, using the photoresist patterned for forming the p-base layer 305 as a mask, p-type impurity ions are implanted and heat treatment is performed, thereby forming the fifth semiconductor layer (p-base layer) 305.

[0060] Next, using the photoresist patterned for forming the n+ source layer 303 as a mask, ion implantation of n-type impurities is performed to form the third semiconductor layer (n+ source layer) 303.

[0061] 《(c) Contact portion formation》

[0062] Next, an interlayer insulating film 302 is deposited on the entire surface of the n- semiconductor substrate 308. Planarization is performed on the interlayer insulating film 302. For planarization, methods such as reflow of a BPSG (Boron-Phosphors Silicate Glass) film, CMP (Chemical Mechanical Polishing), etc. are applied.

[0063] After planarizing the interlayer insulating film 302, contact holes 502 are formed by photolithography and anisotropic etching. At this time, the contact holes 502 penetrate the interlayer insulating film 302 and reach the fifth semiconductor layer (p base layer) 305. Thus, when observing the p base layer 305 in cross-section, a pair of n+ source layers are formed, and a groove portion for contacting the contact metal layer formed in subsequent processes is formed.

[0064] 《(d) Shallow p layer formation, deep p layer formation》

[0065] Next, using the interlayer insulating film 302 as a mask, ion implantation of the shallow p+ layer 304 and the deep p+ layer 306 is performed in sequence to form the fourth semiconductor layer (shallow p+ layer) 304 and the sixth semiconductor layer (deep p+ layer) 306, respectively.

[0066] 《(e) Deep n+ layer formation》

[0067] Next, a resist 503 is coated on the entire surface of the n- semiconductor substrate 308. Through photolithography, the resist 503 is opened only in the central region, and the seventh semiconductor layer (deep n layer) 307 is formed by ion implantation. After removing the resist, heat treatment is performed, thereby forming p+ contacts and n+ source contacts self-aligned with respect to the contact holes 502.

[0068] 《(f) Emitter electrode, back n buffer portion, p collector layer, collector formation》

[0069] Next, the contact holes 502 are filled with a stacked metal film composed of high melting point metals such as Ti, TiN, and W, and planarization is performed by etching or CMP to form a contact metal layer (emitter contact portion 203). Then, a metal layer made of aluminum or the like is deposited, and an emitter electrode 301 and a gate electrode PAD104 (not shown) are formed by photolithography and etching. After that, although not shown, a surface protection film made of polyimide or the like is formed and patterned.

[0070] The above processes are surface-side treatments of the semiconductor substrate 308.

[0071] Next, n-type and p-type impurity ions are implanted into the semiconductor substrate 308 from the back side of the semiconductor substrate 308, and laser annealing is performed, thereby forming a second semiconductor layer (n-type buffer layer) 311 and a first semiconductor layer (p-type collector layer) 312.

[0072] In addition, by appropriately adjusting the acceleration energy during ion implantation, an n-type buffer layer 311 and a p-type collector layer 312 having different depths from the back surface of the semiconductor substrate 308 can be formed. Then, on the back side of the semiconductor substrate 308, a stacked metal layer, such as an Al-Ti-Ni-Au film, is formed by sputtering to form a collector 313.

[0073] The feature of Example 1 is that a pn junction where an electric field easily concentrates is formed in the central region unit 201 in the plane direction of the IGBT semiconductor chip 101 between the sixth semiconductor layer 306 and the seventh semiconductor layer 307, and the unit (outer peripheral region unit 202) outside the central region unit 201 in the plane direction of the IGBT semiconductor chip 101 has a structure without the seventh semiconductor layer 307 compared to the central unit region 201. The effect is that the breakdown withstand during turn-off is improved. The principle is described as follows.

[0074] Figure 5 This is an example of the turn-off waveform of an IGBT semiconductor chip. During the turn-off of the IGBT semiconductor chip, when the gate voltage becomes below the threshold voltage, the active electron injection from the trench gate disappears, so the path of the hole current becomes unstable (easy to move). At this time, due to deviations in the size, shape, etc. of the trench, a portion where the local electric field is slightly stronger is inevitably generated. In such a portion, the electron injection based on impact ionization becomes relatively more, so the hole current begins to concentrate.

[0075] Figure 8 This shows the relationship between the impact ionization coefficient α and the electric field during turn-off of the prior art and the present invention. Impact ionization is very dependent on the electric field. In the case of the prior art shown in Figure 3 there is no Figure 2 the electric field concentration layer pn junction formed by the sixth semiconductor layer (deep p+ layer) 306 and the seventh semiconductor layer (deep n layer) 307 as in the present embodiment shown in

[0076] That is, during turn-off, there are few carriers generated by impact ionization. In such a case, as shown in Figure 6As shown, even when the electric field is slightly locally uneven due to deviations in the size, shape, etc. of the trench, there are differences in impact ionization. Due to current concentration and local heating, a latch that cannot be turned off (off) occurs due to current flowing in the parasitic thyristor (n + source / p-base / n - substrate / p-type collector layer), resulting in thermal damage and a reduction in the breakdown withstand during turn-off.

[0077] The outer peripheral region unit 202 is also supplied with hole current from the chip terminal protection ring region 102, so the current is further concentrated, which is the main reason for reducing the breakdown withstand.

[0078] In Figure 7 the case of the existing IGBT semiconductor chip shown, when an electric field concentration pn junction is formed by the sixth semiconductor layer (deep p+ layer) and the seventh semiconductor layer (deep n layer) in the IGBT unit, the electric field is high during the turn-off period t1 to t2, and the change in the impact ionization coefficient during the period t1 to t2 is small. Therefore, electron injection based on impact ionization is generated equally among the units, and hole current flows equally through the IGBT units, suppressing current concentration. Therefore, the breakdown withstand during turn-off is improved.

[0079] However, the seventh semiconductor layer (deep n layer) is a blocking layer for holes. Therefore, in the unit having the seventh semiconductor layer (deep n layer), it is difficult for the hole current to pass through. The outer peripheral region unit 202 is supplied with hole current from the chip terminal protection ring region 102, so current concentration occurs, which becomes an obstacle to further improving the breakdown withstand.

[0080] Therefore, in the present embodiment, as Figure 9 shown, the central region unit 201 has the following effects: an electric field concentration pn junction is formed by the sixth semiconductor layer (deep p+ layer) and the seventh semiconductor layer (deep n layer), electron injection based on impact ionization is generated equally among the units, the hole current is equalized, and the breakdown withstand can be improved.

[0081] On the other hand, the outer peripheral region unit 202 can efficiently extract the hole current added from the chip terminal protection ring region 102 in the outer peripheral region unit 202 by having a structure without the seventh semiconductor layer (deep n layer). Therefore, it has the effect of being able to suppress current concentration in the outer peripheral region unit 202.

[0082] Thus, an IGBT semiconductor chip with excellent breakdown withstand can be provided.

[0083] Embodiment 2

[0084] Refer to Figure 10 to describe the semiconductor device according to Embodiment 2 of the present invention. Figure 10is a cross-sectional view of the IGBT semiconductor chip of this embodiment, which is equivalent to a modified example of Embodiment 1 ( Figure 2 ).

[0085] The structure of the central region unit 201 of this embodiment is the same as that of Embodiment 1 ( Figure 2 ), and repeated descriptions are omitted.

[0086] On the other hand, the difference between the structure of the peripheral region unit 202 of this embodiment and that of Embodiment 1 ( Figure 2 ) is that a third semiconductor layer (n+ source layer) 303 is not formed in the region between the emitter contact portion 203 and the gate insulating film 310. Therefore, in the region between the emitter contact portion 203 and the gate insulating film 310, it is formed such that the interlayer insulating film 302 is in surface contact with the fifth semiconductor layer (p-base layer) 305.

[0087] In this embodiment, the structure of the central region unit 201 is the same as that of Embodiment 1 ( Figure 9 ), and the same effect can be obtained.

[0088] On the other hand, compared with Embodiment 1 ( Figure 9 ), since the peripheral region unit 202 does not have the third semiconductor layer (n+ source layer) 303, there is no parasitic thyristor (n + source / p-base / n - substrate / p-type collector layer) structure. In addition to the effects of Embodiment 1, latching can be prevented. Thus, an IGBT semiconductor chip with excellent breakdown withstand can be provided.

[0089] Embodiment 3

[0090] Refer to Figure 11 , and the semiconductor device of Embodiment 3 of the present invention will be described. Figure 11 is a cross-sectional view of the IGBT semiconductor chip of this embodiment, which is equivalent to a modified example of Embodiment 2 ( Figure 10 ).

[0091] The structure of the central region unit 201 of this embodiment is the same as that of Embodiment 2 ( Figure 10 ), and repeated descriptions are omitted.

[0092] On the other hand, compared with the peripheral region unit 202 of Embodiment 2 ( Figure 10 ), the difference between the structure of the peripheral region unit 202 of this embodiment and that of Embodiment 2 ( Figure 10 ) is that a seventh semiconductor layer (deep n layer) 307 of the second conductivity type is formed, and the seventh semiconductor layer 307 is formed in contact with the collector 313 side surface of the sixth semiconductor layer (deep p+ layer) 306 and has an impurity concentration higher than that of the semiconductor substrate 308.

[0093] In this embodiment, both the central region unit 201 and the peripheral region unit 202 form an electric field concentrating pn junction in the sixth semiconductor layer (deep p+ layer) 306 and the seventh semiconductor layer (deep n layer) 307, and electron injection based on impact ionization is generated equally between the units, having the effect of equalizing the hole current and being able to improve the breakdown withstand capacity.

[0094] On the other hand, the peripheral region unit 202 is the same as that in Embodiment 2 ( Figure 10 ), and since there is no third semiconductor layer (n+ source layer) 303, there is no parasitic thyristor (n + source / p-base / n - substrate / p-type collector layer) structure, and latching can be prevented.

[0095] In addition, since the peripheral region unit 202 has no third semiconductor layer (n+ source layer) 303, there is no electron injection when turned on, and the amount of holes is less than that of the central region unit 201. Therefore, the hole density during turn-off is also low, and current concentration and latching can be prevented. Thus, an IGBT semiconductor chip with excellent breakdown withstand capacity can be provided.

[0096] Embodiment 4

[0097] Refer to Figure 12 , and a semiconductor device according to Embodiment 4 of the present invention will be described. Figure 12 is a cross-sectional view of the IGBT semiconductor chip of this embodiment, which is a modified example of Embodiment 2 ( Figure 10 ).

[0098] The structures of the central region unit 201 and the peripheral region unit 202 of this embodiment are the same as those of Embodiment 2 ( Figure 10 ), and repeated descriptions are omitted.

[0099] On the other hand, in this embodiment, an intermediate region unit 1201 is disposed at an intermediate position in the planar direction between the central region unit 201 and the peripheral region unit 202 of the IGBT semiconductor chip 101, which is different from the structure of Embodiment 2 ( Figure 10 ).

[0100] The structure of the intermediate region unit 1201 of this embodiment is the same as the structure of the peripheral region unit 202 of Embodiment 3 ( Figure 11 ). Therefore, in the intermediate region unit 1201, a seventh semiconductor layer (deep n layer) 307 of the second conductivity type is formed, and the seventh semiconductor layer 307 is formed to be in contact with the side surface of the collector 313 of the sixth semiconductor layer (deep p+ layer) 306 and has an impurity concentration higher than that of the semiconductor substrate 308.

[0101] Further, a third semiconductor layer (n+ source layer) 303 is not formed in the region between the emitter contact portion 203 and the gate insulating film 310.

[0102] In this embodiment, both the central region unit 201 and the intermediate region unit 1201 form an electric field concentration pn junction in the sixth semiconductor layer (deep p+ layer) 306 and the seventh semiconductor layer (deep n layer) 307, and electron injection based on impact ionization is generated equally between the units, having the effect of equalizing the hole current and improving the breakdown withstand.

[0103] In particular, since there is no third semiconductor layer (n+ source layer) 303 in the intermediate region unit 1201, there is no parasitic thyristor (n + source / p-base / n - substrate / p-type collector layer) structure to extract the carriers of impact ionization, thereby having the effect of alleviating the carrier density difference generated between the central region unit 201 and the peripheral region unit 202 and suppressing local current concentration.

[0104] Further, the peripheral region unit 202 has a structure capable of efficiently extracting the hole current added from the chip terminal protection ring region 102 by removing the seventh semiconductor layer (deep n layer) 307, and also has the effect of suppressing current concentration in the peripheral region unit 202.

[0105] In addition, since there is no third semiconductor layer (n+ source layer) 303 in both the intermediate region unit 1201 and the peripheral region unit 202, there is no parasitic thyristor (n + source / p-base / n - substrate / p-type collector layer), and latch-up can be prevented. Thus, an IGBT semiconductor chip with excellent breakdown withstand can be provided.

[0106] Embodiment 5

[0107] Refer to Figure 13 , and a semiconductor device according to Embodiment 5 of the present invention will be described. Figure 13 is a cross-sectional view of the IGBT semiconductor chip of this embodiment, which is a modification of Embodiment 4 ( Figure 12 ).

[0108] The basic structure of the IGBT semiconductor chip of this embodiment is the same as that of Embodiment 4 ( Figure 12 ) in that an intermediate region unit 1201 is arranged at an intermediate position in the planar direction between the central region unit 201 and the peripheral region unit 202, and repeated descriptions are omitted.

[0109] In Embodiment 4 ( Figure 12) Among them, in all regions of the central region unit 201, the peripheral region unit 202, and the intermediate region unit 1201, the gate electrode is formed in a trench structure (trench gate 204 and gate insulating film 310). In contrast, in this embodiment ( Figure 13 ) Among them, in all regions of the central region unit 201, the peripheral region unit 202, and the intermediate region unit 1201, it is formed in a side gate structure (side gate 1301, Poly-Si field plate 1302, gate insulating film 310), which is different from the structure of Embodiment 4 in this regard ( Figure 12 ).

[0110] As Figure 13 shown, the gate electrode of this embodiment is configured as follows: a trench formed between the emitter electrode 301 and the semiconductor substrate 308; a gate electrode (side gate 1301) formed inside the trench, insulated from the emitter electrode 301 via an insulating layer (interlayer insulating film 302); a Poly-Si field plate 1302 formed inside the trench, connected to the emitter electrode 301 via the emitter contact portion 203.

[0111] In this embodiment, the IGBT unit is formed by a side gate structure, has a small feedback capacitance, and can achieve high switching and low loss.

[0112] In addition, both the central region unit 201 and the intermediate region unit 1201 have the effects of forming an electric field concentration pn junction in the sixth semiconductor layer (deep p+ layer) 306 and the seventh semiconductor layer (deep n layer) 307, the effect of no seventh semiconductor layer (deep n layer) 307 in the peripheral region unit 202, and the effects of no third semiconductor layer (n+ source layer) 303 in both the intermediate region unit 1201 and the peripheral region unit 202 are the same as those in Embodiment 4 ( Figure 12 ).

[0113] In addition, the side gate structure of this embodiment includes Embodiments 6 to 10 described later and can be similarly applied in all embodiments.

[0114] Embodiment 6

[0115] Refer to Figure 14 and Figure 15 , and the semiconductor device of Embodiment 6 of the present invention will be described. Figure 14 is a top view of the unit terminal region ( Figure 1A symbol 105) of the IGBT semiconductor chip of this embodiment. The trench gates of the unit portion of the IGBT are arranged in a striped pattern. Figure 15 is an aerial view of the IGBT semiconductor chip of this embodiment.

[0116] In this embodiment, as Figure 14As shown, striped trench gates 204 are arranged in the y direction to form the outer peripheral region unit 202. The central region unit 201 has the same structure as that of Example 1 ( Figure 2 ) and Example 5 ( Figure 13 ).

[0117] The outer peripheral region unit 202 forms the same structure as that of Example 1 ( Figure 2 ) and Example 2 ( Figure 10 ). Even when the IGBT units are arranged in a striped pattern, as Figure 15 shown, since the central region unit 201 and the outer peripheral region unit 202 are arranged in the depth direction of the trench, an electric field concentration pn junction is formed in the sixth semiconductor layer (deep p+ layer) 306 and the seventh semiconductor layer (deep n layer) 307, and electron injection based on impact ionization is evenly generated between the units, having the effect of equalizing the hole current and improving the breakdown withstand voltage.

[0118] In addition, the outer peripheral region unit 202 has a structure capable of efficiently extracting the hole current added from the chip terminal protection ring region 102 by removing the seventh semiconductor layer (deep n layer) 307, and has the effect of further suppressing current concentration in the outer peripheral region unit 202.

[0119] In addition, since the outer peripheral region unit 202 does not have the third semiconductor layer (n+ source layer) 303, there is no parasitic thyristor (n+ source / p base / n- substrate / p-type collector layer), and latching can be prevented. Thus, an IGBT semiconductor chip with excellent breakdown withstand voltage can be provided.

[0120] Example 7

[0121] Refer to Figure 16 to describe the semiconductor device of Example 7 of the present invention. Figure 16 is a bird's-eye view of the IGBT semiconductor chip of this embodiment, which is a modified example of Example 6 ( Figure 15 ). The trench gates of the unit part of the IGBT are arranged in a striped pattern.

[0122] In this embodiment, as Figure 16 shown, in the trench depth direction, the outer peripheral region unit 202 is formed in the same manner as that of Example 3 ( Figure 11 ). Even when the IGBT units are arranged in a striped pattern, both the central region unit 201 and the outer peripheral region unit 202 form an electric field concentration pn junction in the sixth semiconductor layer (deep p+ layer) 306 and the seventh semiconductor layer (deep n layer) 307, and electron injection based on impact ionization is evenly generated between the units, having the effect of equalizing the hole current and improving the breakdown withstand voltage.

[0123] On the other hand, the peripheral region unit 202 is the same as that in Embodiment 3 ( Figure 11 ) Since there is no third semiconductor layer (n+ source layer) 303, there is no parasitic thyristor (n+ source / p base / n- substrate / p-type collector layer) structure, and latch-up can be prevented.

[0124] In addition, since the peripheral region unit 202 has no third semiconductor layer (n+ source layer) 303, there is no electron injection when turned on, and the amount of holes becomes less than that of the central region unit 201. Therefore, the hole density during turn-off is also low, and current concentration and latch-up can be prevented. Thus, an IGBT semiconductor chip with excellent cut-off tolerance can be provided.

[0125] Embodiment 8

[0126] Refer to Figure 17 to describe the semiconductor device of Embodiment 8 of the present invention. Figure 17 is a bird's-eye view of the IGBT semiconductor chip of this embodiment, which is a modified example of Embodiment 7 ( Figure 16 ). The trench gates of the unit part of the IGBT are arranged in a striped pattern.

[0127] Even when the IGBT units are arranged in a striped pattern, similar to Embodiment 4 ( Figure 12 ), in the depth direction, both the central region unit 201 and the intermediate region unit 1201 form an electric field concentration pn junction in the sixth semiconductor layer (deep p+ layer) 306 and the seventh semiconductor layer (deep n layer) 307, and electron injection based on impact ionization is generated equally between the units, having the effect of equalizing the hole current and improving the cut-off tolerance.

[0128] In particular, since there is no third semiconductor layer (n+ source layer) 303 in the intermediate region unit 1201, carriers of impact ionization are extracted in a structure without a parasitic thyristor (n + source / p base / n - substrate / p-type collector layer), so it has the effect of alleviating the carrier density difference generated between the central region unit 201 and the peripheral region unit 202 and suppressing local current concentration.

[0129] In addition, the peripheral region unit 202 becomes a structure capable of efficiently extracting the hole current added from the chip terminal protection ring region 102 by removing the seventh semiconductor layer (deep n layer) 307, and has the effect of further suppressing current concentration in the peripheral region unit 202.

[0130] In addition, both the intermediate region unit 1201 and the peripheral region unit 202 have no third semiconductor layer (n+ source layer) 303, so there is no parasitic thyristor (n + source / p base / n- (Substrate / p-type collector layer), which can prevent latching. Thus, an IGBT semiconductor chip with excellent breakdown withstand can be provided.

[0131] Example 9

[0132] Refer to Figure 18 and Figure 19 , a semiconductor device according to Example 9 of the present invention will be described. Figure 18 is a top view of the cell terminal region ( Figure 1A symbol 105) of the IGBT semiconductor chip of this embodiment. The trench gates of the cell portion of the IGBT are arranged in a striped pattern. Figure 19 is a bird's-eye view of the IGBT semiconductor chip of this embodiment.

[0133] In the striped configuration of the IGBT, the central region cells 201 and the peripheral region cells 202 are also arranged in both the y-direction and the x-direction. In the central region cell 201, an electric field concentrating pn junction is formed in the sixth semiconductor layer (deep p+ layer) 306 and the seventh semiconductor layer (deep n layer) 307, and electron injection based on impact ionization is generated equally between cells, having the effect of equalizing the hole current and improving the breakdown withstand.

[0134] On the other hand, in the peripheral region cell 202, by removing the seventh semiconductor layer (deep n layer) 307, a structure capable of efficiently extracting the hole current added from the chip terminal protection ring region 102 is formed, having the effect of suppressing current concentration in the peripheral region cell 202.

[0135] In addition, since the peripheral region cell 202 does not have the third semiconductor layer (n+ source layer) 303, there is no parasitic thyristor (n+ source / p-base / n-substrate / p-type collector layer), and latching can be prevented. Thus, an IGBT semiconductor chip with excellent breakdown withstand can be provided.

[0136] Example 10

[0137] Refer to Figure 20 , an example of an embodiment in which the semiconductor device of the present invention is applied to a power conversion device will be described. Figure 20 is a circuit block diagram of a power conversion device 600 using the semiconductor devices according to Examples 1 to 9 of the present invention as components. Figure 20 Shows the circuit structure of the power conversion device 600 of this embodiment and the connection relationship between the DC power supply and the three-phase AC motor (AC load).

[0138] In the power conversion device 600 of the present embodiment, the semiconductor devices of Embodiments 1 to 9 are used as the power switching elements 601 to 606. The power switching elements 601 to 606 are, for example, IGBTs.

[0139] As Figure 20 shown, the power conversion device 600 of the present embodiment includes a pair of DC terminals, namely, a P terminal 631 and an N terminal 632, and the same number of AC terminals as the number of phases of the AC output, namely, a U terminal 633, a V terminal 634, and a W terminal 635.

[0140] It includes a switching leg formed by a series connection of a pair of power switching elements 601 and 602, and the U terminal 633 connected to the series connection point is used as the output. In addition, it includes a switching leg formed by a series connection of power switching elements 603 and 604 having the same structure, and the V terminal 634 connected to the series connection point is used as the output. In addition, it includes a switching leg formed by a series connection of power switching elements 605 and 606 having the same structure, and the W terminal 635 connected to the series connection point is used as the output.

[0141] The three-phase switching legs formed by the power switching elements 601 to 606 are connected between the DC terminals of the P terminal 631 and the N terminal 632, and DC power is supplied from a DC power source (not shown). The three-phase AC terminals of the power conversion device 600, namely, the U terminal 633, the V terminal 634, and the W terminal 635, are connected to a three-phase AC motor (not shown) as a three-phase AC power source.

[0142] Diodes 621 to 626 are respectively connected in antiparallel to the power switching elements 601 to 606. Gate drive circuits 611 to 616 are connected to the gate input terminals of the power switching elements 601 to 606 each formed by an IGBT, and drive control is performed by each of the gate drive circuits 611 to 616.

[0143] That is, the power conversion device 600 of the present embodiment is a power conversion device that inputs DC power from the outside and converts the input DC power into AC power for output, and has the following structure: It includes a pair of DC terminals 631 and 632 for inputting DC power, and AC terminals for outputting AC power and the same number of AC terminals 633 to 635 as the number of phases of the AC involved in the AC power. For each of the AC terminals 633 to 635 corresponding to the number of phases, between one terminal (P terminal 631) and the other terminal (N terminal 632) of the pair of DC terminals 631 and 632, a parallel circuit (for example, a parallel circuit of the power switch element 601 and the diode 621) formed by connecting a switch element (for example, the power switch element 601) and a diode having the opposite polarity to the switch element (for example, the diode 621) in parallel with each other is connected in series twice to form a series circuit (for example, a series circuit of a parallel circuit of the power switch element 601 and the diode 621, and a parallel circuit of the power switch element 602 and the diode 622). The connection point between the two parallel circuits constituting the series circuit is connected to the AC terminal (for example, the U terminal 633) corresponding to the phase (for example, the U phase) of the series circuit.

[0144] According to the IGBT semiconductor chip 101 described in the above embodiments 1 to 9, it is possible to suppress the local current and electric field concentration caused by the electric field deviation between IGBT units due to shape deviation and impurity deviation during manufacturing, and the current concentration at the chip terminal part, and improve the breakdown withstand capacity.

[0145] Therefore, through the IGBT semiconductor chips 101 of Embodiments 1 to 9, it is possible to achieve a high current density of the IGBT chip and miniaturize the power conversion device equipped with the IGBT chip.

[0146] In addition, the present invention is not limited to the above-described embodiments and includes various modification examples. For example, the above-described embodiments are embodiments described in detail for easy understanding of the present invention and are not limited to having all the structures described. A part of the structure of a certain embodiment can be replaced with the structure of another embodiment, and the structure of another embodiment can also be added to the structure of a certain embodiment. In addition, for a part of the structure of each embodiment, other structures can also be added, deleted, or replaced.

[0147] Description of Reference Numerals

[0148] 101…IGBT semiconductor chip, 102…chip terminal protection ring region, 103…cell region, 104…gate electrode PAD, 105…cell terminal region, 201…central region cell, 202…peripheral region cell, 203…emitter contact, 204…trench gate, 301…emitter electrode, 302…interlayer insulating film, 303…third semiconductor layer (n+ source layer), 304…fourth semiconductor layer (shallow p+ layer), 305…fifth semiconductor layer (p base layer), 306…sixth semiconductor layer (deep p+ layer), 307…seventh semiconductor layer (deep n layer), 308…semiconductor substrate (n- semiconductor substrate), 310…gate insulating film, 311…second semiconductor layer (n-type buffer layer), 312…first semiconductor layer (p-type collector layer), 313…collector, 501…trench, 502…contact hole, 503…resist, 600…power conversion device, 601~606…power switching element, 621~626…diode, 611~616…gate drive circuit, 631, 632…DC terminal, 633~635…AC terminal, 1201…intermediate region cell, 1301…side gate, 1302…Poly-Si field plate.

Claims

1. A semiconductor device, characterized in that, Comprising: An emitter electrode formed on the surface of a semiconductor substrate via an interlayer insulating film; A collector formed on the back surface of the semiconductor substrate; A first semiconductor layer of a first conductivity type, which is in contact with the collector and is formed on the back surface of the semiconductor substrate; A second semiconductor layer of a second conductivity type, which is formed closer to the semiconductor substrate side than the first semiconductor layer; A central region unit arranged along the surface of the semiconductor substrate; An outer peripheral region unit, which is located more outward than the central region unit in the plane direction of the semiconductor substrate and is arranged between the central region unit and the chip terminal protection ring region, The outer peripheral region unit includes: A trench formed between the emitter electrode and the semiconductor substrate; A gate electrode formed inside the trench via a gate insulating film and insulated from the emitter electrode via the interlayer insulating film; A fourth semiconductor layer of a first conductivity type, which is formed to be in contact with the semiconductor substrate side of the emitter electrode via an emitter contact portion and has an impurity concentration higher than that of the first semiconductor layer; A fifth semiconductor layer of a first conductivity type, which is formed to be in contact with the gate insulating film and has an impurity concentration lower than that of the fourth semiconductor layer; A sixth semiconductor layer of a first conductivity type, which is formed to be in contact with the surface of the semiconductor substrate side of the fourth semiconductor layer and protrudes toward the semiconductor substrate side from the fifth semiconductor layer, and has a carrier concentration lower than that of the fourth semiconductor layer, In the semiconductor device, at least one of the fifth semiconductor layer is formed to be in contact with the interlayer insulating film and the sixth semiconductor layer is formed to be in contact with the semiconductor substrate.

2. The semiconductor device according to claim 1, characterized in that The intermediate region unit has: the trench; the gate electrode; a third semiconductor layer of a second conductivity type, which is formed to be in contact with the gate and has an impurity concentration higher than that of the semiconductor substrate; The fourth semiconductor layer; the fifth semiconductor layer; the sixth semiconductor layer; And a seventh semiconductor layer of a second conductivity type, which is formed to be in contact with the collector side surface of the sixth semiconductor layer and has an impurity concentration higher than that of the semiconductor substrate.

3. The semiconductor device according to claim 2, characterized in that The outer peripheral region unit includes the third semiconductor layer.

4. The semiconductor device according to claim 2, characterized in that The outer peripheral region unit includes the seventh semiconductor layer.

5. The semiconductor device according to claim 1, characterized in that The outer peripheral region unit has: a third semiconductor layer of a second conductivity type, which is formed to be in contact with the gate insulating film and has an impurity concentration higher than that of the semiconductor substrate.

6. The semiconductor device according to claim 1, characterized in that The outer peripheral region unit has: a seventh semiconductor layer of a second conductivity type, which is formed to be in contact with the collector side surface of the sixth semiconductor layer and has an impurity concentration higher than that of the semiconductor substrate and lower than that of the second semiconductor layer.

7. The semiconductor device according to claim 2, characterized in that In the planar direction of the semiconductor substrate, an intermediate region unit is provided between the central region unit and the outer peripheral region unit. The intermediate region unit has the trench, the gate electrode, the fourth semiconductor layer, the fifth semiconductor layer, the sixth semiconductor layer, and the seventh semiconductor layer, and does not have the third semiconductor layer. The outer peripheral region unit does not have the seventh semiconductor layer.

8. The semiconductor device according to any one of claims 1 to 7, wherein The gate electrode is a trench gate electrode formed along the shape of the trench inside the trench.

9. The semiconductor device according to any one of claims 1 to 7, wherein The gate electrode is a side gate electrode in the shape of a side wall formed along the side wall of the trench inside the trench, The semiconductor device further includes a Poly-Si field plate connected to the emitter electrode via an emitter contact portion inside the trench.

10. The semiconductor device according to any one of claims 1 to 7, wherein The gate electrode is arranged in a striped shape in the planar direction of the semiconductor substrate.

11. A power conversion device, comprising: A pair of DC terminals; AC terminals having the same number as the number of phases of the AC; A switch bridge arm connected between the pair of DC terminals, in which a parallel circuit of two diodes with opposite polarities of the switching element is connected in series, The mutual connection points of the parallel circuits constitute the same number of power conversion units as the number of phases of the AC connected to different AC terminals, wherein The switching element is the semiconductor device according to any one of claims 1 to 10.

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