Semiconductor power device and preparation method thereof

Abstract

The invention relates to the technical field of semiconductors, and discloses a semiconductor power device and a preparation method thereof, and the preparation method of the semiconductor power device comprises the steps: providing a substrate, and forming a plurality of gate grooves in the substrate; providing a composite functional layer, wherein the composite functional layer comprises a first oxide layer, a silicon nitride layer and a second oxide layer which are sequentially formed on the groove bottom and the side wall of the gate groove; depositing a first polycrystalline silicon layer in the gate trench; an isolation oxide layer covering the first polycrystalline silicon layer and the composite function layer is deposited in the gate trench, a third oxide layer is formed on the gate trench, and the third oxide layer covers the side wall of the gate trench and is connected with the adjacent gate trench on the top surface of the substrate; depositing a second polycrystalline silicon layer covering the isolation oxide layer in the gate trench; forming a body region and a source region on the body region on the substrate; and forming a source metal layer on the substrate, and forming a drain region on the back metal of the substrate. The performance of the semiconductor power device is optimized.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and particularly to a semiconductor power device and a manufacturing method thereof. Background Art

[0002] In semiconductor manufacturing processes, SGT (Shield Gate Trench) MOSFET is a new type of semiconductor power device. As a switching device, it is applied to motor drive systems, inverter systems, and power management systems in fields such as new energy electric vehicles, new photovoltaic power generation, and energy-saving household appliances. It is a core power control component. The on-resistance RSP of SGT MOSFET is an important parameter index. In related technologies, SGT MOSFET adopts a shield gate structure, and the insulation design of its gate structure is relatively thick, which is not conducive to further optimizing the RSP parameter and affects the high-density structure requirements of the device. Therefore, how to optimize the design to obtain a smaller RSP and a higher device integration has become an urgent technical problem to be solved. Summary of the Invention

[0003] In view of this, the present application provides a semiconductor power device and a manufacturing method thereof to solve the above-mentioned technical problems.

[0004] To achieve the above object, according to the first aspect, the technical solution adopted is: A manufacturing method of a semiconductor power device, comprising: Providing a substrate, and forming a plurality of gate trenches on the substrate; Providing a composite functional layer, which is disposed on the gate trenches, and the composite functional layer includes a first oxide layer, a silicon nitride layer, and a second oxide layer formed in sequence on the bottom and side walls of the gate trenches; Depositing a first polysilicon layer in the gate trenches, and etching back the first polysilicon layer from the top surface to the bottom surface of the substrate to a first etching-back depth, and then continuing to etch back the first oxide layer, the silicon nitride layer, and the second oxide layer until they are flush with the first polysilicon layer; Depositing an isolation oxide layer covering the first polysilicon layer and the composite functional layer in the gate trenches, and forming a third oxide layer on the gate trenches, the third oxide layer covering the side walls of the gate trenches and connecting adjacent gate trenches on the top surface of the substrate; Depositing a second polysilicon layer covering the isolation oxide layer in the gate trenches, and etching back the second polysilicon layer from the top surface to the bottom surface of the substrate to a second etching-back depth, and then depositing an isolation dielectric layer in the gate trenches; Performing self-aligned ion implantation and annealing push wells between adjacent gate trenches on the substrate to form a body region and a source region located above the body region; A contact hole region connected to the body region is formed on the substrate, and a source metal layer covering the contact hole region is formed, and a drain region is formed by backside metallization of the substrate.

[0005] This application is further configured to: provide a substrate, and form a plurality of gate trenches on the substrate, including: Provide an N+-doped substrate, and form an N-epitaxial layer of the same ion doping type on the N+-doped substrate; A plurality of gate trenches with a set trench size are etched on the epitaxial layer through a trench mask, and the set trench size includes a set trench depth, a set trench width, and a set trench inclination angle. Among them, the set trench depth is greater than 0.9 um, the set trench width includes 0.15 - 0.3 um, and the set trench inclination angle is greater than 88°.

[0006] This application is further configured to: the ratio range of the formation thickness of the first oxide layer and the formation thickness of the silicon nitride layer includes 0.2 - 2.

[0007] This application is further configured to: the formation thickness of the first oxide layer includes 100 - 300 Å, the formation thickness of the silicon nitride layer includes 100 - 500 Å, and the formation thickness of the second oxide layer is greater than 100 Å.

[0008] This application is further configured to: the well depth of the body region is greater than the well depth of the source region, and the well depth of the source region is greater than the second back-etching depth of the second polysilicon layer.

[0009] This application is further configured to: the first back-etching depth of the first polysilicon layer is greater than 0.5 um, and the second back-etching depth of the second polysilicon layer is greater than 0.1 um.

[0010] This application is further configured to: the initial thickness of the first polysilicon layer includes 4000 - 8000 Å, the initial thickness of the second polysilicon layer includes 4000 - 8000 Å, and the remaining thickness of the third oxide layer on the substrate includes 100 - 400 Å.

[0011] This application is further configured to: forming a contact hole region connected to the body region on the substrate, including: Form a contact hole by etching through a contact hole mask on the substrate. The contact hole penetrates into the body region from the top surface to the bottom surface of the substrate. Among them, the opening size width of the contact hole includes 0.05 - 0.2 um, and the inclination angle of the contact hole is greater than 80°; Inject ions of the same ion implantation type as the body region into the contact hole and anneal the well to form the contact hole region.

[0012] The present application is further configured such that: the source metal layer includes an alloy layer and a surface metal layer, the alloy layer is deposited in the contact hole, and a passivation protection layer and / or a PI protection layer is formed on the surface metal layer.

[0013] According to the second aspect, the technical solution adopted is: A semiconductor power device, prepared by the semiconductor power device preparation method described in any one of the above embodiments, includes: A substrate, on which several gate trenches are provided; A composite functional layer, disposed on the gate trenches. The composite functional layer includes a first oxide layer, a silicon nitride layer, and a second oxide layer that are sequentially connected to the bottom and sidewalls of the gate trenches. Among them, a first polysilicon layer is provided in the gate trench, the first polysilicon layer fills on the second oxide layer, an isolation oxide layer and a third oxide layer are provided in the gate trench, the isolation oxide layer covers the first polysilicon layer and the composite functional layer, the third oxide layer in the gate trench is covered by the isolation oxide layer on the sidewalls of the gate trench until the top surface of the substrate and connects adjacent gate trenches, and a second polysilicon layer and an isolation dielectric layer stacked on the isolation oxide layer are provided in the gate trench; A body region, connected between adjacent gate trenches in the substrate; A source region, connected above the body region in the substrate; A contact hole region, provided between adjacent gate trenches on the substrate and connected to the body region; A source metal layer, disposed on the top surface of the substrate and covering the contact hole region; A drain region, disposed on the bottom surface of the substrate.

[0014] In summary, compared with the prior art, the present application discloses a semiconductor power device and a manufacturing method thereof. The manufacturing method of the semiconductor power device includes: forming a plurality of gate trenches on a substrate; disposing a composite functional layer on the gate trenches, including a first oxide layer, a silicon nitride layer, and a second oxide layer formed on the bottom and sidewalls of the gate trenches in sequence; depositing a first polysilicon layer in the gate trenches; after etching back the first polysilicon layer from the top surface to the bottom surface of the substrate to a first etching depth, continuously etching back the first oxide layer, the silicon nitride layer, and the second oxide layer until they are flush with the first polysilicon layer; depositing an isolation oxide layer covering the first polysilicon layer and the composite functional layer in the gate trenches; and forming a third oxide layer on the gate trenches, the third oxide layer covering the sidewalls of the gate trenches and connecting adjacent gate trenches on the top surface of the substrate. Depositing a second polysilicon layer covering the isolation oxide layer in the gate trenches; after etching back the second polysilicon layer from the top surface to the bottom surface of the substrate to a second etching depth, depositing an isolation dielectric layer in the gate trenches; and performing self-aligned ion implantation and annealing to push the well between adjacent gate trenches on the substrate to form a body region and a source region located above the body region. Forming a contact hole region connected to the body region on the substrate and a source metal layer covering the contact hole region, and forming a drain region by back metallization of the substrate. That is, through the above settings, the insulation thickness of the gate structure of the power device is optimized by the composite functional layer and its RSP parameters are optimized. The integration density of the power device is increased by the third oxide layer combined with self-aligned ion implantation, thereby improving the performance of the semiconductor power device. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0016] Figure 1 is a flowchart of the manufacturing method of the semiconductor power device of the present application; Figure 2 is a schematic structural diagram of the first semiconductor power device of the present application; Figure 3 is a schematic structural diagram of the second semiconductor power device of the present application; Figure 4 is a schematic structural diagram of the third semiconductor power device of the present application; Figure 5 is a schematic structural diagram of the fourth semiconductor power device of the present application; Figure 6 is a schematic structural diagram of the fifth semiconductor power device of the present application; Figure 7 is a schematic structural diagram of the sixth semiconductor power device of the present application; Figure 8 It is a schematic structural diagram of the seventh semiconductor power device of the present application. Detailed implementation manners

[0017] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all the implementation manners consistent with the present application. On the contrary, they are only examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0018] It should be noted that in this document, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusively, so that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without more limitations, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or device including the element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined by their explanations in the specific embodiments or further in combination with the context in the specific embodiments.

[0019] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0020] In the subsequent description, the suffixes such as "module", "component" or "unit" used to represent elements are only for the convenience of the description of the present application, and they have no specific meaning in themselves. Therefore, "module", "component" or "unit" can be used interchangeably.

[0021] In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "upper", "lower", "left", "right", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present application. In addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0022] The technical solutions shown in the present application will be described in detail through specific embodiments below. It should be noted that the description order of the following embodiments does not limit the priority order of the embodiments.

[0023] Please refer to Figure 1 , and in combination with Figures 2 to 8 , the method for manufacturing a semiconductor power device according to an embodiment of the present application includes: S101, provide a substrate 1, and form a plurality of gate trenches 2 on the substrate 1.

[0024] In a specific implementation process, referring to Figure 2 , the material for forming the substrate 1 can be single crystal silicon, polycrystalline silicon, amorphous silicon, doped silicon, etc. The material of the substrate 1 can also be a SiGe substrate, a group III-V element compound substrate, a silicon carbide substrate or a stacked structure thereof, or a silicon-on-insulator structure, or a diamond substrate or other semiconductor material substrates well-known to those skilled in the art. For example, P atoms can be implanted into single crystal silicon to form an N-type conductive semiconductor substrate, or B atoms can be implanted into single crystal silicon to form a P-type conductive semiconductor substrate, so as to improve the material selectivity and adaptability to the actual production environment.

[0025] In this embodiment, P atoms are implanted into the substrate 1 to form an N-type conductive semiconductor substrate, that is, the substrate 1 is an N+-doped substrate.

[0026] It should be noted that a buried layer and an epitaxial layer 10 can be sequentially stacked on the substrate 1. At this time, the functional layers of the semiconductor power device can all be formed on the epitaxial layer 10. Then, it can be understood that the subsequent trench gate structure, body region, source region, and contact hole region of the embodiment of the present application can all be formed on the epitaxial layer 10.

[0027] Among them, the epitaxial layer 10 has the same ion doping type as the substrate 1, that is, an N-type epitaxial layer 10 with the same ion doping type is formed on the N+-doped substrate 1.

[0028] In one embodiment, a plurality of cell regions can be defined on the epitaxial layer 10 to include a large number of repeated basic units of the semiconductor power device, and then the gate trench 2 can be regarded as a cell trench.

[0029] In one embodiment, providing a substrate 1 and forming a plurality of gate trenches 2 on the substrate 1 specifically includes: Provide an N+-doped substrate 1, and form an N-type epitaxial layer 10 with the same ion doping type on the N+-doped substrate 1; Form a plurality of gate trenches 2 with a set trench size on the epitaxial layer 10 by etching through a trench mask.

[0030] Among them, setting the groove dimensions includes setting the groove depth, setting the groove width, and setting the groove inclination angle. If the set groove depth is defined as S and the set groove width is defined as K, then S > 1 μm, K includes 0.15 - 0.3 μm, that is, the set groove depth is greater than 0.9 μm, the set groove width includes 0.15 - 0.3 μm, and the set groove inclination angle is greater than 88°. Thus, based on the limitation of the set groove dimensions, the gate groove density per unit area of the power device is increased, and further the integration density of the power device is improved.

[0031] Preferably, the set groove width is 0.2 μm.

[0032] Optionally, the aspect ratio of the gate groove 2 is greater than 8.

[0033] S102, provide a composite functional layer 3, which is disposed on the gate groove 2. The composite functional layer 3 includes a first oxide layer 31, a silicon nitride layer 32, and a second oxide layer 33 formed in sequence on the bottom and side walls of the gate groove 2.

[0034] In the specific implementation process, referring to Figure 3 , that is, through the design of the composite functional layer 3 including the first oxide layer 31, the silicon nitride layer 32, and the second oxide layer 33 as the insulation shielding layer on the gate groove 2, this three-layer structure forms a high-performance gate dielectric, thereby effectively controlling the insulation thickness and the electric field uniformity, and thus reducing the on-resistance (RSP) of the power device. In particular, the silicon nitride layer 32 clamped in the middle layer can inhibit hot carrier injection, improve thermal stability, and reduce the interface state density.

[0035] Moreover, according to the high dielectric constant characteristic of the silicon nitride layer 32, compared with the conventional oxide layer, it can have a thinner film thickness under the same breakdown voltage, so as to facilitate reducing the width of the gate groove 2 and improving the integration density of the power device.

[0036] Among them, the first oxide layer 31 can be formed on the bottom and side walls of the gate groove 2 through a thermal oxidation process, and then the silicon nitride layer 32 and the second oxide layer 33 are deposited in sequence, thereby forming a sandwich structure of oxide - silicon nitride - oxide.

[0037] For the method for manufacturing a semiconductor power device according to an embodiment of the present application, after forming a plurality of gate trenches 2 on a substrate 1, for the design of the gate structure on the gate trenches 2, on the one hand, a composite functional layer 3 composed of a first oxide layer 31 - a silicon nitride layer 32 - a second oxide layer 33 is used to form a gate dielectric with excellent performance. And through the cooperation of the three-layer structure, the overall insulation thickness and the uniformity of the electric field in the trench are effectively controlled to reduce the RSP of the power device and improve the channel turn-on performance and breakdown voltage capability of the power device. On the other hand, the silicon nitride layer 32 located in the middle layer of the composite functional layer 3, due to its high dielectric constant and good thermal stability, can not only reduce the overall insulation layer thickness while maintaining the breakdown voltage capability of the device, reduce the trench width, increase the trench density, but also effectively suppress hot carrier injection and reduce the interface state density, further improving the comprehensive performance and reliability of the power device.

[0038] Preferably, the ratio range of the formation thickness of the first oxide layer 31 to the formation thickness of the silicon nitride layer 32 includes 0.2 - 2 to improve the dielectric performance while ensuring the interface quality. That is, the ratio range of 0.2 - 2 enables the composite functional layer 3 to have both good interface quality and enhance the equivalent gate dielectric capacitance by virtue of the high dielectric characteristics of silicon nitride, thereby enhancing the gate control ability and reducing the on-resistance.

[0039] Optionally, the ratio of the formation thickness of the first oxide layer 31 to the formation thickness of the silicon nitride layer 32 is 0.8.

[0040] In one embodiment, the formation thickness of the first oxide layer 31 includes 100 - 300 Å.

[0041] Preferably, the formation thickness of the first oxide layer 31 is 200 Å, thereby forming a dense and high-quality oxide layer at the bottom and sidewalls of the gate trench 2, suppressing the interface trap state density, and enhancing the subthreshold characteristics and reliability of the device.

[0042] In one embodiment, the formation thickness of the silicon nitride layer 32 includes 100 - 500 Å.

[0043] Preferably, the formation thickness of the silicon nitride layer 32 is 200 Å to serve as the main layer of the high-k gate dielectric, increase the gate capacitance per unit area, enhance the channel modulation, and improve the dielectric performance while ensuring the interface quality.

[0044] It should be noted that if the formation thickness of the silicon nitride layer 32 in the embodiment of the present application is less than 100 Å, leakage points are likely to be formed. If it is higher than 500 Å, the risk of film stress and cracks is likely to be caused.

[0045] In one embodiment, the formation thickness of the second oxide layer 33 is greater than 100 Å.

[0046] Preferably, the formed thickness of the second oxide layer 33 is 300 Å. Then, as the outermost encapsulation insulating layer of the gate structure, the thickness of 300 Å can enhance the breakdown voltage of the trench sidewall and improve the reliable voltage withstand capacity of the device.

[0047] In an application scenario, the formed thicknesses of the first oxide layer 31, the silicon nitride layer 32, and the second oxide layer 33 included in the composite functional layer 3 are the same.

[0048] Among them, the formed materials of the first oxide layer 31 and the second oxide layer 33 include SiO2.

[0049] S103, deposit a first polysilicon layer 41 in the gate trench 2. After etching back the first polysilicon layer 41 from the top surface to the bottom surface of the substrate 1 to the first etching depth, continue to etch back the first oxide layer 31, the silicon nitride layer 32, and the second oxide layer 33 until they are flush with the first polysilicon layer 41.

[0050] In the specific implementation process, refer to Figure 4 , etch back the first polysilicon layer 41 and the composite functional layer 3 successively, that is, the coplanarization treatment of the polysilicon layer and the composite functional layer 3, to ensure the alignment accuracy between layers in the trench and the integrity of dielectric coating, so as to use the first polysilicon layer 41 as the embedded source polysilicon of the power device.

[0051] Among them, the first etching depth of the first polysilicon layer 41 is greater than 0.5 um. If this first etching depth is defined as H1, that is, H1 > 0.5 um, so that after the polysilicon layer is deposited in the trench, it has a suitable depth to form an effective source shielding structure in the gate trench 2, optimize the electric field distribution at the bottom and sidewalls of the gate trench 2, and help reduce the on-resistance and improve the voltage withstand performance of the device.

[0052] Optionally, the initial thickness of the first polysilicon layer 41 includes 4000 - 8000 Å.

[0053] S104, deposit an isolation oxide layer 5 covering the first polysilicon layer 41 and the composite functional layer 3 in the gate trench 2, and form a third oxide layer 6 on the gate trench 2. The third oxide layer 6 covers the sidewalls of the gate trench 2 and connects adjacent gate trenches 2 on the top surface of the substrate 1.

[0054] In the specific implementation process, refer to Figure 5 and Figure 6, the isolation oxide layer 5 isolates the first polysilicon layer 41 and the composite functional layer 3 in the gate trench 2, and the third oxide layer 6 starts from the isolation oxide layer 5, covers the sidewalls of the gate trench 2 until the top surface of the substrate 1 and connects adjacent gate trenches 2. Thus, the structural design of such a top isolation bridge of the third oxide layer 6 can reduce the design pitch between adjacent gate structures, and also facilitate the realization of a more compact gate arrangement, combined with the subsequent self-aligned ion implantation process to obtain a higher cell density, so as to further reduce the on-resistance per unit area. At the same time, the sidewall coverage of the third oxide layer 6 provides a good nucleation platform for the subsequent second polysilicon layer, that is, it provides a regular inner cavity structure for the deposition of the second polysilicon layer to form a complete gate electrode channel.

[0055] In one embodiment, the retention thickness of the third oxide layer 6 on the substrate 1 includes 100 - 400 Å.

[0056] Optionally, the retention thickness of the third oxide layer 6 on the substrate 1 includes 300 Å. As a damage blocking layer, it is convenient to maintain a certain thickness of the oxide layer to effectively absorb the surface impact caused by the implantation energy during the subsequent ion implantation process, and avoid structural defects or electroactive damage to the oxide layer, silicon nitride layer or crystalline silicon structure at the trench edge caused by ion implantation.

[0057] Moreover, the bridge-like structure formed by the third oxide layer 6 between adjacent gate trenches 2 can serve as a natural blocking structure for the implantation window, avoiding over-wide and over-deep implantation expansion, thereby improving the self-alignment accuracy and symmetry of the subsequent body region / source region implantation.

[0058] S105, deposit a second polysilicon layer 42 covering the isolation oxide layer 5 in the gate trench 2. After etching back the second polysilicon layer 42 from the top surface to the bottom surface of the substrate 1 to the second etch depth, deposit an isolation dielectric layer 21 in the gate trench 2.

[0059] In the specific implementation process, referring to Figure 6 and Figure 7 , with the formation of the second polysilicon layer 42 and the isolation dielectric layer 21, the preparation of the complete trench gate structure is completed, and the second polysilicon layer 42 and the first polysilicon layer 41 below it form a distributed double-layer gate structure.

[0060] Among them, the second etch depth of the second polysilicon layer 42 is greater than 0.1 um. If this second etch depth is marked as H2, then H2 > 0.1 um.

[0061] S106, perform self-aligned ion implantation and annealing push well between adjacent gate trenches 2 on the substrate 1 to form a body region 11 and a source region 12 located above the body region 11.

[0062] In the specific implementation process, referring to Figure 7, self-aligned P-ion implantation is performed between adjacent gate trenches 2 on the substrate 1 to form a body region 11, N+ ion implantation is performed to form a source region 12, and after annealing and pushing the well, the well depth of the body region 11 is greater than that of the source region 12, and the well depth of the source region 12 is greater than the second back-etching depth.

[0063] S107, a contact hole region 7 connected to the inside of the body region 11 is formed on the substrate 1, and a source metal layer 8 covering the contact hole region 7 is formed, and a drain region 9 is formed by back metallization of the substrate 1.

[0064] In the specific implementation process, refer to Figure 8 , a contact hole region 7 connected to the inside of the body region 11 is formed on the substrate 1, including: forming a contact hole 71 by etching through a contact hole mask on the substrate 1, and the contact hole 71 penetrates into the body region 11 from the top surface to the bottom surface of the substrate 1; injecting ions of the same ion implantation type as the body region 11 into the contact hole 71 and annealing and pushing the well to form the contact hole region 7.

[0065] Among them, the source metal layer 8 includes an alloy layer 81 and a surface metal layer 82, and the alloy layer 81 is deposited in the contact hole 71.

[0066] Among them, P++ ions of the same ion implantation type as the body region 11 are injected into the contact hole 71 and annealed and pushed the well to form the contact hole region 7. Then, based on the fact that the contact hole 71 penetrates into the body region 11 from the top surface to the bottom surface of the substrate 1, the P++ ions diffuse out of the contact hole region 7 in the body region 11, and by using the design that the concentration of P++ ions is greater than the concentration of P- ions in the body region 11, a graded junction is formed in the body region 11 by the contact hole region 7, reducing the Schottky barrier.

[0067] And, P++ ions of the same ion implantation type as the body region 11 are injected into the contact hole 71 and annealed and pushed the well to form the contact hole region 7, and the well depth of the contact hole 71 is greater than the well depth of the source region 12.

[0068] Among them, the contact hole 71 is formed by etching through a contact hole mask on the substrate 1, the opening size width of the contact hole 71 includes 0.05 - 0.2 um, and the inclination angle of the contact hole 71 is greater than 80°.

[0069] Preferably, the opening size width of the contact hole 71 is 0.1 um.

[0070] Combined with the content of the foregoing embodiments, in the method for manufacturing a semiconductor power device of the present application, the insulating thickness of the gate structure of the power device is optimized by the composite functional layer 3 and its RSP parameters are optimized. The third oxide layer 6 is combined with self-aligned ion implantation to increase the integration density of the power device. Under the setting of the trench width including 0.15 - 0.3 um and the opening size width of the contact hole 71 including 0.05 - 0.2 um, compared with the prior art, the cell size of the power device can be reduced to 0.5 - 0.9 um, thereby further increasing the integration density of the power device and optimizing its Rsp parameters.

[0071] In one embodiment, the deposition material of the alloy layer 81 includes at least one of Ti, TiN, and W.

[0072] Optionally, the deposition material of the surface metal layer 82 includes Al or Cu to facilitate the formation of a good ohmic contact between the alloy layer 81 and the surface metal layer 82.

[0073] In one embodiment, a passivation protection layer 83 is formed on the surface metal layer 82 to isolate and protect the source metal layer 8, and the source / gate window is opened based on the passivation protection layer 83, and / or a PI protection layer is formed on the surface metal layer 82.

[0074] Among them, the passivation protection layer 83 may include a silicon nitride layer and a silicon oxide layer, and the thickness range of the passivation protection layer 83 includes 0.8 - 2 um.

[0075] Among them, the thickness of the PI protection layer is greater than 5 um.

[0076] Among them, the back gold of the substrate 1 forms the drain region 9, which may include thinning the bottom surface of the substrate 1. Among them, the thinning thickness includes 50 - 150 um, and then a metal layer is deposited on the bottom surface of the substrate 1 to form the drain region 9.

[0077] Preferably, the thinning thickness is 100 um.

[0078] Accordingly, in the method for manufacturing a semiconductor power device according to an embodiment of the present application, a plurality of gate trenches 2 are formed on a substrate 1, and a composite functional layer 3 is disposed on the gate trenches 2, including a first oxide layer 31, a silicon nitride layer 32, and a second oxide layer 33 sequentially formed on the bottom and side walls of the gate trenches 2. A first polysilicon layer 41 is deposited in the gate trenches 2. After the first polysilicon layer 41 is etched back to a first etch-back depth in the direction from the top surface to the bottom surface of the substrate 1, the first oxide layer 31, the silicon nitride layer 32, and the second oxide layer 33 are continuously etched back to be flush with the first polysilicon layer 41. An isolation oxide layer 5 covering the first polysilicon layer 41 and the composite functional layer 3 is deposited in the gate trenches 2, and a third oxide layer 6 is formed on the gate trenches 2. The third oxide layer 6 covers the side walls of the gate trenches 2 and connects adjacent gate trenches 2 on the top surface of the substrate 1. A second polysilicon layer 42 covering the isolation oxide layer 5 is deposited in the gate trenches 2. After the second polysilicon layer 42 is etched back to a second etch-back depth in the direction from the top surface to the bottom surface of the substrate 1, an isolation dielectric layer 21 is deposited in the gate trenches 2, and self-aligned ion implantation and annealing are performed between adjacent gate trenches 2 on the substrate 1 to form a body region 11 and a source region 12 located above the body region 11. A contact hole region 7 connected to the body region 11 and a source metal layer 8 covering the contact hole region 7 are formed on the substrate 1, and a drain region 9 is formed by back metallization of the substrate 1. Accordingly, the insulation thickness of the gate structure of the power device is optimized through the composite functional layer 3, and its RSP parameters are optimized. The integration density of the power device is increased by combining the third oxide layer 6 with self-aligned ion implantation, thereby improving the performance of the semiconductor power device.

[0079] The present application also discloses a semiconductor power device, which is manufactured by the method for manufacturing a semiconductor power device according to any one of the above embodiments. Refer to Figure 8 ., the semiconductor power device includes: a substrate 1, the substrate 1 is provided with a plurality of gate trenches 2; a composite functional layer 3, disposed on the gate trenches 2, the composite functional layer 3 includes a first oxide layer 31, a silicon nitride layer 32, and a second oxide layer 33 sequentially connected to the bottom and side walls of the gate trenches 2. Wherein, a first polysilicon layer 41 is provided in the gate trenches 2, the first polysilicon layer 41 is filled on the second oxide layer 33, an isolation oxide layer 5 and a third oxide layer 6 are provided in the gate trenches 2, the isolation oxide layer 5 covers the first polysilicon layer 41 and the composite functional layer 3, the third oxide layer 6 covers the side walls of the gate trenches 2 in the gate trenches 2 by the isolation oxide layer 5 until the top surface of the substrate 1 and connects adjacent gate trenches 2, and, a second polysilicon layer 42 and an isolation dielectric layer 21 stacked on the isolation oxide layer 5 are provided in the gate trenches 2; a body region 11, connected between adjacent gate trenches 2 in the substrate 1; a source region 12, connected above the body region 11 in the substrate 1; a contact hole region 7, provided between adjacent gate trenches 2 on the substrate 1 and connected to the body region 11; a source metal layer 8, provided on the top surface of the substrate 1 and covering the contact hole region 7; a drain region 9, provided on the bottom surface of the substrate 1.

[0080] Among them, a buried layer and an epitaxial layer 10 can be sequentially formed and stacked on the substrate 1. At this time, the above-mentioned functional layers of the semiconductor power device can all be formed on the epitaxial layer 10.

[0081] For other working principles and processes of the semiconductor power device of this embodiment, refer to the description of the manufacturing method of the semiconductor power device in the foregoing this embodiment, which will not be elaborated here.

[0082] The semiconductor power device and its manufacturing method provided by this application have been introduced in detail above. Specific examples are used in this article to elaborate on the principles and implementation manners of this application. It should be noted that in this application, the descriptions of each embodiment have their own emphases. For parts not described in detail or recorded in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0083] The above is only the preferred embodiment of this application, and it does not limit the patent scope of this application. Each technical feature of the technical solution of this application can be combined arbitrarily. For the sake of concise description, not all possible combinations of the various technical features in the above embodiments are described. Any equivalent structural or equivalent process transformation made by using the content of the specification and drawings of this application, or directly or indirectly applied in other related technical fields, as long as the combination of these technical features does not conflict, is similarly included in the patent protection scope of this application.

Claims

1. A method for manufacturing a semiconductor power device, characterized in that, Including: Providing a substrate, and forming a plurality of gate trenches on the substrate; Providing a composite functional layer, which is disposed on the gate trenches, and the composite functional layer includes a first oxide layer, a silicon nitride layer, and a second oxide layer formed in sequence on the bottom and side walls of the gate trenches; Depositing a first polysilicon layer in the gate trenches, and etching the first polysilicon layer from the top surface to the bottom surface of the substrate to a first etching depth, and then continuing to etch the first oxide layer, the silicon nitride layer, and the second oxide layer until they are flush with the first polysilicon layer; Depositing an isolation oxide layer covering the first polysilicon layer and the composite functional layer in the gate trenches, and forming a third oxide layer on the gate trenches, the third oxide layer covering the side walls of the gate trenches and connecting adjacent gate trenches on the top surface of the substrate; Depositing a second polysilicon layer covering the isolation oxide layer in the gate trenches, and etching the second polysilicon layer from the top surface to the bottom surface of the substrate to a second etching depth, and then depositing an isolation dielectric layer in the gate trenches; Performing self-aligned ion implantation and annealing push well between adjacent gate trenches on the substrate to form a body region and a source region located above the body region; Forming a contact hole region connected to the body region on the substrate and a source metal layer covering the contact hole region, and forming a drain region on the back of the substrate; 2. The method for manufacturing a semiconductor power device according to claim 1, characterized in that, The providing a substrate and forming a plurality of gate trenches on the substrate includes: Providing an N+-doped substrate, and forming an N-epitaxial layer of the same ion doping type on the N+-doped substrate; Forming a plurality of gate trenches with set trench dimensions on the epitaxial layer by etching through a trench mask, the set trench dimensions including a set trench depth, a set trench width, and a set trench inclination angle, wherein the set trench depth is greater than 0.9 μm, the set trench width includes 0.15 - 0.3 μm, and the set trench inclination angle is greater than 88°; 3. The method for manufacturing a semiconductor power device according to claim 1, wherein, The ratio range of the formation thickness of the first oxide layer to the formation thickness of the silicon nitride layer includes 0.2 - 2; 4. The method for manufacturing a semiconductor power device according to claim 3, wherein, The formation thickness of the first oxide layer includes 100 - 300 Å, the formation thickness of the silicon nitride layer includes 100 - 500 Å, and the formation thickness of the second oxide layer is greater than 100 Å; 5. The method for manufacturing a semiconductor power device according to claim 1, wherein, The push well junction depth of the body region is greater than the push well junction depth of the source region, and the push well junction depth of the source region is greater than the second etching depth of the second polysilicon layer; 6. The method for manufacturing a semiconductor power device according to claim 5, characterized in that, The first etching depth of the first polysilicon layer is greater than 0.5 μm, and the second etching depth of the second polysilicon layer is greater than 0.1 μm; 7. The method for manufacturing a semiconductor power device according to claim 1, wherein, The initial thickness of the first polysilicon layer includes 4000 - 8000 Å, the initial thickness of the second polysilicon layer includes 4000 - 8000 Å, and the maintained thickness of the third oxide layer on the substrate includes 100 - 400 Å; 8. The method for manufacturing a semiconductor power device according to claim 1, characterized in that, The forming a contact hole region connected to the body region on the substrate includes: A contact hole is etched on the substrate through a contact hole mask, and the contact hole penetrates into the body region from the top surface to the bottom surface of the substrate. Among them, the opening size width of the contact hole includes 0.05 - 0.2 um, and the inclination angle of the contact hole is greater than 80°; Ions of the same ion implantation type as the body region are implanted into the contact hole and annealed to push the well, forming the contact hole region.

9. The method for manufacturing a semiconductor power device according to claim 8, wherein, The source metal layer includes an alloy layer and a surface metal layer. The alloy layer is deposited in the contact hole, and a passivation protection layer and / or a PI protection layer are formed on the surface metal layer.

10. A semiconductor power device, prepared by the method for preparing a semiconductor power device according to any one of claims 1 to 9, characterized in that, Comprising: A substrate provided with a plurality of gate trenches; A composite functional layer disposed on the gate trenches. The composite functional layer includes a first oxide layer, a silicon nitride layer, and a second oxide layer sequentially connected to the bottom and side walls of the gate trenches. Among them, a first polysilicon layer is provided in the gate trench, and the first polysilicon layer is filled on the second oxide layer. An isolation oxide layer and a third oxide layer are provided in the gate trench. The isolation oxide layer covers the first polysilicon layer and the composite functional layer. The third oxide layer in the gate trench is covered by the isolation oxide layer on the side walls of the gate trench until the top surface of the substrate and connects adjacent gate trenches. In addition, a second polysilicon layer and an isolation dielectric layer stacked on the isolation oxide layer are provided in the gate trench; A body region connected between adjacent gate trenches in the substrate; A source region connected above the body region in the substrate; A contact hole region provided between adjacent gate trenches on the substrate and connected to the body region; A source metal layer disposed on the top surface of the substrate and covering the contact hole region; A drain region disposed on the bottom surface of the substrate.

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