Semiconductor device

Abstract

A semiconductor device includes: a first lower interlayer insulating layer; an insulating pattern extending in a first horizontal direction; the first plurality of nanosheets and the second plurality of nanosheets are stacked at intervals in the vertical direction; a first gate electrode extending in a second horizontal direction, the first gate electrode surrounding the first plurality of nanosheets; a second gate electrode extending in a second horizontal direction, the second gate electrode surrounding the second plurality of nanosheets; a source / drain region between the first gate electrode and the second gate electrode; a source / drain contact portion penetrating the first lower interlayer insulating layer and the insulating pattern, the source / drain contact portion being electrically connected to the source / drain region; and a gate contact portion penetrating the first lower interlayer insulating layer and the insulating pattern, the gate contact portion being electrically connected to the second gate electrode, at least a portion of a sidewall of the gate contact portion being in contact with the source / drain contact portion.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority of Korean Patent Application No. 10 - 2023 - 0196304, filed with the Korean Intellectual Property Office on December 29, 2023, the entire contents of which are incorporated herein by reference. Technical field

[0003] Each exemplary embodiment relates to a semiconductor device, and more particularly, to a semiconductor device including a multi - bridge - channel field - effect transistor (MBCFET TM ). Background art

[0004] As a scaling technology for increasing the density of integrated circuit devices, the concept of a multi - gate transistor has been proposed, in which a silicon body in the form of a fin or a nanowire is formed on a substrate, and a gate is formed on the surface of the silicon body.

[0005] The multi - gate transistor utilizes a three - dimensional (3D) channel and can be easily scaled up and down. In addition, the multi - gate transistor can improve the control of current without increasing the gate length. In addition, the multi - gate transistor can effectively alleviate the short - channel effect (SCE), that is, the phenomenon in which the potential of the channel region is affected by the drain voltage. Summary of the invention

[0006] Each exemplary embodiment provides a semiconductor device capable of ensuring a process margin for forming a gate contact portion, a source / drain contact portion, and a bottom via in a back region, and simplifying the processes of forming the gate contact portion, the source / drain contact portion, and the bottom via.

[0007] However, the various exemplary embodiments of the inventive concept are not limited to the embodiments described herein. Through the detailed description of the various exemplary embodiments given below, the above - mentioned and other various exemplary embodiments of the inventive concept will become more apparent to those of ordinary skill in the art to which the present disclosure pertains.

[0008] According to various exemplary embodiments of the inventive concept, there is provided a semiconductor device including: a first interlayer insulating layer; an insulating pattern extending in a first horizontal direction on an upper surface of the first interlayer insulating layer; a first plurality of nanosheets stacked vertically and spaced apart from each other on the insulating pattern; a second plurality of nanosheets stacked vertically and spaced apart from each other on the insulating pattern, the second plurality of nanosheets being spaced apart from the first plurality of nanosheets in the first horizontal direction; a first gate electrode extending in a second horizontal direction different from the first horizontal direction on the insulating pattern, the first gate electrode surrounding the first plurality of nanosheets; a second gate electrode extending in the second horizontal direction on the insulating pattern, the second gate electrode surrounding the second plurality of nanosheets, the second gate electrode being spaced apart from the first gate electrode in the first horizontal direction; a source / drain region on the insulating pattern between the first gate electrode and the second gate electrode; a source / drain contact portion penetrating the first interlayer insulating layer and the insulating pattern in a vertical direction, the source / drain contact portion being electrically connected to the source / drain region; and a gate contact portion penetrating the first interlayer insulating layer and the insulating pattern in a vertical direction, the gate contact portion being electrically connected to the second gate electrode, at least a part of a sidewall of the gate contact portion being in contact with the source / drain contact portion. The source / drain contact portion and the gate contact portion are integrally formed.

[0009] According to various exemplary embodiments of the inventive concept, there is provided a semiconductor device including: a first interlayer insulating layer; an insulating pattern extending in a first horizontal direction on an upper surface of the first interlayer insulating layer; a plurality of nanosheets stacked vertically and spaced apart from each other on the insulating pattern; a gate electrode extending in a second horizontal direction different from the first horizontal direction on the insulating pattern, the gate electrode surrounding the plurality of nanosheets; a source / drain region on at least one side of the gate electrode on the insulating pattern; a source / drain contact portion penetrating the first interlayer insulating layer and the insulating pattern in a vertical direction, the source / drain contact portion being electrically connected to the source / drain region; a gate contact portion penetrating the first interlayer insulating layer and the insulating pattern in a vertical direction, the gate contact portion being electrically connected to the gate electrode; a second interlayer insulating layer on a bottom surface of the first interlayer insulating layer; and a bottom via in the second interlayer insulating layer, the bottom via being in contact with each of a bottom surface of the source / drain contact portion and a bottom surface of the gate contact portion. The bottom via is integrally formed with each of the source / drain contact portion and the gate contact portion.

[0010] According to various exemplary embodiments of the inventive concept, a semiconductor device is provided, including: a first interlayer insulating layer; an insulating pattern extending in a first horizontal direction on an upper surface of the first interlayer insulating layer; a first plurality of nanosheets stacked vertically spaced apart from each other on the insulating pattern; a second plurality of nanosheets stacked vertically spaced apart from each other on the insulating pattern, the second plurality of nanosheets being spaced apart from the first plurality of nanosheets in the first horizontal direction; a third plurality of nanosheets stacked vertically spaced apart from each other on the insulating pattern, the third plurality of nanosheets being spaced apart from the second plurality of nanosheets in the first horizontal direction; a first gate electrode extending in a second horizontal direction different from the first horizontal direction on the insulating pattern, the first gate electrode surrounding the first plurality of nanosheets; a second gate electrode extending in the second horizontal direction on the insulating pattern, the second gate electrode surrounding the second plurality of nanosheets, the second gate electrode being spaced apart from the first gate electrode in the first horizontal direction; a third gate electrode extending in the second horizontal direction on the insulating pattern, the third gate electrode surrounding the third plurality of nanosheets, the third gate electrode being spaced apart from the second gate electrode in the first horizontal direction; a first source / drain region on the insulating pattern between the first gate electrode and the second gate electrode; a second source / drain region on the insulating pattern between the second gate electrode and the third gate electrode; an upper interlayer insulating layer covering each of the first source / drain region and the second source / drain region; a first source / drain contact portion penetrating the upper interlayer insulating layer in a vertical direction, the first source / drain contact portion being electrically connected to the first source / drain region; a second source / drain contact portion penetrating the first interlayer insulating layer and the insulating pattern in a vertical direction, the second source / drain contact portion being electrically connected to the second source / drain region; a gate contact portion penetrating the first interlayer insulating layer and the insulating pattern in a vertical direction, the gate contact portion being electrically connected to the second gate electrode, at least a part of a sidewall of the gate contact portion being in contact with the second source / drain contact portion. The second source / drain contact portion and the gate contact portion are integrally formed.

[0011] It should be noted that the effects of various exemplary embodiments of the inventive concept are not limited to the above effects, and other effects of the present disclosure will be apparent from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other various exemplary embodiments and features of the inventive concept will become more apparent by describing in detail various exemplary embodiments of the present invention with reference to the accompanying drawings, in which:

[0013] Figure 1 is a layout diagram of a semiconductor device for explaining some exemplary embodiments according to the inventive concept;

[0014] Figure 2 is taken along Figure 1 line A-A' of;

[0015] Figure 3 is taken along Figure 1A cross-sectional view taken along line B-B';

[0016] Figure 4 is a cross-sectional view taken along Figure 1 line C-C';

[0017] Figures 5 to 41 is a cross-sectional view for explaining a method of manufacturing a semiconductor device according to some example embodiments of the inventive concept;

[0018] Figures 42 to 44 is a cross-sectional view of a semiconductor device according to some example embodiments of the inventive concept;

[0019] Figures 45 to 47 is a cross-sectional view of a semiconductor device according to some example embodiments of the inventive concept;

[0020] Figures 48 to 50 is a cross-sectional view of a semiconductor device according to some example embodiments of the inventive concept;

[0021] Figure 51 is a cross-sectional view of a semiconductor device according to some example embodiments of the inventive concept;

[0022] Figure 52 is a cross-sectional view of a semiconductor device according to some example embodiments of the inventive concept;

[0023] Figure 53 is a cross-sectional view of a semiconductor device according to some example embodiments of the inventive concept. DETAILED DESCRIPTION

[0024] Some example embodiments of a semiconductor device according to the inventive concept are illustrated in the drawings and include a multi-bridge-channel field-effect transistor (MBCFET TM ) having nanosheets, but the present disclosure is not limited thereto. In other example embodiments, a semiconductor device according to some example embodiments of the inventive concept may include a fin-type field-effect transistor (FinFET), a tunneling field-effect transistor (FET), or a three-dimensional (3D) transistor having a fin-shaped patterned channel region. Additionally, in other example embodiments, a semiconductor device according to some example embodiments of the inventive concept may include a bipolar junction transistor or a lateral double-diffused metal oxide semiconductor (LDMOS) transistor.

[0025] Hereinafter, a semiconductor device according to some example embodiments of the inventive concept will be described with reference to Figures 1 to 4 the following.

[0026] Figure 1 is a layout diagram of a semiconductor device according to some example embodiments of the inventive concept. Figure 2is taken along Figure 1 sectional view taken along line A-A'. Figure 3 is taken along Figure 1 sectional view taken along line B-B'. Figure 4 is taken along Figure 1 sectional view taken along line C-C'.

[0027] Referring to Figures 1 to 4 , semiconductor devices according to some example embodiments of the inventive concept include a first interlayer insulating layer 100, an insulating pattern 101, a first sacrificial pattern 103, a field insulating layer 105, a first plurality of nanosheets NW1, a second plurality of nanosheets NW2, a third plurality of nanosheets NW3, a first gate electrode G1, a second gate electrode G2, a third gate electrode G3, a first gate spacer 111, a second gate spacer 112, and a third gate spacer 113, a first gate insulating layer 121, a second gate insulating layer 122, and a third gate insulating layer 123, a first capping pattern 131, a second capping pattern 132, and a third capping pattern 133, a first source / drain region SD1 and a second source / drain region SD2, a first etch stop layer 140, a first upper interlayer insulating layer 145, a second lower interlayer insulating layer 150, a first source / drain contact CA1 and a second source / drain contact CA2, a first silicide layer SL1 and a second silicide layer SL2, a gate contact CB, a bottom via BV, a second etch stop layer 160, a second upper interlayer insulating layer 165, and an upper via UV.

[0028] The first interlayer insulating layer 100 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a low-k material. The low-k material may be formed by a semiconductor manufacturing process and may be, for example, tetraethyl orthosilicate fluoride (FTEOS), hydrogen silsesquioxane (HSQ), bisbenzocyclobutene (BCB), tetramethyl orthosilicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilyl borate (TMSB), diacetoxyditert-butoxysilane (DADBS), trimethylsilyl phosphate (TMSP), polytetrafluoroethylene (PTFE), carbon-silicon (TOSZ), fluorosilicate glass (FSG), polyimide nanofoam (such as polypropylene oxide), carbon-doped silicon oxide (CDO), organosilicate glass (OSG), SiLK, amorphous fluorocarbon, silica aerogel, silica xerogel, mesoporous silica, or a combination thereof, but example embodiments are not limited thereto.

[0029] The first horizontal direction DR1 and the second horizontal direction DR2 may be defined as directions parallel to the upper surface 100a of the first interlayer insulating layer 100. The second horizontal direction DR2 may be defined as a direction different from the first horizontal direction DR1. The vertical direction DR3 is defined as a direction perpendicular to each of the first horizontal direction DR1 and the second horizontal direction DR2. That is, the vertical direction DR3 is defined as a direction perpendicular to the upper surface 100a of the first interlayer insulating layer 100.

[0030] The insulating pattern 101 may extend along the first horizontal direction DR1 on the upper surface 100a of the first interlayer insulating layer 100. The insulating pattern 101 may protrude from the upper surface 100a of the first interlayer insulating layer 100 in the vertical direction DR3. The insulating pattern 101 may include an insulating material. For example, the insulating pattern 101 may include the same material as the first interlayer insulating layer 100.

[0031] The field insulating layer 105 may be disposed on the upper surface 100a of the first interlayer insulating layer 100. The field insulating layer 105 may surround the sidewalls of the insulating pattern 101. For example, the upper surface of the insulating pattern 101 may protrude in the vertical direction DR3 beyond the upper surface of the field insulating layer 105, but the exemplary embodiments are not limited thereto. In other exemplary embodiments, the upper surface of the insulating pattern 101 may be formed in the same plane as the upper surface of the field insulating layer 105. The field insulating layer 105 may include, for example, an oxide film, a nitride film, a nitrogen oxide film, or a combination thereof.

[0032] The first plurality of nanosheets NW1 may be disposed on the insulating pattern 101. The first plurality of nanosheets NW1 may be disposed at the intersection of the insulating pattern 101 and the first gate electrode G1. The second plurality of nanosheets NW2 may be disposed on the insulating pattern 101. The second plurality of nanosheets NW2 may be disposed at the intersection of the insulating pattern 101 and the second gate electrode G2. The second plurality of nanosheets NW2 may be spaced apart from the first plurality of nanosheets NW1 in the first horizontal direction DR1. The third plurality of nanosheets NW3 may be disposed on the insulating pattern 101. The third plurality of nanosheets NW3 may be disposed at the intersection of the insulating pattern 101 and the third gate electrode G3. The third plurality of nanosheets NW3 may be spaced apart from the second plurality of nanosheets NW2 in the first horizontal direction DR1.

[0033] The first plurality of nanosheets NW1, the second plurality of nanosheets NW2, and the third plurality of nanosheets NW3 may include nanosheet stacks spaced apart from each other in the vertical direction DR3. In Figure 2 and Figure 3In [the figure], the first plurality of nanosheets NW1, the second plurality of nanosheets NW2, and the third plurality of nanosheets NW3 are shown as a stack of three nanosheets spaced apart from each other in the vertical direction DR3, but the exemplary embodiments are not limited thereto. Alternatively, in some exemplary embodiments, the first plurality of nanosheets NW1, the second plurality of nanosheets NW2, and the third plurality of nanosheets NW3 may include a stack of four or more nanosheets spaced apart from each other in the vertical direction DR3. For example, the first plurality of nanosheets NW1, the second plurality of nanosheets NW2, and the third plurality of nanosheets NW3 may include silicon (Si), but the exemplary embodiments are not limited thereto. Alternatively, in some exemplary embodiments, the first plurality of nanosheets NW1, the second plurality of nanosheets NW2, and the third plurality of nanosheets NW3 may include silicon germanium (SiGe).

[0034] The first gate electrode G1 may extend along the second horizontal direction DR2 on the insulating pattern 101 and the field insulating layer 105. The first gate electrode G1 may surround the first plurality of nanosheets NW1. The second gate electrode G2 may extend along the second horizontal direction DR2 on the insulating pattern 101 and the field insulating layer 105. The second gate electrode G2 may surround the second plurality of nanosheets NW2. The second gate electrode G2 may be spaced apart from the first gate electrode G1 in the first horizontal direction DR1. The third gate electrode G3 may extend along the second horizontal direction DR2 on the insulating pattern 101 and the field insulating layer 105. The third gate electrode G3 may surround the third plurality of nanosheets NW3. The third gate electrode G3 may be spaced apart from the second gate electrode G2 in the first horizontal direction DR1.

[0035] The first gate electrode G1, the second gate electrode G2, and the third gate electrode G3 may include, for example, at least one of titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V) or a combination thereof. However, the exemplary embodiments are not limited thereto. The first gate electrode G1, the second gate electrode G2, and the third gate electrode G3 may include a conductive metal oxide or a conductive metal nitride oxide, and may also include an oxidized form of any of the above materials.

[0036] The first gate spacer 111 may extend along two sidewalls of the first gate electrode G1 in a second horizontal direction DR2 on both the upper surface of the upper first nanosheet NW1 and the field insulating layer 105. The second gate spacer 112 may extend along two sidewalls of the second gate electrode G2 in a second direction on both the upper surface of the topmost nanosheet of the second plurality of nanosheets NW2 and the field insulating layer 105. The third gate spacer 113 may extend along two sidewalls of the third gate electrode G3 in a second direction on both the upper surface of the topmost nanosheet of the second plurality of nanosheets NW3 and the field insulating layer 105.

[0037] The first gate spacer 111, the second gate spacer 112, and the third gate spacer 113 may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon dioxide (SiO2), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof, but the exemplary embodiments are not limited thereto.

[0038] The first source / drain region SD1 may be disposed on both sides of the first gate electrode G1 on the insulating pattern 101. For example, the first source / drain region SD1 may be disposed between the first gate electrode G1 and the second gate electrode G2 on the insulating pattern 101. The second source / drain region SD2 may be disposed on both sides of the third gate electrode G3 on the insulating pattern 101. For example, the second source / drain region SD2 may be disposed between the second gate electrode G2 and the third gate electrode G3 on the insulating pattern 101.

[0039] The first source / drain region SD1 and the second source / drain region SD2 may be in contact with the insulating pattern 101. The first source / drain region SD1 may be in contact with sidewalls of the first plurality of nanosheets NW1 and the second plurality of nanosheets NW2 in a first horizontal direction DR1. The second source / drain region SD2 may be in contact with sidewalls of the second plurality of nanosheets NW2 and the third plurality of nanosheets NW3 in a first horizontal direction DR1. For example, upper surfaces of the first source / drain region SD1 and the second source / drain region SD2 may be formed higher than upper surfaces of the topmost nanosheets of each of the first plurality of nanosheets NW1, the second plurality of nanosheets NW2, and the third plurality of nanosheets NW3.

[0040] The first sacrificial pattern 103 may penetrate the first interlayer insulating layer 100 and the insulating pattern 101 in the vertical direction DR3. For example, the upper surface of the first sacrificial pattern 103 may contact the bottom surface of the first source / drain region SD1. The bottom surface of the first sacrificial pattern 103 may be formed on the same plane as the bottom surface 100b of the first interlayer insulating layer 100. The first sacrificial pattern 103 may include a material different from that of each of the first interlayer insulating layer 100 and the insulating pattern 101. For example, the first sacrificial pattern 103 may include SiGe. In other exemplary embodiments, the first sacrificial pattern 103 may include a low-k material different from the low-k materials of each of the first interlayer insulating layer 100 and the insulating pattern 101.

[0041] The first gate insulating layer 121 may be disposed between the first gate electrode G1 and the insulating pattern 101. The first gate insulating layer 121 may also be disposed between the first gate electrode G1 and the field insulating layer 105. The first gate insulating layer 121 may also be disposed between the first gate electrode G1 and the first gate spacer 111. The first gate insulating layer 121 may also be disposed between the first gate electrode G1 and the first plurality of nanosheets NW1. The first gate insulating layer 121 may also be disposed between the first gate electrode G1 and the first source / drain region SD1.

[0042] The second gate insulating layer 122 may be disposed between the second gate electrode G2 and the insulating pattern 101. The second gate insulating layer 122 may also be disposed between the second gate electrode G2 and the field insulating layer 105. The second gate insulating layer 122 may also be disposed between the second gate electrode G2 and the second gate spacer 112. The second gate insulating layer 122 may also be disposed between the second gate electrode G2 and the second plurality of nanosheets NW2. The second gate insulating layer 122 may also be disposed between the second gate electrode G2 and the first source / drain region SD1 and the second source / drain region SD2.

[0043] The third gate insulating layer 123 may be disposed between the third gate electrode G3 and the insulating pattern 101. The third gate insulating layer 123 may also be disposed between the third gate electrode G3 and the field insulating layer 105. The third gate insulating layer 123 may also be disposed between the third gate electrode G3 and the third gate spacer 113. The third gate insulating layer 123 may also be disposed between the third gate electrode G3 and the third plurality of nanosheets NW3. The third gate insulating layer 123 may also be disposed between the third gate electrode G3 and the second source / drain region SD2.

[0044] The first gate insulating layer 121, the second gate insulating layer 122, and the third gate insulating layer 123 may be in contact with the insulating pattern 101. For example, the first gate insulating layer 121 and the second gate insulating layer 122 may be in contact with the first source / drain region SD1, and the second gate insulating layer 122 and the third gate insulating layer 123 may be in contact with the second source / drain region SD2. However, the exemplary embodiments are not limited thereto. Alternatively, in some exemplary embodiments, an internal spacer may be disposed between the first source / drain region SD1 and the first gate insulating layer 121 and the second gate insulating layer 122. Similarly, an internal spacer may be disposed between the second source / drain region SD2 and the second gate insulating layer 122 and the third gate insulating layer 123. These internal spacers may include at least one of, for example, SiN, SiON, SiO2, SiOCN, SiBN, SiOBN, SiOC, and combinations thereof. However, the exemplary embodiments are not limited thereto.

[0045] The first gate insulating layer 121, the second gate insulating layer 122, and the third gate insulating layer 123 may include at least one of silicon oxide, silicon oxynitride, silicon nitride, and a high-k material having a dielectric constant greater than that of silicon oxide. The high-k material may include at least one of, for example, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. However, the exemplary embodiments are not limited thereto.

[0046] A semiconductor device according to some exemplary embodiments of the present inventive concept may include a negative capacitance (NC) FET using a negative capacitor. For example, each of the first gate insulating layer 121, the second gate insulating layer 122, and the third gate insulating layer 123 may include a ferroelectric material film having ferroelectric properties and a paraelectric material film having paraelectric properties.

[0047] The ferroelectric material film may have a negative capacitance, and the paraelectric material film may have a positive capacitance. For example, if two or more capacitors are connected in series and have positive capacitances, the total capacitance of the two or more capacitors may be lower than the capacitance of each of the two or more capacitors. Conversely, if at least one of the two or more capacitors has a negative capacitance, the total capacitance of the two or more capacitors may have a positive value and may be greater than the absolute value of the capacitance of each of the two or more capacitors.

[0048] If a ferroelectric material film having a negative capacitance and a paraelectric material film having a positive capacitance are connected in series, the total capacitance of the ferroelectric material film and the paraelectric material film may increase. Accordingly, a transistor having a ferroelectric material film may have a subthreshold swing (SS) of less than 60 mV / decade at room temperature.

[0049] The ferroelectric material film may have ferroelectric properties. The ferroelectric material film may include at least one of, for example, hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanate, and lead zirconium titanate. For example, hafnium zirconium oxide may be a material obtained by doping hafnium oxide with zirconium (Zr). However, the exemplary embodiments are not limited thereto. In another example, hafnium zirconium oxide may be a compound of hafnium (Hf), Zr, and oxygen (O).

[0050] The ferroelectric material film may further include a dopant. For example, the dopant may include at least one of Al, Ti, Nb, lanthanum (La), yttrium (Y), magnesium (Mg), silicon, calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), Ge, scandium (Sc), strontium (Sr), and tin (Sn). However, the exemplary embodiments are not limited thereto. The type of dopant may vary according to the material type of the ferroelectric material film.

[0051] If the ferroelectric material film includes hafnium oxide, the dopant of the ferroelectric material film may include at least one of, for example, Gd, Si, Zr, Al, and Y. However, the exemplary embodiments are not limited thereto.

[0052] If the dopant of the ferroelectric material film is Al, the ferroelectric material film may include about 3 atomic percent (at%) to about 8 at% of Al. Here, the ratio of the dopant in the ferroelectric material film may refer to the ratio of the sum of the amounts of Hf and Al to the amount of Al in the ferroelectric material film.

[0053] If the dopant of the ferroelectric material film is Si, the ferroelectric material film may include about 2 at% to about 10 at% of Si. If the dopant of the ferroelectric material film is Y, the ferroelectric material film may include about 2 at% to about 10 at% of Y. If the dopant of the ferroelectric material film is Gd, the ferroelectric material film may include about 1 at% to about 7 at% of Gd. If the dopant of the ferroelectric material film is Zr, the ferroelectric material film may include about 50 at% to about 80 at% of Zr.

[0054] The paraelectric material film may include paraelectric properties. The paraelectric material film may include at least one of, for example, silicon oxide and high-k metal oxides. The high-k metal oxides may include at least one of, for example, hafnium oxide, zirconium oxide, and aluminum oxide, but the exemplary embodiments are not limited thereto.

[0055] The ferroelectric material film and the paraelectric material film may include the same material. The ferroelectric material film may have ferroelectric properties, but the paraelectric material film may not have ferroelectric properties. For example, if the ferroelectric material film and the paraelectric material film include hafnium oxide, the hafnium oxide included in the ferroelectric material film may have a crystal structure different from that of the hafnium oxide included in the paraelectric material film.

[0056] The ferroelectric material film can be thick enough to exhibit ferroelectric properties. The thickness of the ferroelectric material film can be, for example, about 0.5 nm to about 10 nm, but the exemplary embodiments are not limited thereto. The critical thickness capable of exhibiting ferroelectric properties can vary depending on the type of ferroelectric material. Thus, the thickness of the ferroelectric material film can vary according to the type of ferroelectric material included in the ferroelectric material film.

[0057] For example, each of the first gate insulating layer 121, the second gate insulating layer 122, and the third gate insulating layer 123 may include a ferroelectric material film. In another example, each of the first gate insulating layer 121, the second gate insulating layer 122, and the third gate insulating layer 123 may include a plurality of ferroelectric material films spaced apart from each other. Each of the first gate insulating layer 121, the second gate insulating layer 122, and the third gate insulating layer 123 may include a stack of a plurality of ferroelectric material films and a plurality of paraelectric material films alternately stacked with the ferroelectric material films.

[0058] The first etch stop layer 140 may be disposed on sidewalls of the first gate spacer 111, the second gate spacer 112, and the third gate spacer 113 in the first horizontal direction DR1. The first etch stop layer 140 may also be disposed on the upper surface of the field insulating layer 105. The first etch stop layer 140 may also be disposed on sidewalls of the first source / drain region SD1 and the second source / drain region SD2 in the second horizontal direction DR2. The first etch stop layer 140 may also be disposed on the upper surfaces of the first source / drain region SD1 and the second source / drain region SD2. For example, the first etch stop layer 140 may be conformally formed. The first etch stop layer 140 may include, for example, at least one of alumina, aluminum nitride, hafnium oxide, zirconium oxide, silicon oxide, silicon nitride, silicon oxynitride, and a low-k material. However, the exemplary embodiments are not limited thereto.

[0059] The first capping pattern 131 may extend in the second horizontal direction DR2 above the first gate spacer 111, the first gate insulating layer 121, and the first gate electrode G1. The second capping pattern 132 may extend in the second horizontal direction DR2 above the second gate spacer 112, the second gate insulating layer 122, and the second gate electrode G2. The third capping pattern 133 may extend in the second horizontal direction DR2 above the third gate spacer 113, the third gate insulating layer 123, and the third gate electrode G3.

[0060] For example, the bottom surfaces of the first capping pattern 131, the second capping pattern 132, and the third capping pattern 133 may be in contact with the first etch stop layer 140, but the exemplary embodiments are not limited thereto. In other exemplary embodiments, the sidewalls of the first capping pattern 131, the second capping pattern 132, and the third capping pattern 133 may also be in contact with the first etch stop layer 140. The first etch stop layer 140 may include, for example, at least one of SiN, SiON, SiO2, SiCN, SiOCN, and combinations thereof, but the exemplary embodiments are not limited thereto.

[0061] The first interlayer insulating layer 145 may be disposed on the first etch stop layer 140. The first interlayer insulating layer 145 may also be disposed on the sidewalls of each of the first capping pattern 131, the second capping pattern 132, and the third capping pattern 133. The first interlayer insulating layer 145 may cover the first source / drain regions SD1 and SD2 on the field insulating layer 105. For example, the upper surface of the first interlayer insulating layer 145 may be formed in the same plane as the upper surfaces of the first capping pattern 131, the second capping pattern 132, and the third capping pattern 133. The first interlayer insulating layer 145 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and low-k materials.

[0062] The first source / drain contact CA1 may be disposed between the first gate electrode G1 and the second gate electrode G2. The first source / drain contact CA1 may be disposed above the first source / drain region SD1. The first source / drain contact CA1 may extend into the first source / drain region SD1 by penetrating the first interlayer insulating layer 145 and the first etch stop layer 140 in the vertical direction DR3. The first source / drain contact CA1 may be electrically connected to the first source / drain region SD1. In Figure 2 the first source / drain contact CA1 is shown as a single layer, but the exemplary embodiments are not limited thereto. Alternatively, in some exemplary embodiments, the first source / drain contact CA1 may be formed as a multi-layer.

[0063] For example, the upper surface of the first source / drain contact CA1 may be formed in the same plane as the upper surface of the first interlayer insulating layer 145, but the exemplary embodiments are not limited thereto. Alternatively, in some exemplary embodiments, the upper surface of the first source / drain contact CA1 may be formed to be higher than the upper surface of the first interlayer insulating layer 145. The first source / drain contact CA1 may include a conductive material.

[0064] The first silicide layer SL1 may be disposed between the first source / drain contact CA1 and the first source / drain region SD1. The first silicide layer SL1 may be disposed along the boundary between the first source / drain contact CA1 and the first source / drain region SD1. The first silicide layer SL1 may include, for example, a metal silicide material.

[0065] The second source / drain contact portion CA2 may be disposed between the second gate electrode G2 and the third gate electrode G3. The second source / drain contact portion CA2 may be disposed under the second source / drain region SD2. The second source / drain contact portion CA2 may be connected to the second source / drain region SD2 by penetrating the first interlayer insulating layer 100 and the insulating pattern 101 in the vertical direction DR3. The second source / drain contact portion CA2 may be electrically connected to the second source / drain region SD2. For example, the second source / drain contact portion CA2 may be formed as a single layer.

[0066] For example, the upper surface of the second source / drain contact portion CA2 may be formed to be lower than the bottom surface of the lowermost nanosheet of the third plurality of nanosheets NW3. The bottom surface of the second source / drain contact portion CA2 may be formed in the same plane as the bottom surface 100b of the first interlayer insulating layer 100. The second source / drain contact portion CA2 may include a conductive material. For example, the second source / drain contact portion CA2 may include one of Al, W, Co, Ru, and Mo. However, the exemplary embodiments are not limited thereto.

[0067] The second silicide layer SL2 may be disposed between the second source / drain contact portion CA2 and the second source / drain region SD2. The second silicide layer SL2 may be disposed along the boundary between the second source / drain contact portion CA2 and the second source / drain region SD2. The second silicide layer SL2 may include, for example, a metal silicide material.

[0068] The gate contact portion CB may be disposed under the third gate electrode G3. The gate contact portion CB may be in contact with the third gate insulating layer 123 by penetrating the first interlayer insulating layer 100 and the insulating pattern 101 in the vertical direction DR3. That is, at least a part of the third gate insulating layer 123 may be disposed between the third gate electrode G3 and the gate contact portion CB. The gate contact portion CB may be electrically connected to the third gate electrode G3. For example, the gate contact portion CB may be formed as a single layer.

[0069] For example, the upper surface of the gate contact portion CB may be formed to be higher than the upper surface of the second source / drain contact portion CA2. The bottom surface of the gate contact portion CB may be formed in the same plane as the bottom surface of the second source / drain contact portion CA2 and the bottom surface 100b of the first interlayer insulating layer 100. At least a part of the sidewall of the gate contact portion CB in the first horizontal direction DR1 may be in contact with the second source / drain contact portion CA2. At least a part of the insulating pattern 101 may be disposed between the gate contact portion CB and the second source / drain contact portion CA2. At least a part of the insulating pattern 101 between the gate contact portion CB and the second source / drain contact portion CA2 may be in contact with the second source / drain region SD2 and the third gate insulating layer 123.

[0070] For example, the gate contact CB and the second source / drain contact CA2 may be integrally formed. The gate contact CB may include the same material as the second source / drain contact CA2. For example, the gate contact CB may include one of Al, W, Co, Ru, and Mo. However, the exemplary embodiments are not limited thereto.

[0071] The second interlayer insulating layer 150 may be disposed on the bottom surface 100b of the first interlayer insulating layer 100. The second interlayer insulating layer 150 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a low-k material. The second interlayer insulating layer 150 may include a material different from that of the first interlayer insulating layer 100, but the exemplary embodiments are not limited thereto. Alternatively, in some exemplary embodiments, the second interlayer insulating layer 150 may include the same material as the first interlayer insulating layer 100.

[0072] The bottom via BV may be disposed in the second interlayer insulating layer 150. The upper surface of the bottom via BV may be in contact with the bottom surfaces of the second source / drain contact CA2 and the gate contact CB. That is, the bottom via BV may be connected to the second source / drain contact CA2 and the gate contact CB. For example, the bottom via BV may be formed as a single layer.

[0073] For example, the upper surface of the bottom via BV may be formed in the same plane as the upper surface of the second interlayer insulating layer 150. Similarly, the lower surface of the bottom via BV may be formed in the same plane as the lower surface of the second interlayer insulating layer 150. The bottom via BV, the second source / drain contact CA2, and the gate contact CB may be integrally formed. The bottom via BV may include the same material as the second source / drain contact CA2 and the gate contact CB. For example, the bottom via BV may include one of Al, W, Co, Ru, and Mo. However, the exemplary embodiments are not limited thereto.

[0074] The second etch stop layer 160 may be disposed on the upper surfaces of the first source / drain contact CA1, the first capping pattern 131, the second capping pattern 132, the third capping pattern 133, and the first interlayer insulating layer 145. In Figures 2 to 4 which, the second etch stop layer 160 is shown as a single layer, but the exemplary embodiments are not limited thereto. Alternatively, in some exemplary embodiments, the second etch stop layer 160 may be formed as a multi-layer. The second etch stop layer 160 may include at least one of, for example, aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, silicon oxide, silicon nitride, silicon oxynitride, and a low-k material. However, the exemplary embodiments are not limited thereto.

[0075] The second upper interlayer insulating layer 165 may be disposed on the second etch stop layer 160. The second upper interlayer insulating layer 165 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a low-k material. However, the exemplary embodiments are not limited thereto. The upper via UV may be connected to the first source / drain contact CA1 by penetrating the second upper interlayer insulating layer 165 and the second etch stop layer 160 in the vertical direction DR3. In Figure 2 the upper via UV is shown as a single layer, but the exemplary embodiments are not limited thereto. Alternatively, in some exemplary embodiments, the upper via UV may be formed as a multi-layer. The upper via UV may include a conductive material.

[0076] A method of manufacturing a semiconductor device according to some exemplary embodiments will be described below with reference to Figures 2 to 41 FIGs.

[0077] Figures 5 to 41 is a cross-sectional view for explaining a method of manufacturing a semiconductor device according to some exemplary embodiments of the present inventive concept.

[0078] Referring to Figure 5 and Figure 6 , a substrate 10 may be provided. The substrate 10 may be a silicon or silicon-on-insulator (SOI) substrate, but the exemplary embodiments are not limited thereto. The substrate 10 may further include materials such as SiGe, silicon-germanium-on-insulator (SGOI), indium antimonide, lead telluride compounds, indium arsenide, indium phosphide, gallium antimonide, or gallium arsenide antimonide, but the exemplary embodiments are not limited thereto.

[0079] Subsequently, a stacked structure 20 may be formed on the upper surface of the substrate 10. The stacked structure 20 may include a first semiconductor layer 21 and a second semiconductor layer 22 alternately stacked on the upper surface of the substrate 10. For example, one of the first semiconductor layers 21 may be formed at the bottom of the stacked structure 20, and one of the second semiconductor layers 22 may be formed at the top of the stacked structure 20. However, the exemplary embodiments are not limited to this example. Alternatively, in some exemplary embodiments, the first semiconductor layer 21 may also be formed at the top of the stacked structure 20. The first semiconductor layer 21 may include, for example, SiGe. The second semiconductor layer 22 may include, for example, Si.

[0080] Subsequently, a portion of the stacked structure 20 may be etched. In the process of etching the stacked structure 20, a portion of the substrate 10 may also be etched. Accordingly, an active pattern 11 may be defined on the upper surface of the substrate 10 below the stacked structure 20. The active pattern 11 may protrude from the upper surface of the substrate 10 in the vertical direction DR3. The active pattern 11 may extend in the first horizontal direction DR1.

[0081] Subsequently, a field insulating layer 105 may be formed on the upper surface of the substrate 10. The field insulating layer 105 may surround the sidewalls of the active pattern 11. For example, the upper surface of the active pattern 11 may be formed to be higher than the upper surface of the field insulating layer 105. Subsequently, a pad oxide layer 30 may be formed to cover the upper surface of the field insulating layer 105, the exposed sidewalls of the active pattern 11, and the sidewalls and upper surface of the stacked structure 20. For example, the pad oxide layer 30 may be conformally formed. The pad oxide layer 30 may include, for example, SiO2.

[0082] Referring Figure 7 and Figure 8 , a first dummy gate DG1, a second dummy gate DG2, and a third dummy gate DG3 extending in the second horizontal direction DR2, and a first dummy capping pattern DC1, a second dummy capping pattern DC2, and a third dummy capping pattern DC3 may be formed on the pad oxide layer 30 above both the stacked structure 20 and the field insulating layer 105. Specifically, the second dummy gate DG2 may be spaced apart from the first dummy gate DG1 in the first horizontal direction DR1. The third dummy gate DG3 may be spaced apart from the second dummy gate DG2 in the first horizontal direction DR1. The first dummy capping pattern DC1 may be disposed on the first dummy gate DG1. The second dummy capping pattern DC2 may be disposed on the second dummy gate DG2. The third dummy capping pattern DC3 may be disposed on the third dummy gate DG3.

[0083] In the formation process of the first dummy gate DG1, the second dummy gate DG2, the third dummy gate DG3, the first dummy capping pattern DC1, the second dummy capping pattern DC2, and the third dummy capping pattern DC3, the entire pad oxide layer 30 on the substrate 10 may be removed except for the portions overlapping with the first dummy gate DG1, the second dummy gate DG2, and the third dummy gate DG3 in the vertical direction DR3.

[0084] Subsequently, a spacer material layer SM may be formed to cover the sidewalls of the first dummy gate DG1, the second dummy gate DG2, and the third dummy gate DG3, the sidewalls and upper surface of the first dummy capping pattern DC1, the second dummy capping pattern DC2, and the third dummy capping pattern DC3, the exposed sidewalls and upper surface of the stacked structure 20, and the upper surface of the field insulating layer 105. For example, the spacer material layer SM may be conformally formed. The spacer material layer SM may include at least one of, for example, SiN, SiON, SiO2, SiOCN, SiBN, SiOBN, SiOC, and combinations thereof. However, the exemplary embodiments are not limited thereto.

[0085] Referring Figures 9 to 11, the first dummy gate DG1, the second dummy gate DG2, and the third dummy gate DG3, as well as the first dummy capping pattern DC1, the second dummy capping pattern DC2, and the third dummy capping pattern DC3 can be used as masks to etch Figure 7 and Figure 8 of the stacked structure 20, thereby forming a first source / drain trench ST1 and a second source / drain trench ST2. The first source / drain trench ST1 can be formed between the first dummy gate DG1 and the second dummy gate DG2, and the second source / drain trench ST2 can be formed between the second dummy gate DG2 and the third dummy gate DG3.

[0086] In addition, a first sacrificial pattern trench 103T can be formed under the first source / drain trench ST1, and a second sacrificial pattern trench 104T can be formed under the second source / drain trench ST2. The first sacrificial pattern trench 103T and the second sacrificial pattern trench 104T are respectively formed in the active pattern 11 and the substrate 10. The substrate 10 can be exposed at the bottoms of the first sacrificial pattern trench 103T and the second sacrificial pattern trench 104T.

[0087] In the process of forming the first source / drain trench ST1 and the second source / drain trench ST2, the Figure 7 and Figure 8 portion of the spacer material layer SM on the upper surfaces of the first dummy capping pattern DC1, the second dummy capping pattern DC2, and the third dummy capping pattern DC3, as well as portions of the first dummy capping pattern DC1, the second dummy capping pattern DC2, and the third dummy capping pattern DC3 can be removed. The portions of the spacer material layer SM remaining on the sidewalls of the first dummy gate DG1, the second dummy gate DG2, and the third dummy gate DG3 and on the sidewalls of the first dummy capping pattern DC1, the second dummy capping pattern DC2, and the third dummy capping pattern DC3 can be defined as a first gate spacer 111, a second gate spacer 112, and a third gate spacer 113.

[0088] For example, after forming the first source / drain trench ST1 and the second source / drain trench ST2, Figure 7 and Figure 8 the remaining portion of the second semiconductor layer 22 in

[0089] under the first dummy gate DG1 on the active pattern 11 can be defined as a first plurality of nanosheets NW1. Similarly, after forming the first source / drain trench ST1 and the second source / drain trench ST2, the remaining portion of the second semiconductor layer 22 under the second dummy gate DG2 on the active pattern 11 can be defined as a second plurality of nanosheets NW2, and the remaining portion of the second semiconductor layer 22 under the third dummy gate DG3 on the active pattern 11 can be defined as a third plurality of nanosheets NW3.

[0089] Refer toFigure 12 and Figure 13 , a first sacrificial pattern 103 can be formed in the first sacrificial pattern trench 103T of Figure 9 , and a second sacrificial pattern 104 can be formed in the second sacrificial pattern trench 104T of Figure 9 and Figure 11 . For example, the upper surfaces of the first sacrificial pattern 103 and the second sacrificial pattern 104 can be formed to be lower than the bottom surface of the lowermost first semiconductor layer 21. The first sacrificial pattern 103 and the second sacrificial pattern 104 can include, for example, SiGe. Alternatively, in some exemplary embodiments, the first sacrificial pattern 103 and the second sacrificial pattern 104 can further include a low-k material.

[0090] Subsequently, a first source / drain region SD1 can be formed in the first source / drain trench ST1 of Figure 9 , and a second source / drain region SD2 can be formed in the second source / drain trench ST2 of Figure 9 . For example, the bottom surface of the first source / drain region SD1 can be in contact with the upper surface of the first sacrificial pattern 103. Similarly, the bottom surface of the second source / drain region SD2 can be in contact with the upper surface of the second sacrificial pattern 104.

[0091] Referring to Figure 14 and Figure 15 , a first etch stop layer 140 can be formed on the exposed upper surface of the field insulating layer 105, on the exposed sidewalls of each of the first gate spacer 111, the second gate spacer 112, and the third gate spacer 113, Figure 12 on the exposed upper surfaces of the first dummy capping pattern DC1, the second dummy capping pattern DC2, and the third dummy capping pattern DC3 of Figure 12 , and on the exposed surfaces of the first source / drain region SD1 and the second source / drain region SD2. Thereafter, a first upper interlayer insulating layer 145 can be formed on the first etch stop layer 140. Thereafter, the upper surfaces of the first dummy gate DG1, the second dummy gate DG2, and the third dummy gate DG3 can be exposed by a planarization process.

[0092] Referring to Figure 16 and Figure 17 , the first dummy gate DG1, the second dummy gate DG2, and the third dummy gate DG3 of Figure 14 , the pad oxide layer 30 of Figure 14 , and the first semiconductor layer 21 of Figure 14 can be etched. Figure 14 The etched portions of the first dummy gate DG1, the pad oxide layer 30, and the first semiconductor layer 21 of Figure 14 can be defined as a first gate trench GT1. Similarly, Figure 14 the etched portions of the second dummy gate DG2, the pad oxide layer 30, and the first semiconductor layer 21 of Figure 14 can be defined as a second gate trench GT2.Figure 14 The third dummy gate DG3, the pad oxide layer 30, and the etched portions of the first semiconductor layer 21 may be defined as the third gate trench GT3.

[0093] Referring to Figure 18 and Figure 19 and, in the first gate trench GT1, a first gate insulating layer 121, a first gate electrode G1, and a first capping pattern 131 may be sequentially formed. Similarly, in the second gate trench GT2, a second gate insulating layer 122, a second gate electrode G2, and a second capping pattern 132 may be sequentially formed. Further, in the third gate trench GT3, a third gate insulating layer 123, a third gate electrode G3, and a third capping pattern 133 may be sequentially formed.

[0094] Referring to Figures 20 to 22 and, a first source / drain contact portion CA1 may be formed on the first source / drain region SD1. The first source / drain contact portion CA1 may extend into the interior of the first source / drain region SD1 by penetrating the first upper interlayer insulating layer 145 and the first etch stop layer 140 in a vertical direction DR3. Further, a first silicide layer SL1 may be formed between the first source / drain region SD1 and the first source / drain contact portion CA1.

[0095] Subsequently, a second etch stop layer 160 and a second upper interlayer insulating layer 165 may be sequentially formed on the upper surfaces of the first upper interlayer insulating layer 145, the first capping pattern 131, the second capping pattern 132, the third capping pattern 133, and the first source / drain contact portion CA1. Subsequently, an upper via UV may be formed, which is connected to the first source / drain contact portion CA1 by penetrating the second etch stop layer 160 and the second upper interlayer insulating layer 165 in a vertical direction DR3.

[0096] Referring to Figures 23 to 25 and, the substrate 10 and the active pattern 11 of Figures 20 to 22 may be etched. As a result, portions of the first gate insulating layer 121, the second gate insulating layer 122, and the third gate insulating layer 123, portions of the first source / drain region SD1 and the second source / drain region SD2, portions of the field insulating layer 105, and portions of the first sacrificial pattern 103 and the second sacrificial pattern 104 may be exposed.

[0097] Referring to Figures 26 to 28 and, a first lower interlayer insulating layer 100 and an insulating pattern 101 may be formed in the etched portions of the substrate 10 of Figures 20 to 22 and the active pattern 11 of Figures 20 to 22 . For example, the insulating pattern 101 may be formed in Figures 20 to 22in the etched portion of the active pattern 11. The insulating pattern 101 may be in contact with the first gate insulating layer 121, the second gate insulating layer 122, and the third gate insulating layer 123, the first source / drain region SD1 and the second source / drain region SD2, the field insulating layer 105, and the first sacrificial pattern 103 and the second sacrificial pattern 104. The insulating pattern 101 may surround a portion of the sidewalls of each of the first sacrificial pattern 103 and the second sacrificial pattern 104.

[0098] In addition, the first interlayer insulating layer 100 may be formed in Figures 20 to 22 the etched portion of the substrate 10. The first interlayer insulating layer 100 may be in contact with the field insulating layer 105 and the first sacrificial pattern 103 and the second sacrificial pattern 104. The first interlayer insulating layer 100 may surround the remaining sidewall portions of each of the first sacrificial pattern 103 and the second sacrificial pattern 104. For example, the bottom surfaces of the first sacrificial pattern 103 and the second sacrificial pattern 104 may be exposed on the bottom surface 100b of the first interlayer insulating layer 100. That is, the bottom surfaces of the first sacrificial pattern 103 and the second sacrificial pattern 104 may be formed in the same plane as the bottom surface 100b of the first interlayer insulating layer 100.

[0099] Referring to Figures 29 to 31 , the second interlayer insulating layer 150 may be formed on the bottom surface 100b of the first interlayer insulating layer 100 and the bottom surfaces of the first sacrificial pattern 103 and the second sacrificial pattern 104. Thereafter, a bottom via trench BVT may be formed in the second interlayer insulating layer 150. For example, the bottom via trench BVT may be formed under the second sacrificial pattern 104 and the third gate electrode G3. The bottom via trench BVT may expose the bottom surface 100b of the first interlayer insulating layer 100 and the bottom surface of the second sacrificial pattern 104.

[0100] Referring to Figure 32 and Figure 33 , the second sacrificial pattern 104 exposed by the bottom via trench BVT in Figure 29 may be etched away. The etched-away portion of the second sacrificial pattern 104 may be defined as the first contact trench CT1. In other words, the first contact trench CT1 may be formed on the bottom via trench BVT. The first contact trench CT1 may expose the bottom surface of the second source / drain region SD2.

[0101] Referring to Figures 34 to 36, a third sacrificial pattern 40 may be formed in the bottom via trench BVT and the first contact trench CT1. For example, the third sacrificial pattern 40 may completely fill the bottom via trench BVT and the first contact trench CT1. The third sacrificial pattern 40 may include a material different from that of the insulating pattern 101, the first interlayer insulating layer 100, and the second interlayer insulating layer 150. For example, the third sacrificial pattern 40 may include a spin-on hard mask (SOH). Alternatively, in some example embodiments, the third sacrificial pattern 40 may further include an insulating material different from the insulating materials of the insulating pattern 101, the first interlayer insulating layer 100, and the second interlayer insulating layer 150.

[0102] Referring to Figure 37 and Figure 38 , a second contact trench CT2 may be formed under the third gate electrode G3. The second contact trench CT2 may extend through the third sacrificial pattern 40, the first interlayer insulating layer 100, and the insulating pattern 101 in the vertical direction DR3 to reach the third gate insulating layer 123. For example, the third gate insulating layer 123 may be exposed through the second contact trench CT2. Portions of the sidewalls of the third sacrificial pattern 40 in the first interlayer insulating layer 100 may be exposed through the second contact trench CT2.

[0103] Referring to Figures 39 to 41 , the third sacrificial pattern 40 may be etched. As a result, the first contact trench CT1, the second contact trench CT2, and the bottom via trench BCT may be connected.

[0104] Referring to Figures 2 to 4 , by the same process, a conductive material layer may be formed in the first contact trench CT1, the second contact trench CT2, and the bottom via trench BCT of Figures 39 to 41 . For example, a portion of the conductive material layer formed in the first contact trench CT1 of Figures 39 to 41 may be defined as the second source / drain contact portion CA2, a portion of the conductive material layer formed in the second contact trench CT2 of Figures 39 to 41 may be defined as the gate contact portion CB, and a portion of the conductive material layer formed in the bottom via trench BCT of Figures 39 to 41 may be defined as the bottom via BV.

[0105] As a result, the second source / drain contact portion CA2, the gate contact portion CB, and the bottom via BV may include the same material. In addition, the second source / drain contact portion CA2, the gate contact portion CB, and the bottom via BV may be in contact with each other. That is, the second source / drain contact portion CA2, the gate contact portion CB, and the bottom via BV may be integrally formed. In this way, a semiconductor device of Figures 2 to 4 may be manufactured.

[0106] The second source / drain contact CA2 can be disposed under the second source / drain region SD2, the gate contact CB can be disposed under the third gate electrode G3, and the bottom via BV can be disposed under the second source / drain region SD2 and the gate contact CB. The second source / drain contact CA2, the gate contact CB, and the bottom via BV can be arranged to be in contact with each other. In other words, the second source / drain contact CA2, the gate contact CB, and the bottom via BV can be integrally formed. Accordingly, the process margin for forming the second source / drain contact CA2, the gate contact CB, and the bottom via BV can be ensured.

[0107] In addition, the second source / drain contact CA2, the gate contact CB, and the bottom via BV can be formed by the same process. Accordingly, the formation of the second source / drain contact CA2, the gate contact CB, and the bottom via BV can be simplified.

[0108] Hereinafter, reference will be made to Figures 42 to 44 to describe semiconductor devices according to other exemplary embodiments of the inventive concept, mainly focusing on the differences from the Figures 1 to 4 semiconductor devices.

[0109] Figures 42 to 44 is a cross-sectional view for explaining semiconductor devices according to some exemplary embodiments of the inventive concept.

[0110] Referring to Figures 42 to 44 , the bottom via BV2 is not integrally formed with the second source / drain contact CA2 and the gate contact CB.

[0111] For example, after forming the second source / drain contact CA2 and the gate contact CB, the bottom via BV2 can be formed by a subsequent process. As a result, a boundary surface can be formed between the bottom via BV2 and the second source / drain contact CA2. A boundary surface can also be formed between the bottom via BV2 and the gate contact CB. For example, the bottom via BV2 can include the same material as the second source / drain contact CA2 and the gate contact CB, but the exemplary embodiments are not limited thereto. Alternatively, in some exemplary embodiments, the bottom via BV2 can include a material different from the material of each of the second source / drain contact CA2 and the gate contact CB.

[0112] Hereinafter, reference will be made to Figures 45 to 47 to describe semiconductor devices according to other exemplary embodiments, mainly focusing on the differences from the Figures 1 to 4 semiconductor devices.

[0113] Figures 45 to 47 is a cross-sectional view for explaining semiconductor devices according to some exemplary embodiments of the inventive concept.

[0114] Referring to Figures 45 to 47, the second source / drain contact portion CA23, the gate contact BC3, and the bottom via BV3 can be formed as a double-layer film.

[0115] For example, the second source / drain contact portion CA23 can include a first contact barrier layer CA23_1 and a first contact filling layer CA23_2. The first contact barrier layer CA23_1 can form the sidewalls and the upper surface of the second source / drain contact portion CA23. For example, the first contact barrier layer CA23_1 can be conformally formed. The first contact filling layer CA23_2 can fill the space between the portions of the first contact barrier layer CA23_1.

[0116] The gate contact portion CB3 can include a second contact barrier layer CB3_1 and a second contact filling layer CB3_2. The second contact barrier layer CB3_1 can form the sidewalls and the upper surface of the gate contact portion CB3. For example, the second contact barrier layer CB3_1 can be conformally formed. The second contact filling layer CB3_2 can fill the space between the portions of the second contact barrier layer CB3_1.

[0117] The bottom via BV3 can include a bottom via barrier layer BV3_1 and a bottom via filling layer BV3_2. The bottom via barrier layer BV3_1 can form the sidewalls and the upper surface of the bottom via BV3. For example, the bottom via barrier layer BV3_1 can be conformally formed. The bottom via filling layer BV3_2 can fill the space between the portions of the bottom via barrier layer BV3_1.

[0118] For example, the first contact barrier layer CA23_1, the second contact barrier layer CB3_1, and the bottom via barrier layer BV3_1 can be formed continuously. The first contact barrier layer CA23_1, the second contact barrier layer CB3_1, and the bottom via barrier layer BV3_1 can be formed integrally. The first contact barrier layer CA23_1, the second contact barrier layer CB3_1, and the bottom via barrier layer BV3_1 can include the same material. For example, the first contact barrier layer CA23_1, the second contact barrier layer CB3_1, and the bottom via barrier layer BV3_1 can include one of Ta, TaN, Ti, TiN, Ru, Co, Ni, nickel boride (NiB), W, WN, tungsten carbonitride (WCN), Zr, zirconium nitride (ZrN), V, vanadium nitride (VN), Nb, NbN, Pt, Ir, and Rh. However, the exemplary embodiments are not limited thereto.

[0119] For example, the first contact fill layer CA23_2, the second contact fill layer CB3_2, and the bottom via fill layer BV3_2 may be integrally formed. At least a part of the sidewall of the second contact fill layer CB3_2 may be in contact with the first contact fill layer CA23_2. Additionally, the bottom surface of each of the first contact fill layer CA23_2 and the second contact fill layer CB3_2 may be in contact with the upper surface of the bottom via fill layer BV3_2. The first contact fill layer CA23_2, the second contact fill layer CB3_2, and the bottom via fill layer BV3_2 may include the same material. For example, the first contact fill layer CA23_2, the second contact fill layer CB3_2, and the bottom via fill layer BV3_2 may include one of Al, W, Co, Ru, and Mo. However, the exemplary embodiments are not limited thereto.

[0120] Reference will be made below to Figures 48 to 50 describe semiconductor devices according to other exemplary embodiments of the inventive concept, with a main focus on the differences from Figures 1 to 4 semiconductor devices.

[0121] Figures 48 to 50 is a cross-sectional view for explaining a semiconductor device according to some exemplary embodiments of the inventive concept.

[0122] Referring to Figures 48 to 50 , the second source / drain contact portion CA24 and the gate contact portion CB4 may be formed as a bilayer film.

[0123] For example, the second source / drain contact portion CA24 may include a first contact barrier layer CA24_1 and a first contact fill layer CA24_2. The first contact barrier layer CA24_1 may form the sidewall and the upper surface of the second source / drain contact portion CA24. For example, the first contact barrier layer CA24_1 may be conformally formed. The first contact fill layer CA24_2 may fill the space between the respective portions of the first contact barrier layer CA24_1.

[0124] The gate contact portion CB4 may include a second contact barrier layer CB4_1 and a second contact fill layer CB4_2. The second contact barrier layer CB4_1 may form the sidewall and the upper surface of the gate contact portion CB4. For example, the second contact barrier layer CB4_1 may be conformally formed. The second contact fill layer CB4_2 may fill the space between the respective portions of the second contact barrier layer CB4_1.

[0125] For example, the first contact barrier layer CA24_1 and the second contact barrier layer CB4_1 may be formed continuously. The first contact barrier layer CA24_1 and the second contact barrier layer CB4_1 may be formed integrally. The first contact barrier layer CA24_1 and the second contact barrier layer CB4_1 may include the same material. For example, the first contact barrier layer CA24_1, the second contact barrier layer CB4_1, and the bottom via barrier layer BV3_1 may include one of Ta, TaN, Ti, TiN, Ru, Co, Ni, NiB, W, WN, WCN, Zr, ZrN, V, VN, Nb, NbN, Pt, Ir, and Rh. However, the exemplary embodiments are not limited thereto.

[0126] For example, the first contact filling layer CA24_2 and the second contact filling layer CB4_2 may be formed integrally. At least a part of the sidewall of the second contact filling layer CB4_2 may be in contact with the first contact filling layer CA24_2. The first contact filling layer CA24_2 and the second contact filling layer CB4_2 may include the same material. For example, the first contact filling layer CA24_2 and the second contact filling layer CB4_2 may include one of Al, W, Co, Ru, and Mo. However, the exemplary embodiments are not limited thereto.

[0127] For example, the bottom via BV4 is not formed integrally with the second source / drain contact portion CA24 and the gate contact portion CB4. For example, after forming the second source / drain contact portion CA24 and the gate contact portion CB4, the bottom via BV4 may be formed through a subsequent process. As a result, a boundary surface may be formed between the bottom via BV4 and the second source / drain contact portion CA24. A boundary surface may also be formed between the bottom via BV4 and the gate contact portion CB4. The bottom via BV4 may include the same material as the second source / drain contact portion CA24 and the gate contact portion CB4, but the exemplary embodiments are not limited thereto. Alternatively, in some exemplary embodiments, the bottom via BV4 may include a material different from that of each of the second source / drain contact portion CA24 and the gate contact portion CB4.

[0128] Hereinafter, reference will be made to Figure 51 a semiconductor device according to other exemplary embodiments of the present inventive concept, mainly focusing on the differences from Figures 1 to 4 the semiconductor device.

[0129] Figure 51 is a cross-sectional view for explaining a semiconductor device according to some exemplary embodiments of the present inventive concept.

[0130] Referring to Figure 51 , the gate contact portion CB5 may be spaced apart from the second source / drain contact portion CA25 in the first horizontal direction DR1.

[0131] For example, the second source / drain contact CA25 and the gate contact CB5 may be separated in a first horizontal direction DR1 by a first interlayer insulating layer 100 and an insulating pattern 101. For example, the second source / drain contact CA25, the gate contact CB5, and the bottom via BV may be integrally formed.

[0132] Other exemplary embodiments of semiconductor devices according to the inventive concept will be described below with a main focus on the differences from Figure 52 the semiconductor devices. Figures 1 to 4

[0133] Figure 52 is a cross-sectional view for explaining semiconductor devices according to some exemplary embodiments of the inventive concept.

[0134] Referring to Figure 52 , the gate contact CB6 may be spaced apart from the second source / drain contact CA26 in a first horizontal direction DR1. Additionally, the second source / drain contact CA26, the gate contact CB6, and the bottom via BV6 may be formed as a bilayer film.

[0135] For example, the second source / drain contact CA26 and the gate contact CB6 may be separated in a first horizontal direction DR1 by a first interlayer insulating layer 100 and an insulating pattern 101. For example, the second source / drain contact CA26 may include a first contact barrier layer CA26_1 and a first contact filling layer CA26_2. The first contact barrier layer CA26_1 may form sidewalls and an upper surface of the second source / drain contact CA26. The first contact barrier layer CA26_1 may be conformally formed. The first contact filling layer CA26_2 may fill spaces between portions of the first contact barrier layer CA26_1.

[0136] The gate contact CB6 may include a second contact barrier layer CB6_1 and a second contact filling layer CB6_2. The second contact barrier layer CB6_1 may form sidewalls and an upper surface of the gate contact CB6. For example, the second contact barrier layer CB6_1 may be conformally formed. The second contact filling layer CB6_2 may fill spaces between portions of the second contact barrier layer CB6_1.

[0137] The bottom via BV6 may include a bottom via barrier layer BV6_1 and a bottom via filling layer BV6_2. The bottom via barrier layer BV6_1 may form sidewalls and an upper surface of the bottom via BV6. For example, the bottom via barrier layer BV6_1 may be conformally formed. The bottom via filling layer BV6_2 may fill spaces between portions of the bottom via barrier layer BV6_1.

[0138] For example, the first contact barrier layer CA26_1, the second contact barrier layer CB6_1, and the bottom via barrier layer BV6_1 may be formed continuously. The first contact barrier layer CA26_1, the second contact barrier layer CB6_1, and the bottom via barrier layer BV6_1 may be formed integrally. The first contact barrier layer CA26_1, the second contact barrier layer CB6_1, and the bottom via barrier layer BV6_1 may include the same material. For example, the first contact barrier layer CA26_1, the second contact barrier layer CB6_1, and the bottom via barrier layer BV6_1 may include one of Ta, TaN, Ti, TiN, Ru, Co, Ni, NiB, W, WN, WCN, Zr, ZrN, V, VN, Nb, NbN, Pt, Ir, and Rh. However, the exemplary embodiments are not limited thereto.

[0139] For example, the first contact fill layer CA26_2, the second contact fill layer CB6_2, and the bottom via fill layer BV6_2 may be formed integrally. At least a part of the sidewall of the second contact fill layer CB6_2 may be in contact with the first contact fill layer CA26_2. In addition, the bottom surfaces of the first contact fill layer CA26_2 and the second contact fill layer CB6_2 may be in contact with the upper surface of the bottom via fill layer BV6_2. The first contact fill layer CA26_2, the second contact fill layer CB6_2, and the bottom via fill layer BV6_2 may include the same material. For example, the first contact fill layer CA26_2, the second contact fill layer CB6_2, and the bottom via fill layer BV6_2 may include one of Al, W, Co, Ru, and Mo. However, the exemplary embodiments are not limited thereto.

[0140] Hereinafter, reference will be made to Figure 53 a description of a semiconductor device according to other exemplary embodiments of the inventive concept, mainly focusing on the differences from Figures 1 to 4 the semiconductor device of

[0141] Figure 53 is a cross-sectional view for explaining a semiconductor device according to some exemplary embodiments of the inventive concept.

[0142] Referring to Figure 53 , no first sacrificial pattern ( Figure 2 "103" in

[0143] Although various example embodiments have been described with reference to the accompanying drawings in accordance with the technical spirit of the various example embodiments, it should be understood that the inventive concept is not limited to these example embodiments. The various example embodiments may be made in various different forms, and those of ordinary skill in the art will understand that the example embodiments may be implemented in other specific forms without changing the technical spirit or essential features of the inventive concept. Therefore, the above example embodiments should be considered illustrative rather than restrictive in all respects.

Claims

1. A semiconductor device, comprising: A first interlayer insulating layer; An insulating pattern extending along a first horizontal direction on an upper surface of the first interlayer insulating layer; A first plurality of nanosheets stacked on the insulating pattern at intervals in a vertical direction; A second plurality of nanosheets stacked on the insulating pattern at intervals in the vertical direction, the second plurality of nanosheets being spaced apart from the first plurality of nanosheets in the first horizontal direction; A first gate electrode extending along a second horizontal direction different from the first horizontal direction on the insulating pattern, the first gate electrode surrounding the first plurality of nanosheets; A second gate electrode extending along the second horizontal direction on the insulating pattern, the second gate electrode surrounding the second plurality of nanosheets, the second gate electrode being spaced apart from the first gate electrode in the first horizontal direction; A source / drain region on the insulating pattern between the first gate electrode and the second gate electrode; A source / drain contact portion penetrating the first interlayer insulating layer and the insulating pattern in the vertical direction, the source / drain contact portion being electrically connected to the source / drain region; And A gate contact portion penetrating the first interlayer insulating layer and the insulating pattern in the vertical direction, the gate contact portion being electrically connected to the second gate electrode, at least a part of a sidewall of the gate contact portion being in contact with the source / drain contact portion, Wherein the source / drain contact portion and the gate contact portion are integrally formed.

2. The semiconductor device according to claim 1, wherein, Bottom surfaces of the source / drain contact portion and the gate contact portion are in the same plane.

3. The semiconductor device according to claim 1, further comprising: A gate insulating layer between the second gate electrode and the second plurality of nanosheets and between the second gate electrode and the gate contact portion, Wherein the gate insulating layer is in contact with the gate contact portion.

4. The semiconductor device according to claim 1, wherein, At least a part of the insulating pattern is between the source / drain contact portion and the gate contact portion.

5. The semiconductor device according to claim 1, further comprising: A second interlayer insulating layer on a bottom surface of the first interlayer insulating layer; And A bottom via in the second interlayer insulating layer, the bottom via being in contact with each of a bottom surface of the source / drain contact portion and a bottom surface of the gate contact portion.

6. The semiconductor device according to claim 5, wherein, The bottom via is integrally formed with each of the source / drain contact portion and the gate contact portion.

7. The semiconductor device according to claim 1, wherein, An upper surface of the source / drain contact portion is lower than a bottom surface of the lowermost nanosheet among the second plurality of nanosheets.

8. The semiconductor device according to claim 1, wherein, An upper surface of the gate contact portion is higher than an upper surface of the source / drain contact portion.

9. The semiconductor device according to claim 1, wherein Each of the source / drain contact portion and the gate contact portion is a single-layer film.

10. The semiconductor device according to claim 1, wherein, The source / drain contact portion includes: a first contact barrier layer forming sidewalls and an upper surface of the source / drain contact portion, and a first contact filling layer filling a space between respective parts of the first contact barrier layer, Wherein the gate contact portion includes: a second contact barrier layer forming sidewalls and an upper surface of the gate contact portion, and a second contact filling layer filling a space between respective parts of the second contact barrier layer, and Among them, the first contact filling layer is in contact with the second contact filling layer.

11. A semiconductor device, comprising: A first interlayer insulating layer; An insulating pattern extending along a first horizontal direction on the upper surface of the first interlayer insulating layer; A plurality of nanosheets stacked vertically and spaced apart from each other on the insulating pattern; A gate electrode extending along a second horizontal direction different from the first horizontal direction on the insulating pattern, the gate electrode surrounding the plurality of nanosheets; Source / drain regions on the insulating pattern on at least one side of the gate electrode; Source / drain contact portions penetrating the first interlayer insulating layer and the insulating pattern in the vertical direction, the source / drain contact portions being electrically connected to the source / drain regions; Gate contact portions penetrating the first interlayer insulating layer and the insulating pattern in the vertical direction, the gate contact portions being electrically connected to the gate electrode; A second interlayer insulating layer on the bottom surface of the first interlayer insulating layer; And Bottom vias in the second interlayer insulating layer, the bottom vias being in contact with each of the bottom surfaces of the source / drain contact portions and the gate contact portions, wherein the bottom vias are integrally formed with each of the source / drain contact portions and the gate contact portions.

12. The semiconductor device according to claim 11, wherein, At least a portion of the insulating pattern is between the source / drain contact portion and the gate contact portion.

13. The semiconductor device according to claim 11, wherein, The upper surface of the gate contact portion is higher than the upper surface of the source / drain contact portion.

14. The semiconductor device according to claim 11, wherein, At least a portion of the sidewall of the gate contact portion is in contact with the source / drain contact portion.

15. The semiconductor device according to claim 11, wherein, The gate contact portion is spaced apart from the source / drain contact portion in the first horizontal direction.

16. The semiconductor device according to claim 11, wherein Each of the bottom vias, the source / drain contact portions, and the gate contact portions is a single-layer film.

17. The semiconductor device according to claim 11, wherein, The source / drain contact portion includes: a first contact barrier layer forming the sidewalls and the upper surface of the source / drain contact portion, and a first contact filling layer filling the spaces between the respective portions of the first contact barrier layer, wherein the gate contact portion includes: a second contact barrier layer forming the sidewalls and the upper surface of the gate contact portion, and a second contact filling layer filling the spaces between the respective portions of the second contact barrier layer, wherein the bottom via includes: a bottom via barrier layer forming the sidewall of the bottom via, and a bottom via filling layer filling the spaces between the respective portions of the bottom via barrier layer, and wherein the bottom via filling layer is in contact with each of the first contact filling layer and the second contact filling layer.

18. A semiconductor device, comprising: A first interlayer insulating layer; An insulating pattern extending along a first horizontal direction on the upper surface of the first interlayer insulating layer; A first plurality of nanosheets stacked vertically and spaced apart from each other on the insulating pattern; A second plurality of nanosheets stacked vertically and spaced apart from each other on the insulating pattern, the second plurality of nanosheets being spaced apart from the first plurality of nanosheets in the first horizontal direction; A third plurality of nanosheets are stacked on the insulating pattern, spaced apart from each other in the vertical direction, and the third plurality of nanosheets are spaced apart from the second plurality of nanosheets in the first horizontal direction; A first gate electrode extends on the insulating pattern in a second horizontal direction different from the first horizontal direction, and the first gate electrode surrounds the first plurality of nanosheets; A second gate electrode extends on the insulating pattern in the second horizontal direction, the second gate electrode surrounds the second plurality of nanosheets, and the second gate electrode is spaced apart from the first gate electrode in the first horizontal direction; A third gate electrode extends on the insulating pattern in the second horizontal direction, the third gate electrode surrounds the third plurality of nanosheets, and the third gate electrode is spaced apart from the second gate electrode in the first horizontal direction; A first source / drain region is on the insulating pattern between the first gate electrode and the second gate electrode; A second source / drain region is on the insulating pattern between the second gate electrode and the third gate electrode; An upper interlayer insulating layer covers each of the first source / drain region and the second source / drain region; A first source / drain contact penetrates the upper interlayer insulating layer in the vertical direction, and the first source / drain contact is electrically connected to the first source / drain region; A second source / drain contact penetrates the first lower interlayer insulating layer and the insulating pattern in the vertical direction, and the second source / drain contact is electrically connected to the second source / drain region; And A gate contact penetrates the first lower interlayer insulating layer and the insulating pattern in the vertical direction, the gate contact is electrically connected to the second gate electrode, and at least a part of a sidewall of the gate contact contacts the second source / drain contact, wherein the second source / drain contact and the gate contact are integrally formed.

19. The semiconductor device according to claim 18, further comprising: A sacrificial pattern penetrates the first lower interlayer insulating layer and the insulating pattern in the vertical direction, the sacrificial pattern is connected to the first source / drain region, and the sacrificial pattern includes a material different from that of each of the first lower interlayer insulating layer and the insulating pattern.

20. The semiconductor device according to claim 18, further comprising: A second lower interlayer insulating layer is on a bottom surface of the first lower interlayer insulating layer; And A bottom via is in the second lower interlayer insulating layer, and the bottom via contacts each of a bottom surface of the second source / drain contact and a bottom surface of the gate contact.

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