Thin film transistor, pixel array substrate, display device and manufacturing method thereof

Abstract

The invention discloses a thin film transistor, a pixel array substrate, a display device and a manufacturing method thereof. The manufacturing method of the thin film transistor comprises the following steps: forming a first metal layer on a substrate and an insulating layer covering the first metal layer; forming an amorphous semiconductor film on the insulating layer; performing heat treatment on the amorphous semiconductor thin film to convert the amorphous semiconductor thin film into a first semiconductor material layer; performing interface removal processing on the first semiconductor material layer; forming a second semiconductor material layer and a third semiconductor material layer on the first semiconductor material layer to form an active layer; forming a second metal layer on the active layer; and performing etching treatment to expose the second semiconductor material layer in the channel region and divide the second metal layer into a source electrode and a drain electrode.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and particularly to a thin film transistor, a pixel array substrate, a display device and a manufacturing method thereof. Background Art

[0002] A thin film transistor (TFT) is a device used as a switching element to control the operation of pixels in a general display screen. Among them, thin film transistors can be roughly divided into amorphous silicon (a-Si) thin film transistors and polycrystalline silicon (poly-Si) thin film transistors according to the material composition of their active layers.

[0003] Amorphous silicon thin film transistors have the advantages of low cost and relatively simple manufacturing process, and have become the mainstream design for large-size panels. In addition, compared with polycrystalline silicon, since amorphous silicon can be manufactured at a lower temperature, it is more suitable for some portable devices. However, the current amorphous silicon thin film transistors have a low carrier mobility, usually only 0.2-0.5 cm 2 / V×S, and such device characteristics will lead to limitations in the application scope of products. Summary of the Invention

[0004] The purpose of the present invention is to provide a thin film transistor, a pixel array substrate, a display device and a manufacturing method thereof to solve the above problems.

[0005] The present invention provides a thin film transistor, comprising a gate, an insulating layer, an active layer, a source electrode and a drain electrode. The insulating layer is formed on the gate. The active layer is formed on the insulating layer. The source electrode is formed on one of the two end portions of the active layer. The drain electrode is formed on the other of the two end portions of the active layer. The active layer comprises a first semiconductor material layer, a second semiconductor material layer and a third semiconductor material layer stacked in sequence. The first semiconductor material layer is formed on the insulating layer and has an orderly arranged lattice structure; the second semiconductor material layer is formed on the first semiconductor material layer and has a disorderly arranged lattice structure; and the third semiconductor material layer is formed on both sides of the second semiconductor material layer, has a disorderly arranged lattice structure and is doped with N-type ions. There is substantially no semiconductor oxide at the interface between the first semiconductor material layer and the second semiconductor material layer.

[0006] The present invention provides a method for manufacturing a thin-film transistor, comprising the following steps: forming a first metal layer on a substrate and an insulating layer covering the first metal layer; forming an amorphous semiconductor thin film on the insulating layer; performing heat treatment on the amorphous semiconductor thin film to convert the amorphous semiconductor thin film into a first semiconductor material layer; performing an interface cleaning process on the first semiconductor material layer to remove the native semiconductor oxide on the surface of the first semiconductor material layer; forming second and third semiconductor material layers on the first semiconductor material layer to form an active layer; forming a second metal layer on the active layer; and performing an etching process to expose the second semiconductor material layer in the channel region and separate the second metal layer into a source electrode and a drain electrode.

[0007] The present invention provides a pixel array substrate, comprising a thin-film transistor manufactured by the method for manufacturing a thin-film transistor as described above.

[0008] The present invention provides a display device, comprising the pixel array substrate as described above.

[0009] Through the technical solution of the present invention, the thin-film transistor, pixel array substrate, display device and their manufacturing methods provided by the embodiments of the present invention can, through a specific interface cleaning process in the manufacturing process of the thin-film transistor, make there be substantially no semiconductor oxide that is likely to cause bonding defects between the microcrystalline or polycrystalline silicon layer and the amorphous silicon layer in the active layer, so that the thin films in the active layer can be well bonded without the problem of film peeling, and the device characteristics such as the carrier mobility and on-off ratio of the thin-film transistor can be effectively improved. Description of the Drawings

[0010] Figure 1A and Figure 1B is a schematic diagram of a display device according to an embodiment of the present invention;

[0011] Figure 2 is a schematic cross-sectional structure diagram of a thin-film transistor according to an embodiment of the present invention;

[0012] Figure 3 is a flowchart of the steps of a method for manufacturing a thin-film transistor according to an embodiment of the present invention;

[0013] Figures 4A to 4F is Figure 3 a schematic flowchart of the method for manufacturing a thin-film transistor;

[0014] Figure 5 is a SEM photograph of a thin-film transistor manufactured by the manufacturing method of the embodiment of the present invention and a comparative example; and

[0015] Figure 6Schematic diagrams of the on - state current of the thin - film transistors fabricated by the manufacturing method of the embodiments of the present invention and the comparative example. Detailed implementation manners

[0016] To make the above - mentioned purposes, features, and advantages of the technical solution more obvious and understandable, the following will describe in detail the specific embodiments of the proposed technical solution with reference to the accompanying drawings. The descriptions of the embodiments of the technical solutions of the present invention below are only for illustration and are not intended to represent all the embodiments of the present invention or limit the present invention to specific embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the scope of protection of the present invention.

[0017] It should be noted that when an element is referred to as being "disposed on" another element, it can be directly on the other element or there can also be an intermediate element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intermediate element at the same time. The terms "vertical", "horizontal", "left", "right", "up", "down" and similar expressions used herein are only for indicating the relative positional relationship based on the drawings and do not limit the elements using the said terms to being implemented only in the indicated manner. When the absolute position of the described object changes, the description of the relative position may also change accordingly.

[0018] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention belongs. The terms used in the description of the present invention herein are only for the purpose of describing specific implementation manners and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0019] Figure 1A and Figure 1B Schematic diagram of a display device according to an embodiment of the present invention, where Figure 1A is a top - view configuration schematic diagram of the display device 100, and Figure 1B is a side - view configuration schematic diagram of the display device 100. For the sake of convenience of description, Figure 1A is represented in a manner that the internal elements of the display device 100 are unfolded in the x - y plane, Figure 1B while presents the configuration state of the internal elements of the display device 100 in the housing.

[0020] Please refer to Figure 1A and Figure 1B, the display device 100 can be any electronic device with a display function, such as a TV, a screen, a laptop, or a mobile phone, and it may include a display panel 110, a scan driving circuit 120, a data driving circuit 130, a connection module 140, and a control circuit 150. In this embodiment, the display panel 110 has a display area DR and a non-display area SR, where the display area DR is the area for displaying images; and the non-display area SR is the area where the display panel 110 does not display images. The non-display area SR usually surrounds the display area DR and can also be regarded as the border area of the display device 100. The scan driving circuit 120 and the data driving circuit 130 are disposed in the non-display area SR of the display panel 110. In the figure, the scan driving circuit 120 is taken as an example of being disposed in the non-display areas SR on the left and right sides of the display panel 110, and the data driving circuit 130 is taken as an example of being disposed in the non-display area SR at the lower side of the display panel 110, but the present invention is not limited thereto. One end of the connection module 140 is disposed on the side of the non-display area SR close to the data driving circuit 130, and the control circuit 150 is coupled to the other end of the connection module 140.

[0021] From the perspective of the electrical relationship between components, the scan driving circuit 120 is electrically connected to the display panel 110 through the traces on the substrate 112. The data driving circuit 130 is electrically connected to the display panel 110 through the first transmission part WR1 and is electrically connected to the flexible circuit board 140 through the second transmission part WR2. On the other hand, the control circuit 150 is electrically connected to the data driving circuit 130 through the connection module 140 and the second transmission part WR2. Among them, the first transmission part WR1 and the second transmission part WR2 can be transmission lines formed on the substrate 112.

[0022] Specifically, the display panel 110 may include a substrate 112 and a pixel array 114 located in the display area DR. The pixel array 114 is disposed on the substrate 112 and is arranged in an array of, for example, m×n, that is, m rows and n columns, where m and n can be natural numbers selected according to design requirements, and the present invention does not limit this. The pixels in the same column of the pixel array 114 correspond to the same scan line, and the pixels in the same row correspond to the same data line of the pixel array 114. In this embodiment, the pixel array 114 can be electrically connected to the scan driving circuit 120 through the scan line to receive the scan signal, and is electrically connected to the data driving circuit 130 through the data line and the first transmission unit WR1 to receive the data driving signal provided by the data driving circuit 130. The data driving circuit 130 provides the data driving signal in coordination with the turn-on timing of the pixel array 114, so that the pixel array 114 adjusts the passing light according to the data driving signal to present a corresponding image in the display area DR. In this embodiment, the display panel 110 can be various types of display panels, such as LCD, LED, OLED, mini-LED, or micro-LED, etc., and the present invention is not limited thereto.

[0023] The scan driving circuit 120 is used to generate a scan signal for turning on / enabling pixels row by row according to the timing control signal. In this embodiment, the scan driving circuit 120 is illustrated as an example of two configurations for enabling odd-row pixels and even-row pixels respectively. Among them, the scan driving circuit 120 on the left is illustrated as including scan units 121_1, 121_3,..., 121_m-1 respectively connected to odd-numbered scan lines, and the scan driving circuit 120 on the right is illustrated as including scan units 121_2, 121_4, 121_m respectively connected to even-numbered scan lines, but the present invention is not limited thereto. In this embodiment, the scan unit 121_x represents any one of the scan units 121_1, 121_3,..., 121_m-1 on the left, and the scan unit 121_y represents any one of the scan units 121_2, 121_4, 121_m on the right. In other words, x can be any odd number less than m, and y can be any even number less than or equal to m, where m is an even number, but the present invention is not limited thereto.

[0024] The data driving circuit 130 is used to generate a driving signal for driving the pixel array 114 according to the data control signal. Although the accompanying drawings of this embodiment illustrate a single data driving circuit 130 for illustration, the present invention is not limited thereto. In some embodiments, the data driving circuit 130 can be integrated into multiple driving chips, and the multiple driving chips can cooperate to drive the pixels in different parts / regions of the pixel array 114.

[0025] The connection module 140 is used to provide a signal transmission path between the data driving circuit 130 and the control circuit 150, so that the data control signal generated by the control circuit 150 can be transmitted to the data driving circuit 130 through the connection module 140 and the second transmission part WR2.

[0026] In the pixel array 114 of the display panel 110, there are a plurality of thin film transistors. The plurality of thin film transistors are turned on or off in response to the received signals, and are used to control the operation of the corresponding pixels, so as to achieve the effect of adjusting the transmitted light according to the data driving signal and presenting the corresponding image in the display area DR.

[0027] In some embodiments, the structural configuration of the thin film transistor can be as Figure 2 shown, where Figure 2 is a schematic cross-sectional structure diagram of a thin film transistor according to an embodiment of the present invention. Please refer to Figure 2 , the thin film transistor 200 includes a gate 210, an insulating layer 220, an active layer 230, a source electrode 240S and a drain electrode 240D. The gate 210, the insulating layer 220 and the active layer 230 are stacked in sequence from bottom to top (based on the illustrated direction). An active source electrode 240S and a drain electrode 240D are respectively formed on both ends of the active layer 230, and the middle region of the active layer 230 is etched to form a channel region CHA.

[0028] The gate 210, the source electrode 240S and the drain electrode 240D can be composed of metals such as molybdenum (Mo), aluminum (Al), titanium (Ti), copper (Cu) or a stacked combination of the above metals, but the present invention is not limited thereto. The insulating layer 220 can be a non-metallic dielectric material, such as silicon dioxide (SiOx), silicon nitride (SiNx) or a stacked combination of the above materials, but the present invention is also not limited thereto.

[0029] The active layer 230 of this embodiment has a three-layer stacked structure at both ends, which includes a first semiconductor material layer 231, a second semiconductor material layer 232, and a third semiconductor material layer stacked in sequence from bottom to top. The first semiconductor material layer 231 is formed on the insulating layer 220 and has an orderly arranged lattice structure, such as microcrystalline silicon or polycrystalline silicon. The second semiconductor material layer 232 is formed on the first semiconductor material layer 231 and has a disorderly arranged lattice structure, such as amorphous silicon (a-Si). The third semiconductor material layer 233 is formed on both sides of the second semiconductor material layer 232, where the third semiconductor material layer 233 has a disorderly arranged lattice structure and is doped with N-type ions. In other words, at both ends of the active layer 230, both the second semiconductor material layer 232 and the third semiconductor material layer 233 can be made of amorphous silicon, and the difference is that the N-type ion concentration of the third semiconductor material layer 233 is higher than that of the second semiconductor material layer 232.

[0030] On the other hand, the thickness of the active layer 230 within the channel region CHA is less than that outside the channel region CHA (i.e., both ends), and the third semiconductor material layer 233 is removed from the active layer 230 within the channel region CHA through an etching process, and the second semiconductor material layer 232 is exposed. In other words, only a two-layer structure of the first semiconductor material layer 231 and the second semiconductor material layer 232 exists within the channel region CHA.

[0031] The thin-film transistor 200 having the active layer 230 composed of the above-described first to third semiconductor material layers 231 to 233 has a higher carrier mobility compared to a conventional amorphous silicon thin-film transistor. Under the structure of this embodiment, the carrier mobility can be increased to 6 - 8 cm 2 / V×SM, which is more than 10 times that of a conventional amorphous silicon thin-film transistor.

[0032] In addition, in this embodiment, most of the native semiconductor oxide (such as SiOx) between the first semiconductor material layer 231 and the second semiconductor material layer 232 is removed, so that there is substantially no semiconductor oxide at the interface between the first semiconductor material layer 231 and the second semiconductor material layer 232. Therefore, the first semiconductor material layer 231 and the second semiconductor material layer 232 can be basically well joined without the problem of film peeling, and the device characteristics such as the carrier mobility and on / off ratio of the thin-film transistor 200 can be effectively improved.

[0033] The source electrode 240S and the drain electrode 240D are respectively formed at two ends of the active layer 230, and extend from the side surface of the active layer 230 to cover a part of the insulating layer 220. More specifically, the source electrode 240S and the drain electrode 240D respectively contact the top of the third semiconductor material layer 233 (i.e., the side away from the second semiconductor material layer 232) and the side walls of the first semiconductor material layer 231, the second semiconductor material layer 232, and the third semiconductor material layer 233 (i.e., the side of the active layer 230 away from the channel region CHA), and extend through the side walls to contact the top of the insulating layer 220 (i.e., the side away from the gate 210).

[0034] In some embodiments, the thin film transistor 200 may further include a functional layer 250 covering the surface of the element, and the functional layer 250 may be formed, for example, on a partial area or all of the exposed surfaces of the source electrode 240S, the drain electrode 240D, and the active layer 230. In some embodiments, the functional layer 250 may be, for example, a protective film implemented by silicon nitride (SiN) or the like, but the present invention is not limited thereto.

[0035] Figure 3 It is a flowchart of the steps of a manufacturing method of a thin film transistor according to an embodiment of the present invention, wherein Figure 3 the manufacturing method can be used to manufacture the thin film transistor 200 as described in Figure 2 the embodiment. The following is combined with Figures 4A to 4F to illustrate the manufacturing process of the thin film transistor 200, wherein Figures 4A to 4F is a schematic flowchart of the manufacturing method of the thin film transistor according to Figure 3 .

[0036] Please refer to Figure 3 and Figure 4A , first, a first metal layer 210 and an insulating layer 220 covering the first metal layer 210 are formed on a substrate SUB (step S110), wherein the first metal layer 210 is used as the gate of the thin film transistor 200.

[0037] Next, please refer to Figure 3 , Figure 4B and Figure 4C , an amorphous semiconductor thin film 231p is formed on the insulating layer 220 (step S120), and the amorphous semiconductor thin film 231p is heat-treated to convert the amorphous semiconductor thin film 231p into a first semiconductor material layer 231 having an orderly arranged lattice structure (step S130).

[0038] In some embodiments, the amorphous semiconductor thin film 231p is, for example, amorphous silicon. The heat treatment may be, for example, an Excimer Laser Annealing (ELA) technique that irradiates amorphous silicon with an excimer laser to achieve a manufacturing process of converting amorphous silicon into microcrystalline silicon or polycrystalline silicon (i.e., the first semiconductor material layer 231) having an orderly arranged lattice structure, but the present invention is not limited thereto.

[0039] After the amorphous semiconductor thin film 231p is converted into the first semiconductor material layer 231, this embodiment will further perform an interface cleaning process on the first semiconductor material layer 231 to remove the native semiconductor oxide SO on the surface of the first semiconductor material layer 231 (step S140).

[0040] In some embodiments, the interface cleaning process may be implemented, for example, by surface treatment manufacturing processes such as wet etching (e.g., chemical agent treatment), dry etching (e.g., plasma treatment), etc. In the interface cleaning process using wet etching, it can be implemented by using a chemical liquid that is corrosive to the semiconductor oxide SO, such as a diluted Buffered Oxide Etch (BOE), diluted hydrofluoric acid (HF), or a chemical liquid mixing hydrofluoric acid and ammonium fluoride (NH4F), but the present invention is not limited thereto.

[0041] In an embodiment where a corrosive chemical liquid is used for the interface cleaning process, the chemical liquid can be diluted to an etching rate of 5 to and the interface cleaning process is maintained for a time between 5 and 30 seconds to avoid corrosion of the insulating layer 220 and / or the first semiconductor material layer 231 while removing the semiconductor oxide SO. In some embodiments, if the chemical liquid is HF or BOE, the dilution concentration can be, for example, 1% to 2%, but the present invention is not limited thereto.

[0042] Please then refer to Figure 3 and Figure 4D , after the interface cleaning process is completed, a second semiconductor material layer 232 and a third semiconductor material layer 233 are formed on the first semiconductor material layer 231 (step S150), where the first to third semiconductor material layers 231 to 233 stacked in sequence from bottom to top form the active layer 230 of the thin film transistor 200. In this embodiment, the second semiconductor material layer 232 is, for example, composed of amorphous silicon, and the third semiconductor material layer 233 is, for example, composed of n-doped amorphous silicon, but the present invention is not limited thereto.

[0043] In some embodiments, to ensure that the semiconductor oxide SO removed in step S140 does not reform during the manufacturing process, the execution time interval between step S140 and step S150 needs to be set to less than 1 hour. That is, the steps of forming the second and third semiconductor material layers 232-233 need to be performed within one hour after the interface cleaning process is completed.

[0044] Please then refer to Figure 3 and Figure 4E , after forming the active layer 230, the active layer 230 can then be patterned, and a second metal layer 240 is formed on the patterned active layer 230 (step S160).

[0045] Please then refer to Figure 3 and Figure 4F , after forming the second metal layer 240, the device is etched to expose the second semiconductor material layer 232 of the channel region CHA, and the second metal layer 240 is separated into left and right parts by the channel region CHA (step S170), where the left second metal layer 240 serves as the source 240S of the thin film transistor 200, and the right second metal layer 240 serves as the drain 240D of the thin film transistor 200.

[0046] In some embodiments, after step S170, a functional layer 250 covering the surfaces of the source 240S, drain 240D, and channel region CHA can further be formed on the device according to the design or device requirements.

[0047] Figure 5 SEM photos of the thin film transistor manufactured by the manufacturing method according to the embodiments of the present invention and the comparative example. Please refer to Figure 5 , the left comparative example is a thin film transistor fabricated by a preparation process that does not include the interface cleaning step S140, which includes a gate 210', an insulating layer 220', and an active layer composed of a first semiconductor layer to a third semiconductor layer 231'-233'. It can be seen from the experimental comparison result photos that for the thin film transistor (experimental example) fabricated by the above Figure 3 manufacturing method, there is no film peeling between the first semiconductor material layer 231 and the second semiconductor material layer 232 compared with the comparative example.

[0048] Figure 6 Schematic diagrams of the on-current of the thin film transistor experimental example and the comparative example manufactured by the manufacturing method according to the embodiments of the present invention. Please refer to Figure 6 , it can be seen from the experimental result data in the figure that the on-off ratio of the thin film transistor fabricated through the Figure 3 step process is significantly higher than that of the comparative example without the interface cleaning treatment (step S140).

[0049] In addition, in some experimental examples, the carrier mobility of the thin film transistor manufactured by the Figure 3 step process can reach 11.12 cm 2 / V×S. In contrast, in the comparative example without the interface cleaning treatment (step S140), its carrier mobility may be affected by defects and be only about 1.29 cm 2 / V×S.

[0050] In summary, the thin film transistor, pixel array substrate, display device and manufacturing method thereof proposed in the embodiments of the present invention can, through a specific interface cleaning treatment in the manufacturing process of the thin film transistor, make there be substantially no semiconductor oxides that are likely to cause bonding defects between the microcrystals or polycrystalline silicon layers (such as the first semiconductor material layer) and the amorphous silicon layers (such as the second semiconductor material layer) in the active layer, so that the thin film layers in the active layer can be well bonded without the problem of film layer peeling, and the component characteristics such as the carrier mobility and on-off ratio of the thin film transistor 200 can be effectively improved.

[0051] Although the present invention has been disclosed by the above embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various changes and modifications to the above embodiments without departing from the spirit and scope of the present invention, and these still belong to the technical scope protected by the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims

1. A thin film transistor, characterized in that, Comprising: A gate; An insulating layer formed on the gate; An active layer formed on the insulating layer; A source electrode formed on one of the two end portions of the active layer; And A drain electrode formed on the other of the two end portions of the active layer, wherein the active layer comprises a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer that are sequentially stacked, the first semiconductor material layer is formed on the insulating layer and has an orderly arranged lattice structure; the second semiconductor material layer is formed on the first semiconductor material layer and has a disorderly arranged lattice structure; and the third semiconductor material layer is formed on both sides of the second semiconductor material layer, has a disorderly arranged lattice structure and is doped with N-type ions, wherein there is substantially no semiconductor oxide at the interface between the first semiconductor material layer and the second semiconductor material layer.

2. A manufacturing method of a thin film transistor, characterized in that, Comprising: Forming a first metal layer on a substrate and an insulating layer covering the first metal layer; Forming an amorphous semiconductor thin film on the insulating layer; Performing heat treatment on the amorphous semiconductor thin film to convert the amorphous semiconductor thin film into a first semiconductor material layer; Performing an interface cleaning process on the first semiconductor material layer to remove the native semiconductor oxide on the surface of the first semiconductor material layer; Forming a second and a third semiconductor material layer on the first semiconductor material layer to form an active layer; Forming a second metal layer on the active layer; And Performing an etching process to expose the second semiconductor material layer in the channel region and to separate the second metal layer into a source electrode and a drain electrode.

3. A pixel array substrate, characterized in that, Comprising: A thin film transistor fabricated by the manufacturing method according to claim 2.

4. A display device, characterized in that, Comprising: A pixel array substrate as claimed in claim 3.

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