Semiconductor device and memory device including the same

Abstract

A semiconductor device includes a substrate having an active region, the active region including a central active region and a plurality of separate active regions; and a plurality of gate structures disposed over the active region, where the plurality of gate structures, the central active region, and the plurality of separate active regions constitute a plurality of pass transistors, and the plurality of pass transistors share the same source / drain region in the central active region.

Description

Cross - reference to Related Applications

[0001] This application claims priority based on and claims the benefit of Korean Patent Application No. 10 - 2024 - 0002304, filed with the Korean Intellectual Property Office on January 5, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Devices and methods consistent with embodiments of the present disclosure relate to a semiconductor device and a storage device including the semiconductor device, and more particularly, to a semiconductor device having a unique shape and a wiring structure of word lines connected to the semiconductor device. Background Art

[0003] Storage devices are used to store data and are classified into volatile storage devices and non - volatile storage devices. The demand for large - capacity and miniaturized non - volatile storage devices has led to the development of three - dimensional storage devices, in which a memory cell array and peripheral circuits are arranged in a vertical direction. For large - capacity non - volatile storage devices, as the number of word lines stacked on a substrate increases, the number of transfer transistors connected to the word lines can increase. Therefore, the number, length, and complexity of connection lines for connection between the word lines and transfer transistors increase, and due to coupling problems between the connection lines, the reliability of the storage device may be impaired. Summary of the Invention

[0004] One or more embodiments provide a semiconductor device and a storage device including the semiconductor device that can improve the complexity of the wiring structure of the storage device.

[0005] According to an aspect of the present disclosure, a semiconductor device may include: a substrate having an active region, the active region including a central active region and a plurality of separated active regions extending from the central active region; and a plurality of gate structures disposed above the active region, wherein the plurality of gate structures, the central active region, and the plurality of separated active regions constitute a plurality of transfer transistors, and the plurality of transfer transistors share the same source / drain region in the central active region.

[0006] Each of the plurality of gate structures may have a rectangular shape or an L - shaped shape.

[0007] The active region may have an H - shaped shape, wherein the central active region has a rectangular shape, two of the plurality of separated active regions extend from the central active region in one direction to be parallel to each other, and the other two of the plurality of separated active regions extend from the central active region in an opposite direction to be parallel to each other.

[0008] The active region may have a cross shape, where the central active region has a rectangular shape and is located at the midpoint of four outer points, and a plurality of separated active regions extend from the midpoint to the four outer points respectively, or the active region has a Y shape, where the central active region has a triangular shape and is located at the midpoint of three corner points, and a plurality of separated active regions extend from the midpoint to the three corner points respectively.

[0009] The semiconductor device may further include: a drain contact connected to the central active region; and a plurality of source contacts of a plurality of transfer transistors, respectively connected to the plurality of separated active regions.

[0010] The drain contact may be connected to a global word line, and the plurality of source contacts may be connected to a plurality of different local word lines.

[0011] The plurality of source contacts may be respectively connected to different memory cell blocks.

[0012] According to another aspect of the present disclosure, a storage device may include: a plurality of memory blocks including a plurality of memory cells connected to a plurality of word lines stacked in a vertical direction; and a plurality of transfer transistor circuit blocks connected to the plurality of memory blocks and arranged parallel to each other in a second horizontal direction, wherein each of the plurality of transfer transistor circuit blocks may include a plurality of semiconductor devices arranged parallel to each other in a first horizontal direction, and each of the plurality of semiconductor devices may include: a substrate having an active region including a central active region and a plurality of separated active regions extending from the central active region; and a plurality of gate structures disposed above the active region, the plurality of gate structures, the central active region, and the plurality of separated active regions form a plurality of transfer transistors, and the plurality of transfer transistors share the same source / drain region in the central active region.

[0013] The patterns of the plurality of semiconductor devices may be the same within the same transfer transistor circuit block among the plurality of transfer transistor circuit blocks.

[0014] The patterns of the semiconductor devices included in the transfer transistor circuit blocks adjacent to each other in the second horizontal direction among the plurality of transfer transistor circuit blocks are different from each other.

[0015] The semiconductor devices included in the adjacent transfer transistor circuit blocks adjacent to each other in the second horizontal direction among the plurality of transfer transistor circuit blocks are electrically connected to each other via wirings in the second horizontal direction or the first horizontal direction.

[0016] The global word line connected via the wiring in the second horizontal direction is connected to the source / drain region of the semiconductor device included in each of the plurality of transfer transistor circuit blocks arranged adjacent to each other in the second horizontal direction.

[0017] The plurality of transfer transistor circuit blocks are electrically connected to each other via a plurality of local word lines among the plurality of word lines.

[0018] According to another aspect of the present disclosure, a storage device may include: a plurality of memory cell blocks arranged parallel to each other in a second direction; and a plurality of semiconductor devices connected to the plurality of memory cell blocks, wherein the plurality of semiconductor devices are arranged parallel to each other in the second direction, and N of the plurality of semiconductor devices are arranged parallel to each other in a first direction, where N is a natural number greater than or equal to 1. Each of the plurality of semiconductor devices may include: a substrate having an active region, the active region including a central active region and a plurality of separated active regions extending from the central active region; and a plurality of gate structures disposed above the active region. The plurality of gate structures, the central active region, and the plurality of separated active regions constitute a plurality of transfer transistors, and the plurality of transfer transistors may share the same source / drain region in the central active region.

[0019] A global word line is connected to the source / drain region of each of the plurality of semiconductor devices, and different local word lines are connected to the plurality of separated active regions of each of the plurality of semiconductor devices.

[0020] The plurality of semiconductor devices arranged parallel to each other in the second direction are respectively connected to different global word lines.

[0021] Each of the plurality of semiconductor devices arranged parallel to each other in the second direction is electrically connected to each other through the connection of different local word lines.

[0022] Each of the plurality of semiconductor devices arranged parallel to each other in the second direction is electrically connected to each other based on the numbers of word line pads corresponding to the plurality of separated active regions and the number of the global word line.

[0023] Each of the plurality of semiconductor devices arranged parallel to each other in the second direction is electrically connected to each other through wirings in the first direction and / or the second direction.

[0024] The wirings in the first direction and / or the second direction share one or more tracks. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Embodiments will be understood more clearly from the following detailed description in conjunction with the accompanying drawings, in which:

[0026] Figure 1 is a block diagram of a storage device according to one or more embodiments;

[0027] Figure 2 is an equivalent circuit diagram of a memory cell array of a semiconductor device according to one or more embodiments;

[0028] Figure 3 shows an example of a memory cell array according to one or more embodiments;

[0029] Figure 4 shows an example of a transfer transistor circuit block and a memory cell array according to one or more embodiments;

[0030] Figure 5A is a layout diagram of a semiconductor device according to one or more embodiments;

[0031] Figure 5B is along Figure 5A cross-sectional view taken along line A-A';

[0032] Figure 5C is along Figure 5A cross-sectional view taken along line B-B';

[0033] Figure 6 is a layout diagram of a semiconductor device according to one or more embodiments;

[0034] Figure 7 is a layout diagram of a semiconductor device according to one or more embodiments;

[0035] Figure 8 is a layout diagram of a semiconductor device according to one or more embodiments;

[0036] Figure 9A is a diagram depicting the arrangement structure of a semiconductor device according to one or more embodiments;

[0037] Figure 9B is a diagram depicting the arrangement structure of a semiconductor device according to one or more embodiments;

[0038] Figure 10 is a diagram depicting the arrangement structure of a semiconductor device according to one or more embodiments;

[0039] Figure 11 is a diagram depicting an example of a semiconductor device arranged to correspond to a plurality of block structures according to one or more embodiments;

[0040] Figure 12 is a diagram depicting an example of a semiconductor device arranged to correspond to a plurality of block structures according to one or more embodiments;

[0041] Figure 13 is a diagram depicting an example of a semiconductor device arranged to correspond to a plurality of block structures according to one or more embodiments;

[0042] Figure 14 is a diagram depicting an example of a semiconductor device arranged to correspond to a plurality of block structures according to one or more embodiments;

[0043] Figure 15A diagram depicting an example in which a semiconductor device according to one or more embodiments is arranged to correspond to a plurality of block structures;

[0044] Figure 16 A diagram depicting an example in which a semiconductor device according to one or more embodiments is arranged to correspond to a plurality of block structures;

[0045] Figure 17 A diagram depicting an example in which a semiconductor device according to one or more embodiments is arranged to correspond to a plurality of block structures;

[0046] Figure 18 A diagram depicting an example in which a semiconductor device according to one or more embodiments is arranged to correspond to a plurality of block structures;

[0047] Figure 19 A diagram depicting an example in which a semiconductor device according to one or more embodiments is arranged to correspond to a plurality of block structures;

[0048] Figure 20 A diagram depicting an example in which a semiconductor device according to one or more embodiments is arranged to correspond to a plurality of block structures;

[0049] Figure 21 A diagram depicting a connection structure between a semiconductor device according to one or more embodiments and a word line;

[0050] Figure 22 A diagram depicting a connection structure between a semiconductor device according to one or more embodiments and a word line;

[0051] Figure 23 A diagram depicting a connection structure between a semiconductor device according to one or more embodiments and a local word line;

[0052] Figure 24 A diagram depicting a connection structure between a semiconductor device according to one or more embodiments and a global word line; and

[0053] Figure 25 A diagram depicting a connection structure between a semiconductor device according to one or more embodiments and a global word line. Detailed Description

[0054] Hereinafter, various embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0055] Figure 1 A block diagram of a storage device 10 according to one or more embodiments.

[0056] Referring to Figure 1, the storage device 10 may include a memory cell array 11 and a peripheral circuit PECT. Among them, the peripheral circuit PECT may include a transfer transistor circuit 12, a row decoder 13, a control logic circuit 14, and a page buffer 15. The peripheral circuit PECT may further include a voltage generator, a data input / output circuit, an input / output interface, a temperature sensor, a command decoder, or an address decoder. In some embodiments, the storage device 10 may be a non-volatile storage device, and hereinafter, the term "storage device" refers to a non-volatile storage device.

[0057] The memory cell array 11 may be connected to the transfer transistor circuit 12 via word lines WL, string select lines SSL, and ground select lines GSL, and may be connected to the page buffer 15 via bit lines BL. The memory cell array 11 may include a plurality of memory cells. For example, the memory cells may be flash memory cells. Hereinafter, taking the plurality of memory cells as NAND flash memory cells as an example, various embodiments of the present disclosure will be described. However, the embodiments are not limited thereto, and in some embodiments, the plurality of memory cells may be resistive memory cells, such as resistive RAM (ReRAM), phase change RAM (PRAM), or magnetic RAM (MRAM).

[0058] In one or more embodiments, the memory cell array 11 may include a three-dimensional memory cell array. The three-dimensional memory cells may include a plurality of NAND strings, and each NAND string may include memory cells respectively connected to word lines vertically stacked on a substrate. However, the embodiments are not limited thereto, and in some embodiments, the memory cell array 11 may include a two-dimensional memory cell array, and the two-dimensional memory cell array may include a plurality of NAND strings arranged in row and column directions.

[0059] The control logic circuit 14 may generate various control signals based on a command CMD, an address ADDR, and a control signal CTRL to program data into the memory cell array 11, read data from the memory cell array 11, or erase data stored in the memory cell array 11. For example, the control logic circuit 14 may output a row address X-ADDR and a column address Y-ADDR. Therefore, the control logic circuit 14 may generally control various operations within the storage device 10. In some embodiments, the control logic circuit 14 may include a common source line driver, and the common source line driver may be connected to the memory cell array 11 via a common source line CSL. The common source line driver may apply a common source voltage (e.g., a power supply voltage) or a ground voltage to the common source line CSL based on the control signal of the control logic circuit 14.

[0060] The row decoder 13 can output a block selection signal for selecting one of a plurality of memory blocks via a block selection signal line BS in response to a row address X-ADDR. In addition, in response to the row address X-ADDR, the row decoder 13 can output a word line drive signal for selecting one of the word lines WL of the selected memory block via a word line drive signal line SI, output a string selection line drive signal for selecting one of the string selection lines SSL via a string selection line drive signal line SS, and output a ground selection line drive signal for selecting one of the ground selection lines GSL via a ground selection line drive signal line GS. In some embodiments, the word line drive signal line SI can be referred to as a global word line. The page buffer 15 can select some bit lines BL in response to a column address Y-ADDR. Specifically, the page buffer 15 can operate as a write driver or a read amplifier according to an operation mode. In some embodiments, the word lines WL of the selected memory block can be referred to as local word lines.

[0061] The transfer transistor circuit 12 can be connected to the row decoder 13 via the block selection signal line BS, the string selection line drive signal line SS, the word line drive signal line SI, and the ground selection line drive signal line GS. The string selection line drive signal line SS, the word line drive signal line SI, and the ground selection line drive signal line GS can be collectively referred to as drive signal lines. The transfer transistor circuit 12 can include a plurality of transfer transistors, the plurality of transfer transistors can be controlled by the block selection signal received via the block selection signal line BS, and the string selection line drive signal, the word line drive signal, and the ground selection line drive signal can be respectively provided to the string selection line SSL, the word line WL, and the ground selection line GSL.

[0062] The transfer transistor circuit 12 according to one or more embodiments can include a plurality of semiconductor devices arranged parallel to each other in a first direction and a second direction and having a certain shape. This will be described in detail below with reference to Figure 4 and other drawings.

[0063] Figure 2 is an equivalent circuit diagram of the memory cell array 11 of the memory device 10 according to one or more embodiments.

[0064] Referring to Figure 2 , the memory cell array 11 can include a plurality of memory cell strings MS. The memory cell array 11 can include a plurality of bit lines BL (BL1, BL2,..., and BLm), a plurality of word lines WL (WL1, WL2,..., WLn-1, and WLn), at least one string selection line SSL, at least one ground selection line GSL, and a common source line CSL. The plurality of memory cell strings MS can be formed between the plurality of bit lines BL (BL1, BL2,..., and BLm) and the common source line CSL. Figure 2An example is shown in which each of a plurality of memory cell strings MS includes two string selection lines SSL, but the embodiments are not limited thereto. For example, each of the plurality of memory cell strings MS may include one string selection line SSL. For example, each of the plurality of memory cell strings MS may include at least three string selection lines SSL.

[0065] Each of the plurality of memory cell strings MS may include a string selection transistor SST, a ground selection transistor GST, and a plurality of memory cell transistors MC1, MC2, …, MCn-1, and MCn. The drain region of the string selection transistor SST may be connected to bit lines BL (BL1, BL2, …, and BLm), and the source region of the ground selection transistor GST may be connected to a common source line CSL. The common source line CSL may be a region where the source regions of the plurality of ground selection transistors GST are commonly connected to each other.

[0066] The string selection transistor SST may be connected to the string selection line SSL, and the ground selection transistor GST may be connected to the ground selection line GSL. The plurality of memory cell transistors MC1, MC2, …, MCn-1, and MCn may be respectively connected to a plurality of word lines WL (WL1, WL2, …, WLn-1, and WLn).

[0067] Figure 3 An example of a memory cell array 11 according to one or more embodiments is shown. Referring to Figure 3 , the memory cell array 11 may include a plurality of memory blocks BLK0 to BLKi, where i may be a positive integer. Each of the plurality of memory blocks BLK0 to BLKi may have a three-dimensional structure (or a vertical structure). Specifically, each of the plurality of memory blocks BLK0 to BLKi may include a plurality of stacked NAND strings extending in the vertical direction Z. At this time, the plurality of NAND strings may be arranged to be spaced apart from each other by a certain distance in the first direction X and the second direction Y. The plurality of memory blocks BLK0 to BLKi may be selected by a row decoder 13 (in Figure 1 ). For example, the row decoder 13 may select a memory block corresponding to a block address among the plurality of memory blocks BLK0 to BLKi.

[0068] In the present disclosure, the terms “memory block” and “memory cell block” may be used interchangeably.

[0069] Figure 4 An example of a transfer transistor circuit block and a memory cell array according to one or more embodiments is shown.

[0070] Referring to Figure 4, the memory cell array 11 may include a plurality of memory blocks BLK0 to BLKi, where i may be a positive integer. The transfer transistor circuit 12 may include a plurality of transfer transistor circuit blocks 12_0 to 12_n, where n may be a positive integer. According to one or more embodiments, i may be an integer equal to n, or i may be an integer different from n. According to one or more embodiments, when i and n are the same integer, the transfer transistor circuit blocks 12_0 to 12_n may correspond to the memory blocks BLK0 to BLKi one-to-one respectively.

[0071] Referring to Figure 4 , the length of the plurality of memory blocks BLK0 to BLKi in the second direction may be referred to as the block height. According to one or more embodiments, the length of the transfer transistor circuit blocks 12_0 to 12_n in the second direction may correspond to the block height of the plurality of memory blocks BLK0 to BLKi.

[0072] A plurality of semiconductor devices may be aligned and arranged in the first direction and the second direction in the plurality of transfer transistor circuit blocks 12_0 to 12_n. According to one or more embodiments, the first direction may be the X-axis direction, and the second direction may be the Y-axis direction. Hereinafter, the specific structure of the plurality of semiconductor devices will be described.

[0073] According to one or more embodiments, the transfer transistor may receive a voltage from the word line voltage generation circuit and apply the voltage to each corresponding word line. According to one or more embodiments, each block and each word line may require such a transfer transistor. As the number of word lines increases, the number of transfer transistors may also increase. Therefore, since the proportion of the transfer transistors in the chip area is increasing, it is necessary to reduce the size of the transfer transistors. To solve this problem, a transfer transistor having a different shape from the existing transistors is proposed.

[0074] Figure 5A is a layout diagram of a semiconductor device according to one or more embodiments. Figure 5B is along Figure 5A The cross-sectional view taken along line A-A'. Figure 5C is along Figure 5A The cross-sectional view taken along line B-B'.

[0075] Referring together to Figure 5A , Figure 5B and Figure 5C , the semiconductor device 100 may include a substrate 101 and first to fourth gate structures 120a, 120b, 120c, and 120d. The semiconductor device 100 may be arranged in the transfer transistor circuit blocks 12_0 to 12_n described with reference to Figure 4 .

[0076] The substrate 101 may include a semiconductor substrate. For example, the substrate 101 may include Si, Ge, or SiGe. The active region 110 may be defined in the substrate 101 by the device isolation film 150. The first transfer transistor PTR1, the second transfer transistor PTR2, the third transfer transistor PTR3, and the fourth transfer transistor PTR4 may be formed on the active region 110.

[0077] The active region 110 may include a central active region 110_1, and a first separated active region 110_2a, a second separated active region 110_2b, a third separated active region 110_2c, and a fourth separated active region 110_2d. In one or more embodiments, the central active region 110_1 and the first separated active region 110_2a, the second separated active region 110_2b, the third separated active region 110_2c, and the fourth separated active region 110_2d (i.e., the active region 110) may jointly form an H shape in the X-Y plane. Although the active region 110 is described as including several sub-regions, such as the central active region 110_1 and the first separated active region 110_2a, the second separated active region 110_2b, the third separated active region 110_2c, and the fourth separated active region 110_2d, these sub-regions may be interconnected to create a unified integrated active region, denoted as the active region 110.

[0078] The central active region 110_1 may extend in a first direction. The central active region 110_1 may have a rectangular shape in the X-Y plane.

[0079] The drain region D may be located above the central active region 110_1. The drain region D may be a region doped with a first impurity. The first impurity may be, for example, an n-type impurity such as phosphorus (P). The drain region D may be connected to the drain contact 140. The drain contact 140 may receive the operating voltage from a voltage generation circuit included in the peripheral circuit PECT (see Figure 1 ), and may apply the operating voltage to the word line WL (see Figure 1 ) of the selected memory cell block, the string selection line SSL (see Figure 1 ), and the ground selection line GSL. The operating voltage may be, for example, the programming voltage V pgm。In one or more embodiments, the drain contact 140 may be arranged diagonally in the X-Y plane with respect to the first to fourth gate structures 120a, 120b, 120c, and 120d. In one or more embodiments, the spacing distances d1, d2, d3, and d4 between the drain contact 140 and the respective first to fourth gate structures 120a, 120b, 120c, and 120d may be equal to each other. Since the drain contact 140 is diagonally positioned with respect to the first to fourth gate structures 120a, 120b, 120c, and 120d, the spacing distances between the drain contact 140 and the first to fourth gate structures 120a, 120b, 120c, and 120d are maintained, while the area occupied by the first to fourth transfer transistors PTR1, PTR2, PTR3, and PTR4 can be reduced. This arrangement can prevent the breakdown of the first to fourth gate dielectric films 120al, 120bl, 120cl, and 120dl due to the electric field generated by the reduction in the spacing distance between the drain contact 140 and the first to fourth gate structures 120a, 120b, 120c, and 120d, and at the same time, can reduce the area of the first to fourth transfer transistors PTR1, PTR2, PTR3, and PTR4.

[0080] It should be noted that, according to one or more embodiments, the drain region D shown in the central active region 110_1 may be a source / drain region. In the present disclosure, the term "source / drain region" may represent either or both of the source region and the drain region.

[0081] The first separated active region 110_2a, the second separated active region 110_2b, the third separated active region 110_2c, and the fourth separated active region 110_2d may extend from the central active region 110_1 in a second direction perpendicular to the first direction. Specifically, the first separated active region 110_2a may extend from one edge of the central active region 110_1 in the second direction to the top side of the surface of the substrate 101, the second separated active region 110_2b may extend from another edge of the central active region 110_1 in the second direction to the top side T, the third separated active region 110_2c may extend from one edge of the central active region 110_1 in the second direction to the bottom side of the surface of the substrate 101, and the fourth separated active region 110_2d may extend from another edge of the central active region 110_1 in the second direction to the bottom side. The first separated active region 110_2a, the second separated active region 110_2b, the third separated active region 110_2c, and the fourth separated active region 110_2d may have a rectangular shape in the X-Y plane. The terms "top side" and "bottom side" of the substrate 101 represent two opposite sides in the X-Y plane. From the perspective of the semiconductor device 100, these names may be interchanged.

[0082] In one or more embodiments, the first isolated active region 110_2a and the second isolated active region 110_2b may be symmetric to each other with respect to an imaginary line S-S' passing through the central portion of the central active region 110_1, and the third isolated active region 110_2c and the fourth isolated active region 110_2d may be symmetric to each other with respect to the imaginary line S-S'.

[0083] The first source region Sa, the second source region Sb, the third source region Sc, and the fourth source region Sd may be located above the first isolated active region 110_2a, the second isolated active region 110_2b, the third isolated active region 110_2c, and the fourth isolated active region 110_2d, respectively. Specifically, in the z direction, the first source region Sa may be located above the first isolated active region 110_2a, the second source region Sb may be located above the second isolated active region 110_2b, the third source region Sc may be located above the third isolated active region 110_2c, and the fourth source region Sd may be located above the fourth isolated active region 110_2d. The first isolated active region 110_2a, the second isolated active region 110_2b, the third isolated active region 110_2c, and the fourth isolated active region 110_2d may be regions doped with a second impurity. The second impurity may be, for example, an n-type impurity such as phosphorus (P).

[0084] The first source region Sa, the second source region Sb, the third source region Sc, and the fourth source region Sd may be connected to the first contact portion 130a, the second contact portion 130b, the third contact portion 130c, and the fourth contact portion 130d, respectively. According to one or more embodiments, the first contact portion 130a, the second contact portion 130b, the third contact portion 130c, and the fourth contact portion 130d may be source contact portions. The first contact portion 130a, the second contact portion 130b, the third contact portion 130c, and the fourth contact portion 130d may receive an operating voltage from the drain contact portion 140 and may apply the operating voltage to the word line WL (see Figure 1 ) of the selected memory cell block, the string selection line SSL (see Figure 1 ), and the ground selection line GSL. For example, when selecting the memory cell block connected to the first contact portion 130a (hereinafter referred to as the first memory cell block), the first contact portion 130a may receive an operating voltage from the drain contact portion 140 and apply the operating voltage to the word line of the first memory cell block.

[0085] The first gate structure 120a, the second gate structure 120b, the third gate structure 120c, and the fourth gate structure 120d can be arranged at intervals from each other on the substrate 101. Specifically, the first gate structure 120a can be disposed on the first separated active region 110_2a of the substrate 101, the second gate structure 120b can be disposed on the second separated active region 110_2b of the substrate 101, the third gate structure 120c can be disposed on the third separated active region 110_2c of the substrate 101, and the fourth gate structure 120d can be disposed on the fourth separated active region 110_2d of the substrate 101, wherein the first gate structure 120a, the second gate structure 120b, the third gate structure 120c, and the fourth gate structure 120d can be spaced apart from each other. The shared drain region D of the four transfer transistors PTR1, PTR2, PTR3, and PTR4 can be located at the midpoint of the four corners, while the four gate structures 120a, 120b, 120c, and 120d of the four transfer transistors PTR1, PTR2, PTR3, and PTR4 are located at the four corners, forming a symmetric arrangement.

[0086] The first channel region CHa, the second channel region CHb, the third channel region CHc, and the fourth channel region CHd can be respectively located above the first separated active region 110_2a, the second separated active region 110_2b, the third separated active region 110_2c, and the fourth separated active region 110_2d in a third direction perpendicular to the first direction and the second direction, and respectively overlap with the first gate structure 120a, the second gate structure 120b, the third gate structure 120c, and the fourth gate structure 120d. For example, the first channel region CHa can be located above the first separated active region 110_2a in the third direction and overlap with the first gate structure 120a.

[0087] The first gate structure 120a can form the first transfer transistor PTR1 together with the first source region Sa and the drain region D. The second gate structure 120b can form the second transfer transistor PTR2 together with the second source region Sb and the drain region D. The third gate structure 120c can form the third transfer transistor PTR3 together with the third source region Sc and the drain region D. The fourth gate structure 120d can form the fourth transfer transistor PTR4 together with the fourth source region Sd and the drain region D. In other words, as described above, the first transfer transistor PTR1, the second transfer transistor PTR2, the third transfer transistor PTR3, and the fourth transfer transistor PTR4 can share a drain region D.

[0088] The first transfer transistor PTR1, the second transfer transistor PTR2, the third transfer transistor PTR3, and the fourth transfer transistor PTR4 can be configured to apply an operating voltage to different memory cell blocks. For example, one of the first transfer transistor PTR1, the second transfer transistor PTR2, the third transfer transistor PTR3, and the fourth transfer transistor PTR4 can be configured to apply an operating voltage to one of different memory cell blocks based on a memory cell block selection signal.

[0089] In one or more embodiments, the first transfer transistor PTR1, the second transfer transistor PTR2, the third transfer transistor PTR3, and the fourth transfer transistor PTR4 can be high-voltage transfer transistors capable of applying a high voltage to the memory cell blocks. The high voltage can be, for example, from about 10V to about 30V.

[0090] The first gate structure 120a, the second gate structure 120b, the third gate structure 120c, and the fourth gate structure 120d can respectively include a first gate dielectric film 120al, a second gate dielectric film 120bl, a third gate dielectric film 120cl, and a fourth gate dielectric film 120dl, and a first gate electrode 120ag, a second gate electrode 120bg, a third gate electrode 120cg, and a fourth gate electrode 120dg respectively disposed on the first gate dielectric film 120al, the second gate dielectric film 120bl, the third gate dielectric film 120cl, and the fourth gate dielectric film 120dl. Each of the first gate dielectric film 120al, the second gate dielectric film 120bl, the third gate dielectric film 120cl, and the fourth gate dielectric film 120dl can include, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof. Each of the first gate electrode 120ag, the second gate electrode 120bg, the third gate electrode 120cg, and the fourth gate electrode 120dg can include, for example, aluminum, silver, copper, molybdenum, chromium, tantalum, titanium, or a combination thereof.

[0091] In the substrate 101, the isolation region 160 can be located below the device isolation film 150. The isolation region 160 can be a region doped with a third impurity. The third impurity can be, for example, a p-type impurity such as boron (B). The isolation region 160 can electrically isolate the first source region Sa, the second source region Sb, the third source region Sc, and the fourth source region Sd from each other.

[0092] The isolation region 160 may include a first isolation region 160_1 surrounding the active region 110, and a first extended isolation region 160_2a and a second extended isolation region 160_2b extending from the first isolation region 160_1 towards the central active region 110_1 in a second direction. The first extended isolation region 160_2a and the second extended isolation region 160_2b may be symmetric to each other with respect to the line S-S'. In one or more embodiments, the first extended isolation region 160_2a may extend in the second direction along a path between the first contact portion 130a and the second contact portion 130b, and the second extended isolation region 160_2b may extend in the second direction along a path between the third contact portion 130c and the fourth contact portion 130d. Thus, the first extended isolation region 160_2a may electrically isolate the first contact portion 130a from the second contact portion 130b from each other, and the second extended isolation region 160_2b may electrically isolate the third contact portion 130c from the fourth contact portion 130d from each other. In Figure 5B it, the first extended isolation region 160_2a extends in the second direction to be located between the first gate structure 120a and the second gate structure 120b, and the second extended isolation region 160_2b extends in the second direction to be located between the third gate structure 120c and the fourth gate structure 120d. However, as needed, the first extended isolation region 160_2a and the second extended isolation region 160_2b may be further extended or shortened.

[0093] The semiconductor device 100 according to one or more embodiments includes an active region 110 having an H shape and first to fourth gate structures 120a, 120b, 120c, and 120d disposed on the active region 110, wherein the active region 110 and the corresponding first to fourth gate structures 120a, 120b, 120c, and 120d form corresponding first to fourth transfer transistors PTR1, PTR2, PTR3, and PTR4, and share one drain region of the active region 110. Thus, compared with a conventional semiconductor device including an active region, two gate structures disposed above the active region, and two transfer transistors sharing one drain region of the active region, the area of each transfer transistor can be reduced. In addition, compared with a conventional semiconductor device, in the semiconductor device 100 according to an embodiment of the present disclosure, the interval distance between adjacent drain contact portions 140 is relatively increased, thereby allowing better electrical isolation between adjacent drain contact portions 140. Therefore, the performance and reliability of the semiconductor device 100 according to one or more embodiments can be improved.

[0094] The active region of a semiconductor device including a transfer transistor according to an embodiment of the present disclosure may have an H shape. The central active region 110_1 may have a rectangular shape. The first separated active region 110_2a and the second separated active region 110_2b may extend from the central active region 110_1 in one direction to be parallel to each other. The third separated active region 110_2c and the fourth separated active region 110_2d may extend from the central active region 110_1 in the opposite direction to be parallel to each other. The semiconductor device in an embodiment of the present disclosure may include a common source / drain region, that is, a region connected to a global word line, and may include local source / drain regions respectively connected to four different blocks.

[0095] Figure 6 is a layout diagram of a semiconductor device according to one or more embodiments. Figure 6 Each component of the semiconductor device 100a in is the same as each component of the semiconductor device 100 referred to in Figure 5A , Figure 5B and Figure 5C described, and thus, differences will be mainly described hereinafter.

[0096] Figure 6 The semiconductor device 100a in may include a substrate 101, a first gate structure 120a_1, a second gate structure 120b_1, a third gate structure 120c_1, and a fourth gate structure 120d_1. According to one or more embodiments, each of the first gate structure 120a_1, the second gate structure 120b_1, the third gate structure 120c_1, and the fourth gate structure 120d_1 may be set to have a rectangular shape.

[0097] According to one or more embodiments, the first gate structure 120a_1, the second gate structure 120b_1, the third gate structure 120c_1, and the fourth gate structure 120d_1 may be set to have various shapes other than the shapes shown in Figure 5A and Figure 6 shown.

[0098] Figure 7 is a layout diagram of a semiconductor device according to one or more embodiments. Figure 7 Each component of the semiconductor device 100b in is the same as each component of the semiconductor device 100 referred to in Figure 5A , Figure 5B and Figure 5C described, and thus, differences will be mainly described hereinafter.

[0099] Figure 7The semiconductor device 100b therein may include a substrate 101b, a first gate structure 120a_2, a second gate structure 120b_2, a third gate structure 120c_2, and a fourth gate structure 120d_2. Figure 7 The semiconductor device 100b therein may include a central active region 110_1b, a first isolated active region 110_2a2, a second isolated active region 110_2b2, a third isolated active region 110_2c2, and a fourth isolated active region 110_2d2. Each of the first isolated active region 110_2a2, the second isolated active region 110_2b2, the third isolated active region 110_2c2, and the fourth isolated active region 110_2d2 may be arranged spaced apart from the central active region 110_1b.

[0100] The central active region 110_1b may be connected to a drain contact 140b, the first isolated active region 110_2a2 may be connected to a first contact 130a_2, the second isolated active region 110_2b2 may be connected to a second contact 130b_2, the third isolated active region 110_2c2 may be connected to a third contact 130c_2, and the fourth isolated active region 110_2d2 may be connected to a fourth contact 130d_2.

[0101] According to one or more embodiments, the active region formed by the central active region 110_1b, the first isolated active region 110_2a2, the second isolated active region 110_2b2, the third isolated active region 110_2c2, and the fourth isolated active region 110_2d2 may be arranged to have a cross shape. The central active region 110_1b may have a square or rectangular shape and may be located at the midpoint of four outer points. The first isolated active region 110_2a2, the second isolated active region 110_2b2, the third isolated active region 110_2c2, and the fourth isolated active region 110_2d2 may extend from the midpoint to the four outer points respectively, so as to ensure that the cross shape of the active region is symmetric in both the vertical and horizontal directions.

[0102] Figure 8 is a layout diagram of a semiconductor device according to one or more embodiments. Figure 8 Each component of the semiconductor device 100c therein is the same as each component of the semiconductor device 100 described with reference to Figure 5A 、 Figure 5B and Figure 5C Therefore, hereinafter, the differences will be mainly described.

[0103] Figure 8 The semiconductor device 100c therein may include a substrate 101c, a first gate structure 120a_3, a second gate structure 120b_3, and a third gate structure 120c_3. Figure 8The semiconductor device 100c therein may include a central active region 110_1c, a first separated active region 110_2a3, a second separated active region 110_2b3, and a third separated active region 110_2c3. Each of the first separated active region 110_2a3, the second separated active region 110_2b3, and the third separated active region 110_2c3 may extend from the central active region 110_1c. According to one or more embodiments, three gate structures may be spaced apart from each other by the central active region 110_1c.

[0104] The central active region 110_1c may be connected to a drain contact 140c, the first separated active region 110_2a3 may be connected to a first contact 130a_3, the second separated active region 110_2b3 may be connected to a second contact 130b_3, and the third separated active region 110_2c3 may be connected to a third contact 130c_3.

[0105] According to one or more embodiments, the active region formed by the central active region 110_1c, the first separated active region 110_2a3, the second separated active region 110_2b3, and the third separated active region 110_2c3 may be arranged in a Y shape. The central active region 110_1c may have a triangular shape located at the midpoint of three corner points, and the first separated active region 110_2a3, the second separated active region 110_2b3, and the third separated active region 110_2c3 may extend from the midpoint to the three corner points, respectively.

[0106] According to embodiments of the present disclosure, the shape of the active region and the shape of the gate structure may not be limited to Figures 5A to 8 the shapes shown therein, and it should be noted that various modifications may be provided within the scope of achieving the objectives of the embodiments of the present disclosure. Hereinafter, for ease of explanation, the layout structure and wiring structure of a semiconductor device are described based on a semiconductor device having an H-shaped active region. However, the following layout structure and wiring structure are not limited to a semiconductor device having an H-shaped active region, but may also be applied to semiconductor devices having other-shaped active regions.

[0107] Figure 9A is a diagram illustrating the layout structure of a semiconductor device according to one or more embodiments.

[0108] Refer to Figure 9A, four semiconductor devices 210, 220, 230, and 240 having H-shaped active regions are arranged in a 2×2 matrix. According to one or more embodiments, two of the semiconductor devices 210, 220, 230, and 240 are arranged parallel to each other in a first direction, and the other two are arranged parallel to each other in the first direction. The structures and patterns of the semiconductor devices 210, 220, 230, and 240 are the same as each other, and thus, a description is provided only for one semiconductor device 210.

[0109] Each of the semiconductor devices 210, 220, 230, and 240 may include first through fourth gate structures G1, G2, G3, and G4. The first gate structure G1 and the second gate structure G2 may be positioned adjacent to each other in a first direction within one semiconductor device. The third gate structure G3 and the fourth gate structure G4 may be positioned adjacent to each other in a first direction within one semiconductor device. The first gate structure G1 and the third gate structure G3 may be positioned adjacent to each other in a second direction within one semiconductor device.

[0110] Referring to Figure 9A , the first gate structure G1, the second gate structure G2, the third gate structure G3, and the fourth gate structure G4 of the semiconductor device 210 may share a common source / drain region GA1. The common source / drain region GA1 may correspond to the above-mentioned central active region. Referring to Figure 9A , the first gate structure G1 of the semiconductor device 210 may be adjacent to a first local source / drain region LA1. The second gate structure G2 of the semiconductor device 210 may be adjacent to a second local source / drain region LA2. The third gate structure G3 of the semiconductor device 210 may be adjacent to a third local source / drain region LA3. The fourth gate structure G4 of the semiconductor device 210 may be adjacent to a fourth local source / drain region LA4.

[0111] According to one or more embodiments, the common source / drain region GA1, the first local source / drain region LA1, and the first gate structure G1 may form a first transfer transistor. The common source / drain region GA1, the second local source / drain region LA2, and the second gate structure G2 may form a second transfer transistor. The common source / drain region GA1, the third local source / drain region LA3, and the third gate structure G3 may form a third transfer transistor. The common source / drain region GA1, the fourth local source / drain region LA4, and the fourth gate structure G4 may form a fourth transfer transistor.

[0112] Referring to Figure 9A, the contact connected to the common source / drain region GA1 of the semiconductor device 210 may be connected to the first global word line GWL1. The contact connected to the first local source / drain region LA1 of the semiconductor device 210 may be connected to the first local word line LWL1. The contact connected to the second local source / drain region LA2 of the semiconductor device 210 may be connected to the second local word line LWL2. The contact connected to the third local source / drain region LA3 of the semiconductor device 210 may be connected to the third local word line LWL3. The contact connected to the fourth local source / drain region LA4 of the semiconductor device 210 may be connected to the fourth local word line LWL4. According to one or more embodiments, the first transfer transistor included in the semiconductor device 210 may be connected to the first local word line LWL1. The second transfer transistor included in the semiconductor device 210 may be connected to the second local word line LWL2. The third transfer transistor included in the semiconductor device 210 may be connected to the third local word line LWL3. The fourth transfer transistor included in the semiconductor device 210 may be connected to the fourth local word line LWL4.

[0113] According to one or more embodiments, the common source / drain region GA1 included in the semiconductor device 210 may be connected to the first global word line GWL1, and the first local source / drain region LA1 to the fourth local source / drain region LA4 included in the semiconductor device 210 may be connected to the local word lines of different blocks. According to one or more embodiments, there are memory cell blocks respectively connected to the first local source / drain region LA1 to the fourth local source / drain region LA4, and a working voltage may be applied to the word lines of the corresponding memory cell blocks. According to one or more embodiments, the first local source / drain region LA1, the second local source / drain region LA2, the third local source / drain region LA3, and the fourth local source / drain region LA4 included in the semiconductor device 210 may be respectively connected to the local word lines of different blocks.

[0114] Referring to Figure 9A , the first global word line GWL1 may be connected to the common source / drain region GA1 of the semiconductor device 210, the second global word line GWL2 may be connected to the common source / drain region GA2 of the semiconductor device 220, the third global word line GWL3 may be connected to the common source / drain region GA3 of the semiconductor device 230, and the fourth global word line GWL4 may be connected to the common source / drain region GA4 of the semiconductor device 240.

[0115] In other words, the common source / drain regions GA1, GA2, GA3, and GA4 of the respective semiconductor devices 210, 220, 230, and 240 can be connected to different global word lines respectively. Between the local word lines corresponding to each other in the local source / drain regions of each of the semiconductor devices 210, 220, 230, and 240, wirings can be connected in the second direction or the first direction.

[0116] According to one or more embodiments, when Figure 9A the third gate structure G3 adjacent to the region A is turned on, the local word line connected to the region A can be selected, and all the word lines connected to the local source / drain region adjacent to the region A can be local word lines of different blocks. Therefore, the local source / drain region adjacent to the region A can be floated. Accordingly, a consistent voltage condition for the surrounding local source / drain regions can be established.

[0117] Referring to Figure 9A , the gap in the first direction between the separated active regions within each semiconductor device can be B. According to one or more embodiments, B can be an active space. Referring to Figure 9A , the gap in the first direction between the separated active regions of each semiconductor device can be C. Referring to Figure 9A , the gap in the second direction between the separated active regions of each semiconductor device can be D. According to one or more embodiments, B, C, and D can be positive numbers greater than 0. According to one or more embodiments, B, C, and D can be equal to each other. In other words, a plurality of semiconductor devices can be arranged such that B, C, and D satisfy the same conditions.

[0118] According to Figure 9A one or more embodiments, the arrangements of the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure in the semiconductor devices 210, 220, 230, and 240 can be the same as each other, and through such a structure, a consistent voltage condition for the local source / drain region environment around the selected local source / drain region can be established.

[0119] According to one or more embodiments, it should be noted that in the arrangement structures of the plurality of semiconductor devices described below, the wiring structure between the semiconductor devices described with reference to Figure 9A can be similarly applied. The wiring structure between the plurality of semiconductor devices is described in more detail with reference to Figures 19 to 23 .

[0120] Figure 9B is a diagram illustrating the arrangement structure of semiconductor devices according to one or more embodiments.

[0121] In Figure 9B the embodiment, the content that has been referred to with reference to Figure 9AThe description given. Refer to Figure 9B , which shows the first semiconductor device to the fourth semiconductor devices 211, 221, 231, and 241. Each of the first semiconductor device to the fourth semiconductor devices 211, 221, 231, and 241 may include a first gate structure G1, a second gate structure G2, a third gate structure G3, and a fourth gate structure G4.

[0122] The first semiconductor device 211 and the second semiconductor device 221 may be arranged adjacent to each other in a first direction. The first semiconductor device 211 and the third semiconductor device 231 may be arranged adjacent to each other in a second direction.

[0123] The gate structure provided above the central portions of the first semiconductor device 211 and the second semiconductor device 221 may be arranged symmetrically about the Y-axis between the first semiconductor device 211 and the second semiconductor device 221. Refer to Figure 9B , the gate structures provided above the central portion of the first semiconductor device 211 may be arranged in the order of the first gate structure G1 and the second gate structure G2, and the gate structures provided above the central portion of the second semiconductor device 221 may be arranged in the order of the second gate structure G2 and the first gate structure G1.

[0124] The gate structures below the central portions of the first semiconductor device 211 and the second semiconductor device 221 may be arranged symmetrically about the Y-axis between the first semiconductor device 211 and the second semiconductor device 221. Refer to Figure 9B , the gate structures provided below the central portion of the first semiconductor device 211 may be arranged in the order of the third gate structure G3 and the fourth gate structure G4, and the gate structures provided below the central portion of the second semiconductor device 221 may be arranged in the order of the fourth gate structure G4 and the third gate structure G3.

[0125] The third semiconductor device 231 and the fourth semiconductor device 241 located in the second row may also be arranged with the same structure as the first semiconductor device 211 and the second semiconductor device 221.

[0126] Figure 10 is a diagram illustrating the arrangement structure of semiconductor devices according to one or more embodiments. In Figure 10 's embodiment, the description that has been referred to Figure 9A given may be omitted.

[0127] Refer to Figure 10, which shows a first semiconductor device 212 and a second semiconductor device 232 arranged adjacent to each other in a second direction. The gate structure disposed above the central portions of the first semiconductor device 212 and the second semiconductor device 232 may be arranged in a left-right symmetric manner between the first semiconductor device 212 and the second semiconductor device 232. Refer to Figure 10 , the gate structure disposed above the central portion of the first semiconductor device 212 may be arranged in the order of a first gate structure G1 and a second gate structure G2, and the gate structure disposed above the central portion of the second semiconductor device 232 may be arranged in the order of the second gate structure G2 and the first gate structure G1.

[0128] The gate structure disposed below the central portions of the first semiconductor device 212 and the second semiconductor device 232 may be arranged in a left-right symmetric manner between the first semiconductor device 212 and the second semiconductor device 232. Refer to Figure 10 , the gate structure disposed below the central portion of the first semiconductor device 212 may be arranged in the order of a third gate structure G3 and a fourth gate structure G4, and the gate structure disposed below the central portion of the second semiconductor device 232 may be arranged in the order of the fourth gate structure G4 and the third gate structure G3.

[0129] In other words, refer to Figure 10 , one row of gates of each of the semiconductor devices 212 and 232 may be left-right symmetric to each other, and two rows of gates of each of the semiconductor devices 212 and 232 may be left-right symmetric to each other.

[0130] In an embodiment of the present disclosure, a method for connecting word lines of the semiconductor devices proposed herein and a layout method thereof without adding a separate metal (i.e., without increasing the process cost) are disclosed. In the embodiment, semiconductor devices having the same shape may be repeatedly arranged in a first direction, and gate structures having various symmetric shapes may be repeatedly arranged in a second direction. Further, the semiconductor devices may each require at least one metal in the bit line direction for connection to the same word line, and one track may be shared between the semiconductor devices arranged in the same column for connecting the word lines. According to the embodiment, by arranging a plurality of semiconductor devices in a specific pattern in units of four blocks, the use of metal when connecting the word lines can be minimized, and a similar metal pattern can be formed for each group.

[0131] Figure 11 is a diagram illustrating an example in which semiconductor devices according to one or more embodiments are arranged corresponding to a plurality of block structures.

[0132] Refer to Figure 11, showing a structure in which a plurality of semiconductor devices are arranged parallel to each other in a first direction and a second direction corresponding to a height of four blocks. The height of each semiconductor device may correspond to the height of one memory block.

[0133] Referring to Figure 11 , six semiconductor devices are arranged in the first direction in each row, and four semiconductor devices are arranged in the second direction in each column. According to one or more embodiments, the plurality of semiconductor devices arranged in the first row may correspond to Figure 4 the first transfer transistor circuit block in Figure 4 . The plurality of semiconductor devices arranged in the second row may correspond to Figure 4 the second transfer transistor circuit block in Figure 4 . The plurality of semiconductor devices arranged in the third row may correspond to

[0134] the third transfer transistor circuit block in Figure 9A . The plurality of semiconductor devices arranged in the fourth row may correspond to

[0135] Figure 12 the fourth transfer transistor circuit block in

[0136] In the following embodiments, it can be understood that the plurality of semiconductor devices arranged in one row are included in one transfer transistor circuit block. Figure 12

[0137] Figure 10 According to one or more embodiments, the gate structure above the central portion of the plurality of semiconductor devices arranged in the first row may be left - right symmetric with the gate structure above the central portion of the plurality of semiconductor devices arranged in the second row. According to one or more embodiments, the gate structure provided below the central portion of the plurality of semiconductor devices arranged in the first row may be left - right symmetric with the gate structure provided below the central portion of the plurality of semiconductor devices arranged in the second row. This may be the same as Figure 10The layout structures of the semiconductor devices shown are the same. In such a structure, the connection relationships between the gates in adjacent rows can be Y-axis symmetric with respect to the central portion of the semiconductor device.

[0138] Figure 13 is a diagram illustrating an example in which semiconductor devices according to one or more embodiments are arranged to correspond to a plurality of block structures.

[0139] Referring to Figure 13 , a structure is shown in which a plurality of semiconductor devices are arranged parallel to each other in a first direction and a second direction to correspond to a four-block height. The plurality of semiconductor devices may be arranged parallel to each other along a first row, a second row, a third row, and a fourth row in the first direction. According to one or more embodiments, the patterns of the plurality of semiconductor devices arranged in the first row may be the same as the patterns of the plurality of semiconductor devices arranged in the second row. The patterns of the plurality of semiconductor devices arranged in the third row may be the same as the patterns of the plurality of semiconductor devices arranged in the fourth row.

[0140] According to one or more embodiments, the gate structure provided above the central portion of the plurality of semiconductor devices arranged in the second row may be left-right symmetric with the gate structure provided above the central portion of the plurality of semiconductor devices arranged in the third row. According to one or more embodiments, the gate structure provided below the central portion of the plurality of semiconductor devices arranged in the second row may be left-right symmetric with the gate structure provided below the central portion of the plurality of semiconductor devices arranged in the third row. This may be the same as the layout structure of the semiconductor devices shown in Figure 10 .

[0141] It can be provided by dividing half of the total n rows as shown in Figure 12 and Figure 13 to provide a configuration in which the gates in a specific row within the column structure are Y-axis symmetric with each other as shown in Figure 10 , or an asymmetric arrangement configuration such as 1:n-1 or 2:n-2 may be employed.

[0142] Figure 14 is a diagram illustrating an example in which semiconductor devices according to one or more embodiments are arranged to correspond to a plurality of block structures.

[0143] Referring to Figure 14, shows a structure in which a plurality of semiconductor devices are arranged parallel to each other in a first direction and a second direction corresponding to four block heights. The plurality of semiconductor devices may be arranged parallel to each other along a first row, a second row, a third row, and a fourth row in the first direction. According to one or more embodiments, the pattern of the plurality of semiconductor devices arranged in the first row may be the same as the pattern of the plurality of semiconductor devices arranged in the third row. The pattern of the plurality of semiconductor devices arranged in the second row may be the same as the pattern of the plurality of semiconductor devices arranged in the fourth row. In other words, the semiconductor devices in the first row may have the same pattern as the semiconductor devices in the third row, while the semiconductor devices in the second row may have the same pattern as the semiconductor devices in the fourth row, but have a different pattern from the semiconductor devices in the first row and the third row.

[0144] Referring to Figure 14 , the pattern of the plurality of semiconductor devices arranged in the first row may be arranged to have origin symmetry with respect to a middle portion with respect to the pattern of the plurality of semiconductor devices arranged in the second row. The middle portion may refer to the midpoint between the plurality of local source / drain regions and between the first row and the second row. Origin symmetry may refer to diagonal symmetry with respect to a symmetry reference point.

[0145] Referring to Figure 14 , the result of the origin symmetry of the first gate structure G1 and the second gate structure G2 provided above the central portion of the pattern of the plurality of semiconductor devices arranged in the first row may correspond to the second gate structure G2 and the first gate structure G1 provided below the central portion of the pattern of the plurality of semiconductor devices arranged in the second row. The result of the origin symmetry of the third gate structure G3 and the fourth gate structure G4 provided below the central portion of the pattern of the plurality of semiconductor devices arranged in the first row may correspond to the fourth gate structure G4 and the third gate structure G3 provided above the central portion of the pattern of the plurality of semiconductor devices arranged in the second row.

[0146] Figure 15 is a diagram illustrating an example in which semiconductor devices according to one or more embodiments are arranged corresponding to a plurality of block structures.

[0147] Referring to Figure 15 , shows a structure in which a plurality of semiconductor devices are arranged parallel to each other in a first direction and a second direction corresponding to four block heights. The plurality of semiconductor devices may be arranged parallel to each other along a first row, a second row, a third row, and a fourth row in the first direction. According to Figure 15 the embodiments, the pattern of the plurality of semiconductor devices arranged in the first row may be the same as the pattern of the plurality of semiconductor devices arranged in the third row. The pattern of the plurality of semiconductor devices arranged in the second row may be the same as the pattern of the plurality of semiconductor devices arranged in the fourth row.

[0148] Reference Figure 15 , the patterns of multiple semiconductor devices arranged in the first row can have mirror symmetry about an imaginary line between the first row and the second row in a first direction with respect to the patterns of multiple semiconductor devices arranged in the second row. The result of the mirror symmetry in the first direction of the first gate structure G1 and the second gate structure G2 provided above the center points of the patterns of multiple semiconductor devices arranged in the first row can correspond to the first gate structure G1 and the second gate structure G2 provided below the center points of the patterns of multiple semiconductor devices arranged in the second row. The result of the mirror symmetry in the first direction of the third gate structure G3 and the fourth gate structure G4 provided below the center points of the patterns of multiple semiconductor devices arranged in the first row can correspond to the third gate structure G3 and the fourth gate structure G4 provided above the center points of the patterns of multiple semiconductor devices arranged in the second row.

[0149] According to one or more embodiments, in such a structure, as shown in regions A and A', blocks of local source / drain regions that face each other in a second direction of specific local source / drain regions can face each other. In this case, the voltages around the selected local source / drain regions may not all float.

[0150] Figure 16 is a diagram illustrating an example in which semiconductor devices according to one or more embodiments are arranged to correspond to multiple block structures.

[0151] Reference Figure 16 , a structure is shown in which multiple semiconductor devices are arranged parallel to each other in a first direction and a second direction to correspond to a four-block height. The multiple semiconductor devices can be arranged parallel to each other along a first row, a second row, a third row, and a fourth row in the first direction. Reference Figure 16 , the patterns of multiple semiconductor devices arranged in the first row, the patterns of multiple semiconductor devices arranged in the second row, the patterns of multiple semiconductor devices arranged in the third row, and the patterns of multiple semiconductor devices arranged in the fourth row can be the same as each other.

[0152] Reference Figure 16 , each of the multiple semiconductor devices in the first row can be Y-axis symmetric with an adjacent semiconductor device in the same row. According to one or more embodiments, such an arrangement structure can be the same as the arrangement structure of the semiconductor devices in Figure 9B .

[0153] In this configuration, a voltage can be applied to a block in which gate structures adjacent to each other in a first direction are the same, and at this time, gate nodes of gates in the same block may not be isolated. In this regard, the gate node may refer to a gate contact. In this structure, corresponding local source / drain regions of gate structures adjacent to each other may be the same as each other, and thus, in this structure, B may be greater than C (B > C).

[0154] Figure 17 is a diagram illustrating an example in which a semiconductor device according to one or more embodiments is arranged to correspond to a plurality of block structures.

[0155] Referring to Figure 17 , a structure is shown in which a plurality of semiconductor devices are arranged parallel to each other in a first direction and a second direction to correspond to a four-block height. The plurality of semiconductor devices may be arranged parallel to each other along a first row, a second row, a third row, and a fourth row in the first direction. Referring to Figure 17 , patterns of the plurality of semiconductor devices arranged in the first row, patterns of the plurality of semiconductor devices arranged in the second row, patterns of the plurality of semiconductor devices arranged in the third row, and patterns of the plurality of semiconductor devices arranged in the fourth row may be the same as each other.

[0156] Referring to Figure 17 , the pattern of the plurality of semiconductor devices in the first row may have origin symmetry in the second direction with respect to adjacent semiconductor devices in the same row. As a result of the origin symmetry in the second direction of the first gate structure G1 and the second gate structure G2 provided above the central portion of the pattern of the plurality of semiconductor devices arranged in the first row, it may correspond to the second gate structure G2 and the first gate structure G1 provided below the central portion of the pattern of adjacent semiconductor devices in the first row. As a result of the origin symmetry in the second direction of the third gate structure G3 and the fourth gate structure G4 provided below the central portion of the pattern of the plurality of semiconductor devices arranged in the first row, it may correspond to the fourth gate structure G4 and the third gate structure G3 provided above the central portion of the pattern of adjacent semiconductor devices in the first row.

[0157] Figure 18 is a diagram illustrating an example in which a semiconductor device according to one or more embodiments is arranged to correspond to a plurality of block structures.

[0158] Referring to Figure 18 , a structure is shown in which a plurality of semiconductor devices are arranged parallel to each other in a first direction and a second direction to correspond to a four-block height. The plurality of semiconductor devices may be arranged parallel to each other along a first row, a second row, a third row, and a fourth row in the first direction. Referring to Figure 18, the patterns of the multiple semiconductor devices arranged in the first row, the patterns of the multiple semiconductor devices arranged in the second row, the patterns of the multiple semiconductor devices arranged in the third row, and the patterns of the multiple semiconductor devices arranged in the fourth row can be the same as each other.

[0159] Referring to Figure 18 , the pattern of the multiple semiconductor devices in the first row can be symmetric about the X-axis with respect to the pattern of an adjacent semiconductor device in the same row. Referring to Figure 18 , the gate structure disposed above the central portion of the pattern of the multiple semiconductor devices arranged in the first row can correspond to the gate structure disposed below the central portion of the pattern of an adjacent semiconductor device in the same row. According to one or more embodiments, the result of the X-axis symmetry of the first gate structure G1 and the second gate structure G2 disposed above the central portion of the multiple semiconductor devices arranged in the first row can correspond to the first gate structure G1 and the second gate structure G2 disposed below the central portion of the pattern of an adjacent semiconductor device in the first row. Due to the result of the X-axis symmetry of the third gate structure G3 and the fourth gate structure G4 disposed below the central portion of the pattern of the multiple semiconductor devices arranged in the first row can correspond to the third gate structure G3 and the fourth gate structure G4 disposed above the central portion of the pattern of an adjacent semiconductor device in the first row.

[0160] According to Figures 16 to 18 the embodiment, multiple semiconductor devices can be arranged in different patterns within the same row. In addition, in Figures 16 to 18 the embodiment, multiple semiconductor devices are arranged in the same pattern in adjacent rows, but the embodiment is not limited thereto, and it should be noted that multiple semiconductor devices can be arranged in different patterns in adjacent rows. In addition, in the embodiments of the drawings, the patterns within the same row or the patterns in adjacent rows are formed by repeating 1:1, but it should be noted that the arrangement ratio of the semiconductor patterns can be formed in various ways.

[0161] Figure 19 is a diagram illustrating an example in which semiconductor devices according to one or more embodiments are arranged to correspond to multiple block structures.

[0162] Referring to Figure 19, which shows a structure in which a plurality of semiconductor devices are arranged in a first direction and a second direction to correspond to a four-block height. The plurality of semiconductor devices may be arranged parallel to each other along a first row, a second row, a third row, and a fourth row in the first direction. According to one or more embodiments, the plurality of semiconductor devices arranged in the first row and the plurality of semiconductor devices arranged in the second row may be offset from each other by half of the pitch of the semiconductor devices. The plurality of semiconductor devices arranged in the second row and the plurality of semiconductor devices arranged in the third row may be offset from each other by half of the pitch of the semiconductor devices. The plurality of semiconductor devices arranged in the third row and the plurality of semiconductor devices arranged in the fourth row may be offset from each other by half of the pitch of the semiconductor devices. Thus, the plurality of semiconductor devices may be arranged in a zigzag pattern for each row.

[0163] Referring to Figure 19 , region E is a node connected to the global word line of the semiconductor device, and region E' is located at a point corresponding to the gap between the semiconductor devices in adjacent columns. In other words, in this case, according to the misalignment point of the global word line routing (e.g., in region F), the global word line routing is provided in two units.

[0164] Figure 20 is a diagram illustrating an example in which semiconductor devices according to one or more embodiments are arranged to correspond to a plurality of block structures.

[0165] Referring to Figure 20 , which shows a structure in which a plurality of semiconductor devices are arranged parallel to each other in a first direction and a second direction to correspond to a four-block height. The plurality of semiconductor devices may be arranged parallel to each other along a first row, a second row, and a third row in the first direction.

[0166] In the above embodiment, a structure has been described in which the semiconductor devices are arranged in four layers to correspond to the block height of four memory blocks. However, this structure may vary according to the height of the blocks and the size of the semiconductor devices in the vertical direction. Referring to Figure 20 , the height of the plurality of semiconductor devices may not correspond 1:1 to the height of the memory blocks respectively, and the semiconductor devices may be provided respectively in a size larger than the height of the memory blocks. Figure 20 shows an example in which three semiconductor devices corresponding to the height of four memory blocks are arranged parallel to each other in each column in the second direction, but the embodiment is not limited thereto, and n semiconductor devices corresponding to the height of four memory blocks may also be arranged parallel to each other in each column in the second direction. In this regard, n may be a natural number of 1 or greater.

[0167] Figure 21 is a diagram describing the connection structure between semiconductor devices and word lines according to one or more embodiments.

[0168] Referring toFigure 21 , which shows word lines that can be respectively connected to semiconductor devices as an example. According to one or more embodiments, the word line connected to the semiconductor device arranged in the first column of the first row may have a word line number 0. According to one or more embodiments, the word line connected to the semiconductor device arranged in the first column of the second row may have a word line number 1. The word line connected to the semiconductor device arranged in the first column of the third row may have a word line number 2. The word line connected to the semiconductor device arranged in the first column of the fourth row may have a word line number 3. In this way, the word lines that can be respectively connected to semiconductor devices can be determined.

[0169] Figure 22 is a diagram illustrating a connection structure between a semiconductor device and a word line according to one or more embodiments. Figure 23 is a diagram illustrating a connection structure between a semiconductor device and a local word line according to one or more embodiments.

[0170] Referring to Figure 22 , the numbers of word lines respectively connected to semiconductor devices are shown, and each semiconductor device can be connected to word line pads respectively corresponding to a plurality of gate structures. According to one or more embodiments, the number of the word line pad corresponding to the first gate structure of the semiconductor device arranged in the first column of the first row may be 0. The number of the word line pad corresponding to the second gate structure of the semiconductor device arranged in the first column of the first row may be 2. The number of the word line pad corresponding to the third gate structure of the semiconductor device arranged in the first column of the first row may be 1. The number of the word line pad corresponding to the fourth gate structure of the semiconductor device arranged in the first column of the first row may be 3.

[0171] According to one or more embodiments, the number of the word line pad corresponding to the first gate structure of the semiconductor device arranged in the first column of the second row may be 1. The number of the word line pad corresponding to the second gate structure of the semiconductor device arranged in the first column of the second row may be 3. The number of the word line pad corresponding to the third gate structure of the semiconductor device arranged in the first column of the second row may be 0. The number of the word line pad corresponding to the fourth gate structure of the semiconductor device arranged in the first column of the second row may be 2.

[0172] Figure 23 is a diagram describing a wiring structure between different semiconductor devices based on Figure 22 word line pads. According to one or more embodiments, the word line pads respectively corresponding to a plurality of gate structures included in a plurality of semiconductor devices may be connected to word line pads located in different blocks.

[0173] According to one or more embodiments, the semiconductor device 1000 located in the first memory block BLK0 that should be connected to word line number 0 can be connected to other blocks having word line pad number 0 of a plurality of other semiconductor devices arranged in the same column. Thus, the semiconductor device located in the first memory block BLK0 that should be connected to word line number 0 can be connected to word line pad number 0 of the semiconductor devices in the first memory block BLK0, word line pad number 0 of the semiconductor devices in the second memory block BLK1, word line pad number 0 of the semiconductor devices in the third memory block BLK2, and word line pad number 0 of the semiconductor devices in the fourth memory block BLK3. In other words, the word line pads corresponding to the multiple gate structures included in the multiple semiconductor devices can be respectively connected to the word lines in another block, and the number of the word line is the same as the number of the corresponding word line pad.

[0174] For example, the local source / drain regions of each semiconductor device can be respectively connected to word line pad number 0, word line pad number 1, word line pad number 2, and word line pad number 3 in the semiconductor device that should be connected to word line number 0. In this regard, in the case of the local source / drain region corresponding to word line pad number 0, the number of the word line pad is the same as the number of the word line of the corresponding semiconductor device, and thus, connection to another block may not be required. The local source / drain region corresponding to word line pad number 1 can be connected to word line pad number 0 located in block number 1. The local source / drain region corresponding to word line pad number 2 can be connected to word line 0 located in block number 2. The local source / drain region corresponding to word line pad number 3 can be connected to word line pad number 0 located in block number 3.

[0175] Refer to Figure 22 and Figure 23 , the local source / drain regions corresponding to the multiple gate structures included in each semiconductor device can respectively correspond to different memory cell blocks, and referring to the number of the word line pad corresponding to the local source / drain region, the vertical wiring and horizontal wiring of the local word lines between different blocks within the same column can be connected to each other. According to one or more embodiments, the active regions of the nodes of the local word lines of the four blocks share the nodes of the global word line, so as to be able to connect to the same word line of different four blocks. According to one or more embodiments, one of the wirings in the four local source / drain regions can be connected to the same block where the corresponding semiconductor device is placed, and the remaining three wirings can be connected to the other three blocks.

[0176] Figure 24 is a diagram illustrating the connection structure between a semiconductor device and a global word line according to one or more embodiments.

[0177] Refer to Figure 24, Four global word lines are connected to a plurality of semiconductor devices arranged in the first column, four global word lines are connected to a plurality of semiconductor devices arranged in the second column, four global word lines are connected to a plurality of semiconductor devices arranged in the third column, four global word lines are connected to a plurality of semiconductor devices arranged in the fourth column, four global word lines are connected to a plurality of semiconductor devices arranged in the fifth column, and four global word lines are connected to a plurality of semiconductor devices arranged in the sixth column. The global word lines can be respectively connected to the corresponding semiconductor devices. According to one or more embodiments, the number of global word lines included in a column can correspond to the number of a plurality of semiconductor devices included in a column. Refer to Figure 24 , The number of a plurality of semiconductor devices included in a column can be four, and thus, the number of global word lines included in each column can also be four. According to one or more embodiments, the routing of the global word lines included in each column can be arranged to gather around the global word line nodes of the H-shaped active pattern.

[0178] Figure 25 is a diagram illustrating a connection structure between a semiconductor device and a global word line according to one or more embodiments.

[0179] Refer to Figure 25 , Examples of various arrangements of global word lines in each column are shown. According to one or more embodiments, the routing of the global word lines can be freely arranged on lines that do not interfere with the connection structure of the local word lines.

[0180] Refer to column E, the global word lines can be evenly arranged left and right within column E. Refer to column F, the global word lines can be arranged to have the same spacing within the H-shaped active pattern. Refer to column G, the global word lines can be arranged with a wide spacing on the left and a narrow spacing on the right with respect to the central portion of column G. Refer to column H, three global word lines can be arranged on the left and one global word line can be arranged on the right with respect to the central portion of column H.

[0181] According to one or more embodiments, in the structure as shown in Figure 24 , the routing of the global word lines can be arranged at the center of the H-shaped active pattern, and the vertical routing of the local word lines can be arranged in the remaining regions. In the structure as shown in Figure 25 , the vertical routing of the local word lines can be arranged between the routings of the global word lines.

[0182] In Figure 25 , in columns G and H, the routings of some global word lines are arranged adjacent to each other. However, in the case where the routings of the global word lines are arranged adjacent to each other, the vertical routing of the local word lines can be arranged in the space between the adjacent routings of the global word lines and the remaining routings.

[0183] According to an embodiment of the present disclosure, when a plurality of semiconductor devices are arranged parallel to each other in a first direction and a second direction, the wiring of global word lines corresponding to the number of semiconductor devices in the column direction and the wiring between local word lines within the corresponding column should be included within the pitch of the active region of one of the semiconductor devices among the plurality of semiconductor devices (i.e., the width obtained by adding the horizontal width of the H shape and the gap between the H shapes). At this time, when the pitch of the active region of the semiconductor device is greater than the sum of the pitches of the number of vertical metal wirings, vertical wiring with separate tracks can be used. According to one or more embodiments, some of the vertical wirings can share tracks. According to one or more embodiments, the global word lines pass through the semiconductor devices in the entire column direction and can be wired as separate tracks, and the vertical or horizontal wiring of the local word lines can share tracks.

[0184] According to an embodiment of the present disclosure, a semiconductor device is shown that can connect to word lines of multiple different blocks by using an active pattern having a shape other than a rectangle. According to one or more embodiments, based on the nodes of the word lines to which the selected word line is connected, the voltage environment at all positions can be the same. According to one or more embodiments, the surrounding environment except the selected word line can all be floated. According to an embodiment of the present disclosure, the arrangement of transfer transistors corresponding to four memory blocks can be arranged in a basic repeating unit. According to one or more embodiments, the wiring of the word lines can be repeated in the same pattern for every four blocks. Therefore, the active positions of each word line can be freely connected.

[0185] The semiconductor device according to an embodiment of the present disclosure can have an H-type active region, and a plurality of isolation gate structures included in the semiconductor device can respectively select different memory blocks. A plurality of semiconductor devices according to an embodiment of the present disclosure are arranged parallel to each other in a second direction, and a vertical wiring structure for connecting to other word lines in different blocks is shown. Therefore, a stack of a plurality of semiconductor devices can be formed, and various connection methods can be adopted, thereby increasing the degree of freedom of the arrangement method.

[0186] The above exemplary embodiments should not be construed as limiting, merely by way of example. The present teachings can be readily applied to other types of devices. Moreover, the description of the exemplary embodiments is intended to be illustrative and not to limit the scope of the claims, and various alternatives, modifications, and variations will be apparent to those skilled in the art.

Claims

1. A semiconductor device, comprising: A substrate having an active region, the active region including a central active region and a plurality of separated active regions extending from the central active region; And A plurality of gate structures disposed above the active region, Wherein the plurality of gate structures, the central active region, and the plurality of separated active regions constitute a plurality of transfer transistors, and Wherein the plurality of transfer transistors share the same source / drain region in the central active region.

2. The semiconductor device according to claim 1, wherein, Each of the plurality of gate structures has a rectangular shape or an L-shaped shape.

3. The semiconductor device according to claim 1, wherein, The active region has an H-shaped shape, wherein the central active region has a rectangular shape, two of the plurality of separated active regions extend from the central active region in one direction and are parallel to each other, and the other two of the plurality of separated active regions extend from the central active region in the opposite direction and are parallel to each other.

4. The semiconductor device according to claim 1, wherein, The active region has: A cross shape, wherein the central active region has a rectangular shape and is located at the midpoint of four outer points, and the plurality of separated active regions extend from the midpoint to the four outer points respectively; or A Y shape, wherein the central active region has a triangular shape and is located at the midpoint of three corner points, and the plurality of separated active regions extend from the midpoint to the three corner points respectively.

5. The semiconductor device according to claim 1, further comprising: A drain contact connected to the central active region; And A plurality of source contacts of the plurality of transfer transistors, respectively connected to the plurality of separated active regions.

6. The semiconductor device according to claim 5, wherein, The drain contact is connected to a global word line, and Wherein the plurality of source contacts are connected to a plurality of different local word lines.

7. The semiconductor device according to claim 6, wherein, The plurality of source contacts are respectively connected to different memory cell blocks.

8. A storage device, comprising: A plurality of memory blocks including a plurality of memory cells connected to a plurality of word lines stacked in a vertical direction; And A plurality of transfer transistor circuit blocks connected to the plurality of memory blocks and arranged parallel to each other in a second horizontal direction, Wherein each of the plurality of transfer transistor circuit blocks includes a plurality of semiconductor devices arranged parallel to each other in a first horizontal direction, and Wherein each of the plurality of semiconductor devices includes: A substrate having an active region, the active region including a central active region and a plurality of separated active regions extending from the central active region; and A plurality of gate structures disposed above the active region, The plurality of gate structures, the central active region, and the plurality of separated active regions constitute a plurality of transfer transistors, and The plurality of transfer transistors share the same source / drain region in the central active region.

9. The storage device according to claim 8, wherein, The patterns of the plurality of semiconductor devices are the same within the same transfer transistor circuit block among the plurality of transfer transistor circuit blocks.

10. The storage device according to claim 8, wherein, The patterns of the semiconductor devices included in the transfer transistor circuit blocks adjacent to each other in the second horizontal direction among the plurality of transfer transistor circuit blocks are different from each other.

11. The storage device according to claim 8, wherein, Semiconductor devices included in adjacent transmission transistor circuit blocks adjacent to each other in the second horizontal direction among the plurality of transmission transistor circuit blocks are electrically connected to each other via wirings in the second horizontal direction or the first horizontal direction.

12. The storage device according to claim 8, wherein, Global word lines connected via the wirings in the second horizontal direction are connected to the source / drain regions of the semiconductor devices included in each of the plurality of transmission transistor circuit blocks arranged adjacent to each other in the second horizontal direction.

13. The storage device according to claim 8, wherein, The plurality of transmission transistor circuit blocks are electrically connected to each other via a plurality of local word lines among the plurality of word lines, respectively.

14. A storage device, comprising: A plurality of memory cell blocks arranged parallel to each other in a second direction; And A plurality of semiconductor devices connected to the plurality of memory cell blocks, wherein the plurality of semiconductor devices are arranged parallel to each other in the second direction, and N semiconductor devices among the plurality of semiconductor devices are arranged parallel to each other in a first direction, where N is a natural number greater than or equal to 1, and wherein each of the plurality of semiconductor devices includes: A substrate having an active region, the active region including a central active region and a plurality of separated active regions extending from the central active region; and A plurality of gate structures provided above the active region, The plurality of gate structures, the central active region, and the plurality of separated active regions constitute a plurality of transmission transistors, and The plurality of transmission transistors share the same source / drain region in the central active region.

15. The storage device according to claim 14, wherein, Global word lines are connected to the source / drain regions of each of the plurality of semiconductor devices, and wherein different local word lines are connected to the plurality of separated active regions of each of the plurality of semiconductor devices.

16. The storage device according to claim 15, wherein, The plurality of semiconductor devices arranged parallel to each other in the second direction are respectively connected to different global word lines.

17. The storage device according to claim 15, wherein, Each of the plurality of semiconductor devices arranged parallel to each other in the second direction is electrically connected to each other via the connection of the different local word lines.

18. The storage device according to claim 17, wherein, Each of the plurality of semiconductor devices arranged parallel to each other in the second direction is electrically connected to each other based on the numbers of word line pads corresponding to the plurality of separated active regions and the numbers of global word lines, respectively.

19. The storage device according to claim 17, wherein, Each of the plurality of semiconductor devices arranged parallel to each other in the second direction is electrically connected to each other via wirings in the first direction and / or the second direction.

20. The storage device according to claim 19, wherein, The wirings in the first direction and / or the second direction share one or more tracks.

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