Array substrate, display panel and electronic equipment

Abstract

According to the array substrate, the display panel and the electronic equipment provided by the invention, the two adjacent driving units in the first direction in the array substrate are arranged to share the first scanning line and the second scanning line; the semiconductor wiring section in the driving unit can extend along a straight line and is respectively overlapped with the first scanning wiring and the second scanning wiring to form the first switch transistor and the second switch transistor, so that the space occupied by the semiconductor wiring section can be reduced.

Description

[0001] This application claims the priority of a Chinese patent application with the application number 2024100085465 and the title "Array Substrate, Display Panel and Electronic Device" filed with the Chinese Patent Office on January 2, 2024, the entire content of which is incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, and more particularly, to an array substrate, a display panel and an electronic device. Background Art

[0003] In some display panels, in order to implement an under-screen camera or under-screen optical fingerprint recognition in a full-screen display, a light-transmissive display area is provided in the display panel. Under the condition of meeting the display function, external light can enter the optical acquisition device under the display panel through this light-transmissive display area. However, with the increase in pixel density (PPI), the wiring in the array substrate of the display panel becomes more dense, resulting in the compression of the light-transmissive area in the array substrate and affecting the overall transmittance of the display panel. Summary of the Invention

[0004] In order to overcome the above deficiencies in the prior art, the purpose of this application is to provide an array substrate, which includes:

[0005] A substrate;

[0006] A first semiconductor layer on one side of the substrate, the first semiconductor layer includes a first semiconductor trace segment and a second semiconductor trace segment; the first semiconductor trace segment and the second semiconductor trace segment extend side by side in a first direction;

[0007] A first conductive layer on the side of the first semiconductor layer away from the substrate, the first conductive layer includes a first scan trace and a second scan trace, the first scan trace and the second scan trace extend side by side in a second direction; the first direction intersects with the second direction;

[0008] The array substrate includes a plurality of driving units, and the driving units include a first driving unit and a second driving unit adjacent to each other in the first direction;

[0009] In the first direction, the first driving unit is located on the side of the first scan trace away from the second scan trace, and the second driving unit is located on the side of the second scan trace away from the first scan trace;

[0010] The positive projections of the first semiconductor trace segments on the substrate coincide at least partially with the positive projections of the first scan trace and the second scan trace on the substrate, and the first switching transistor and the second switching transistor of the first driving unit are located at the positions where the positive projections of the first semiconductor trace segments coincide with the positive projections of the first scan trace and the second scan trace;

[0011] The positive projections of the second semiconductor trace segments on the substrate coincide at least partially with the positive projections of the first scan trace and the second scan trace on the substrate, and the first switching transistor and the second switching transistor of the second driving unit are located at the positions where the positive projections of the second semiconductor trace segments coincide with the positive projections of the first scan trace and the second scan trace.

[0012] In some possible implementation manners, the first semiconductor layer further includes a third semiconductor trace segment corresponding to other transistors in the first driving unit except for the first switching transistor and the second switching transistor of the first driving unit, and a fourth semiconductor trace segment corresponding to other transistors in the second driving unit except for the first switching transistor and the second switching transistor of the second driving unit; the third semiconductor trace segment and the fourth semiconductor trace segment are symmetrically arranged with respect to an axis of symmetry extending along the second direction;

[0013] Preferably, the positive projection of the axis of symmetry on the substrate is located between the first scan trace and the second scan trace.

[0014] In some possible implementation manners, the driving unit includes a driving transistor; the first semiconductor layer further includes a third semiconductor trace segment corresponding to other transistors in the first driving unit except for the first switching transistor, the second switching transistor, and the driving transistor of the first driving unit, and a fourth semiconductor trace segment corresponding to other transistors in the second driving unit except for the first switching transistor, the second switching transistor, and the driving transistor of the second driving unit; the third semiconductor trace segment and the fourth semiconductor trace segment are symmetrically arranged with respect to an axis of symmetry extending along the second direction;

[0015] Preferably, the positive projection of the axis of symmetry on the substrate is located between the first scan trace and the second scan trace;

[0016] Preferably, the semiconductor trace segment corresponding to the driving transistor is asymmetrically arranged with respect to the axis of symmetry extending along the second direction.

[0017] In some possible implementations, the array substrate further includes a first initialization trace extending along the second direction; a positive projection of the first initialization trace on the substrate is located between positive projections of the first scanning trace and the second scanning trace on the substrate;

[0018] Preferably, the driving unit includes a driving transistor; the first driving unit and the second driving unit share the first initialization trace, and the first initialization trace is used to provide a first initialization voltage to a first electrode of the driving transistor of the first driving unit and the driving transistor of the second driving unit.

[0019] In some possible implementations, the first scanning trace and the second scanning trace synchronously transmit the same scanning signal; the first switching transistor and the second switching transistor are connected in series between the first electrode of the driving transistor and the first initialization trace, and the first switching transistor and the second switching transistor are used to perform voltage initialization control on the first electrode of the driving transistor.

[0020] In some possible implementations, the array substrate further includes a fifth conductive layer on a side of the first conductive layer away from the substrate; the first initialization trace is located in the fifth conductive layer;

[0021] Preferably, the material of the first conductive layer includes metal;

[0022] Preferably, the material of the fifth conductive layer includes metal.

[0023] In some possible implementations, the fourth conductive layer includes a first connection trace segment;

[0024] The driving transistor of the first driving unit is located on a side of the first scanning trace away from the second scanning trace, and the driving transistor of the second driving unit is located on a side of the second scanning trace away from the first scanning trace;

[0025] One end of the first semiconductor trace segment close to the first scanning trace is connected to the first electrode of the driving transistor of the first driving unit through the first connection trace segment, and one end of the first semiconductor trace segment close to the second scanning trace is connected to the first initialization trace through the first connection trace segment;

[0026] One end of the second semiconductor trace segment close to the second scanning trace is connected to the first electrode of the driving transistor of the second driving unit through the first connection trace segment, and one end of the second semiconductor trace segment close to the first scanning trace is connected to the first initialization trace through the first connection trace segment.

[0027] In some possible implementations, the array substrate further includes a second initialization trace extending in the second direction, and a positive projection of the second initialization trace on the substrate is located between positive projections of the first scan trace and the second scan trace on the substrate;

[0028] The driving unit further includes a pixel electrode connection point. The first driving unit and the second driving unit share the second initialization trace, and the second initialization trace is configured to provide a second initialization voltage for the pixel electrode connection points of the first driving unit and the second driving unit.

[0029] In some possible implementations, the array substrate further includes a third conductive layer and a fourth conductive layer on a side of the first conductive layer away from the substrate. The second initialization trace includes a first portion and a second portion. The first portion is located in the third conductive layer, and the second portion is located in the fourth conductive layer. The first portion and the second portion are alternately arranged in the second direction;

[0030] Preferably, the material of the third conductive layer includes metal, and / or the material of the fourth conductive layer includes metal.

[0031] In some possible implementations, the driving unit includes a third switching transistor. The third switching transistor is connected between the pixel electrode connection point and the second initialization trace, and the third switching transistor is configured to perform voltage initialization control on the pixel electrode connection point.

[0032] In some possible implementations, the array substrate includes a plurality of first driving unit groups, and each first driving unit group includes one first driving unit and the second driving unit; the first driving unit and the second driving unit in the same first driving unit group share the first scan trace and the second scan trace;

[0033] Preferably, the array substrate further includes a third initialization trace; in the first direction, a positive projection of the third initialization trace on the substrate is located between two adjacent first driving unit groups; in the first direction, the first driving unit and the second driving unit that are adjacent and belong to different first driving unit groups share the third initialization trace;

[0034] Preferably, the driving unit includes a driving transistor, and the third initialization trace is configured to provide a third initialization voltage for a gate of the driving transistor.

[0035] In some possible implementations, the array substrate further includes a fourth conductive layer and a fifth conductive layer on a side of the first conductive layer away from the substrate;

[0036] The third initialization routing packet includes a third part and a fourth part. The third part is located on the first conductive layer and / or the fourth conductive layer, and the fourth part is located on the fifth conductive layer. The third part and the fourth part are alternately arranged along the second direction; the fourth part includes a light-transmitting hollow area.

[0037] In some possible implementation manners, the driving unit includes a fourth switching transistor and a fifth switching transistor; the fourth switching transistor and the fifth switching transistor are connected between the gate of the driving transistor and the third initialization routing, and the fourth switching transistor and the fifth switching transistor are used to perform voltage initialization control on the gate of the driving transistor.

[0038] In some possible implementation manners, the array substrate further includes a plurality of fourth initialization routings extending along the second direction;

[0039] The array substrate includes a plurality of second driving unit groups, and each second driving unit group includes two adjacent driving units in the second direction;

[0040] Two driving units in the same second driving unit group are symmetrically arranged with respect to a fourth initialization routing;

[0041] In the second direction, there is a light leakage gap between the driving transistors of two adjacent driving units belonging to different second driving unit groups.

[0042] This application further provides a display panel, and the display panel includes the array substrate provided by this application.

[0043] This application further provides an electronic device, and the electronic device includes the display panel provided by this application.

[0044] Compared with the prior art, this application has the following beneficial effects:

[0045] This application provides an array substrate, a display panel and an electronic device. By setting two adjacent driving units in the first direction in the array substrate to share the first scanning routing and the second scanning routing, in this way, the semiconductor routing segments in these driving units can extend along a straight line and respectively overlap with the first scanning routing and the second scanning routing to form a first switching transistor and a second switching transistor, thereby reducing the space occupied by the semiconductor routing segments. Description of the Drawings

[0046] To more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and thus should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0047] Figure 1 Schematic diagram of the film layer structure of the array substrate provided in this embodiment;

[0048] Figure 2 One of the perspective views of the film layer of the array substrate provided in this embodiment;

[0049] Figure 3 Another perspective view of the film layer of the array substrate provided in this embodiment;

[0050] Figure 4 A third perspective view of the film layer of the array substrate provided in this embodiment;

[0051] Figure 5 A fourth perspective view of the film layer of the array substrate provided in this embodiment;

[0052] Figure 6 Schematic circuit diagram of the driving unit provided in this embodiment;

[0053] Figure 7 A fifth perspective view of the film layer of the array substrate provided in this embodiment;

[0054] Figure 8 A sixth perspective view of the film layer of the array substrate provided in this embodiment;

[0055] Figure 9 A seventh perspective view of the film layer of the array substrate provided in this embodiment;

[0056] Figure 10 An eighth perspective view of the film layer of the array substrate provided in this embodiment;

[0057] Figure 11 A ninth perspective view of the film layer of the array substrate provided in this embodiment;

[0058] Figure 12 A tenth perspective view of the film layer of the array substrate provided in this embodiment;

[0059] Figure 13 An eleventh perspective view of the film layer of the array substrate provided in this embodiment;

[0060] Figure 14 A twelfth perspective view of the film layer of the array substrate provided in this embodiment;

[0061] Figure 15 The thirteenth membrane layer perspective view of the array substrate provided for this embodiment;

[0062] Figure 16 The fourteenth membrane layer perspective view of the array substrate provided for this embodiment;

[0063] Figure 17 The fifteenth membrane layer perspective view of the array substrate provided for this embodiment;

[0064] Figure 18 The sixteenth membrane layer perspective view of the array substrate provided for this embodiment;

[0065] Figure 19 The seventeenth membrane layer perspective view of the array substrate provided for this embodiment;

[0066] Figure 20 The eighteenth membrane layer perspective view of the array substrate provided for this embodiment;

[0067] Figure 21 The nineteenth membrane layer perspective view of the array substrate provided for this embodiment;

[0068] Figure 22 The twentieth membrane layer perspective view of the array substrate provided for this embodiment.

[0069] Icons: 10 - First driving unit group; 11 - First driving unit; 12 - Second driving unit; 20 - Second driving unit group; 30 - Hollow area; 40 - Light leakage gap; 100 - Substrate; 101 - First insulating layer; 102 - Second insulating layer; 103 - Third insulating layer; 104 - Fourth insulating layer; 105 - Fifth insulating layer; 106 - Sixth insulating layer; 107 - Seventh insulating layer; 120 - Pixel electrode connection point; 200 - First semiconductor layer; 201 - First semiconductor trace segment; 202 - Second semiconductor trace segment; 203 - Third semiconductor trace segment; 204 - Fourth semiconductor trace segment; 300 - First conductive layer; 301 - First scanning trace; 302 - Second scanning trace; 303 - First extension; 304 - Fourth initialization trace; 305 - Fifth scanning trace; 306 - Light emission control trace; 400 - Second conductive layer; 500 - Second semiconductor layer; 501 - Fifth semiconductor trace segment; 502 - Sixth semiconductor trace segment; 600 - Third conductive layer; 601 - First part; 603 - Third scanning trace; 604 - Fourth scanning trace; 700 - Fourth conductive layer; 701 - First connection trace segment; 702 - Second connection trace segment; 703 - Third connection trace segment; 704 - Second part; 705 - Second extension; 800 - Fifth conductive layer; 801 - First initialization trace; 802 - Fourth part; 901 - Second initialization trace; 902 - Third initialization trace; D1 - First direction; D2 - Second direction; T1 - Driving transistor; T2 - Eighth switching transistor; T3 - Fourth switching transistor; T4 - Fifth switching transistor; T5 - Sixth switching transistor; T6 - Seventh switching transistor; T7 - Third switching transistor; T8-1 - First switching transistor; T8-2 - Second switching transistor. Detailed implementation manners

[0070] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are some, but not all, of the embodiments of the present application. The components of the embodiments of the present application usually described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.

[0071] Therefore, the detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed present application, but merely represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0072] It should be noted that similar reference numerals and letters indicate similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0073] In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the inventive product is habitually placed during use. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application. In addition, the terms "first", "second", "third", etc. are only used for distinguishing descriptions and cannot be understood as indicating or implying relative importance.

[0074] It should be noted that, without conflict, different features in the embodiments of the present application can be combined with each other.

[0075] Please refer to Figure 1 , Figure 1 , which is a schematic cross-sectional view of an array substrate provided in this embodiment. The array substrate may include a substrate 100, a first semiconductor layer 200 on one side of the substrate 100, and a first conductive layer 300 on the side of the first semiconductor layer 200 away from the substrate 100.

[0076] In this embodiment, a first insulating layer 101 may also be provided between the first semiconductor layer 200 and the first conductive layer 300.

[0077] Please refer to Figure 2 , the first semiconductor layer 200 may include multiple semiconductor trace segments. Among them, the multiple semiconductor trace segments may include a first semiconductor trace segment 201 and a second semiconductor trace segment 202, and the first semiconductor trace segment 201 and the second semiconductor trace segment 202 extend in parallel along a first direction D1.

[0078] Please refer to Figure 3 , the first conductive layer 300 may include multiple traces. For example, it may include a first scan trace 301 and a second scan trace 302. The first scan trace 301 and the second scan trace 302 extend in parallel along a second direction D2 and synchronously transmit the same scan signal. The first direction D1 intersects the second direction D2. For example, the first direction D1 is perpendicular to the second direction D2.

[0079] Optionally, in one example, the material of the first conductive layer 300 may include a metal, and the first scan trace 301 and the second scan trace 302 may be metal traces.

[0080] In another example, the material of the first conductive layer 300 may also include non-metallic materials, such as metal oxides (such as indium tin oxide), graphene, conductive semiconductor materials, etc.

[0081] In this embodiment, multiple film layers of the array substrate cooperate with each other to form multiple thin film transistors (TFTs) at different positions. The multiple thin film transistors cooperate with each other to form multiple driving units, and the driving units are used to drive the pixels to emit light. Among them, one driving unit may include multiple different transistors.

[0082] Please refer to Figure 4 , as Figure 4 shown by the rectangular dashed box in, multiple driving units of the array substrate may include a first driving unit 11 and a second driving unit 12 adjacent to each other in the first direction D1.

[0083] In the first direction D1, the first driving unit 11 is located on the side of the first scanning trace 301 away from the second scanning trace 302, and the second driving unit 12 is located on the side of the second scanning trace 302 away from the first scanning trace 301.

[0084] For example, regarding the first scanning trace 301 and the second scanning trace 302 as a whole, the first driving unit 11 and the second driving unit 12 are located on both sides of the first scanning trace 301 and the second scanning trace 302 in the first direction D1.

[0085] Please refer to Figure 5 , the positive projections of the first semiconductor trace segment 201 on the substrate 100 coincide at least partially with the positive projections of the first scanning trace 301 and the second scanning trace 302 on the substrate 100. The first switching transistor T8-1 and the second switching transistor T8-2 of the first driving unit 11 are located at the positions where the first semiconductor trace segment 201 coincides with the positive projections of the first scanning trace 301 and the second scanning trace 302.

[0086] The positive projections of the second semiconductor trace segment 202 on the substrate 100 coincide at least partially with the positive projections of the second scanning trace 302 and the first scanning trace 301 on the substrate 100. The first switching transistor T8-1 and the second switching transistor T8-2 of the second driving unit 12 are located at the positions where the second semiconductor trace segment 202 coincides with the positive projections of the first scanning trace 301 and the second scanning trace 302.

[0087] For example, the first semiconductor trace 201 belongs to the first driving unit 11. The first semiconductor trace 201 extending along the first direction D1 overlaps with the first scanning trace 301 and the second scanning trace 302 extending along the second direction D2. At the overlapping positions, the first switching transistor T8-1 and the second switching transistor T8-2 of the first driving unit 11 are respectively corresponding.

[0088] The second semiconductor trace 202 belongs to the second driving unit 12. The second semiconductor trace 202 extending along the first direction D1 overlaps with the first scanning trace 301 and the second scanning trace 302 extending along the second direction D2. At the overlapping positions, the first switching transistor T8-1 and the second switching transistor T8-2 of the first driving unit 11 are respectively corresponding.

[0089] Based on the above design, in the array substrate provided in this embodiment, two scanning traces (i.e., the first scanning trace 301 and the second scanning trace 302) for transmitting the same signal are provided between the first driving unit 11 and the second driving unit 12 adjacent in the first direction D1, and the first driving unit 11 and the second driving unit 12 share the first scanning trace 301 and the second scanning trace 302. Thus, for the first switching transistor T8-1 and the second switching transistor T8-2 that need to be serially arranged and require the same gate control signal, semiconductor traces extending in a straight line can be respectively overlapped with the first scanning trace 301 and the second scanning trace 302 to form transistors. Compared with the prior art solution in which the semiconductor trace is set as a U shape and overlaps with the same scanning trace twice, the solution provided in this embodiment can save more wiring space, which is more conducive to improving the light transmittance or pixel density of the array substrate.

[0090] Optionally, please refer to again Figure 1 , in some possible implementation manners, the array substrate may further include a second conductive layer 400, a second semiconductor layer 500, a third conductive layer 600, a fourth conductive layer 700, and a fifth conductive layer 800 located on a side of the first conductive layer 300 away from the substrate 100.

[0091] Optionally, the array substrate may further include an insulating layer located between adjacent film layers. For example, a first insulating layer 101 (such as a first gate insulating layer) is located between the first semiconductor layer 200 and the first conductive layer 300, a second insulating layer 102 (such as a capacitive dielectric layer) is located between the first conductive layer 300 and the second conductive layer 400, a third insulating layer 103 (such as a buffer layer) is located between the second conductive layer 400 and the second semiconductor layer 500, a fourth insulating layer 104 (such as a second gate insulating layer) is located between the second semiconductor layer 500 and the third conductive layer 600, a fifth insulating layer 105 (such as an interlayer insulating layer) is located between the third conductive layer 600 and the fourth conductive layer 700, and a sixth insulating layer 106 (such as a first planarization layer) is located between the fourth conductive layer 700 and the fifth conductive layer 800.

[0092] Optionally, in one example, the material of the second conductive layer 400 may include a metal, and / or the material of the third conductive layer 600 may include a metal, and / or the material of the fourth conductive layer 700 may include a metal, and / or the material of the fifth conductive layer 800 may include a metal.

[0093] In another example, the material of the second conductive layer 400 may also include a non-metal conductive material, and / or the material of the third conductive layer 600 may include a non-metal conductive material, and / or the material of the fourth conductive layer 700 may include a non-metal conductive material, and / or the material of the fifth conductive layer 800 may include a non-metal conductive material. For example, the non-metal conductive material may include: metal oxides (such as indium tin oxide), graphene, conductive semiconductor materials, etc.

[0094] Optionally, the array substrate may further include a sixth conductive layer on the side of the fifth conductive layer 800 away from the array substrate, and a seventh insulating layer 107 (such as a second planarization layer) located between the fifth conductive layer 800 and the sixth conductive layer.

[0095] In some possible implementation manners, please refer to Figure 2 or Figure 4 ..., the first semiconductor layer 200 further includes a third semiconductor trace segment 203A corresponding to other transistors in the first driving unit 11 except the first switching transistor T8-1 and the second switching transistor T8-2 of the first driving unit 11, and a fourth semiconductor trace segment 204A corresponding to other transistors in the second driving unit 12 except the first switching transistor T8-1 and the second switching transistor T8-2 of the second driving unit 12.

[0096] The third semiconductor trace segment 203A and the fourth semiconductor trace segment 204A are symmetrically arranged with respect to the axis of symmetry extending along the second direction D2, and the orthogonal projection of the axis of symmetry on the substrate 100 is located between the first scanning trace 301 and the second scanning trace 302.

[0097] For example, in this embodiment, except for the first switching transistor T8-1 and the second switching transistor T8-2, the other transistors in the first driving unit 11 and the other transistors in the second driving unit 12 can be symmetrically distributed in the first direction D1. In this way, the first driving unit 11 and the second driving unit 12 can also share other traces extending in the second direction D2, thereby saving more routing space and ensuring the layout consistency of the switching transistors, thus reducing the risk of display unevenness.

[0098] In some possible implementation manners, the driving unit includes a driving transistor T1. Please refer to Figure 7 or Figure 8 , the first semiconductor layer 200 further includes a third semiconductor trace segment 203B corresponding to the other transistors in the first driving unit 11 except the first switching transistor T8-1, the second switching transistor T8-2, and the driving transistor T1 of the first driving unit 11, and a fourth semiconductor trace segment 204B corresponding to the other transistors in the second driving unit 12 except the first switching transistor T8-1, the second switching transistor T8-2, and the driving transistor T1 of the second driving unit 12.

[0099] The third semiconductor trace segment 203B and the fourth semiconductor trace segment 204B are symmetrically arranged with respect to the symmetry axis extending in the second direction D2, and the orthogonal projection of the symmetry axis on the substrate 100 is located between the first scanning trace 301 and the second scanning trace 302.

[0100] For example, in this embodiment, except for the first switching transistor T8-1, the second switching transistor T8-2, and the driving transistor T1, the other transistors in the first driving unit 11 and the other transistors in the second driving unit 12 can be symmetrically distributed in the first direction D1.

[0101] The semiconductor trace segment corresponding to the driving transistor T1 is asymmetrically arranged with respect to the symmetry axis extending in the second direction D2. That is, the driving transistor T1 is asymmetrically distributed in the first direction D1.

[0102] In this way, the first driving unit 11 and the second driving unit 12 can also share other traces extending in the second direction D2, thereby saving more routing space and ensuring the layout consistency of the switching transistors, thus reducing the risk of display unevenness.

[0103] In some possible implementation manners, referring to Figure 9 and Figure 10 as shown, the array substrate further includes a first initialization trace 801 extending in the second direction D2. The orthogonal projection of the first initialization trace 801 on the substrate 100 is located between the orthogonal projections of the first scanning trace 301 and the second scanning trace 302 on the substrate 100.

[0104] The driving unit includes a driving transistor T1, and the driving transistor T1 includes a first electrode, a second electrode, and a gate. The first driving unit 11 and the second driving unit 12 share a first initialization trace 801, and the first initialization trace 801 is used to provide a first initialization voltage for the first electrodes of the driving transistors T1 of the first driving unit 11 and the second driving unit 12. The first electrode and the second electrode can be respectively one of the source and the drain of the driving transistor T1.

[0105] For example, please refer to Figure 6 and Figure 9 , the driving unit provided in this embodiment can adopt an 8T1C driving circuit. Among them, the core component of the driving unit can include a driving transistor T1. The driving transistor T1 of the first driving unit 11 is located on the side of the first scanning trace 301 away from the second scanning trace 302, and the driving transistor T1 of the second driving unit 12 is located on the side of the second scanning trace 302 away from the first scanning trace 301.

[0106] During the display process, in order to improve the display effect, it is necessary to initialize the voltage of the first electrode of the driving transistor T1 at a specific time point. Therefore, it is necessary to set a trace (i.e., the first initialization trace 801) for transmitting the first initialization voltage Vref3 in the array substrate.

[0107] In this case, please refer to Figure 9 , for the first driving unit 11 and the second driving unit 12 provided in this embodiment, except for the first switching transistor T8-1 and the second switching transistor T8-2, other transistors are generally symmetrically arranged in the first direction D1. Therefore, the first initialization trace 801 can be set so that its orthographic projection on the substrate 100 is located between the orthographic projections of the first scanning trace 301 and the second scanning trace 302 on the substrate 100. In this way, the first driving unit 11 and the second driving unit 12 can share the first initialization trace 801, thereby reducing the number of traces and saving trace space.

[0108] In some possible implementation manners, please refer to Figure 6 and Figure 9 again. The first switching transistor T8-1 and the second switching transistor T8-2 are connected in series between the first electrode of the driving transistor T1 and the first initialization trace 801, and the first switching transistor T8-1 and the second switching transistor T8-2 are used to perform voltage initialization control on the first electrode of the driving transistor T1.

[0109] That is, the gates of the first switching transistor T8-1 and the second switching transistor T8-2 are respectively formed by the first scanning trace 301 and the second scanning trace 302. When the first scanning signal ScanP2 synchronously transmitted by the first scanning trace 301 and the second scanning trace 302 is received, the electrical connection between the first electrode of the driving transistor T1 and the first initialization trace 801 can be simultaneously controlled to be turned on or off for both the first switching transistor T8-1 and the second switching transistor T8-2, thereby realizing the voltage initialization control of the first electrode of the driving transistor T1.

[0110] Specifically, the first initialization trace 801 may be located in the fifth conductive layer 800.

[0111] Further, please refer to Figure 1 and Figure 10 , the driving transistor T1 of the first driving unit 11 is located on the side of the first scanning trace 301 away from the second scanning trace 302, and the driving transistor T1 of the second driving unit 12 is located on the side of the second scanning trace 302 away from the first scanning trace 301.

[0112] The fourth conductive layer 700 includes a first connection segment 701, a second connection segment 702, and a third connection segment 703. One end of the first semiconductor segment 201 close to the first scanning trace 301 is connected to the first electrode of the driving transistor T1 of the first driving unit 11 through the first connection segment 701, and one end of the first semiconductor segment 201 close to the second scanning trace 302 is connected to the first initialization trace 801 through the second connection segment 702.

[0113] One end of the second semiconductor segment 202 close to the second scanning trace 302 is connected to the first electrode of the driving transistor T1 of the second driving unit 12 through the third connection segment 703, and one end of the second semiconductor segment 202 close to the first scanning trace 301 is connected to the first initialization trace 801 through the second connection segment 702.

[0114] In some possible implementation manners, the array substrate further includes a second initialization trace 901 extending along the second direction D2. Please refer to Figure 11 , the orthographic projection of the second initialization trace 901 on the substrate 100 is located between the orthographic projections of the first scanning trace 301 and the second scanning trace 302 on the substrate 100. For example, the second initialization trace 901 and the first initialization trace 801 may be located in different film layers, and the orthographic projection of the second initialization trace 901 on the substrate 100 and the orthographic projection of the first initialization trace 801 on the substrate 100 may at least partially overlap.

[0115] Please refer to again Figure 1, the driving unit includes a pixel electrode connection point 120, and the pixel electrode connection point 120 is used for electrically connecting to the anode of the light-emitting sub-pixel to transmit a driving signal to the anode. The first driving unit 11 and the second driving unit 12 share a second initialization trace 901, and the second initialization trace 901 is used to provide a second initialization voltage Vref2 as shown in Figure 6 to the pixel electrode connection points 120 of the first driving unit 11 and the second driving unit 12, that is, the second initialization trace 901 is used to provide the second initialization voltage Vref2 to the anode.

[0116] The first driving unit 11 and the second driving unit 12 provided in this embodiment are generally symmetrically arranged in the first direction D1. Therefore, the second initialization trace 901 can be set such that its orthographic projection on the substrate 100 is located between the orthographic projections of the first scanning trace 301 and the second scanning trace 302 on the substrate 100. In this way, the first driving unit 11 and the second driving unit 12 can share the second initialization trace 901, thereby reducing the number of traces and saving trace space.

[0117] Furthermore, in some possible implementation manners, please refer to Figure 11 again. The second initialization trace 901 includes a first part 601 and a second part 704. The first part 601 is located in the third conductive layer 600, and the second part 704 is located in the fourth conductive layer 700. The first part 601 and the second part 704 are alternately arranged along the second direction D2 to avoid other traces extending along the first direction D1 arranged in the same layer. The first part 601 and the second part 704 can be electrically connected to each other through a through hole penetrating through a partial insulating layer of the array substrate.

[0118] In some possible implementation manners, the driving unit includes a third switching transistor T7. Please refer to Figure 6 again. The third switching transistor T7 is connected between the pixel electrode connection point 120 and the second initialization trace 901, and the third switching transistor T7 is used to perform voltage initialization control on the pixel electrode connection point 120.

[0119] Specifically, the third switching transistor T7 of the first driving unit 11 can be formed by overlapping a third semiconductor trace segment 203 in the first driving unit 11 with the first scanning trace 301, and the third switching transistor T7 of the second driving unit 12 can be formed by overlapping a fourth semiconductor trace segment 204 in the second driving unit 12 with the second scanning trace 302. The signal transmitted by the first scanning trace 301 or the second scanning trace 302 can control the third switching transistor T7 to connect or disconnect the electrical connection between the pixel electrode connection point 120 and the second initialization trace 901, thereby realizing voltage initialization control of the pixel electrode connection point 120.

[0120] In some possible implementation manners, please refer to Figure 12 or Figure 13 , the array substrate includes a plurality of first driving unit groups 10, each first driving unit group 10 includes a first driving unit 11 and a second driving unit 12, and the first driving unit 11 and the second driving unit 12 in the same first driving unit group 10 share a first scanning trace 301 and a second scanning trace 302.

[0121] The array substrate further includes a third initialization trace 902. In the first direction D1, the orthographic projection of the third initialization trace 902 on the substrate 100 is located between two adjacent first driving unit groups 10. The first driving unit 11 and the second driving unit 12 that are adjacent in the first direction D1 and belong to different first driving unit groups 10 share the third initialization trace 902. In this way, the number of traces can be reduced and the trace space can be saved. The third initialization trace 902 is used to provide the third initialization voltage Vref1 as shown in Figure 6 .

[0122] In some possible implementation manners, please refer to Figure 12 or Figure 13 , the third initialization trace 902 includes a third part and a fourth part 802. The third part is located in the first conductive layer 300 and / or the fourth conductive layer 700, and the fourth part 802 is located in the fifth conductive layer 800. The third part and the fourth part 802 are alternately arranged along the second direction D2. The fourth part 802 includes a light-transmitting hollow area 30.

[0123] For example, the third part includes a first extension 303 located in the first conductive layer 300 or includes a second extension 705 located in the fourth conductive layer 700.

[0124] Alternatively, the third part may include both the first extension 303 and the second extension 705, and the orthographic projections of the first extension 303 and the second extension 705 on the substrate 100 at least partially overlap. In this way, the resistance of the third part can be reduced, and further the overall resistance of the third initialization trace 902 can be reduced.

[0125] Both the third part and the fourth part 802 extend along the second direction D2 and are alternately arranged to together form the third initialization trace 902. The third part and the fourth part 802 are electrically connected through a through hole in the insulating layer between at least some metal layers.

[0126] Wherein, the fourth part 802 extending in the fifth conductive layer 800 may have a hollow area 30, and the orthographic projection of the hollow area 30 on the substrate 100 at least partially does not overlap with the orthographic projections of the traces in other film layers on the substrate 100. In this way, the hollow area 30 can form a light-transmitting area to improve the light transmittance of the array substrate.

[0127] In some possible implementations, please refer to Figure 6 , the driving unit includes a fourth switching transistor T3 and a fifth switching transistor T4. The fourth switching transistor T3 and the fifth switching transistor T4 are connected between the gate of the driving transistor T1 and the third initialization trace 902, and the fourth switching transistor T3 and the fifth switching transistor T4 are used to perform voltage initialization control on the gate of the driving transistor T1.

[0128] For example, please refer to Figure 14 , the fourth switching transistor T3 can be formed by the cooperation of the third scanning trace 603 in the third conductive layer 600 and the fifth semiconductor trace segment 501 in the second semiconductor layer 500, and the fifth switching transistor T4 can be formed by the cooperation of the fourth scanning trace 604 in the third conductive layer 600 and the sixth semiconductor trace segment 502 in the second semiconductor layer 500.

[0129] The second scanning signal ScanN2 transmitted by the third scanning trace 603 and the third scanning signal ScanN1 transmitted by the fourth scanning trace 604 can control the fourth switching transistor T3 and the fifth switching transistor T4 to connect or disconnect the electrical connection between the gate of the driving transistor T1 and the third initialization trace 902, so as to realize the voltage initialization control of the gate of the pixel electrode connection point 120.

[0130] In some possible implementations, please refer to Figure 6 and Figure 15 , the array substrate may include a first scanning trace 301 for transmitting the first scanning signal ScanP2, a second scanning trace 302 for transmitting the first scanning signal ScanP2, a third scanning trace 603 for transmitting the second scanning signal ScanN2, a fourth scanning trace 604 for transmitting the third scanning signal ScanN1, a fifth scanning trace 305 for transmitting the fourth scanning signal ScanP1, and a light emission control trace 306 for transmitting the light emission control signal EM. Among them, the first scanning trace 301, the second scanning trace 302, the fifth scanning trace 305, and the light emission control trace 306 are located in the first conductive layer 300, and the third scanning trace 603 and the fourth scanning trace 604 are located in the third conductive layer 600.

[0131] The driving unit may include a driving transistor T1, an eighth switching transistor T2, a fourth switching transistor T3, a fifth switching transistor T4, a sixth switching transistor T5, a seventh switching transistor T6, a third switching transistor T7, a first switching transistor T8-1, and a second switching transistor T8-2.

[0132] Among them, the driving transistor T1 is formed by the cooperation of the semiconductor trace segment of the first semiconductor layer 200 and the gate electrode of the first conductive layer 300.

[0133] The eighth switching transistor T2 is formed by the cooperation of the fifth scanning trace 305 and the semiconductor trace segment of the first semiconductor layer 200. The eighth switching transistor T2 is used to perform data writing control on the capacitor Cst in the driving unit according to the fourth scanning signal ScanP1 transmitted by the fifth scanning trace 305.

[0134] The fourth switching transistor T3 is formed by the cooperation of the third scanning trace 603 of the third conductive layer 600 and the semiconductor trace segment of the second semiconductor layer 500. The fourth switching transistor T3 is used to perform voltage compensation control on the driving transistor T1 according to the second scanning signal ScanN2 transmitted by the third scanning trace 603.

[0135] The fifth switching transistor T4 is formed by the cooperation of the fourth scanning trace 604 of the third conductive layer 600 and the semiconductor trace segment of the second semiconductor layer 500. The fourth switching transistor T3 and the fifth switching transistor T4 are used to perform voltage initialization control on the gate of the driving transistor T1 according to the second scanning signal ScanN2 transmitted by the third scanning trace 603 and the third scanning signal ScanN1 transmitted by the fourth scanning trace 604, respectively.

[0136] The sixth switching transistor T5 and the seventh switching transistor T6 are formed by the cooperation of the light emission control trace 306 of the first conductive layer 300 and the semiconductor trace segment of the first semiconductor layer 200. The sixth switching transistor T5 and the seventh switching transistor T6 are used to perform light emission enabling control on the driving unit according to the transmitted light emission control signal EM transmitted by the light emission control trace 306.

[0137] The third switching transistor T7 is formed by the cooperation of one of the first scanning trace 301 and the second scanning trace 302 and the semiconductor trace segment of the first semiconductor layer 200. The third switching transistor T7 is used to perform voltage initialization control on the pixel electrode access point of the driving unit according to the first scanning signal ScanP2 transmitted by the first scanning trace 301 or the second scanning trace 302.

[0138] The first switching transistor T8-1 and the second switching transistor T8-2 are formed by the cooperation of the first scanning trace 301 and the second scanning trace 302 with the semiconductor trace segments of the first semiconductor layer 200, respectively. The first switching transistor T8-1 and the second switching transistor T8-2 are used to perform voltage initialization control on the first electrode of the driving transistor T1 according to the first scanning signal ScanP2 transmitted by the first scanning trace 301 and the second scanning trace 302.

[0139] In some possible implementation manners, please refer to Figure 16, the array substrate further includes a plurality of fourth initialization traces 304 extending along the second direction D2. Optionally, the fourth initialization traces 304 may be located in the fourth conductive layer 700. The fourth initialization traces 304 and the second initialization traces 901 may be electrically connected through vias penetrating at least one insulating layer, and the fourth initialization traces 304 and the second initialization traces 901 may be intertwined to form a mesh structure.

[0140] The array substrate includes a plurality of second driving unit groups 20, and each second driving unit group 20 includes two driving units adjacent in the second direction D2. The two driving units in the same second driving unit group 20 are symmetrically arranged with respect to a fourth initialization trace 304.

[0141] It should be noted that, please refer to Figures 18 to 22 , in addition to the traces mentioned above, each film layer of the array substrate provided in this embodiment may further have other more traces or trace segments. Among them, since the adjacent first driving unit 11 and second driving unit 12 in the first direction D1 of the array substrate provided in this embodiment are arranged symmetrically in the first direction D1, the first driving unit 11 and the second driving unit 12 can share at least part of the signal traces or power supply traces extending along the second direction D2, saving the wiring space of the array substrate.

[0142] Therefore, in some possible implementation manners, the array substrate provided in this embodiment may have a certain light leakage gap 40. For example, please refer to Figure 17 , in the second direction D2, there is a light leakage gap 40 between the driving transistors T1 (such as, Figure 14 shown by the dotted box in the trusteeship) of two driving units that are adjacent and belong to different second driving unit groups 20. That is, the positive projection of the light leakage gap 40 on the substrate 100 does not coincide with the positive projection of the traces in any film layer on the substrate 100. Therefore, the traces in each film layer will not block the light transmission at the light leakage gap 40. In this way, the overall light transmittance of the array substrate can be improved, and the acquisition effect of the under-screen optical acquisition device disposed under the display panel can be improved.

[0143] This application also provides a display panel, and the display panel includes the array substrate provided in this application.

[0144] In some possible implementation manners, the display panel further includes a light-emitting layer located on one side of the array substrate. The light-emitting layer may include a plurality of film layer structures such as a pixel definition layer, a light-emitting material layer, a cathode layer, and a packaging layer, which will not be elaborated here one by one.

[0145] In another possible implementation, the display panel further includes a light-emitting layer located on one side of the array substrate. The light-emitting layer may include multiple film layer structures such as a pixel definition layer, an isolation structure, a light-emitting material layer, a cathode layer, and a packaging layer. Among them, the related technical solutions of the isolation structure are described in Patent PCT / CN2023 / 134518, Patent 202310759370.2, Patent 202310740412.8, Patent 202310707209.0, and Patent 202311346196.5. The content thereof is incorporated into this application by reference for reference and will not be elaborated in this embodiment.

[0146] This application also provides an electronic device. The electronic device includes the display panel provided by this application. The electronic device may include devices with a display function such as mobile phones, tablet computers, smart wearable devices, televisions, laptop computers, and monitors.

[0147] In summary, this application provides an array substrate, a display panel, and an electronic device. By setting two adjacent driving units in the first direction in the array substrate to share the first scanning trace and the second scanning trace, in this way, the semiconductor trace segments in these driving units can extend linearly and overlap with the first scanning trace and the second scanning trace respectively to form a first switching transistor and a second switching transistor, thereby reducing the space occupied by the semiconductor trace segments.

[0148] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0149] The above embodiments only represent several implementation manners of the present invention. The description is relatively specific and detailed, but it cannot be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several deformations and improvements can be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the invention patent shall be subject to the appended claims.

Claims

1. An array substrate, characterized in that, The array substrate includes: A substrate; A first semiconductor layer on one side of the substrate, the first semiconductor layer including a first semiconductor trace segment and a second semiconductor trace segment; the first semiconductor trace segment and the second semiconductor trace segment extend side by side in a first direction; A first conductive layer on the side of the first semiconductor layer away from the substrate, the first conductive layer including a first scan trace and a second scan trace, the first scan trace and the second scan trace extend side by side in a second direction; the first direction intersects the second direction; The array substrate includes a plurality of driving units, the driving units including a first driving unit and a second driving unit adjacent to each other in the first direction; In the first direction, the first driving unit is located on a side of the first scan trace away from the second scan trace, and the second driving unit is located on a side of the second scan trace away from the first scan trace; The positive projections of the first semiconductor trace segment on the substrate respectively at least partially coincide with the positive projections of the first scan trace and the second scan trace on the substrate, and the first switching transistor and the second switching transistor of the first driving unit are located at positions where the first semiconductor trace segment coincides with the positive projections of the first scan trace and the second scan trace; The positive projections of the second semiconductor trace segment on the substrate respectively at least partially coincide with the positive projections of the first scan trace and the second scan trace on the substrate, and the first switching transistor and the second switching transistor of the second driving unit are located at positions where the second semiconductor trace segment coincides with the positive projections of the first scan trace and the second scan trace.

2. The array substrate according to claim 1, wherein The first semiconductor layer further includes a third semiconductor trace segment corresponding to other transistors in the first driving unit except for the first switching transistor and the second switching transistor of the first driving unit, and a fourth semiconductor trace segment corresponding to other transistors in the second driving unit except for the first switching transistor and the second switching transistor of the second driving unit; the third semiconductor trace segment and the fourth semiconductor trace segment are symmetrically arranged with respect to an axis of symmetry extending in the second direction; Preferably, the positive projection of the axis of symmetry on the substrate is located between the first scan trace and the second scan trace.

3. The array substrate according to claim 1, wherein The driving unit includes a driving transistor; the first semiconductor layer further includes a third semiconductor trace segment corresponding to other transistors in the first driving unit except for the first switching transistor, the second switching transistor and the driving transistor of the first driving unit, and a fourth semiconductor trace segment corresponding to other transistors in the second driving unit except for the first switching transistor, the second switching transistor and the driving transistor of the second driving unit; the third semiconductor trace segment and the fourth semiconductor trace segment are symmetrically arranged with respect to an axis of symmetry extending in the second direction; Preferably, the positive projection of the axis of symmetry on the substrate is located between the first scan trace and the second scan trace; Preferably, the symmetry axis of the semiconductor trace corresponding to the driving transistor extends asymmetrically along the second direction.

4. The array substrate according to claim 1, wherein The array substrate further includes a first initialization trace extending along the second direction; the orthographic projection of the first initialization trace on the substrate is located between the orthographic projections of the first scanning trace and the second scanning trace on the substrate; Preferably, the driving unit includes a driving transistor; the first driving unit and the second driving unit share the first initialization trace, and the first initialization trace is used to provide a first initialization voltage to the first electrodes of the driving transistors of the first driving unit and the second driving unit.

5. The array substrate according to claim 4, wherein The first scanning trace and the second scanning trace synchronously transmit the same scanning signal; the first switching transistor and the second switching transistor are connected in series between the first electrode of the driving transistor and the first initialization trace, and the first switching transistor and the second switching transistor are used to perform voltage initialization control on the first electrode of the driving transistor.

6. The array substrate according to claim 4, wherein The array substrate further includes a fifth conductive layer on a side of the first conductive layer away from the substrate; the first initialization trace is located on the fifth conductive layer; Preferably, the material of the first conductive layer includes metal; Preferably, the material of the fifth conductive layer includes metal; Preferably, the fourth conductive layer includes a first connection trace segment; The driving transistor of the first driving unit is located on a side of the first scanning trace away from the second scanning trace, and the driving transistor of the second driving unit is located on a side of the second scanning trace away from the first scanning trace; One end of the first semiconductor trace segment close to the first scanning trace is connected to the first electrode of the driving transistor of the first driving unit through the first connection trace segment, and one end of the first semiconductor trace segment close to the second scanning trace is connected to the first initialization trace through the first connection trace segment; One end of the second semiconductor trace segment close to the second scanning trace is connected to the first electrode of the driving transistor of the second driving unit through the first connection trace segment, and one end of the second semiconductor trace segment close to the first scanning trace is connected to the first initialization trace through the first connection trace segment.

7. The array substrate according to claim 1, wherein The array substrate further includes a second initialization trace extending along the second direction, and the orthographic projection of the second initialization trace on the substrate is located between the orthographic projections of the first scanning trace and the second scanning trace on the substrate; The driving unit further includes a pixel electrode connection point, and the first driving unit and the second driving unit share the second initialization trace, and the second initialization trace is used to provide a second initialization voltage to the pixel electrode connection points of the first driving unit and the second driving unit.

8. The array substrate according to claim 7, wherein, The array substrate further includes a third conductive layer and a fourth conductive layer on a side of the first conductive layer away from the substrate. The second initialization trace includes a first portion and a second portion. The first portion is located in the third conductive layer, and the second portion is located in the fourth conductive layer. The first portion and the second portion are alternately arranged along the second direction. Preferably, the material of the third conductive layer includes metal, and / or the material of the fourth conductive layer includes metal.

9. The array substrate according to claim 7, wherein The driving unit includes a third switching transistor. The third switching transistor is connected between the pixel electrode connection point and the second initialization trace, and the third switching transistor is configured to perform voltage initialization control on the pixel electrode connection point.

10. The array substrate according to claim 1, wherein The array substrate includes a plurality of first driving unit groups. Each first driving unit group includes one of the first driving units and the second driving unit. The first driving unit and the second driving unit in the same first driving unit group share the first scanning trace and the second scanning trace. Preferably, the array substrate further includes a third initialization trace. In the first direction, a positive projection of the third initialization trace on the substrate is located between two adjacent first driving unit groups. The first driving unit and the second driving unit that are adjacent in the first direction and belong to different first driving unit groups share the third initialization trace. Preferably, the driving unit includes a driving transistor, and the third initialization trace is configured to provide a third initialization voltage to a gate of the driving transistor.

11. The array substrate according to claim 10, wherein The array substrate further includes a fourth conductive layer and a fifth conductive layer on a side of the first conductive layer away from the substrate. The third initialization trace includes a third portion and a fourth portion. The third portion is located in the first conductive layer and / or the fourth conductive layer, and the fourth portion is located in the fifth conductive layer. The third portion and the fourth portion are alternately arranged along the second direction. The fourth portion includes a light-transmitting hollow area.

12. The array substrate according to claim 10, wherein The driving unit includes a fourth switching transistor and a fifth switching transistor. The fourth switching transistor and the fifth switching transistor are connected between the gate of the driving transistor and the third initialization trace, and the fourth switching transistor and the fifth switching transistor are configured to perform voltage initialization control on the gate of the driving transistor.

13. The array substrate according to claim 1, wherein The array substrate further includes a plurality of fourth initialization traces extending along the second direction. The array substrate includes a plurality of second driving unit groups. Each second driving unit group includes two of the driving units adjacent in the second direction. Two of the driving units in the same second driving unit group are symmetrically arranged with respect to one of the fourth initialization traces. In the second direction, there is a light leakage gap between driving transistors of two driving units that are adjacent and belong to different second driving unit groups.

14. A display panel, characterized in that, The display panel includes the array substrate according to any one of claims 1-13.

15. An electronic device, characterized in that, The electronic device includes the display panel according to claim 14.

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