Photoelectric chip manufacturing method

Abstract

The invention provides a photoelectric chip manufacturing method comprising the steps that a photoelectric chip is provided, the photoelectric chip comprises an external connection area and an optical port pre-buried area, an optical port is arranged in the optical port pre-buried area, and a passivation layer is arranged above the optical port to cover the optical port; forming a conductive connection part above the external connection area, wherein the conductive connection part is electrically connected with the photoelectric chip; and forming a passivation layer opening in the passivation layer, wherein the passivation layer opening exposes the light port. According to the photoelectric chip manufacturing method, the optical port is covered by the passivation layer before the conductive connecting part is formed, and the passivation layer is opened to expose the optical port after the conductive connecting part is formed, so that the optical port can be prevented from being polluted in the process of forming the conductive connecting part, the production yield is improved, and the cost is reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors and relates to a method for manufacturing a photoelectric chip. Background Art

[0002] An optoelectronic chip is a microchip that integrates electronic devices and optical devices. It uses its photoelectric conversion function to achieve the conversion and processing between optical signals and electrical signals. The optical port is a very important part of the optoelectronic chip and is used to receive or output optical signals.

[0003] At present, in the production of optoelectronic chips, the wet patterning process will contaminate the light port. Usually, a photosensitive polyimide dry film or a photoresist dry film is laminated on the optoelectronic chip to avoid light port contamination, and then a patterning process is used to prepare conductive pads for connecting external devices. However, in the actual operation process, the wet process still exists, and there is a risk of light port contamination, which reduces the production yield and increases the cost.

[0004] Therefore, how to provide a method for manufacturing an optoelectronic chip to ensure that the optical port will not be contaminated during the manufacturing process, improve the production yield, and reduce costs has become a technical problem that needs to be urgently solved by those skilled in the art. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for manufacturing an optoelectronic chip, which is used to solve the problem in the prior art that the optical port is contaminated, resulting in reduced production yield and increased cost.

[0006] To achieve the above-mentioned object and other related objects, the present invention provides a method for manufacturing an optoelectronic chip, comprising the following steps:

[0007] Providing an optoelectronic chip, the optoelectronic chip comprising an external connection area and an optical port pre-buried area, wherein an optical port is arranged in the optical port pre-buried area, and a passivation layer is arranged above the optical port to cover the optical port;

[0008] forming a conductive connection portion above the external connection area, wherein the conductive connection portion is electrically connected to the optoelectronic chip;

[0009] A passivation layer opening is formed in the passivation layer, wherein the passivation layer opening exposes the light port.

[0010] Optionally, the passivation layer comprises a silicon dioxide layer.

[0011] Optionally, the method of forming the passivation layer opening includes laser drilling or dry etching.

[0012] Optionally, the conductive connection portion includes a first conductive connection portion and a second conductive connection portion, and the steps of forming the first conductive connection portion and the second conductive connection portion include:

[0013] A polyimide layer is formed on the optoelectronic chip and patterned to form a first polyimide layer opening and a second polyimide layer opening. The first polyimide layer opening defines the position of the first conductive connection portion, and the second polyimide layer opening defines the position of the second conductive connection portion;

[0014] A seed layer is formed, and the seed layer is filled into the first polyimide layer opening and the first polyimide layer opening;

[0015] A first photoresist layer is formed on the polyimide layer and patterned. The patterned first photoresist layer exposes the first polyimide layer opening. The first conductive connection portion is formed in the first polyimide layer opening, and the first photoresist layer is removed;

[0016] A second photoresist layer is formed on the polyimide layer and patterned. The patterned second photoresist layer exposes the second polyimide layer opening. The second conductive connection portion is formed in the second polyimide layer opening.

[0017] Optionally, the first conductive connection portion includes a Cu / Ni / Au composite layer stacked from bottom to top.

[0018] Optionally, the second conductive connection portion includes a Cu / Ni / SnAg composite layer stacked from bottom to top.

[0019] Optionally, after forming the second conductive connection portion, it further includes a step of reflux treatment with formic acid.

[0020] Optionally, the seed layer includes a Ti / Cu composite layer stacked from bottom to top.

[0021] As described above, in the method for manufacturing an optoelectronic chip of the present invention, the optical port is covered by a passivation layer before forming the conductive connection portion, and the passivation layer is opened to expose the optical port after forming the conductive connection portion, which can avoid contamination of the optical port during the formation of the conductive connection portion, improve the production yield, and reduce the cost. Description of the Drawings

[0022] Figure 1 It shows a process flow chart of the method for manufacturing an optoelectronic chip of the present invention.

[0023] Figure 2 It shows a schematic diagram of the optoelectronic chip provided in the present invention.

[0024] Figure 3 It shows a schematic diagram of forming a polyimide layer on the optoelectronic chip and patterning it in the present invention.

[0025] Figure 4 It shows a schematic diagram of forming a seed layer in the present invention.

[0026] Figure 5 It shows a schematic diagram of forming the first photoresist layer and patterning in the present invention.

[0027] Figure 6 It shows a schematic diagram of forming the first conductive connection part in the present invention.

[0028] Figure 7 It shows a schematic diagram of forming the second photoresist layer and patterning in the present invention.

[0029] Figure 8 It shows a schematic diagram of forming the second conductive connection part in the present invention.

[0030] Figure 9 It shows a schematic diagram of removing the second photoresist layer and the exposed seed layer in the present invention.

[0031] Figure 10 It shows a schematic diagram of forming a passivation layer opening to expose the optical port in the present invention.

[0032] Figure 11 It shows a schematic diagram after formic acid reflux treatment in the present invention.

[0033] Element number description

[0034] 1 Photoelectric chip

[0035] 10 External connection area

[0036] 11 Optical port pre-embedded area

[0037] 110 Optical port

[0038] 111 Passivation layer

[0039] 2 Polyimide layer

[0040] 20 First polyimide layer opening

[0041] 21 Second polyimide layer opening

[0042] 3 Seed layer

[0043] 4 First photoresist layer

[0044] 50 First conductive connection part

[0045] 51 Second conductive connection part

[0046] 6 Second photoresist layer

[0047] Steps S1 to S3 Detailed implementation manner

[0048] The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0049] Please refer to Figures 1 to 11 . It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the layout type of its components may also be more complex.

[0050] This embodiment provides a method for fabricating an optoelectronic chip. Please refer to Figure 1 , which shows a process flow chart of this fabrication method, including the following steps:

[0051] S1: Provide an optoelectronic chip. The optoelectronic chip includes an external connection area and an optical port pre-embedded area. An optical port is provided in the optical port pre-embedded area, and a passivation layer is provided above the optical port to cover the optical port.

[0052] S2: Form a conductive connection part above the external connection area. The conductive connection part is electrically connected to the optoelectronic chip.

[0053] S3: Form a passivation layer opening in the passivation layer. The passivation layer opening exposes the optical port.

[0054] First, please refer to Figure 2 , and perform step S1: Provide an optoelectronic chip 1. The optoelectronic chip 1 includes an external connection area 10 and an optical port pre-embedded area 11. An optical port 110 is provided in the optical port pre-embedded area 11, and a passivation layer 111 is provided above the optical port 110 to cover the optical port 110.

[0055] As an example, the optoelectronic chip 1 includes a photonic integrated circuit chip (PIC).

[0056] As an example, the passivation layer 111 includes a SiO2 passivation layer. The passivation layer 111 is used to protect the optical port 110 from being contaminated when fabricating the conductive connection part, that is, the optical port 110 is pre-embedded in the optoelectronic chip 1.

[0057] Next, please refer to Figures 3 to 8 , and perform step S2: Form a conductive connection part above the external connection area 10. The conductive connection part is electrically connected to the optoelectronic chip 1.

[0058] As an example, the conductive connection part includes a first conductive connection part 50 and a second conductive connection part 51. The steps of forming the conductive connection part include:

[0059] (1) As Figure 3 shown in the figure, a polyimide layer 2 is formed on the optical chip 1 and patterned to form a first polyimide layer opening 20 and a second polyimide layer opening 21. The first polyimide layer opening 20 defines the position of the first conductive connection part 50, and the second polyimide layer opening 21 defines the position of the second conductive connection part 51.

[0060] In this step, liquid polyimide is coated on the upper surface of the optoelectronic chip 1, and then the polyimide layer 2 is patterned by exposure and development processes to form the first polyimide layer opening 20 and the second polyimide layer opening 21. In other examples, a polyimide dry film can also be provided and laminated on the optical chip 1, and then the polyimide layer 2 is patterned by exposure and development processes.

[0061] (2) As Figure 4 shown in the figure, a seed layer 3 is formed, and the seed layer 3 is filled into the first polyimide layer opening 20 and the first polyimide layer opening 21.

[0062] In this step, the seed layer 3 is formed by electroplating or other suitable methods. During the deposition process, the seed layer 3 is also deposited on the upper surface of the polyimide layer 2 and the exposed upper surface of the optoelectronic chip 1. Specifically, the seed layer 3 includes a Ti / Cu composite layer stacked from bottom to top.

[0063] (3) As Figure 5 shown in the figure, a first photoresist layer 4 is formed on the polyimide layer 2 and patterned, and the patterned first photoresist layer 4 exposes the first polyimide layer opening 20.

[0064] In this step, the first photoresist layer 4 is coated above the polyimide layer 2, the first photoresist layer 4 covers the exposed seed layer 3, and then the first photoresist layer 4 is patterned by exposure and development processes to expose the first polyimide layer opening 20.

[0065] (4) As Figure 6 shown in the figure, a first conductive connection part 50 is formed in the first polyimide layer opening 20.

[0066] In this step, the first conductive connection portion 50 is formed by electroplating or other suitable methods. The first conductive connection portion 50 includes a Cu / Ni / Au composite layer stacked from bottom to top, and the first conductive connection portion 50 is used as a pad for connecting an amplifier. After forming the first conductive connection portion 50, it further includes the step of removing the first photoresist layer 4.

[0067] (V) As shown in Figure 7 , a second photoresist layer 6 is formed on the polyimide layer 2 and patterned. The patterned second photoresist layer 6 exposes the opening 21 of the second polyimide layer.

[0068] In this step, the second photoresist layer 6 is coated above the polyimide layer 2. The second photoresist layer 6 covers the exposed seed layer 3 and the first conductive connection portion 50, and then the second photoresist layer 6 is patterned by an exposure and development process to expose the opening 21 of the second polyimide layer.

[0069] (VI) As shown in Figure 8 , a first conductive connection portion 51 is formed in the opening 21 of the second polyimide layer.

[0070] In this step, the second conductive connection portion 51 is formed by electroplating or other suitable methods. The second conductive connection portion 51 includes a Cu / Ni / SnAg composite layer stacked from bottom to top, and the second conductive connection portion 51 is used as a pad for connecting devices such as an external power supply.

[0071] (VII) As shown in Figure 9 , the second photoresist layer 6 is removed, and the exposed seed layer 3 is removed.

[0072] In this step, the second photoresist layer 6 is removed by an ashing process, and the seed layer 3 is etched away by an etching process.

[0073] As an example, during the process of forming the first conductive connection portion 50 and the second conductive connection portion 51, since the passivation layer 111 covers above the optical port 110, it will not cause contamination to the optical port 110; and the passivation layer 111 covering the optical port 110 avoids the risk of the optical port 110 being contaminated. The first conductive connection portion 50 and the second conductive connection portion 51 can be fabricated by conventional processes, reducing the process processing difficulty and the limitations of process equipment.

[0074] Next, please refer to Figure 10 , and perform step S3: form a passivation layer opening in the passivation layer 111, and the passivation layer opening exposes the optical port 110.

[0075] As an example, methods such as laser drilling or dry etching are used to form the passivation layer opening. Preferably, in this embodiment, laser drilling is used to form the passivation layer opening, and the exposed optical port 110 serves as an optical receiving port or an optical output port.

[0076] As an example, as Figure 11 shown, it further includes a step of formic acid reflux treatment to make the SnAg layer in the second conductive connection portion 51 spherical and denser, while removing the SnAg surface oxide layer and increasing the soldering wettability. Of course, in other examples, formic acid reflux treatment can also be carried out before forming the passivation layer opening, and then the passivation layer opening is formed to expose the optical port 110.

[0077] In summary, in the method for manufacturing an optoelectronic chip of the present invention, the optical port is covered by a passivation layer before forming the conductive connection portion, and the passivation layer is opened to expose the optical port after forming the conductive connection portion, which can avoid the optical port being contaminated during the process of forming the conductive connection portion, improve the production yield, and reduce the cost. Therefore, the present invention effectively overcomes various drawbacks in the prior art and has high industrial utilization value.

[0078] The above embodiments are only illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A method for manufacturing an optoelectronic chip, characterized in that, Comprising the following steps: Providing an optoelectronic chip, the optoelectronic chip including an external connection region and an optical port pre-embedded region, an optical port being provided in the optical port pre-embedded region, and a passivation layer being provided above the optical port to cover the optical port; Forming a conductive connection portion above the external connection region, the conductive connection portion being electrically connected to the optoelectronic chip; Forming a passivation layer opening in the passivation layer, the passivation layer opening exposing the optical port.

2. The method for manufacturing an optoelectronic chip according to claim 1, wherein: The passivation layer includes a silicon dioxide layer.

3. The method for manufacturing an optoelectronic chip according to claim 1, wherein: The method for forming the passivation layer opening includes a laser drilling method or a dry etching method.

4. The method for manufacturing an optoelectronic chip according to claim 1, wherein, The conductive connection portion includes a first conductive connection portion and a second conductive connection portion. The steps for forming the first conductive connection portion and the second conductive connection portion include: Forming and patterning a polyimide layer on the optoelectronic chip to form a first polyimide layer opening and a second polyimide layer opening, the first polyimide layer opening defining the position of the first conductive connection portion, and the second polyimide layer opening defining the position of the second conductive connection portion; Forming a seed layer, the seed layer being filled into the first polyimide layer opening and the second polyimide layer opening; Forming and patterning a first photoresist layer on the polyimide layer, the patterned first photoresist layer exposing the first polyimide layer opening, forming the first conductive connection portion in the first polyimide layer opening, and removing the first photoresist layer; Forming and patterning a second photoresist layer on the polyimide layer, the patterned second photoresist layer exposing the second polyimide layer opening, and forming the second conductive connection portion in the second polyimide layer opening.

5. The method for manufacturing an optoelectronic chip according to claim 4, wherein: The first conductive connection portion includes a Cu / Ni / Au composite layer stacked from bottom to top.

6. The method for manufacturing an optoelectronic chip according to claim 4, wherein: The second conductive connection portion includes a Cu / Ni / SnAg composite layer stacked from bottom to top.

7. The method for manufacturing an optoelectronic chip according to claim 6, characterized in that: After forming the second conductive connection portion, it further includes a step of reflux treatment with formic acid.

8. The method for manufacturing an optoelectronic chip according to claim 4, wherein: The seed layer includes a Ti / Cu composite layer stacked from bottom to top.

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