Display panel and manufacturing method thereof

Abstract

The invention provides a display panel and a manufacturing method thereof. The display panel comprises a substrate; the plurality of pixel circuits are arranged on the substrate; a plurality of light-emitting units, wherein the light-emitting units and the pixel circuits are arranged in a one-to-one correspondence manner; the first wire is arranged above the pixel circuit, and the first wire is connected to the positive electrode of the corresponding light-emitting unit through the pixel circuit; the first wire is arranged above the pixel circuit, the second wire is arranged above the pixel circuit, the second wire is connected with the negative electrode of the corresponding light-emitting unit, and a stacking structure is formed through the first wire and the second wire so as to shield a light path, irradiating to the pixel circuit, of the light-emitting unit. According to the invention, the wiring voltage drop can be effectively reduced, the power consumption is reduced, the brightness uniformity is improved, and the phenomenon of abnormal display caused by leakage current generated by illumination is avoided.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit applications, and particularly to a display panel and a manufacturing method thereof. Background Art

[0002] LED (Light Emitting Diode) is widely recognized as the fourth-generation lighting source or green light source. Due to various characteristics such as energy saving, environmental protection, long lifespan, and small size, it has been widely applied in various fields such as backlights, general lighting, decoration, display, and indication. Especially in recent years, with the wide acceptance of LED in the field of general lighting by the general public, the entire LED industry has developed rapidly.

[0003] With the development of LED technology, the size of LED chips has gradually been miniaturized to the micron level (M-LED, M-LED includes Micro LED and Mini LED). Due to the characteristics of small size, high integration, and self-luminescence of M-LED chips, it has greater advantages in terms of brightness, resolution, contrast, energy consumption, service life, response speed, and thermal stability compared with LCD and OLED in the display aspect.

[0004] However, at present, the M-LED display panel circuit has problems of high power consumption and uneven brightness, which greatly affect the product quality and user experience. Summary of the Invention

[0005] In view of the problems existing in the above-related technologies, the present invention proposes a display panel and a manufacturing method thereof, mainly solving the problems of high power consumption and uneven brightness of the display panel.

[0006] In order to achieve the above object and other objects, the technical solution adopted by the present invention is as follows.

[0007] The present application provides a display panel, including: a substrate; a plurality of pixel circuits disposed on the substrate; a plurality of light-emitting units, the light-emitting units being disposed in one-to-one correspondence with the pixel circuits; a first trace disposed above the pixel circuits, the first trace being connected to the positive electrode of the corresponding light-emitting unit via the pixel circuit; a second trace disposed above the pixel circuits, the second trace being connected to the negative electrode of the corresponding light-emitting unit, and a stacked structure being formed by the first trace and the second trace to block the optical path of the light-emitting unit irradiating the pixel circuit.

[0008] In an embodiment of the present application, a first groove is provided at the connection position between the light-emitting unit and the pixel circuit, and the positive electrode of the light-emitting unit is embedded in the first groove for fixation; and / or, a second groove is provided at the connection position between the light-emitting unit and the second trace, and the negative electrode of the light-emitting unit is embedded in the second groove for fixation.

[0009] In an embodiment of the present application, the stacked structure includes: a first insulating layer disposed on a side of the pixel circuit facing away from the substrate; the first trace disposed on a side of the first insulating layer facing away from the pixel circuit and connected to an input end of the pixel circuit through a first through hole reserved on the first insulating layer, so that an external power supply voltage is connected to the pixel circuit through the first trace; a second insulating layer disposed on a side of the first trace facing away from the first insulating layer; the second trace disposed on a side of the second insulating layer facing away from the second trace and connected to an output end of the pixel circuit through a second through hole penetrating the first insulating layer and the second insulating layer, and the second trace is not in contact with the first trace; a third trace located on the same layer as the second trace, one end of the third trace is connected to a positive electrode of the light-emitting unit, and the other end is connected to the output end of the pixel circuit through a third through hole penetrating the first insulating layer and the second insulating layer.

[0010] In an embodiment of the present application, a first metal layer, a second metal layer, and a third metal layer are spaced apart on a side of the pixel circuit facing away from the substrate, and the first metal layer, the second metal layer, and the third metal layer are located on the same layer. The first metal layer is connected to an input end of the pixel circuit, the second metal layer is connected to a negative electrode of an external power supply, and the third metal layer is connected to a positive end of the light-emitting unit.

[0011] In an embodiment of the present application, the pixel circuit includes a driving unit, and the first trace and the second trace partially extend above the driving unit to shield the driving unit.

[0012] The present application further provides a method for manufacturing a display panel, including: providing a substrate and a plurality of light-emitting units; manufacturing a plurality of pixel circuits on the substrate, and the light-emitting units and the pixel circuits are arranged in one-to-one correspondence; manufacturing a first trace and a second trace above the pixel circuits, and the first trace is connected to a positive electrode of a corresponding light-emitting unit through the pixel circuit; the second trace is connected to a negative electrode of the corresponding light-emitting unit, and a stacked structure is formed by the first trace and the second trace to shield an optical path of the light-emitting unit irradiating the pixel circuit.

[0013] In an embodiment of the present application, the steps of fabricating a first trace and a second trace above the pixel circuit include: coating a first photoresist layer above the pixel circuit; performing exposure and development on the first photoresist layer to form a first through hole, a second through hole, and a third through hole; wherein, the first through hole penetrates through the first photoresist layer and extends to the input end of the pixel circuit, the second through hole penetrates through the first photoresist layer to form a path connecting the light-emitting unit and the negative electrode of an external power supply, and the third through hole penetrates through the first photoresist layer to form a path connecting the output end of the pixel circuit and the positive electrode of the light-emitting unit; fabricating the first trace on the first photoresist layer such that the first trace covers the first through hole and extends above the driving unit of the pixel circuit; coating a second photoresist layer on the basis of the first photoresist layer and the first trace; performing exposure and development on the second photoresist layer to form a groove for placing the corresponding electrode of the light-emitting unit, and making the second through hole penetrate through the second photoresist layer; fabricating the second trace on the second photoresist layer such that the second trace extends above the driving unit to cooperate with the first trace to shield the driving unit.

[0014] In an embodiment of the present application, the steps of performing exposure and development on the first photoresist layer to form a first through hole and a second through hole include: providing a first mask; wherein, the first mask includes a first light-shielding portion, a second light-shielding portion, and a first semi-transparent portion; the first light-shielding portion is used to shield the area for forming the first through hole, the second light-shielding portion is used to shield the area for forming the second through hole, and the first semi-transparent portion is used to shield the area for forming the groove; after exposure based on the first mask, the first through hole and the second through hole are obtained through development.

[0015] In an embodiment of the present application, the steps of performing exposure and development on the second photoresist layer include: providing a second mask, wherein the second mask includes a third light-shielding portion and a second semi-transparent portion, the third light-shielding portion is used to shield the area for forming the second through hole, and the second semi-transparent portion is used to shield the area for forming the groove; after exposure based on the second mask, the second through hole and the groove are obtained through development.

[0016] In an embodiment of the present application, the first photoresist layer and the second photoresist layer are negative photoresists.

[0017] As described above, a display panel and a manufacturing method thereof provided by the present application have the following beneficial effects.

[0018] By optimizing the layout of the first trace and the second trace, the present application can greatly increase the surface area of the first trace and the second trace, thereby reducing the trace voltage drop, further reducing the product power consumption, and improving the finished product performance; in addition, by the cooperation of the first trace and the second trace to shield the pixel circuit, it is possible to prevent the light emitted by the light-emitting unit from irradiating the pixel circuit to form photo-generated carriers, thereby avoiding the problem of display abnormality caused by the increase in leakage current due to photo-generated carriers. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a top view of a display panel in an embodiment of the present application.

[0020] Figure 2 It is a schematic diagram of the connection manner between a trace and a light-emitting unit in an embodiment of the present application.

[0021] Figure 3 It is a schematic cross-sectional projection diagram of a pixel circuit in an embodiment of the present application.

[0022] Figure 4 For the present application Figure 1 It is a schematic diagram of a partial cross-sectional structure of the display panel in the present application along the X direction at the positive electrode position of the light-emitting unit.

[0023] Figure 5 For the present application Figure 1 It is a schematic diagram of a partial cross-sectional structure of the display panel in the present application along the Y direction at the negative electrode position of the light-emitting unit.

[0024] Figure 6 It is a schematic flowchart of a manufacturing method of a display panel in an embodiment of the present application.

[0025] Figure 7 It is a schematic cross-sectional diagram after coating the first glue layer in an embodiment of the present application.

[0026] Figure 8 It is a schematic cross-sectional structure diagram during exposure in an embodiment of the present application.

[0027] Figure 9 It is a schematic cross-sectional structure diagram after development in an embodiment of the present application.

[0028] Figure 10 It is a schematic cross-sectional structure diagram after manufacturing the first trace in an embodiment of the present application.

[0029] Figure 11 It is a schematic cross-sectional structure diagram after coating the second glue layer in an embodiment of the present application.

[0030] Figure 12 It is a schematic cross-sectional structure diagram during exposure in an embodiment of the present application.

[0031] Figure 13Schematic cross-sectional structure diagram after development in an embodiment of the present application.

[0032] Figure 14 Schematic cross-sectional structure diagram after manufacturing the second trace in an embodiment of the present application.

[0033] Explanation of the reference numerals in the accompanying drawings:

[0034] 01 - Light-emitting unit; 02 - Pixel circuit; 03 - First trace; 04 - Second trace; 05 - First metal layer; 06 - Second metal layer; 07 - Concave hole; 08 - First through hole; 09 - Second through hole; 10 - Second groove; 11 - Third through hole; 12 - Negative electrode pad position; 13 - Positive electrode pad position; 14 - Substrate; 15 - Third metal layer; 16 - First groove; 17 - Third trace; 18 - First adhesive layer; 19 - Second adhesive layer; 20 - First light-shielding portion; 21 - Second light-shielding portion; 22 - Third light-shielding portion; 23 - First semi-transmissive portion; 24 - Second semi-transmissive portion; 25 - Light-transmissive substrate; Poly - Polysilicon layer; Buffer - Buffer layer; PLN1 - First insulating layer; PLN2 - Second insulating layer; Gl1 - Third insulating layer; M1 - Fourth metal layer; Gl2 - Fourth insulating layer; M2 - Fifth metal layer; PVX - Fifth insulating layer; M3 - Sixth metal layer. Detailed implementation manners

[0035] The following illustrates the implementation manners of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0036] It should be noted that the diagrams provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0037] After research by the inventor, it is found that the currents of all the light-emitting units 01 in the related display panel will converge to the positive electrode (VDD) and the negative electrode (VSS) of the external power supply. If the voltage drops of the VDD trace and the VSS trace are too large, it is necessary to increase the output voltage of the power supply terminal, resulting in high power consumption on VDD and VSS, large differences in VDD / VSS voltages at different positions in the display panel, and large differences in brightness.

[0038] In addition, in a display panel, pixels are usually driven by thin film transistors (TFTs). However, due to the generation of photo-generated carriers caused by the illumination of the light-emitting units connected to the pixel circuits in the TFT devices, the leakage current increases, resulting in abnormal display.

[0039] Moreover, the light-emitting units in the display panel are also prone to falling off, which greatly restricts the yield of the finished product and increases the manufacturing cost.

[0040] Based on the above problems existing in the display panel, this application proposes a display panel and a manufacturing method thereof. The technical solutions of this application will be elaborated in detail below with reference to specific embodiments.

[0041] Please refer to Figure 1-5 , Figure 1 , which is a top view of the display panel in an embodiment of this application; Figure 2 , which is a schematic diagram of the connection manner between the trace and the light-emitting unit in an embodiment of this application; Figure 3 , which is a schematic cross-sectional projection diagram of the pixel circuit in an embodiment of this application; Figure 4 In this application Figure 1 , a partial cross-sectional structure diagram of the display panel in the positive electrode position of the light-emitting unit along the X direction; Figure 5 In this application Figure 1Schematic diagram of the partial cross-sectional structure of the display panel along the Y direction at the negative electrode position of the light-emitting unit. The display panel according to the embodiment of the present application includes a substrate 14, a plurality of pixel circuits 02, a plurality of light-emitting units 01, a first trace 03, and a second trace 04. Among them, the plurality of pixel circuits 02 can be integrated on the substrate 14, and a pixel array is formed through the plurality of pixel circuits 02. The specific arrangement manner of the pixel circuits 02 can be adjusted according to actual application requirements and is not limited here. Each pixel circuit 02 can correspond to one light-emitting unit 01, that is, one light-emitting unit 01 is connected to one pixel circuit 02. A negative electrode pad position 12 and a positive electrode pad position 13 for connecting the light-emitting unit 01 are provided above the pixel circuit 02. The negative electrode pad position 12 is used for bonding with the negative electrode of the light-emitting unit 01, and the positive electrode pad position 13 is used for bonding with the positive electrode of the light-emitting unit 01. The light-emitting unit 01 here can include LED, Micro LED, Mini LED, etc. The specific type of the light-emitting unit 01 can be selected according to actual application requirements and is not limited here. The first trace 03 and the second trace 04 are respectively disposed above each pixel circuit 02. The output end of the pixel circuit 02 is connected to the positive electrode of the light-emitting unit 01. The input end of the pixel circuit 02 is connected to the positive pole (VDD) of the external power supply through the first trace 03. The voltage magnitude is adjusted through the pixel circuit 02 to meet the power supply voltage requirement of the light-emitting unit 01. The negative electrode of the light-emitting unit 01 is connected to the second trace 04 and is connected to the negative pole (VSS) of the external power supply through the second trace 04. Taking the LED as the light-emitting unit 01 as an example, the connection manner between the LED and the traces is as Figure 2 shown. The positive pole (VDD) of the external power supply is connected to the input end of the pixel circuit 02 through the first trace 03. The output end of the pixel circuit 02 is connected to the positive electrode of the LED. The negative electrode of the LED is connected to the negative pole (VSS) of the external power supply through the second trace 04.

[0042] Please refer to Figure 1 , since when the polycrystalline silicon layer Poly in the transistor in the pixel circuit 02 of the related display panel is irradiated by the LED light, carriers will be generated, which will cause the problem of abnormal display. In the embodiment of the present application, a stacked structure is formed by the cooperation of the first trace 03 and the second trace 04 to shield the pixel circuit 02, which can prevent the light of the LED from irradiating the pixel circuit 02, and thus effectively solve the influence of the photo-generated carriers of the pixel circuit 02 on the display.

[0043] Please refer to FIG. Figure 1 , Figure 4 and Figure 5, the stacked structure includes a first insulating layer PLN1 disposed on a side of the pixel circuit 02 away from the substrate 14; a first trace 03 disposed on a side of the first insulating layer PLN1 away from the pixel circuit 02 and connected to an input end of the pixel circuit 02 through a first through hole 08 reserved on the first insulating layer PLN1, so that an external power supply voltage is connected to the pixel circuit 02 through the first trace 03; a second insulating layer PLN2 disposed on a side of the first trace 03 away from the first insulating layer PLN1; a second trace 04 disposed on a side of the second insulating layer PLN2 away from the first trace 03 and connected to a negative electrode (VSS) of an external power supply through a second through hole 09 penetrating through the first insulating layer PLN1 and the second insulating layer PLN2, and the second trace 04 is not in contact with the first trace 03; a third trace 17 located on the same layer as the second trace 04, one end of the third trace 17 is connected to a positive electrode of the light-emitting unit 01, and the other end is connected to an output end of the pixel circuit 02 through a third through hole 11 penetrating through the first insulating layer PLN1 and the second insulating layer PLN2.

[0044] Specifically, please refer to Figure 1 and Figure 4, in the embodiment of the present application, by forming a stacked structure of the first trace 03 and the second trace 04, and using this stacked structure to block the light path of the pixel circuit 02, the influence of photo-generated carriers on the display effect can be effectively avoided. At the same time, the wiring area of the first trace 03 and the second trace 04 can be increased, thereby reducing the voltage drop of the traces, reducing the trace power consumption, and improving the brightness uniformity of the light-emitting unit 01. The stacked structure includes: a first insulating layer PLN1, a first trace 03, a second trace 04, and a second insulating layer PLN2. The first insulating layer PLN1 is disposed on the side of the pixel circuit 02 away from the substrate 14; the first trace 03 is disposed on the side of the first insulating layer PLN1 away from the pixel circuit 02, and is connected to the input end of the pixel circuit 02 through a first through hole 08 reserved on the first insulating layer PLN1; the second insulating layer PLN2 is disposed on the side of the first trace 03 away from the first insulating layer PLN1; the second trace 04 is disposed on the side of the second insulating layer PLN2 away from the second trace 04, and forms a path connecting the negative electrode (VSS) of the external power supply and the negative electrode of the light-emitting unit 01 through a second through hole 09 penetrating the first insulating layer PLN1 and the second insulating layer PLN2. The second trace 04 does not contact the first trace 03. By partially extending the first trace 03 to the surface of the driving unit of the pixel circuit 02 to completely block the front surface of the polysilicon layer Poly of the driving unit, and then covering the second through hole 09 with the second trace 04 and extending it above the driving unit, the second trace 04 and the first trace 03 form a relatively closed shielding structure, which can completely block the light path from the light-emitting unit 01 and avoid the influence of the light-emitting unit 01 on the polysilicon layer Poly. At the same time, this wiring structure can also greatly increase the area of the first trace 03 and the second trace 04, thereby reducing the trace voltage drop. A layer of the second trace 04 is covered in the second groove 10. After the negative electrode of the light-emitting unit 01 is embedded in the second groove 10, it is directly connected to the second trace 04 in the groove. The negative electrode of the light-emitting unit 01 can be fixed through the groove design to prevent the light-emitting unit 01 from falling off. Specifically, the areas of the first trace 03 and the second trace 04 can be set and adjusted according to actual application requirements, and are not limited here.

[0045] In one embodiment, the pixel circuit 02 includes a driving unit, and the first trace 03 and the second trace 04 partially extend above the driving unit to block the driving unit. Exemplarily, the driving unit can adopt a circuit composed of TFT (Thin Film Transistor), but is not limited thereto.

[0046] Please refer to Figure 3, the pixel circuit 02 may include a polysilicon layer Poly, a third insulating layer Gl1, a fourth metal layer M1, a fourth insulating layer Gl2, a fifth metal layer M2, a fifth insulating layer PVX, and a sixth metal layer M3. Among them, the sixth metal layer M3 includes a first metal layer 05, a second metal layer 06, and a third metal layer 15, and the polysilicon layer Poly is a component in the driving unit. The pixel circuit 02 is disposed on the substrate 14, and a buffer layer Buffer may be disposed between the pixel circuit 02 and the substrate 14. The polysilicon layer Poly and the third insulating layer Gl1 are disposed on the side of the buffer layer Buffer away from the substrate 14, and the third insulating layer Gl1 covers the polysilicon layer Poly. The polysilicon layer Poly generally serves as a conductive layer in the driving unit of the pixel circuit 02. The fourth metal layer M1 is disposed on the polysilicon layer Poly and the third insulating layer Gl1. The fourth metal layer M1 is used to lead out the gate signal of the transistor corresponding to the polysilicon layer Poly and partially shields the polysilicon layer Poly. The fourth insulating layer Gl2 is formed on the fourth metal layer M1. The fifth metal layer M2 is disposed on the basis of the fourth insulating layer Gl2. The fifth insulating layer PVX is disposed on the fifth metal layer M2. A recess 07 is formed on the fifth insulating layer PVX. The recess 07 penetrates the fifth insulating layer PVX, and the first metal layer 05 is disposed on the basis of the recess 07.

[0047] Please refer to Figure 3 and Figure 4 , in an embodiment, the first metal layer 05 is connected to the input end of the pixel circuit 02, the second metal layer 06 is connected to the negative electrode (VSS) of the external power supply. A second groove 10 may be provided at the connection position between the light-emitting unit 01 and the second trace 04. The inner wall of the second groove 10 is covered by the second trace 04, and the negative electrode of the light-emitting unit 01 is embedded in the second groove 10 to be connected to the second trace 04. The negative electrode of the light-emitting unit 01 is fixed by the second groove 10 to prevent the light-emitting unit 01 from falling off. The first trace 03 and the second trace 04 form a stacked structure to shield the pixel circuit 02, preventing the light emitted by the light-emitting unit 01 from irradiating the semiconductor material in the pixel circuit 02 and generating photocarriers, which affects the display effect of the display panel.

[0048] Specifically, as Figure 3As shown, the sixth metal layer M3 includes a first metal layer 05 and a second metal layer 06. The first metal layer 05 and the second metal layer 06 are arranged at intervals and do not come into contact with each other. The first metal layer 05 is connected to the fifth metal layer M2 through a concave hole 07 penetrating the fifth insulating layer PVX as the input trace of the pixel circuit 02. The fourth metal layer M1 is connected to the gate of the transistor corresponding to the polysilicon layer Poly. The fourth metal layer M1 is partially disposed on the polysilicon layer Poly. The second metal layer 06 is used to connect the second trace 04. Since the fourth metal layer M1 in the pixel circuit 02 cannot completely shield the polysilicon layer Poly, and the light-emitting diode is disposed on the pixel circuit 02, the light emitted by the light-emitting diode will irradiate the polysilicon layer Poly, and the polysilicon layer Poly generates photo-generated carriers, thereby causing a display abnormality. In this application, by optimizing the wiring structure of the first trace 03 and the second trace 04, the first trace 03 and the second trace 04 cooperate to shield the polysilicon layer Poly in the pixel circuit 02, preventing the light emitted by the light-emitting diode from irradiating the polysilicon layer Poly to form photo-generated carriers.

[0049] Please refer to Figure 1 、 Figure 4 and Figure 5, a first groove 16 can be set at the position where the light-emitting unit 01 is connected to the pixel circuit 02. Specifically, the first groove 16 can be set at the corresponding position of the positive electrode pad 13. The third trace 17 covers the first groove 16 and extends to the third via 11. The light-emitting unit 01 is embedded in the first groove 16 to be connected to the third trace 17. The third trace 17 and the second trace 04 are located on the same layer, but they do not contact each other. The third via 11 penetrates through the first insulating layer PLN1 and the second insulating layer PLN2. The third via 11 connects the third trace 17 and the third metal layer 15. The output end of the pixel circuit 02 is connected to the positive electrode of the light-emitting unit 01 through the conductive path formed by the third metal layer 15, the third via 11, and the third trace 17. The positive electrode of the light-emitting unit 01 establishes a circuit connection with the output end of the pixel circuit 02 through the third trace 17 in the first groove 16. The positive pole (VDD) of the external power supply is connected to the input end of the pixel circuit 02 through the first trace 03. The output end of the pixel circuit 02 is connected to the positive electrode of the light-emitting unit 01 through the third trace 17. The negative electrode of the light-emitting unit 01 is connected to the negative pole (VSS) of the external power supply through the second trace 04, thereby forming the driving circuit structure of the light-emitting unit 01. The second groove 10 is set in the area where the negative electrode pad 12 is located. The negative electrode of the light-emitting unit 01 can be embedded in the second groove 10 and connected to the second trace 04 through the negative electrode pad 12. The light-emitting unit 01 is fixed by the first groove 16 and the second groove 10 to prevent the light-emitting unit 01 from falling off, and at the same time, to avoid the situation where the electrodes of the light-emitting unit 01 are on a flat metal surface, resulting in poor fixing effect. In another embodiment, one of the first groove 16 and the second groove 10 can also be selectively set, and the effect of fixing the light-emitting unit 01 can also be achieved. The specific setting method can be selected according to actual application requirements and is not limited here. Please refer to Figure 6 , the embodiment of the present application also provides a manufacturing method of a display panel, and the method includes the following steps:

[0050] Step S500, provide a substrate 14 and a plurality of light-emitting units 01.

[0051] In one embodiment, the substrate 14 can be made of silicon, silicon carbide, etc. The light-emitting unit 01 can include a light-emitting diode LED, a micro light-emitting diode Micro LED, a millimeter-scale light-emitting diode Mini LED, etc. The specific device types of the substrate 14 and the light-emitting unit 01 can be selected and adjusted according to actual application requirements and are not limited here.

[0052] Step S510, fabricate a plurality of pixel circuits 02 on the substrate 14, and the light-emitting units 01 and the pixel circuits 02 are arranged in one-to-one correspondence.

[0053] Please refer to Figure 3, the pixel circuit 02 is provided in one-to-one correspondence with the light-emitting unit 01. Specifically, one pixel circuit 02 can be connected to one light-emitting unit 01. Figure 3 FIG. is a schematic cross-sectional structure diagram showing only a partial area of a single pixel circuit 02. Multiple pixel circuits 02 in the display panel usually form an array arrangement, and the specific arrangement method is not limited here. The pixel circuit 02 includes: a polysilicon layer Poly, a third insulating layer Gl1, a fourth metal layer M1, a fourth insulating layer Gl2, a fifth metal layer M2, a fifth insulating layer PVX, and a sixth metal layer M3. The pixel circuit 02 can be disposed on the substrate 14. A buffer layer Buffer can be disposed between the pixel circuit 02 and the substrate 14. The polysilicon layer Poly and the third insulating layer Gl1 are disposed on the side of the buffer layer Buffer away from the substrate 14, and the third insulating layer Gl1 covers the polysilicon layer Poly. The polysilicon layer Poly generally serves as a conductive layer in the driving unit of the pixel circuit 02. The driving unit can include a TFT transistor. The fourth metal layer M1 is disposed on the polysilicon layer Poly and the third insulating layer Gl1, and the fourth metal layer M1 partially obscures the polysilicon layer Poly. The fourth insulating layer Gl2 is fabricated on the fourth metal layer M1, the fifth metal layer M2 is disposed on the basis of the fourth insulating layer Gl2, the fifth insulating layer PVX is disposed on the fifth metal layer M2, a concave hole 07 is formed in the fifth insulating layer PVX, the concave hole 07 penetrates the fifth insulating layer PVX, and the sixth metal layer M3 is disposed on the basis of the concave hole 07. The sixth metal layer M3 includes a first metal layer 05, a second metal layer 06, and a third metal layer 15. The first metal layer 05, the second metal layer 06, and the third metal layer 15 are spaced apart and do not come into contact with each other. The first metal layer 05 is connected to the fifth metal layer M2 through the concave hole 07 penetrating the fifth insulating layer PVX as the input end of the pixel circuit 02, and the first metal layer 05 is connected to the gate of the transistor corresponding to the polysilicon layer Poly. The second metal layer 06 is used to connect to the second trace 04.

[0054] Step S520, fabricate a first trace 03 and a second trace 04 above the pixel circuit 02. The first trace 03 is connected to the positive electrode of the corresponding light-emitting unit 01 via the pixel circuit 02; the second trace 04 is connected to the negative electrode of the corresponding light-emitting unit 01, and a stacked structure is formed by the first trace 03 and the second trace 04 to block the light path of the light-emitting unit 01 irradiating the pixel circuit 02.

[0055] In one embodiment, the steps of fabricating the first trace 03 and the second trace 04 above the pixel circuit 02 include: coating a first photoresist layer 18 above the pixel circuit 02; performing exposure and development on the first photoresist layer 18 to form a first through hole 08, a second through hole 09, and a third through hole 11; wherein, the first through hole 08 penetrates through the first photoresist layer 18 and extends to the input end of the pixel circuit 02, the second through hole 09 penetrates through the first photoresist layer 18 to form a path connecting the light-emitting unit 01 and the negative electrode (VSS) of the external power supply, and the third through hole 11 penetrates through the first photoresist layer 18 to form a path connecting the output end of the pixel circuit 02 and the positive electrode of the light-emitting unit 01, thereby obtaining the first insulating layer PLN1 as shown in Figure 4 and Figure 5 ; fabricating the first trace 03 on the first photoresist layer 18 (i.e., the first insulating layer PLN1) such that the first trace 03 covers the first through hole 08 and extends above the driving unit of the pixel circuit 02; coating a second photoresist layer 19 on the basis of the first photoresist layer 18 and the first trace 03; performing exposure and development on the second photoresist layer 19 to form a groove for placing the corresponding electrode of the light-emitting unit 01, and making the second through hole 09 and the third through hole 11 penetrate through the second photoresist layer 19, thereby obtaining the second insulating layer PLN2 as shown in Figure 4 and Figure 5 ; fabricating the second trace 04 on the second photoresist layer 19 (i.e., the second insulating layer PLN2) such that the second trace 04 extends above the driving unit to cooperate with the first trace 03 to shield the driving unit.

[0056] Specifically, please refer to Figure 7 , Figure 7 which is a schematic cross-sectional view after coating the first photoresist layer 18 in an embodiment of the present application. The first photoresist layer 18 is coated on the top layer of the pixel circuit 02, and the first photoresist layer 18 can be a negative photoresist. The first photoresist layer 18 here is the first insulating layer PLN1 in the foregoing display panel embodiment.

[0057] In one embodiment, the steps of performing exposure and development on the first photoresist layer 18 to form the first through hole 08 and the second through hole 09 include: providing a first mask; wherein, the first mask includes a first light-shielding portion 20, a second light-shielding portion 21, and a first semi-transmissive portion 23; the first light-shielding portion 20 is used to shield the area for forming the first through hole 08, the second light-shielding portion 21 is used to shield the area for forming the second through hole 09, and the first semi-transmissive portion 23 is used to shield the area for forming the groove; after exposure based on the first mask, the first through hole 08 and the second through hole 09 are obtained through development.

[0058] In one embodiment, the steps of forming the third through hole 11 are the same as those of forming the second through hole 09, and will not be elaborated here.

[0059] Specifically, please refer to Figure 8 ,Figure 8 It is a schematic cross-sectional structure diagram during exposure in an embodiment of the present application. The first mask plate may include a light-transmissive substrate 25. On one side plane of the light-transmissive substrate 25, a first light-shielding portion 20, a second light-shielding portion 21, and a first semi-transmissive portion 23 are provided. The first semi-transmissive portion 23 is located between the first light-shielding portion 20 and the second light-shielding portion 21. The first light-shielding portion 20 and the second light-shielding portion 21 are completely light-impermeable, and the light transmittance of the first semi-transmissive portion 23 can be set to be greater than 0% and less than 100%. The specific light transmittance can be adjusted according to actual production requirements and is not limited here.

[0060] Specifically, please refer to Figure 9 , Figure 9 It is a schematic cross-sectional structure diagram after development in an embodiment of the present application. The negative photoresist will solidify under light. The solidified negative photoresist will not react with the developer. The areas blocked by the first light-shielding portion 20 and the second light-shielding portion 21 are not solidified, and the areas blocked by the first semi-transmissive portion 23 are partially solidified. Therefore, after exposure, in the development stage, the non-solidified areas will be dissolved by the developer, and the partially solidified areas react with the developer and are only partially dissolved, and part of the photoresist layer can be retained.

[0061] Please refer to Figure 10 , Figure 10 It is a schematic cross-sectional structure diagram after manufacturing the first trace 03 in an embodiment of the present application. The first trace 03 can be manufactured on the basis of the first photoresist layer 18. The first via 08 and the second via 09 are formed on the first photoresist layer 18 through exposure and development using the first mask plate. The first trace 03 covers the first via 08 and is connected to the metal layer at the bottom of the first via 08. In addition, when manufacturing the first trace 03, the area of the second via 09 is reserved, that is, no wiring is performed in the area of the second via 09. The first trace 03 extends directly above the driving unit of the pixel circuit 02 to block the optical path directly above the driving unit and at the same time increase the wiring area of the first trace 03.

[0062] Please refer to Figure 11 , Figure 11 It is a schematic cross-sectional structure diagram after coating the second photoresist layer 19 in an embodiment of the present application. After manufacturing the first trace 03, a layer of negative photoresist can be coated again as the second photoresist layer 19. The second photoresist layer 19 here is the second insulating layer PLN2 in the foregoing display panel embodiment.

[0063] In one embodiment, the steps of exposing and developing the second photoresist layer 19 include: providing a second mask plate, where the second mask plate includes a third light-shielding portion 22 and a second semi-transmissive portion 24. The third light-shielding portion 22 is used to block the area for forming the second via 09, and the second semi-transmissive portion 24 is used to block the area for forming the groove; after exposure based on the second mask, the second via 09 and the groove are obtained through development.

[0064] Specifically, please refer to Figure 12 , Figure 12 which is a schematic cross-sectional structure diagram during exposure in an embodiment of the present application. The second mask plate may include a Mask substrate, a third light-shielding portion 22, and a second semi-transmissive portion 24. The third light-shielding portion 22 and the second semi-transmissive portion 24 are disposed on one side plane of the Mask substrate. The third light-shielding portion 22 is completely light-impermeable. The light transmittance of the second semi-transmissive portion 24 is greater than 0% and less than 100%, and the specific light transmittance can be adjusted according to actual production requirements, which is not limited here. The third light-shielding portion 22 is used to block the area where the second through hole 09 formed in the previous step is located, and the second semi-transmissive portion 24 is used to block the area blocked by the first light-shielding portion 20.

[0065] Please refer to Figure 13 , Figure 13 which is a schematic cross-sectional structure diagram after development in an embodiment of the present application. After the light irradiates the second mask plate, the second glue layer 19 corresponding to the 100% light-transmissive area is completely cured, the positions not irradiated by the light are not cured, and the glue layer portion blocked by the second semi-transmissive portion 24 is partially cured. By reacting with the developer, the uncured second glue layer 19 is dissolved and removed, and the partially cured second glue layer 19 retains a certain thickness, thereby forming a groove in the area blocked by the second semi-transmissive portion 24.

[0066] Please refer to Figure 14 , Figure 14 which is a schematic cross-sectional structure diagram after manufacturing the second trace 04 in an embodiment of the present application. The second trace 04 is manufactured on the basis of the second glue layer 19 after exposure and development. The second trace 04 covers the groove and the second through hole 09 obtained in the previous step and extends directly above the driving unit of the pixel circuit 02. By stacking the second trace 04 and the first trace 03 above the driving unit, the optical path of the light emitted by the light-emitting unit 01 irradiating the driving unit can be completely blocked, thereby avoiding the generation of carriers in the driving unit under light irradiation and affecting the display effect. In addition, after avoiding the pad positions for connecting the light-emitting unit 01, the second trace 04 can be widely wired. Increasing the wiring area can reduce the voltage drop of the trace and avoid the problem of poor brightness uniformity caused by too large a pressure difference between the first trace 03 and the second trace 04. The increase in the areas of the first trace 03 and the second trace 04 can greatly reduce the trace resistance, reduce the power consumption, and at the same time, the brightness uniformity of the light-emitting unit 01 can be greatly improved.

[0067] In one embodiment, the pad position of the positive electrode of the light-emitting unit 01 can also form a groove through the aforementioned exposure and development method. The light-emitting unit 01 is fixed by the cooperation of the groove of the positive electrode pad position 13 and the groove of the negative electrode pad position 12, which can enhance the fixing effect and effectively improve the problem of the light-emitting unit 01 falling off in the display panel. At the same time, fixing the light-emitting unit 01 through the groove can avoid the problems of short circuit or failure of the light-emitting unit 01 caused by displacement after the light-emitting unit 01 contacts the flat metal surface, and improve the reliability of the finished product.

[0068] The above embodiments are only illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A display panel, characterized in that, include: substrate; A plurality of pixel circuits are disposed on the substrate; A plurality of light-emitting units, wherein the light-emitting units are arranged in a one-to-one correspondence with the pixel circuits; A first wiring, which is arranged above the pixel circuit, and the first wiring is connected to the positive electrode of the corresponding light-emitting unit via the pixel circuit; A second wiring is arranged above the pixel circuit, the second wiring is connected to the negative electrode of the corresponding light-emitting unit, and a stacking structure is formed by the first wiring and the second wiring to block the light path of the light-emitting unit irradiating the pixel circuit.

2. The display panel according to claim 1, characterized in that, A first groove is provided at a connection position between the light emitting unit and the pixel circuit, and the positive electrode of the light emitting unit is embedded in the first groove for fixation; and / or, A second groove is provided at a connection position between the light emitting unit and the second wiring, and the negative electrode of the light emitting unit is embedded in the second groove for fixation.

3. The display panel according to claim 2, wherein The stacking structure comprises: A first insulating layer, which is disposed on a side of the pixel circuit away from the substrate; The first wiring is arranged on a side of the first insulating layer away from the pixel circuit and connected to an input terminal of the pixel circuit through a first through hole reserved on the first insulating layer, so that an external power supply voltage is connected to the pixel circuit through the first wiring; a second insulating layer, disposed on a side of the first wiring away from the first insulating layer; The second wiring is arranged on a side of the second insulating layer away from the first wiring, and is connected to the negative electrode of the external power supply through a second through hole penetrating the first insulating layer and the second insulating layer, and the second wiring is not in contact with the first wiring; The third wiring is located in the same layer as the second wiring, one end of the third wiring is connected to the positive electrode of the light-emitting unit, and the other end is connected to the output end of the pixel circuit through a third through hole that penetrates the first insulating layer and the second insulating layer.

4. The display panel according to claim 3, wherein A first metal layer, a second metal layer and a third metal layer are arranged at intervals on a side of the pixel circuit facing away from the substrate, and the first metal layer, the second metal layer and the third metal layer are located on the same layer, the first metal layer is connected to the input end of the pixel circuit, the second metal layer is connected to the negative pole of the external power supply, and the third metal layer is connected to the positive end of the light-emitting unit.

5. The display panel according to claim 1, wherein The pixel circuit includes a driving unit, and the first wiring and the second wiring partially extend to directly above the driving unit to shield the driving unit.

6. A method for manufacturing a display panel, characterized in that, include: providing a substrate and a plurality of light-emitting units; A plurality of pixel circuits are manufactured on the substrate, wherein the light emitting units are arranged in a one-to-one correspondence with the pixel circuits; A first routing line and a second routing line are made above the pixel circuit, the first routing line is connected to the positive electrode of the corresponding light-emitting unit via the pixel circuit; the second routing line is connected to the negative electrode of the corresponding light-emitting unit, and a stacked structure is formed by the first routing line and the second routing line to block the light path of the light-emitting unit irradiating the pixel circuit.

7. The manufacturing method of the display panel according to claim 6, wherein, The step of forming a first wiring and a second wiring above the pixel circuit comprises: Applying a first glue layer on the pixel circuit; The first glue layer is exposed and developed to form a first through hole, a second through hole, and a third through hole; wherein, the first through hole penetrates the first glue layer and extends to the input end of the pixel circuit, the second through hole penetrates the first glue layer to form a path connecting the light emitting unit and the negative electrode of the external power supply, and the third through hole penetrates the first glue layer to form a path connecting the output end of the pixel circuit and the positive electrode of the light emitting unit; A first trace is fabricated on the first glue layer such that the first trace covers the first through hole and extends above the driving unit of the pixel circuit; A second glue layer is coated on the basis of the first glue layer and the first trace; The second glue layer is exposed and developed to form a groove for placing the corresponding light emitting unit electrode, and the second through hole penetrates the second glue layer; A second trace is fabricated on the second glue layer such that the second trace extends above the driving unit to cooperate with the first trace to shield the driving unit.

8. The manufacturing method of the display panel according to claim 7, characterized in that The steps of exposing and developing the first glue layer to form the first through hole and the second through hole include: Providing a first mask; wherein, the first mask includes a first light-shielding portion, a second light-shielding portion, and a first semi-transparent portion; the first light-shielding portion is used to shield the area for forming the first through hole, the second light-shielding portion is used to shield the area for forming the second through hole, and the first semi-transparent portion is used to shield the area for forming the groove; After exposure based on the first mask, the first through hole and the second through hole are obtained through development.

9. The manufacturing method of the display panel according to claim 8, wherein The steps of exposing and developing the second glue layer include: Providing a second mask, wherein the second mask includes a third light-shielding portion and a second semi-transparent portion, the third light-shielding portion is used to shield the area for forming the second through hole, and the second semi-transparent portion is used to shield the area for forming the groove; After exposure based on the second mask, the second through hole and the groove are obtained through development.

10. The manufacturing method of the display panel according to claim 7, wherein, The first glue layer and the second glue layer are made of negative photoresist.

Images