Display substrate, preparation method thereof and display device

Abstract

The invention discloses a display substrate, a preparation method thereof and a display device. The display substrate comprises a plurality of circuit units, each circuit unit comprises a pixel driving circuit, the pixel driving circuit at least comprises a driving transistor, a first reset transistor, a data write-in transistor, a light-emitting control transistor, a first capacitor and a second capacitor, a first pole of the first reset transistor is connected with a reference signal line, and a second pole of the second reset transistor is connected with a second capacitor. A second electrode of the first reset transistor is connected with a gate electrode of the driving transistor, a first electrode of the light-emitting control transistor is connected with a first power line, a second electrode of the light-emitting control transistor is connected with a first electrode of the driving transistor, and a second electrode of the driving transistor is connected with a second pole plate of the first capacitor. A first pole of the data writing transistor is connected with a data signal line, and a second pole of the data writing transistor is connected with a fourth pole plate of the second capacitor; the driving transistor is an oxide transistor, and the width-to-length ratio of the driving transistor is 1.25 to 2.67.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technologies, and more particularly to a display substrate, a method for manufacturing the same, and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of self-luminescence, wide viewing angle, high contrast ratio, low power consumption, extremely high response speed, light weight, flexibility, and low cost. With the continuous development of display technologies, flexible display devices that use OLEDs or QLEDs as light-emitting devices and are controlled by Thin Film Transistors (TFTs) have become the mainstream products in the current display field.

[0003] Currently, existing OLED display devices have problems such as a relatively large border width. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of protection of the claims.

[0005] The technical problem to be solved by this disclosure is to provide a display substrate, a method for manufacturing the same, and a display device to solve problems such as a relatively large border width existing in existing display devices.

[0006] On the one hand, the present disclosure provides a display substrate, including a plurality of circuit units, a plurality of data signal lines extending along a second direction, a plurality of first data connection lines extending along a first direction, and a plurality of second data connection lines extending along the second direction. One end of at least one first data connection line is connected to the data signal line, and the other end is connected to the second data connection line. The first direction and the second direction intersect. At least one circuit unit includes a pixel driving circuit, and the pixel driving circuit at least includes a driving transistor, a first reset transistor, a data writing transistor, a light emitting control transistor, a first capacitor, and a second capacitor. The first capacitor includes a first electrode plate and a second electrode plate, and the second capacitor includes a third electrode plate and a fourth electrode plate. The first pole of the first reset transistor is connected to a reference signal line, the second pole of the first reset transistor is connected to the gate electrode of the driving transistor, the first pole of the light emitting control transistor is connected to a first power supply line, the second pole of the light emitting control transistor is connected to the first pole of the driving transistor, the second pole of the driving transistor is connected to the second electrode plate of the first capacitor, the first pole of the data writing transistor is connected to the data signal line, the second pole of the data writing transistor is connected to the fourth electrode plate of the second capacitor, and the first electrode plate of the first capacitor is connected to the third electrode plate of the second capacitor. The driving transistor is an oxide transistor, and the width-to-length ratio of the driving transistor is from 1.25 to 2.67.

[0007] In an exemplary embodiment, the orthographic projection of the data signal line on the substrate does not overlap with the orthographic projections of the channel regions of the driving transistor, the first reset transistor, the data writing transistor, and the light emitting control transistor on the substrate.

[0008] In an exemplary embodiment, in at least one circuit unit, the data signal line includes at least one straight segment and at least one bent segment, and the bent segment is configured to increase the extension length of the data signal line.

[0009] In an exemplary embodiment, at least one second data connection line is disposed between two first power supply lines adjacent in the first direction, or at least one second data connection line is disposed between two data signal lines adjacent in the first direction.

[0010] In an exemplary embodiment, in at least one circuit unit and a circuit unit adjacent in the first direction, the first power supply lines of the two circuit units are an integrally connected structure.

[0011] In an exemplary embodiment, at least one circuit unit further includes a first power supply connection line extending along the first direction, the shape of the first power supply line being a straight line or a broken line extending along the second direction, and the first power supply line being connected to the first power supply connection line to form a mesh structure for transmitting a first power signal.

[0012] In an exemplary embodiment, at least one circuit unit further includes a second power supply line, the width of the second power supply line being greater than the width of the first power supply line, and the width being the dimension in the first direction.

[0013] In an exemplary embodiment, the display substrate further includes a plurality of auxiliary cathodes, the auxiliary cathodes being disposed on a side of the second power supply line away from the substrate, at least one auxiliary cathode having a positive projection on the substrate that at least partially overlaps with a positive projection of the second power supply line on the substrate, and the auxiliary cathodes being connected to the second power supply line through auxiliary vias, and the auxiliary cathodes being configured to be connected to cathodes of light-emitting devices.

[0014] In an exemplary embodiment, a positive projection of the first power supply line on the substrate at least partially overlaps with positive projections of the first reset transistor and the data writing transistor on the substrate, and a positive projection of the second power supply line on the substrate at least partially overlaps with positive projections of the driving transistor and the light-emitting control transistor on the substrate.

[0015] In an exemplary embodiment, at least one circuit unit further includes a data connection electrode, the data connection electrode being connected to the first data connection line, and the second data connection line being connected to the data connection electrode through a via; at least one circuit unit further includes a dummy electrode, the second data connection line being connected to the dummy electrode through a via, and the position and shape of the dummy electrode in one circuit unit being the same as the position and shape of the data connection electrode in another circuit unit.

[0016] In an exemplary embodiment, in a direction perpendicular to the substrate, the display substrate at least includes a first source-drain metal layer and a second source-drain metal layer sequentially disposed along a direction away from the substrate, and the first data connection line is disposed in the first source-drain metal layer; at least one first data connection line is provided with a first break, the first break truncating the first data connection line, and a positive projection of the first break on the substrate at least partially overlaps with a positive projection of the second source-drain metal layer on the substrate.

[0017] In an exemplary embodiment, in a direction perpendicular to the substrate, the display substrate at least includes a first source-drain metal layer and a second source-drain metal layer sequentially arranged along a direction away from the substrate, and the second data connection line is disposed in the second source-drain metal layer; at least one second data connection line is provided with a second break, the second break truncates the second data connection line, and a positive projection of the second break on the substrate at least partially overlaps with a positive projection of the first source-drain metal layer on the substrate.

[0018] In an exemplary embodiment, the pixel driving circuit further includes a second reset transistor, a third reset transistor, and a data control transistor; a first pole of the second reset transistor is connected to a reference signal line, a second pole of the second reset transistor is connected to a first electrode plate of the first capacitor and a third electrode plate of the second capacitor; a first pole of the third reset transistor is connected to an initial signal line, a second pole of the third reset transistor is connected to a second pole of the driving transistor; a first pole of the data control transistor is connected to a gate electrode of the driving transistor, a second pole of the data control transistor is connected to a second pole of the data writing transistor; the first reset transistor, the second reset transistor, the third reset transistor, the data writing transistor, the light-emitting control transistor, and the data control transistor are oxide transistors.

[0019] In an exemplary embodiment, the first reset transistor at least includes a first bottom gate electrode and a first top gate electrode. In at least one circuit unit and a circuit unit adjacent to the first direction, the first bottom gate electrodes in the two circuit units are an integrally connected structure, and the first top gate electrodes in the two circuit units are an integrally connected structure; and / or, the data writing transistor at least includes a fourth bottom gate electrode and a fourth top gate electrode. In at least one circuit unit and a circuit unit adjacent to the first direction, the fourth bottom gate electrodes in the two circuit units are an integrally connected structure, and the fourth top gate electrodes in the two circuit units are an integrally connected structure; and / or, the data control transistor at least includes a sixth bottom gate electrode and a sixth top gate electrode. In at least one circuit unit and a circuit unit adjacent to the first direction, the sixth bottom gate electrodes in the two circuit units are an integrally connected structure, and the sixth top gate electrodes in the two circuit units are an integrally connected structure.

[0020] In an exemplary embodiment, a first bottom gate connection block is provided on the first bottom gate electrode, and a first top gate connection block is provided on the first top gate electrode. The first bottom gate connection block is configured to be connected to a first scan signal line through a first bottom gate connection via hole, and the first top gate connection block is configured to be connected to the first scan signal line through a first top gate connection via hole. Among at least one circuit unit and a circuit unit adjacent thereto in the first direction, two circuit units share the first bottom gate connection via hole and the first top gate connection via hole; and / or, a fourth bottom gate connection block is provided on the fourth bottom gate electrode, and a fourth top gate connection block is provided on the fourth top gate electrode. The fourth bottom gate connection block is configured to be connected to a third scan signal line through a fourth bottom gate connection via hole, and the fourth top gate connection block is configured to be connected to the third scan signal line through a fourth top gate connection via hole. Among at least one circuit unit and a circuit unit adjacent thereto in the first direction, two circuit units share the fourth bottom gate connection via hole and the fourth top gate connection via hole; and / or, a sixth bottom gate connection block is provided on the sixth bottom gate electrode, and a sixth top gate connection block is provided on the sixth top gate electrode. The sixth bottom gate connection block is configured to be connected to a fourth scan signal line through a sixth bottom gate connection via hole, and the sixth top gate connection block is configured to be connected to the fourth scan signal line through a sixth top gate connection via hole. Among at least one circuit unit and a circuit unit adjacent thereto in the first direction, two circuit units share the sixth bottom gate connection via hole and the sixth top gate connection via hole.

[0021] In an exemplary embodiment, the second reset transistor includes at least a second bottom gate electrode and a second top gate electrode. In at least one circuit unit, the first bottom gate electrode and the second bottom gate electrode are integrally connected to each other, and the first top gate electrode and the second top gate electrode are integrally connected to each other.

[0022] In an exemplary embodiment, the first reset transistor includes at least a first active layer. Among at least one circuit unit and a circuit unit adjacent thereto in the first direction, the first active layers in two circuit units are integrally connected to each other.

[0023] In an exemplary embodiment, the reference signal line is connected to a first region of the first active layer through a first active via hole. Among at least one circuit unit and a circuit unit adjacent thereto in the first direction, two circuit units share the first active via hole.

[0024] In an exemplary embodiment, the third reset transistor includes at least a seventh active layer. Among at least one circuit unit and a circuit unit adjacent thereto in the first direction, the seventh active layers in two circuit units are integrally connected to each other.

[0025] In an exemplary embodiment, the initial signal line is connected to a first region of the seventh active layer through a seventh active via. Among at least one circuit unit and the circuit units adjacent to it in the first direction, two circuit units share the seventh active via.

[0026] On the other hand, the present disclosure also provides a display device, including the aforementioned display substrate.

[0027] In yet another aspect, the present disclosure also provides a method for manufacturing a display substrate. The display substrate includes a plurality of circuit units, a plurality of data signal lines extending along a second direction, a plurality of first data connection lines extending along a first direction, and a plurality of second data connection lines extending along the second direction. One end of at least one first data connection line is connected to the data signal line, and the other end is connected to the second data connection line. The first direction and the second direction intersect. The manufacturing method includes:

[0028] Forming a pixel driving circuit in at least one circuit unit. The pixel driving circuit at least includes a driving transistor, a first reset transistor, a data writing transistor, a light emitting control transistor, a first capacitor, and a second capacitor. The first capacitor includes a first electrode plate and a second electrode plate, and the second capacitor includes a third electrode plate and a fourth electrode plate. The first pole of the first reset transistor is connected to a reference signal line, the second pole of the first reset transistor is connected to the gate electrode of the driving transistor, the first pole of the light emitting control transistor is connected to a first power supply line, the second pole of the light emitting control transistor is connected to the first pole of the driving transistor, the second pole of the driving transistor is connected to the second electrode plate of the first capacitor, the first pole of the data writing transistor is connected to the data signal line, the second pole of the data writing transistor is connected to the fourth electrode plate of the second capacitor, and the first electrode plate of the first capacitor is connected to the third electrode plate of the second capacitor. The driving transistor is an oxide transistor, and the aspect ratio of the driving transistor is from 1.25 to 2.67.

[0029] The present disclosure provides a display substrate, a method for manufacturing the same, and a display device. By combining the oxide pixel driving circuit technology and the technology of data connection lines located in the display area, the display substrate has the advantages of both a narrow border and a new circuit architecture.

[0030] Other aspects will be apparent after reading and understanding the drawings and the detailed description. Description of the Drawings

[0031] The drawings are used to provide an understanding of the technical solutions of the present disclosure, and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure, and do not constitute a limitation to the technical solutions of the present disclosure.

[0032] Figure 1Schematic structural diagram of a display device;

[0033] Figure 2 Schematic structural diagram of a display substrate;

[0034] Figure 3A Schematic plan view of a display area in a display substrate;

[0035] Figure 3B Schematic plan view of a display area in another display substrate;

[0036] Figure 4 Schematic cross-sectional view of a display area in a display substrate;

[0037] Figure 5 Equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0038] Figure 6 is Figure 5 A driving timing diagram of the pixel driving circuit shown;

[0039] Figure 7A Schematic plan view of a display substrate according to an exemplary embodiment of the present disclosure;

[0040] Figure 7B Schematic structural diagram of a data connection line according to an exemplary embodiment of the present disclosure;

[0041] Figure 8 Schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0042] Figure 9 Schematic diagram after forming the first conductive layer pattern according to an embodiment of the present disclosure;

[0043] Figure 10A and Figure 10B Schematic diagram after forming the second conductive layer pattern according to an embodiment of the present disclosure;

[0044] Figure 11A and Figure 11B Schematic diagram after forming the semiconductor layer pattern according to an embodiment of the present disclosure;

[0045] Figure 12A and Figure 12B Schematic diagram after forming the third conductive layer pattern according to an embodiment of the present disclosure;

[0046] Figure 12C is Figure 12A An enlarged view of the third transistor in;

[0047] Figure 13 Schematic diagram after forming the fourth insulating layer pattern according to an embodiment of the present disclosure;

[0048] Figure 14A and Figure 14B is a schematic diagram after forming a fourth conductive layer pattern in an embodiment of the present disclosure;

[0049] Figure 15 is a schematic diagram after forming a first planarization layer pattern in an embodiment of the present disclosure;

[0050] Figure 16A and Figure 16B is a schematic diagram after forming a fifth conductive layer pattern in an embodiment of the present disclosure;

[0051] Figure 17 is a schematic diagram of the structure of another display substrate in an exemplary embodiment of the present disclosure;

[0052] Figure 18 is a schematic diagram of the structure of yet another display substrate in an exemplary embodiment of the present disclosure;

[0053] Figure 19 is a schematic diagram of the structure of yet another display substrate in an exemplary embodiment of the present disclosure;

[0054] Figure 20A and Figure 20B is Figure 19 a schematic diagram after forming a fourth conductive layer pattern in the illustrated embodiment;

[0055] Figure 21A and Figure 21B is Figure 19 a schematic diagram after forming a fifth conductive layer pattern in the illustrated embodiment;

[0056] Figure 22 is a schematic diagram of the structure of yet another display substrate in an exemplary embodiment of the present disclosure;

[0057] Figure 23 is Figure 22 a schematic diagram after forming a first conductive layer pattern in the illustrated embodiment;

[0058] Figure 24 is Figure 22 a schematic diagram after forming a second conductive layer pattern in the illustrated embodiment;

[0059] Figure 25 is Figure 22 a schematic diagram after forming a semiconductor layer pattern in the illustrated embodiment;

[0060] Figure 26 is Figure 22 a schematic diagram after forming a third conductive layer pattern in the illustrated embodiment;

[0061] Figure 27 is Figure 22 a schematic diagram after forming a fourth insulating layer pattern in the illustrated embodiment;

[0062] Figure 28 Schematic diagram after forming the fourth conductive layer pattern in the illustrated embodiment; Figure 22 Schematic diagram after forming the fourth conductive layer pattern in the illustrated embodiment;

[0063] Figure 29 Schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0064] Figure 30 Schematic diagram after forming the first conductive layer pattern in the illustrated embodiment; Figure 29 Schematic diagram after forming the first conductive layer pattern in the illustrated embodiment;

[0065] Figure 31 Schematic diagram after forming the second conductive layer pattern in the illustrated embodiment; Figure 29 Schematic diagram after forming the second conductive layer pattern in the illustrated embodiment;

[0066] Figure 32 Schematic diagram after forming the semiconductor layer pattern in the illustrated embodiment; Figure 29 Schematic diagram after forming the semiconductor layer pattern in the illustrated embodiment;

[0067] Figure 33 Schematic diagram after forming the third conductive layer pattern in the illustrated embodiment; Figure 29 Schematic diagram after forming the third conductive layer pattern in the illustrated embodiment;

[0068] Figure 34 Schematic diagram after forming the fourth conductive layer pattern in the illustrated embodiment; Figure 29 Schematic diagram after forming the fourth conductive layer pattern in the illustrated embodiment.

[0069] Explanation of reference numerals:

[0070] 11 - First electrode plate; 12 - Second electrode plate; 13 - Third electrode plate;

[0071] 14 - Fourth electrode plate; 15 - Electrode plate connection block; 21 - First bottom gate electrode;

[0072] 22 - Second bottom gate electrode; 24 - Fourth bottom gate electrode; 26 - Sixth bottom gate electrode;

[0073] 27 - First shielding line; 28 - Second shielding line; 31 - First active layer;

[0074] 32 - Second active layer; 33 - Third active layer; 34 - Fourth active layer;

[0075] 35 - Fifth active layer; 36 - Sixth active layer; 37 - Seventh active layer;

[0076] 41 - First top gate electrode; 42 - Second top gate electrode; 43 - Third top gate electrode;

[0077] 44 - Fourth top gate electrode; 46 - Sixth top gate electrode; 51 - First connection electrode;

[0078] 52—the second connection electrode; 53—the third connection electrode; 54—the fourth connection electrode;

[0079] 55—the fifth connection electrode; 61—the first scan signal line; 62—the second scan signal line;

[0080] 63—the third scan signal line; 64—the fourth scan signal line; 65—the light-emitting signal line;

[0081] 66—the reference signal line; 67—the initial signal line; 68—the first power connection line;

[0082] 71—the first power line; 72—the second power line; 73—the data signal line;

[0083] 74—the anode connection electrode; 81—the first data connection line; 82—the second data connection line;

[0084] 83—the data connection block; 84—the data connection electrode; 85—the dummy electrode;

[0085] 90—the auxiliary cathode; 101—the substrate; 102—the driving circuit layer;

[0086] 103—the light-emitting structure layer; 104—the encapsulation structure layer. Detailed implementation manners

[0087] To make the objectives, technical solutions and advantages of the present disclosure clearer and more understandable, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that the implementation manners can be implemented in multiple different forms. Those of ordinary skill in the art can easily understand the fact that the manners and contents can be transformed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited only to the contents described in the following implementation manners. Without conflict, the embodiments and features in the embodiments of the present disclosure can be combined arbitrarily with each other.

[0088] The drawing ratios in the present disclosure can be used as a reference in actual processes, but are not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in the present disclosure are only schematic diagrams, and one implementation manner of the present disclosure is not limited to the shapes or values shown in the drawings.

[0089] The ordinal numbers such as "first", "second", and "third" in this specification are set to avoid confusion of components, rather than to limit in terms of quantity.

[0090] In this specification, for convenience, terms indicating orientation or positional relationships such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationships of the constituent elements with reference to the accompanying drawings. This is only for the convenience of describing this specification and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present disclosure. The positional relationships of the constituent elements are appropriately changed according to the directions describing the constituent elements. Therefore, it is not limited to the terms described in the specification and can be appropriately replaced according to the circumstances.

[0091] In this specification, unless otherwise clearly specified and limited, the terms "mounted", "connected", and "coupled" shall be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be a direct connection, an indirect connection through an intermediate member, or the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0092] In this specification, a transistor refers to an element that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region where current mainly flows.

[0093] In this specification, the first pole can be the drain electrode and the second pole can be the source electrode, or the first pole can be the source electrode and the second pole can be the drain electrode. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, etc., the functions of the "source electrode" and "drain electrode" sometimes swap with each other. Therefore, in this specification, the "source electrode" and "drain electrode" can swap with each other, and the "source terminal" and "drain terminal" can swap with each other.

[0094] In this specification, "electrically connected" includes the case where the constituent elements are connected together through an element having a certain electrical effect. There is no particular limitation on the "element having a certain electrical effect" as long as it can transfer electrical signals between the constituent elements that can be connected. Examples of the "element having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0095] In this specification, "parallel" means a state where the angle formed by two straight lines is more than -10° and less than 10°, and thus also includes a state where the angle is more than -5° and less than 5°. Additionally, "perpendicular" means a state where the angle formed by two straight lines is more than 80° and less than 100°, and thus also includes an angle state of more than 85° and less than 95°.

[0096] In this specification, "film" and "layer" can be interchanged with each other. For example, sometimes "conductive layer" can be changed to "conductive film". Similarly, sometimes "insulating film" can be changed to "insulating layer".

[0097] Triangles, rectangles, trapezoids, pentagons, hexagons, etc. in this specification are not in a strict sense and can be approximate triangles, rectangles, trapezoids, pentagons, hexagons, etc. There can be some small deformations caused by tolerances, chamfers, arc edges, and deformations, etc. "About" in this disclosure means not strictly limiting the boundary and allowing values within the process and measurement error ranges.

[0098] Figure 1 It is a schematic structural diagram of a display device. As Figure 1As shown, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is respectively connected to the data driver, the scan driver, and the light-emitting driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn). The scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm). The light-emitting driver is respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may at least include a pixel driving circuit. The pixel driving circuit is respectively connected to the scan signal line, the light-emitting signal line, and the data signal line. The light-emitting unit may include a light-emitting device, and the light-emitting device is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide a gray value and a control signal suitable for the specification of the data driver to the data driver, may provide a clock signal, a scan start signal, etc. suitable for the specification of the scan driver to the scan driver, and may provide a clock signal, an emission stop signal, etc. suitable for the specification of the light-emitting driver to the light-emitting driver. The data driver may use the gray value and the control signal received from the timing controller to generate data voltages to be provided to the data signal lines D1, D2, D3, ……, and Dn. For example, the data driver may sample the gray value using a clock signal and apply data voltages corresponding to the gray value to the data signal lines D1 to Dn in pixel row units, where n may be a natural number. The scan driver may generate scan signals to be provided to the scan signal lines S1, S2, S3, ……, and Sm by receiving a clock signal, a scan start signal, etc. from the timing controller. For example, the scan driver may sequentially provide scan signals having conductive level pulses to the scan signal lines S1 to Sm. For example, the scan driver may be configured in the form of a shift register and may generate scan signals in a manner of sequentially transmitting a scan start signal provided in the form of a conductive level pulse to the next-stage circuit under the control of a clock signal, where m may be a natural number. The light-emitting driver may generate emission signals to be provided to the light-emitting signal lines E1, E2, E3, ……, and Eo by receiving a clock signal, an emission stop signal, etc. from the timing controller. For example, the light-emitting driver may sequentially provide emission signals having cut-off level pulses to the light-emitting signal lines E1 to Eo. For example, the light-emitting driver may be configured in the form of a shift register and may generate emission signals in a manner of sequentially transmitting an emission stop signal provided in the form of a cut-off level pulse to the next-stage circuit under the control of a clock signal, where o may be a natural number. In an exemplary embodiment, the pixel array may be disposed on a display substrate.

[0099] Figure 2 is a schematic structural diagram of a display substrate. As Figure 2As shown, the display substrate may include a display area 100, a bonding area 200 located on one side of the display area 100, and a border area 300 located on other sides of the display area 100. In an exemplary embodiment, the display area 100 may be a flat area including a plurality of sub-pixels Pxij that make up a pixel array. The plurality of sub-pixels Pxij are configured to display a dynamic picture or a still image, and the display area 100 may be referred to as an active area (AA for short). In an exemplary embodiment, the display substrate may adopt a flexible substrate, so the display substrate may be deformable, such as being curled, bent, folded, or rolled up.

[0100] In an exemplary embodiment, the bonding area 200 may include a lead-out line area 201, a bending area 202, a driving chip area, and a bonding pin area that are sequentially arranged along the direction away from the display area. The lead-out line area 201 is connected to the display area 100 and includes at least data lead-out lines. The bending area 202 is connected to the lead-out line area 201 and may at least include a composite insulating layer provided with grooves, and the grooves are configured to bend the bonding area to the back of the display area. The driving chip area may include an integrated circuit (IC for short), and the integrated circuit is configured to be connected to a plurality of data lead-out lines. The bonding pin area may include bonding pads, and the bonding pads are configured to be bonded and connected to an external flexible printed circuit (FPC for short).

[0101] In an exemplary embodiment, the border area 300 may include a circuit area, a power supply line area, a crack dam area, and a cutting area that are sequentially arranged along the direction away from the display area 100. The circuit area is connected to the display area 100 and may at least include a gate driving circuit, and the gate driving circuit is connected to scan signal lines and light-emitting signal lines in the display area 100. The power supply line area is connected to the circuit area and may at least include border power supply leads, and the border power supply leads extend along a direction parallel to the edge of the display area and are connected to cathodes in the display area 100. The crack dam area is connected to the power supply line area and may at least include a plurality of cracks provided on the composite insulating layer. The cutting area is connected to the crack dam area and may at least include cutting grooves provided on the composite insulating layer, and the cutting grooves are configured to be cut by a cutting device along the cutting grooves respectively after all the film layers of the display substrate are prepared.

[0102] In an exemplary embodiment, isolation dams may be provided in the lead-out line area in the bonding area 200 and the power supply line area in the border area 300. The isolation dams may extend along a direction parallel to the edge of the display area to form an annular structure surrounding the display area 100, and the edge of the display area is the edge of the display area bonding area or one side of the border area.

[0103] Figure 3A It is a schematic plan view of a display area in a display substrate. As Figure 3A shown, the display area may include a plurality of pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may at least include a pixel driving circuit. The pixel driving circuit is respectively connected to a scanning signal line, a light-emitting signal line, and a data signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scanning signal line and the light-emitting signal line, and output a corresponding current to the light-emitting unit. The light-emitting unit may include a light-emitting device. The light-emitting device is connected to the pixel driving circuit of the sub-pixel where it is located. The light-emitting device is configured to emit light with a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel where it is located.

[0104] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) that emits red light, the second sub-pixel P2 and the fourth sub-pixel P4 may be green sub-pixels (G) that emit green light, and the third sub-pixel P3 may be a blue sub-pixel (B) that emits blue light. In an exemplary embodiment, the shape of the sub-pixel may be rectangular, rhombic, pentagonal, or hexagonal, and the four sub-pixels may be arranged in an RGBG manner.

[0105] Figure 3B It is another schematic plan view of a display area in a display substrate. As Figure 3B shown, the pixel unit P may include three sub-pixels. The first sub-pixel P1 may be a red sub-pixel that emits red light, the second sub-pixel P2 may be a blue sub-pixel that emits blue light, and the third sub-pixel P3 may be a green sub-pixel that emits green light. The three sub-pixels may be arranged in a Real RGB manner.

[0106] In other exemplary embodiments, the three sub-pixels or the four sub-pixels may be arranged in a horizontally juxtaposed or vertically juxtaposed manner, etc., and the present disclosure does not limit this here.

[0107] Figure 4 It is a schematic cross-sectional view of a display area in a display substrate, showing the structures of four sub-pixels in the display area. As Figure 4 shown, in a plane perpendicular to the display substrate, the display area may include a driving circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101, and a packaging structure layer 104 disposed on a side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementation manners, the display area may include other film layers, such as a touch control structure layer, etc., and the present disclosure does not limit this here.

[0108] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 may include a plurality of circuit units, and each circuit unit may at least include a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 may include a plurality of light-emitting units, and each light-emitting unit may include a light-emitting device. The light-emitting device may at least include an anode, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of a corresponding color under the drive of the anode and the cathode. The encapsulation structure layer 104 may include a stacked first encapsulation layer, second encapsulation layer, and third encapsulation layer. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external moisture cannot enter the light-emitting structure layer 103.

[0109] With the development of OLED display technology, consumers have higher and higher requirements for the display effect of display products. An extremely narrow bezel has become a new trend in the development of display products. Therefore, the narrowing of the bezel or even the borderless design has received increasing attention in the design of OLED display products. In a display substrate, since the signal lines of the integrated circuit and the bonding pads in the bonding area need to be introduced into a wider display area in a fanout manner through data lead-out lines, the lead-out line area occupies a large space, resulting in a relatively large width of the lower bezel. In addition, as the size of the display substrate increases, the yield of the display substrate using low-temperature poly-silicon (LTPS) thin-film transistors decreases, resulting in a relatively high cost.

[0110] The exemplary embodiments of the present disclosure provide a display substrate. In an exemplary embodiment, the display substrate may include a plurality of circuit units, a plurality of data signal lines extending along a second direction, a plurality of first data connection lines extending along a first direction, and a plurality of second data connection lines extending along the second direction. One end of at least one first data connection line is connected to the data signal line, and the other end is connected to the second data connection line. The first direction and the second direction intersect; at least one circuit unit includes a pixel driving circuit, and the pixel driving circuit at least includes a driving transistor, a first reset transistor, a data writing transistor, a light emitting control transistor, a first capacitor, and a second capacitor. The first capacitor includes a first electrode plate and a second electrode plate, and the second capacitor includes a third electrode plate and a fourth electrode plate; the first pole of the first reset transistor is connected to a reference signal line, the second pole of the first reset transistor is connected to the gate electrode of the driving transistor, the first pole of the light emitting control transistor is connected to a first power supply line, the second pole of the light emitting control transistor is connected to the first pole of the driving transistor, the second pole of the driving transistor is connected to the second electrode plate of the first capacitor, the first pole of the data writing transistor is connected to the data signal line, the second pole of the data writing transistor is connected to the fourth electrode plate of the second capacitor, and the first electrode plate of the first capacitor is connected to the third electrode plate of the second capacitor; the driving transistor is an oxide transistor, and the aspect ratio of the driving transistor is from 1.25 to 2.67.

[0111] In an exemplary embodiment, the orthographic projection of the data signal line on the substrate does not overlap with the orthographic projections of the channel regions of the driving transistor, the first reset transistor, the data writing transistor, and the light emitting control transistor on the substrate.

[0112] In an exemplary embodiment, in at least one circuit unit, the data signal line includes at least one straight segment and at least one bent segment, and the bent segment is configured to increase the extension length of the data signal line.

[0113] In an exemplary embodiment, at least one second data connection line is disposed between two first power supply lines adjacent in the first direction, or at least one second data connection line is disposed between two data signal lines adjacent in the first direction.

[0114] In an exemplary embodiment, in at least one circuit unit and the circuit unit adjacent in the first direction, the first power supply lines of the two circuit units are an integrally connected structure.

[0115] In an exemplary embodiment, at least one circuit unit further includes a first power supply connection line extending along the first direction. The shape of the first power supply line is a straight line or a broken line extending along the second direction. The first power supply line is connected to the first power supply connection line to form a mesh structure for transmitting a first power signal.

[0116] In an exemplary embodiment, at least one circuit unit further includes a second power supply line, and the width of the second power supply line is greater than the width of the first power supply line, where the width is the dimension in the first direction.

[0117] In an exemplary embodiment, the display substrate further includes a plurality of auxiliary cathodes. The auxiliary cathodes are disposed on a side of the second power supply line away from the substrate. At least one auxiliary cathode at least partially overlaps with the second power supply line in the positive projection on the substrate. The auxiliary cathodes are connected to the second power supply line through auxiliary vias, and the auxiliary cathodes are configured to be connected to the cathodes of the light-emitting devices.

[0118] In an exemplary embodiment, the positive projection of the first power supply line on the substrate at least partially overlaps with the positive projections of the first reset transistor and the data writing transistor on the substrate. The positive projection of the second power supply line on the substrate at least partially overlaps with the positive projections of the driving transistor and the light-emitting control transistor on the substrate.

[0119] The display substrate of this embodiment is illustrated by some examples below.

[0120] Figure 5 It is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure. As Figure 5 shown, in an exemplary embodiment, the pixel driving circuit of the exemplary embodiment of the present disclosure adopts a 7T2C structure. The pixel driving circuit may include seven transistors (a first transistor T1 to a seventh transistor T7) and two capacitors C. The pixel driving circuit is respectively connected to nine signal lines (a first scan signal line S1, a second scan signal line S2, a third scan signal line S3, a fourth scan signal line S4, a light-emitting signal line EM, a reference signal line REF, an initial signal line INIT, a data signal line DATA, and a first power supply line VDD).

[0121] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. Among them, the first node N1 is respectively connected to the second pole of the first transistor T1, the first pole of the sixth transistor T6, and the gate electrode of the third transistor T3; the second node N2 is respectively connected to the second pole of the fourth transistor T4, the second pole of the sixth transistor T6, and the second end of the second capacitor C2; the third node N3 is respectively connected to the second pole of the third transistor T3, the second pole of the seventh transistor T7, and the second end of the first capacitor C1; the fourth node N4 is respectively connected to the second pole of the second transistor T2, the first end of the first capacitor C1, and the first end of the second capacitor C2.

[0122] In an exemplary embodiment, the first transistor T1 may be referred to as a first reset transistor. The gate electrode of the first transistor T1 is connected to the first scan signal line S1, the first pole of the first transistor T1 is connected to the reference signal line REF, and the second pole of the first transistor T1 is connected to the first node N1.

[0123] In an exemplary embodiment, the second transistor T2 may be referred to as a second reset transistor. The gate electrode of the second transistor T2 is connected to the first scan signal line S1, the first pole of the second transistor T2 is connected to the reference signal line REF, and the second pole of the second transistor T2 is connected to the fourth node N4.

[0124] In an exemplary embodiment, the third transistor T3 may be referred to as a driving transistor. The gate electrode of the third transistor T3 is connected to the first node N1, the first pole of the third transistor T3 is connected to the second pole of the fifth transistor T5, and the second pole of the third transistor T3 is connected to the third node N3.

[0125] In an exemplary embodiment, the fourth transistor T4 may be referred to as a data writing transistor. The gate electrode of the fourth transistor T4 is connected to the third scan signal line S3, the first pole of the fourth transistor T4 is connected to the data signal line DATA, and the second pole of the fourth transistor T4 is connected to the second node N2.

[0126] In an exemplary embodiment, the fifth transistor T5 may be referred to as a light emission control transistor. The gate electrode of the fifth transistor T5 is connected to the light emission signal line EM, the first pole of the fifth transistor T5 is connected to the first power supply line VDD, and the second pole of the fifth transistor T5 is connected to the first pole of the third transistor T3.

[0127] In an exemplary embodiment, the sixth transistor T6 may be referred to as a data control transistor. The gate electrode of the sixth transistor T6 is connected to the fourth scan signal line S4, the first pole of the sixth transistor T6 is connected to the first node N1, and the second pole of the sixth transistor T6 is connected to the second node N2.

[0128] In an exemplary embodiment, the seventh transistor T7 may be referred to as a third reset transistor. The gate electrode of the seventh transistor T7 is connected to the second scan signal line S2, the first pole of the seventh transistor T7 is connected to the initial signal line INIT, and the second pole of the seventh transistor T7 is connected to the third node N3.

[0129] In an exemplary embodiment, the first pole of the light-emitting device EL is connected to the third node N3, and the second pole of the light-emitting device EL is connected to the second power supply line VSS. The light-emitting device EL may be an OLED, including a stacked first pole (anode), an organic light-emitting layer, and a second pole (cathode), or may be a QLED, including a stacked first pole (anode), a quantum dot light-emitting layer, and a second pole (cathode).

[0130] In an exemplary embodiment, the seven transistors of the pixel driving circuit may be N-type transistors. Using transistors of the same type in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield of the product.

[0131] In an exemplary embodiment, the seven transistors of the pixel driving circuit may all use oxide transistors. The active layer of the oxide transistor may use an oxide semiconductor (Oxide). Oxide transistors have advantages such as high electron mobility, low operating voltage, and low leakage characteristics. By using a display substrate provided with oxide transistors, low-frequency driving can be achieved, power consumption can be reduced, and display quality can be improved.

[0132] In an exemplary embodiment, the first power supply line VDD may be configured to provide a constant first voltage signal to the pixel driving circuit, the second power supply line VSS may be configured to provide a constant second voltage signal to the light-emitting device, and the first voltage signal is a high-level signal, and the second voltage signal is a low-level signal. The reference signal line REF and the initial voltage signal may be constant voltage signals, which are not limited in the present disclosure.

[0133] Figure 6 For Figure 5 a driving timing diagram of the pixel driving circuit shown. As Figure 6 shown, in an exemplary embodiment, the working process of the pixel driving circuit may include:

[0134] A first stage A1, called an initialization stage. The signals of the first scan signal line S1 and the second scan signal line S2 are high-level signals, and the signals of the third scan signal line S3, the fourth scan signal line S4, and the light-emitting signal line EM are low-level signals, so that the first transistor T1, the second transistor T2, and the seventh transistor T7 are turned on, and other switching transistors are turned off.

[0135] When the first transistor T1 is turned on, the reference signal provided by the reference signal line REF is supplied to the first node N1 to initialize the first node N1 (reset the gate electrode of the third transistor T3), and the potential of the first node N1 is Vref. When the second transistor T2 is turned on, the reference signal provided by the reference signal line REF is supplied to the fourth node N4 to initialize the fourth node N4 (reset the first ends of the first capacitor C1 and the second capacitor C2), and the potential of the fourth node N4 is Vref. When the seventh transistor T7 is turned on, the initial signal provided by the initial signal line INIT is supplied to the third node N3 to initialize the third node N3 (reset the second pole of the third transistor T3 and the second end of the second capacitor C2), and the potential of the third node N3 is Vinit. At the same time, the third transistor T3 can be turned on by the voltage difference between Vinit and Vref.

[0136] In an exemplary embodiment, Vref is the voltage of the reference signal, which can be about 2.5V, and Vinit is the voltage of the initial signal, which can be about 1.5V.

[0137] In an exemplary embodiment, the reset of the first node N1, the third node N3, and the fourth node N4 can be performed in stages or simultaneously, and the present disclosure does not limit this here.

[0138] The second stage A2 is called the compensation stage. The signals of the first scan signal line S1 and the emission signal line EM are high-level signals, and the signals of the second scan signal line S2, the third scan signal line S3, and the fourth scan signal line S4 are low-level signals, so that the first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, and other switching transistors are turned off.

[0139] When the first transistor T1 and the second transistor T2 are turned on, the potentials of the first node N1 and the fourth node N4 remain Vref. Since the third transistor T3 is turned on, when the fifth transistor T5 is turned on, the first power signal output by the first power supply line VDD is written into the third node N3 through the turned-on third transistor T3, and the potential of the third node N3 gradually increases.

[0140] In an exemplary embodiment, the voltage of the first power signal output by the first power supply line VDD can be about 11.5V.

[0141] The third stage A3 is called the data writing stage. The signal of the emission signal line EM is a continuous high-level signal, the signals of the second scan signal line S2 and the fourth scan signal line S4 are continuous low-level signals, the signals of the first scan signal line S1 and the third scan signal line S3 are high-level signals for a period of time and then become low-level signals, so that the fifth transistor T5 remains turned on, and the first transistor T1, the second transistor T2, and the fourth transistor T4 are turned on for a period of time and then turned off.

[0142] The conduction of the fourth transistor T4 causes the data signal output from the data signal line DATA to be written into the second node N2, that is, stored in the second capacitor C2. The continuous conduction of the fifth transistor T5 causes the potential of the third node N3 to gradually increase until the potential increases to Vref - Vth, at which time the gate-source voltage difference Vgs of the third transistor T3 is equal to Vth, and the third transistor T3 is turned off. Thus, the threshold voltage Vth of the third transistor T3 is written into the third node N3, that is, stored in the first capacitor C1. In this way, the threshold voltage Vth starts to be written in the second stage (compensation stage) A2, and the writing of the threshold voltage is completed in the third stage (data writing stage) A3. The writing of the threshold voltage continues from the second stage A2 to the third stage A3. After the threshold voltage Vth is written into the third node N3, the first transistor T1 and the second transistor T2 change from conduction to cutoff.

[0143] The fourth stage A4 is called the light-emitting stage. The signals of the fourth scan signal line S4 and the light-emitting signal line EM are high-level signals, and the signals of the first scan signal line S1, the second scan signal line S2, and the third scan signal line S3 are low-level signals, causing the fifth transistor T5 and the sixth transistor T6 to conduct.

[0144] The conduction of the sixth transistor T6 connects the first node N1 and the second node N2, and the data voltage stored in the second node N2 is written into the first node N1. The potential of the first node N1 (the potential of the gate electrode of the third transistor T3) Vg = Vd + Vld + VSS - (Vref - Vth); the potential of the third node N3 (the potential of the second pole of the third transistor T3) Vs = Vld + VSS; then the gate-source voltage difference Vgs of the third transistor T3 is Vgs = Vdata - Vref + Vth. Vld is the voltage of the light-emitting device EL, VSS is the voltage of the second power supply signal, and Vd is the voltage of the data signal. The conduction of the fifth transistor T5 causes the first power supply signal output from the first power supply line VDD to provide a driving voltage to the first pole of the light-emitting element EL through the conducting third transistor T3, driving the light-emitting element EL to emit light.

[0145] The output current I of the third transistor T3 satisfies the following formula:

[0146] I = (μWCox / 2L)(Vgs - Vth) 2 = (μWCox / 2L)(Vdata - Vref) 2 .

[0147] Where, μ is the carrier mobility; Cox is the gate electrode capacitance per unit area, W is the channel width of the third transistor T3, and L is the channel length of the third transistor T3.

[0148] It can be seen from the formula for the output current of the third transistor T3 described above that the output current of the pixel driving circuit is independent of the threshold voltage Vth of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the output current. The output current can be controlled by controlling the data voltage Vd to control the brightness of the light-emitting device EL.

[0149] In the pixel driving circuit and its driving method provided by the exemplary embodiment of the present disclosure, the data signal is stored in the second capacitor during the writing stage instead of being directly written to the gate electrode of the third transistor T3. The threshold voltage of the third transistor T3 is stored in the first capacitor during the compensation stage, so that the data signal and the threshold voltage of the third transistor T3 are stored independently, and the stored data signal and the stored threshold voltage do not interfere with each other. During the light-emitting stage, the data signal is written to the gate electrode of the third transistor T3 by using the second capacitor, which can not only ensure the stability of the voltage difference between the data signal and the second pole of the driving transistor T3, but also prevent the actual brightness of the light-emitting device from differing from the designed brightness due to different interference degrees of different data signals, thereby improving the picture quality.

[0150] Figure 7A It is a schematic plan view of a display substrate according to an exemplary embodiment of the present disclosure. In a plane perpendicular to the display substrate, the display substrate may include a driving structure layer provided on a substrate, a light-emitting structure layer provided on a side of the driving structure layer away from the substrate, and a packaging structure layer provided on a side of the light-emitting structure layer away from the substrate. As Figure 7A shown, in a plane parallel to the display substrate, the display substrate may at least include a display area 100, a bonding area 200 located on a second direction Y side of the display area 100, and a border area 300 located on other sides of the display area 100. In an exemplary embodiment, the driving structure layer of the display area 100 may include a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, a plurality of data signal lines 73, a plurality of first data connection lines 81, and a plurality of second data connection lines 82. At least one circuit unit may include a pixel driving circuit configured to output a corresponding current to a connected light-emitting device. The light-emitting structure layer of the display area 100 may include a plurality of light-emitting units, and at least one light-emitting unit may include a light-emitting device connected to the pixel driving circuit of the corresponding circuit unit, and the light-emitting device is configured to emit light with a corresponding brightness in response to the current output by the connected pixel driving circuit.

[0151] In an exemplary embodiment, the circuit unit referred to in the present disclosure refers to the area divided according to the pixel driving circuit, and the light-emitting unit referred to in the present disclosure refers to the area divided according to the light-emitting device. In an exemplary embodiment, the position of the light-emitting unit projected orthogonally onto the substrate may correspond to the position of the circuit unit projected orthogonally onto the substrate, or the position of the light-emitting unit projected orthogonally onto the substrate may not correspond to the position of the circuit unit projected orthogonally onto the substrate.

[0152] In an exemplary embodiment, a plurality of circuit units arranged in sequence along the first direction X may be referred to as a unit row, and a plurality of circuit units arranged in sequence along the second direction Y may be referred to as a unit column. A plurality of unit rows and a plurality of unit columns form an array-arranged circuit unit array, and the first direction X intersects with the second direction Y.

[0153] In an exemplary embodiment, the shape of the first data connection line 81 may be a straight line or a broken line extending along the first direction X, and the shape of the data signal line 73 and the second data connection line 82 may be a straight line or a broken line extending along the second direction Y. At least one data signal line 73 is connected to a plurality of pixel driving circuits in a unit column, and the data signal line 73 is configured to provide a data signal to the connected pixel driving circuits. One end of at least one first data connection line 81 is connected to one data signal line 73, and the other end is connected to one end of one second data connection line 82. The other end of the second data connection line 82 extends to the bonding area and is connected to one data lead-out line 80, so that the data signal lines 73 in the display area are connected to the data lead-out line 80 in the bonding area 200 through the first data connection line 81 and the second data connection line 82, forming a structure where the data connection lines are located in the display area (Fanout in AA, abbreviated as FIAA). In an exemplary embodiment, the data connection lines include the first data connection line 81 and the second data connection line 82.

[0154] In an exemplary embodiment, the bonding region 200 may include a lead-out line region 201, a bending region 202, a driving chip region, and a bonding pin region that are sequentially arranged along the direction away from the display region. The lead-out line region 201 is connected to the display region 100, and the bending region 202 is connected to the lead-out line region 201. A plurality of data lead-out lines 80 may be provided in the lead-out line region 201. The plurality of data lead-out lines 80 extend along the direction away from the display region. The first ends of a part of the data lead-out lines 80 are correspondingly connected to the second data connection lines 82 in the display region 100, and the first ends of another part of the data lead-out lines 80 are correspondingly connected to the data signal lines 73 in the display region 100. The second ends of all the data lead-out lines 80 extend along the second direction Y and then cross the bending region to be connected to the integrated circuit in the driving chip region, so that the integrated circuit applies data signals to the data signal lines through the data lead-out lines and the data connection lines. Since the first data connection line 81 and the second data connection line 82 are provided in the display region, the length of the lead-out line region in the second direction Y can be effectively reduced, the lower border width can be greatly reduced, the screen-to-body ratio can be improved, and it is beneficial to realize full-screen display.

[0155] Figure 7B This is a schematic structural diagram of a data connection line according to an exemplary embodiment of the present disclosure. As Figure 7B shown, since the first data connection line 81 and the second data connection line 82 are provided in a partial region of the display region, the display region can be divided into a first region 110, a second region 120, and a third region 130 according to the presence or absence of data connection lines and the extension direction of the data connection lines as the division basis. The first region 110 may be a region where the first data connection line 81 is provided (which may be referred to as a connection line horizontal routing region), the second region 120 may be a region where the second data connection line 82 is provided (which may be referred to as a connection line vertical routing region), and the third region 130 may be a region where neither the first data connection line 81 nor the second data connection line 82 is provided (which may be referred to as a normal region). The first region 110, the second region 120, and the third region 130 are all provided with data signal lines 73.

[0156] In an exemplary embodiment, Figure 8 the division of each region shown is only an exemplary illustration. Since the first region 110, the second region 120, and the third region 130 are divided according to the presence or absence of data connection lines and the extension direction of the data connection lines as the division basis, the shapes of the three regions may be regular polygons or irregular polygons. One or more first regions 110, one or more second regions 120, and one or more third regions 130 may be divided in the display region, and the present disclosure does not make any limitation herein.

[0157] Figure 8 This is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure. For Figure 7BAn enlarged view of area A schematically shows the structure of circuit units in one circuit row and four circuit columns. As Figure 8 shown, in a plane parallel to the display substrate, the driving structure layer may include a plurality of circuit units that form a plurality of unit rows and a plurality of unit columns. At least one circuit unit may include a pixel driving circuit, and the pixel driving circuit may be respectively connected to a first scanning signal line 61, a second scanning signal line 62, a third scanning signal line 63, a fourth scanning signal line 64, a light-emitting signal line 65, a reference signal line 66, an initial signal line 67, a first power supply line 71, and a data signal line 73. The first scanning signal line 61 to the fourth scanning signal line 64 are configured to respectively provide a first scanning signal to a fourth scanning signal to the pixel driving circuit, and the light-emitting signal line 63 is configured to provide a light-emitting control signal to the pixel driving circuit. The reference signal line 66, the initial signal line 67, the first power supply line 71, and the data signal line 73 are configured to respectively provide a reference signal, an initial signal, a first power supply signal, and a data signal to the pixel driving circuit. Among them, multiple signal lines connected to the pixel driving circuit may be located within the circuit unit.

[0158] In an exemplary embodiment, the shapes of the first scanning signal line 61, the second scanning signal line 62, the third scanning signal line 63, the fourth scanning signal line 64, the light-emitting signal line 65, the reference signal line 66, and the initial signal line 67 may be straight or zigzag along the first direction X, the shape of the first power supply line 71 may be zigzag along the second direction Y, and the shape of the data signal line 73 may be straight along the second direction Y.

[0159] In the present disclosure, A extending along the B direction means that A may include a main part and a secondary part connected to the main part. The main part is in the shape of a line, a line segment, or a strip, the main part extends along the B direction, and the length of the main part extending along the B direction is greater than the length of the secondary part extending along other directions. The "A extending along the B direction" mentioned in the following description all means that the main body part of A extends along the B direction. In an exemplary embodiment, the first direction X may be the unit row direction, and the second direction Y may be the unit column direction.

[0160] In an exemplary embodiment, a plurality of circuit units on the display substrate may compress out routing spaces by means of horizontal compression and vertical compression. The routing spaces are configured to arrange a first data connection line 81 and a second data connection line 82. Among them, every two unit columns may be grouped as a set, and a vertical routing space is compressed out by horizontal compression, that is, a vertical routing space for arranging the second data connection line 82 is compressed out every two unit columns. Every four unit rows may be grouped as a set, and a horizontal routing space is compressed out by vertical compression, that is, a horizontal routing space for arranging the first data connection line 81 is compressed out every four unit rows.

[0161] In an exemplary embodiment, the pixel driving circuit may include at least a first capacitor, a second capacitor, and a plurality of oxide transistors. The plurality of oxide transistors may include a first transistor T1 as a first reset transistor, a second transistor T2 as a second reset transistor, a third transistor T3 as a driving transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 as a light emitting control transistor, a sixth transistor T6 as a data control transistor, and a seventh transistor T7 as a third reset transistor. The first capacitor may include a first electrode plate and a second electrode plate stacked thereon, and the second capacitor may include a third electrode plate and a fourth electrode plate stacked thereon.

[0162] In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the first scan signal line 61, the first pole of the first transistor T1 is connected to the reference signal line 66, and the second pole of the first transistor T1 is connected to the gate electrode of the third transistor T3. The gate electrode of the second transistor T2 is connected to the first scan signal line 61, the first pole of the second transistor T2 is connected to the reference signal line 66, and the second pole of the second transistor T2 is connected to the first electrode plate of the first capacitor and the third electrode plate of the second capacitor respectively. The first pole of the third transistor T3 is connected to the second pole of the fifth transistor T5, and the second pole of the third transistor T3 is connected to the second electrode plate of the first capacitor. The gate electrode of the fourth transistor T4 is connected to the third scan signal line 63, the first pole of the fourth transistor T4 is connected to the data signal line 73, and the second pole of the fourth transistor T4 is connected to the fourth electrode plate of the second capacitor. The gate electrode of the fifth transistor T5 is connected to the light emitting signal line 65, and the first pole of the fifth transistor T5 is connected to the first power supply line 71. The gate electrode of the sixth transistor T6 is connected to the fourth scan signal line 64, the first pole of the sixth transistor T6 is connected to the gate electrode of the third transistor T3, and the second pole of the sixth transistor T6 is connected to the fourth electrode plate of the second capacitor. The gate electrode of the seventh transistor T7 is connected to the second scan signal line 62, the first pole of the seventh transistor T7 is connected to the initial signal line 67, and the second pole of the seventh transistor T7 is connected to the second electrode plate of the first capacitor.

[0163] In an exemplary embodiment, the aspect ratio of the third transistor T3 may be from 1.25 to 2.67.

[0164] In an exemplary embodiment, in at least one circuit unit, the positive projection of the data signal line 73 on the substrate does not overlap with the positive projection of the channel regions of the first transistor T1 to the seventh transistor T7 on the substrate.

[0165] In an exemplary embodiment, at least one circuit unit may further include at least one first power connection line 68 extending along the first direction X, and the first power supply line 71 is connected to the first power connection line 68 to form a mesh structure for transmitting the first power signal.

[0166] In an exemplary embodiment, the positive projection of the first power line 71 on the substrate at least partially overlaps with the positive projections of the first transistor T1, the fourth transistor T4, and the sixth transistor T6 on the substrate.

[0167] In an exemplary embodiment, at least one circuit unit may further include a second power line 72, and the shape of the second power line 72 may be a broken line shape extending along the second direction Y or a broken line shape.

[0168] In an exemplary embodiment, the width of the second power line 72 may be greater than the width of the first power line 71, and the width may be the dimension in the first direction X.

[0169] In an exemplary embodiment, the positive projection of the second power line 72 on the substrate at least partially overlaps with the positive projections of the third transistor T3, the fifth transistor T5, and the seventh transistor T7 on the substrate.

[0170] In an exemplary embodiment, the driving structure layer may further include at least one first data connection line 81 and at least one second data connection line 82. The shape of the first data connection line 81 may be a straight line shape or a broken line shape extending along the first direction X, and it may be disposed in the horizontal routing space between unit rows. The shape of the second data connection line 82 may be a straight line shape or a broken line shape extending along the second direction Y, and it may be disposed in the vertical routing space between unit columns. One end of at least one first data connection line 81 is connected to the data signal line 73, and the other end is connected to the second data connection line 82, forming a structure where the data connection line is located in the display area.

[0171] In an exemplary embodiment, at least one second data connection line 82 may be disposed between the first power lines 71 adjacent in the first direction X. For example, the second data connection line 82 may be disposed between the first power line 71 of the Nth unit column and the first power line 71 of the (N + 1)th unit column. Another example is that the second data connection line 82 may be disposed between the first power line 71 of the (N + 2)th unit column and the first power line 71 of the (N + 3)th unit column.

[0172] In an exemplary embodiment, at least one circuit unit may further include a data connection block 83 and a data connection electrode 84. The data connection electrode 84 is connected to the first data connection line 81 through the data connection block 83, and the second data connection line 82 may be connected to the data connection electrode 84 through a via, realizing the connection between the first data connection line 81 and the second data connection line 82.

[0173] In an exemplary embodiment, the first data connection line 81, the data connection block 83, and the data connection electrode 84 may be an integrally connected structure.

[0174] In an exemplary embodiment, at least one circuit unit may further include a dummy electrode 85, and the second data connection line 82 may be connected to the dummy electrode 85 through a via. The position and shape of the dummy electrode 85 in one circuit unit may be substantially the same as the position and shape of the data connection electrode 84 in another circuit unit, such that the data connection electrode 84 and the dummy electrode 85 present the same morphology and via connection structure.

[0175] In an exemplary embodiment, a first break K1 may be provided on at least one first data connection line 81, and the first break K1 truncates the first data connection line 81. The orthographic projection of the first break K1 on the substrate overlaps at least partially with the orthographic projection of the first power supply line 71 or the second power supply line 72 on the substrate.

[0176] In an exemplary embodiment, the orthographic projection of the first break K1 on the substrate may be located within the range of the orthographic projection of the first power supply line 71 or the second power supply line 72 on the substrate.

[0177] In an exemplary embodiment, a second break K2 may be provided on at least one second data connection line 82, and the second break K2 truncates the second data connection line 82. The orthographic projection of the second break K2 on the substrate overlaps at least partially with the orthographic projection of the reference signal line 66 or the initial signal line 67 on the substrate.

[0178] In an exemplary embodiment, the orthographic projection of the second break K2 on the substrate may be located within the range of the orthographic projection of the reference signal line 66 or the initial signal line 67 on the substrate.

[0179] In an exemplary embodiment, in one unit row, the pixel driving circuits in two adjacent circuit units may be symmetrically arranged with respect to the column center line, and the column center line may be a straight line located between two adjacent circuit units in the first direction X and extending along the second direction Y. For example, the pixel driving circuits of the Nth unit column and the (N + 1)th unit column may be symmetrically arranged with respect to the column center line. Another example is that the pixel driving circuits of the (N + 1)th unit column and the (N + 2)th unit column may be symmetrically arranged with respect to the column center line.

[0180] In an exemplary embodiment, the pixel driving circuits in adjacent unit rows may be substantially the same.

[0181] In an exemplary embodiment, in a direction perpendicular to the substrate, the driving circuit layer may at least include a first conductive layer (first gate metal layer), a second conductive layer (second gate metal layer), a semiconductor layer, a third conductive layer (third gate metal layer), a fourth conductive layer (first source / drain metal layer), and a fifth conductive layer (second source / drain metal layer) sequentially arranged along a direction away from the substrate. The first electrode plate of the first capacitor and the third electrode plate of the second capacitor may be disposed in the first conductive layer, the second electrode plate of the first capacitor and the fourth electrode plate of the second capacitor may be disposed in the second conductive layer, the second scanning signal line 62 and the light-emitting signal line 65 may be disposed in the third conductive layer, the first scanning signal line 61, the third scanning signal line 63, the fourth scanning signal line 64, the reference signal line 66, the initial signal line 67, and the first data connection line 81 may be disposed in the fourth conductive layer, and the first power supply line 71, the second power supply line 72, the data signal line 73, and the second data connection line 82 may be disposed in the fifth conductive layer.

[0182] The preparation process of the substrate is exemplarily described below through this exemplary embodiment. The "patterning process" as mentioned in the present disclosure, for metal materials, inorganic materials, or transparent conductive materials, includes processes such as depositing a film layer, coating a photoresist on the film layer, mask exposure, development, etching, and photoresist stripping. For organic materials, it includes processes such as coating an organic material, mask exposure, and development. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition. Coating can be carried out by any one or more of spraying, spin coating, and inkjet printing. Etching can be carried out by any one or more of dry etching and wet etching. The present disclosure does not make any limitations. A "thin film" refers to a thin film made of a certain material on a substrate by using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" requires a patterning process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The statement "A and B are disposed in the same layer" as mentioned in the present disclosure means that A and B are simultaneously formed through the same patterning process. The "thickness" of a film layer is the dimension of the film layer in a direction perpendicular to the display substrate. In the exemplary embodiment of the present disclosure, the statement "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0183] In an exemplary embodiment, taking four circuit units of one unit row (the M-th unit row) and four unit columns (the N-th unit column, the (N + 1)-th unit column, the (N + 2)-th unit column, and the (N + 3)-th unit column) as an example, the preparation process of the display substrate in this embodiment may include the following operations.

[0184] (11) Form a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a first conductive thin film on a substrate, patterning the first conductive thin film through a patterning process, and forming a first conductive layer pattern on the substrate, as Figure 9 shown. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0185] In an exemplary embodiment, the first conductive layer pattern of each circuit unit in the display substrate may at least include a first electrode plate 11 of a first capacitor, a third electrode plate 13 of a second capacitor, and an electrode plate connection block 15.

[0186] In an exemplary embodiment, the shape of the first electrode plate 11 of the first capacitor may be in the shape of a wine glass, chamfers or grooves may be provided at the corners of the wine glass shape, and the first electrode plate 11 may serve as the lower electrode plate of the first capacitor.

[0187] In an exemplary embodiment, the third electrode plate 13 of the second capacitor may be disposed on one side opposite to the second direction Y of the first electrode plate 11. The shape of the third electrode plate 13 may be rectangular, chamfers or grooves may be provided at the corners of the rectangular shape, and the third electrode plate 13 may serve as the lower electrode plate of the second capacitor.

[0188] In an exemplary embodiment, the first electrode plate 11 and the third electrode plate 13 may be an integrally connected structure, that is, the lower electrode plates of the first capacitor and the second capacitor are an integrally connected structure.

[0189] In an exemplary embodiment, the shape of the electrode plate connection block 15 may be block-shaped (such as rectangular), and may be disposed on one side or the opposite side in the first direction X of the first electrode plate 11, and is connected to the first electrode plate 11. The electrode plate connection block 15 is configured to be connected to a fourth connection electrode formed subsequently.

[0190] In an exemplary embodiment, the first electrode plate 11, the third electrode plate 13, and the electrode plate connection block 15 may be an integrally connected structure.

[0191] In an exemplary embodiment, in one unit row, the spacing between the first conductive layers of adjacent two circuit units may be different. For example, the spacing between the first conductive layer in the Nth unit column and the first conductive layer in the N + 1th unit column may be greater than the spacing between the first conductive layer in the N + 1th unit column and the first conductive layer in the N + 2th unit column.

[0192] In an exemplary embodiment, in a unit row, the first conductive layers in two adjacent circuit units may be symmetrically arranged with respect to the column center line, and the column center line may be a straight line located between two adjacent circuit units in the first direction X and extending along the second direction Y. For example, the first conductive layers of the Nth unit column and the (N + 1)th unit column may be symmetrically arranged with respect to the column center line. Another example is that the first conductive layers of the (N + 1)th unit column and the (N + 2)th unit column may be symmetrically arranged with respect to the column center line.

[0193] In an exemplary embodiment, the first conductive layers in adjacent unit rows may be substantially the same.

[0194] (12) Form a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: sequentially depositing a first insulating thin film and a second conductive thin film on the substrate on which the foregoing pattern is formed, patterning the second conductive thin film through a patterning process to form a first insulating layer covering the first conductive layer pattern, and a second conductive layer pattern disposed on the first insulating layer, as Figure 10A and Figure 10B shown, Figure 10B is Figure 10A a plan view of the second conductive layer in

[0195] In an exemplary embodiment, the second conductive layer pattern of each circuit unit in the display substrate at least includes: a second electrode plate 12 of a first capacitor, a fourth electrode plate 14 of a second capacitor, a first bottom gate electrode 21, a second bottom gate electrode 22, a fourth bottom gate electrode 24, a sixth bottom gate electrode 26, a first shielding line 27, and a second shielding line 28.

[0196] In an exemplary embodiment, the shape of the second electrode plate 12 of the first capacitor may be a wine glass shape, and the orthographic projection of the second electrode plate 12 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 11 on the substrate. In an exemplary embodiment, the second electrode plate 12 may serve as the upper electrode plate of the first capacitor, and the first electrode plate 11 and the second electrode plate 12 form the first capacitor.

[0197] In an exemplary embodiment, the orthographic projection of the second electrode plate 12 on the substrate is within the range of the orthographic projection of the first electrode plate 11 on the substrate.

[0198] In an exemplary embodiment, the fourth electrode plate 14 of the second capacitor may be disposed on one side opposite to the second direction Y of the second electrode plate 12. The shape of the fourth electrode plate 14 may be rectangular, and chamfers or grooves may be provided at the corners of the rectangular shape. The orthographic projection of the fourth electrode plate 14 on the substrate at least partially overlaps with the orthographic projection of the third electrode plate 13 on the substrate. In an exemplary embodiment, the third electrode plate 13 and the fourth electrode plate 14 form the second capacitor.

[0199] In an exemplary embodiment, the orthographic projection of the fourth electrode plate 14 on the substrate is within the range of the orthographic projection of the third electrode plate 13 on the substrate.

[0200] In an exemplary embodiment, the shape of the first bottom gate electrode 21 may be block-shaped (such as rectangular), and it may be disposed on one side of the second electrode plate 12 in the first direction X or on the opposite side of the first direction X. The first bottom gate electrode 21 can serve as the bottom gate electrode of the first transistor T1 and can also serve as a shielding layer of the first transistor T1 to shield the channel region of the first transistor T1 and ensure the electrical performance of the oxide first transistor T1.

[0201] In an exemplary embodiment, the shape of the second bottom gate electrode 22 may be block-shaped (such as rectangular), and it may be disposed between the second electrode plate 12 and the first bottom gate electrode 21. The second bottom gate electrode 22 can serve as the bottom gate electrode of the second transistor T2 and can also serve as a shielding layer of the second transistor T2 to shield the channel region of the second transistor T2 and ensure the electrical performance of the oxide second transistor T2.

[0202] In an exemplary embodiment, in at least one circuit unit, the first bottom gate electrode 21 and the second bottom gate electrode 22 are integrally connected to each other.

[0203] In an exemplary embodiment, the first bottom gate electrodes 21 of two circuit units adjacent to each other in a part of the first direction X may be integrally connected to each other. For example, the first bottom gate electrode 21 of the Nth unit column and the first bottom gate electrode 21 of the (N + 1)th unit column may be integrally connected to each other. Another example is that the first bottom gate electrode 21 of the (N + 2)th unit column and the first bottom gate electrode 21 of the (N + 3)th unit column may be integrally connected to each other.

[0204] In an exemplary embodiment, since the first bottom gate electrode 21 and the second bottom gate electrode 22 in one circuit unit are integrally connected to each other, the first bottom gate electrodes 21 and the second bottom gate electrodes 22 of two circuit units adjacent to each other in a part of the first direction X are integrally connected to each other. For example, the first bottom gate electrode 21 and the second bottom gate electrode 22 in the Nth unit column and the (N + 1)th unit column in one unit row may be integrally connected to each other. Another example is that the first bottom gate electrode 21 and the second bottom gate electrode 22 in the (N + 2)th unit column and the (N + 3)th unit column in one unit row may be integrally connected to each other.

[0205] In an exemplary embodiment, a first bottom gate connection block 21-1 may be provided on the first bottom gate electrode 21. The shape of the first bottom gate connection block 21-1 may be block-shaped (such as rectangular), and may be provided on a side of the first bottom gate electrode 21 away from the sixth bottom gate electrode 26 and connected to the first bottom gate electrode 21. The first bottom gate connection block 21-1 is configured to be connected to a subsequently formed first scan signal line.

[0206] In an exemplary embodiment, the first bottom gate connection block 21-1 may be provided at a middle position of the integrally structured first bottom gate electrode 21, that is, between two circuit units adjacent in the first direction X, such that the first bottom gate electrodes 21 of the two circuit units share the same first bottom gate connection block 21-1.

[0207] By providing the first bottom gate electrodes of adjacent circuit units as an integrally connected structure, the first transistors T1 of adjacent two pixel driving circuits share the same bottom gate electrode and bottom gate connection block, which can effectively reduce the occupied space of the pixel driving circuit and is beneficial to the compression of circuit units on the premise of ensuring the display resolution (PPI).

[0208] In an exemplary embodiment, the shape of the fourth bottom gate electrode 24 may be block-shaped (such as rectangular), and may be provided on one side of the fourth electrode plate 14 in the first direction X or on the opposite side of the first direction X. The fourth bottom gate electrode 24 can serve as the bottom gate electrode of the fourth transistor T4 and can also serve as a shielding layer of the fourth transistor T4 to shield the channel region of the fourth transistor T4 and ensure the electrical performance of the oxide fourth transistor T4.

[0209] In an exemplary embodiment, the fourth bottom gate electrodes 24 of two circuit units adjacent in part in the first direction X may be an integrally connected structure. For example, the fourth bottom gate electrode 24 of the Nth unit column and the fourth bottom gate electrode 24 of the N+1th unit column may be an integrally connected structure. Also, for example, the fourth bottom gate electrode 24 of the N+2th unit column and the fourth bottom gate electrode 24 of the N+3th unit column may be an integrally connected structure.

[0210] In an exemplary embodiment, a fourth bottom gate connection block 24-1 may be provided on the fourth bottom gate electrode 24. The shape of the fourth bottom gate connection block 24-1 may be block-shaped (such as rectangular), and may be provided on a side of the fourth bottom gate electrode 24 away from the sixth bottom gate electrode 26 and connected to the fourth bottom gate electrode 24. The fourth bottom gate connection block 24-1 is configured to be connected to a subsequently formed third scan signal line.

[0211] In an exemplary embodiment, the fourth bottom gate connection block 24-1 may be disposed at the middle position of the fourth bottom gate electrode 24 of the integrated structure, that is, between two circuit units adjacent in the first direction X, such that the fourth bottom gate electrodes 24 of the two circuit units share the same fourth bottom gate connection block 24-1.

[0212] By providing the fourth bottom gate electrodes of adjacent circuit units as an interconnected integrated structure, the fourth transistors T4 of two adjacent pixel driving circuits share the same bottom gate electrode and bottom gate connection block, which can effectively reduce the occupied space of the pixel driving circuit and is beneficial to the compression of the circuit unit on the premise of ensuring the display resolution (PPI).

[0213] In an exemplary embodiment, the shape of the sixth bottom gate electrode 26 may be block-shaped (such as rectangular), and it may be disposed on one side of the fourth electrode plate 14 in the first direction X or on the opposite side of the first direction X, and is located on one side of the fourth bottom gate electrode 24 in the second direction Y. The sixth bottom gate electrode 26 may serve as the bottom gate electrode of the sixth transistor T6 and may also serve as the shielding layer of the sixth transistor T6 to shield the channel region of the sixth transistor T6 and ensure the electrical performance of the oxide sixth transistor T6.

[0214] In an exemplary embodiment, the sixth bottom gate electrodes 26 of two circuit units adjacent in part in the first direction X may be an interconnected integrated structure. For example, the sixth bottom gate electrode 26 of the Nth unit column and the sixth bottom gate electrode 26 of the N+1th unit column may be an interconnected integrated structure. Another example is that the sixth bottom gate electrode 26 of the N+2th unit column and the sixth bottom gate electrode 26 of the N+3th unit column may be an interconnected integrated structure.

[0215] In an exemplary embodiment, a sixth bottom gate connection block 26-1 may be disposed on the sixth bottom gate electrode 26. The shape of the sixth bottom gate connection block 26-1 may be block-shaped (such as rectangular), and it may be disposed on the side of the sixth bottom gate electrode 26 close to the first bottom gate electrode 21 and is connected to the sixth bottom gate electrode 26. The sixth bottom gate connection block 26-1 is configured to be connected to a subsequent formed fourth scan signal line.

[0216] In an exemplary embodiment, the sixth bottom gate connection block 26-1 may be disposed at the middle position of the sixth bottom gate electrode 26 of the integrated structure, that is, between two circuit units adjacent in the first direction X, such that the sixth bottom gate electrodes 26 of the two circuit units share the same sixth bottom gate connection block 26-1.

[0217] By setting the sixth bottom gate electrodes of adjacent circuit units as an integrally connected structure, the sixth transistors T6 of two adjacent pixel driving circuits share the same bottom gate electrode and bottom gate connection block, which can effectively reduce the occupied space of the pixel driving circuit and is conducive to the compression of circuit units on the premise of ensuring the display resolution (PPI).

[0218] In an exemplary embodiment, the shape of the first shielding line 27 can be a straight line or a broken line extending along the first direction X, and it can be disposed on the side of the second electrode plate 12 away from the fourth electrode plate 14. In an exemplary embodiment, the first shielding line 27 can be a non-uniform-width straight line, and the width of the overlapping position of the first shielding line 27 and the subsequently formed seventh active layer can be greater than that of other positions. The wider-position first shielding line 27 can serve as a shielding layer for the seventh transistor T7 to shield the channel region of the seventh transistor T7 and ensure the electrical performance of the oxide seventh transistor T7. In an exemplary embodiment, the first shielding line 27 can simultaneously serve as the bottom gate electrode of the seventh transistor T7.

[0219] In an exemplary embodiment, the shape of the second shielding line 28 can be a straight line or a broken line extending along the first direction X, and it can be disposed on the side of the fourth electrode plate 14 away from the second electrode plate 12. In an exemplary embodiment, the second shielding line 28 can be a non-uniform-width straight line, and the width of the overlapping position of the second shielding line 28 and the subsequently formed fifth active layer can be greater than that of other positions. The wider-position second shielding line 28 can serve as a shielding layer for the fifth transistor T5 to shield the channel region of the fifth transistor T5 and ensure the electrical performance of the oxide fifth transistor T5. In an exemplary embodiment, the second shielding line 28 can simultaneously serve as the bottom gate electrode of the fifth transistor T5.

[0220] In an exemplary embodiment, in one unit row, the second conductive layers in two adjacent circuit units can be symmetrically disposed with respect to the column center line. For example, the second conductive layers of the Nth unit column and the (N + 1)th unit column can be symmetrically disposed with respect to the column center line. Another example is that the second conductive layers of the (N + 1)th unit column and the (N + 2)th unit column can be symmetrically disposed with respect to the column center line.

[0221] In an exemplary embodiment, the second conductive layers in adjacent unit rows can be substantially the same.

[0222] (13) Form a semiconductor layer pattern. In an exemplary embodiment, forming the semiconductor layer pattern may include: sequentially depositing a second insulating film and a semiconductor film on the substrate on which the foregoing patterns are formed, patterning the semiconductor film through a patterning process to form a second insulating layer covering the second conductive layer, and a semiconductor layer pattern disposed on the second insulating layer, such as Figure 11A and Figure 11BAs shown Figure 11B is Figure 11A a plan view of the semiconductor layer in

[0223] In an exemplary embodiment, the semiconductor layer patterns of each circuit unit in the display substrate may include a first active layer 31 of a first transistor T1 to a seventh active layer 37 of a seventh transistor T7, and the first active layer 31, the second active layer 32, the fourth active layer 34, and the sixth active layer 36 may be an integrally connected structure, and the third active layer 33, the fifth active layer 35, and the seventh active layer 37 may be an integrally connected structure.

[0224] In an exemplary embodiment, in the first direction X, the first active layer 31, the second active layer 32, the fourth active layer 34, and the sixth active layer 36 may be located on the same side of the third active layer 33 in the first direction X. In the second direction Y, the fourth active layer 34 and the fifth active layer 35 may be located on one side opposite to the second direction Y of the third active layer 33, and the first active layer 31, the second active layer 32, and the seventh active layer 37 may be located on one side of the third active layer 33 in the second direction Y.

[0225] In an exemplary embodiment, the shape of the third active layer 33 may be hexagonal, the shapes of the first active layer 31, the second active layer 32, the fourth active layer 34, the fifth active layer 35, and the sixth active layer 36 may be strip-shaped extending along the second direction Y, and the shape of the seventh active layer 37 may be "L"-shaped.

[0226] In an exemplary embodiment, in an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first region and the second region. The orthographic projection of the first active layer 31 on the substrate at least partially overlaps with the orthographic projection of the first bottom gate electrode 21 on the substrate, and the overlapping region may serve as the channel region of the first transistor T1. The orthographic projection of the second active layer 32 on the substrate at least partially overlaps with the orthographic projection of the second bottom gate electrode 22 on the substrate, and the overlapping region may serve as the channel region of the second transistor T2. The orthographic projection of the third active layer 33 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate 12 (the bottom gate electrode of the third transistor T3) on the substrate, and the overlapping region may serve as the channel region of the third transistor T3. The orthographic projection of the fourth active layer 34 on the substrate at least partially overlaps with the orthographic projection of the fourth bottom gate electrode 24 on the substrate, and the overlapping region serves as the channel region of the fourth transistor T4. The orthographic projection of the fifth active layer 35 on the substrate at least partially overlaps with the orthographic projection of the second shielding line 28 on the substrate, and the overlapping region serves as the channel region of the fifth transistor T5. The orthographic projection of the sixth active layer 36 on the substrate at least partially overlaps with the orthographic projection of the sixth bottom gate electrode 26 on the substrate, and the overlapping region serves as the channel region of the sixth transistor T6. The orthographic projection of the seventh active layer 37 on the substrate at least partially overlaps with the orthographic projection of the first shielding line 27 on the substrate, and the overlapping region serves as the channel region of the seventh transistor T7.

[0227] In an exemplary embodiment, the first region 31-1 of the first active layer and the first region 32-1 of the second active layer may be connected to each other, and the first region 31-1 of the first active layer may serve as the first region 32-1 of the second active layer. The second region 31-2 of the first active layer and the first region 36-1 of the sixth active layer may be connected to each other, and the second region 31-2 of the first active layer may serve as the first region 36-1 of the sixth active layer. The first region 33-1 of the third active layer and the second region 35-2 of the fifth active layer may be connected to each other, and the first region 33-1 of the third active layer may serve as the second region 35-2 of the fifth active layer. The second region 33-2 of the third active layer and the second region 37-2 of the seventh active layer may be connected to each other, and the second region 33-2 of the third active layer may serve as the second region 37-2 of the seventh active layer. The second region 34-2 of the fourth active layer and the second region 36-2 of the sixth active layer may be connected to each other, and the second region 34-2 of the fourth active layer may serve as the second region 36-2 of the sixth active layer. The second region 32-2 of the second active layer, the first region 34-1 of the fourth active layer 34, the first region of the fifth active layer 35, and the first region 37-1 of the seventh active layer may be provided separately.

[0228] In an exemplary embodiment, in a unit row, semiconductor layers in two adjacent circuit units may be symmetrically arranged with respect to the column center line. For example, semiconductor layers in the Nth unit column and the (N + 1)th unit column may be symmetrically arranged with respect to the column center line. For another example, semiconductor layers in the (N + 1)th unit column and the (N + 2)th unit column may be symmetrically arranged with respect to the column center line.

[0229] In an exemplary embodiment, semiconductor layers in adjacent unit rows may be substantially the same.

[0230] In an exemplary embodiment, the semiconductor layer may be an oxide, that is, the first transistor T1 to the seventh transistor T7 are oxide transistors, and the oxide transistors have advantages such as high electron mobility, low operating voltage, and low leakage characteristics. In an exemplary embodiment, the oxide may be any one or more of the following: indium gallium zinc oxide (InGaZnO), indium gallium zinc nitride oxide (InGaZnON), zinc oxide (ZnO), zinc nitride oxide (ZnON), zinc tin oxide (ZnSnO), cadmium tin oxide (CdSnO), gallium tin oxide (GaSnO), titanium tin oxide (TiSnO), copper aluminum oxide (CuAlO), strontium copper oxide (SrCuO), lanthanum copper oxygen sulfide (LaCuOS), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), and indium gallium aluminum nitride (InGaAlN). In some possible implementation manners, the semiconductor thin film may be indium gallium zinc oxide (IGZO), and the electron mobility of indium gallium zinc oxide (IGZO) is higher than that of amorphous silicon.

[0231] (14) Form a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: sequentially depositing a third insulating film and a third conductive film on the substrate on which the foregoing patterns are formed, patterning the third conductive film through a patterning process to form a third insulating layer covering the semiconductor layer pattern, and a third conductive layer pattern provided on the third insulating layer, as Figure 12A and Figure 12B shown, Figure 12B is Figure 12A a schematic diagram of the third conductive layer in

[0232] In an exemplary embodiment, the third conductive layer pattern of each circuit unit in the display substrate at least includes: a first top gate electrode 41, a second top gate electrode 42, a third top gate electrode 43, a fourth top gate electrode 44, a sixth top gate electrode 46, a second scan signal line 62, and a light emitting signal line 65.

[0233] In an exemplary embodiment, the shape of the first top gate electrode 41 may be block-shaped (such as rectangular), the orthographic projection of the first top gate electrode 41 on the substrate at least partially overlaps with the orthographic projection of the first active layer on the substrate, and the first top gate electrode 41 may serve as the top gate electrode of the first transistor T1. In an exemplary embodiment, the orthographic projection of the first top gate electrode 41 on the substrate at least partially overlaps with the orthographic projection of the first bottom gate electrode 21 on the substrate, and the first top gate electrode 41 and the first bottom gate electrode 21 form the first transistor T1 with a top gate-bottom gate structure.

[0234] In an exemplary embodiment, the shape of the second top gate electrode 42 may be block-shaped (such as rectangular), the orthographic projection of the second top gate electrode 42 on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate, and the second top gate electrode 42 may serve as the top gate electrode of the second transistor T2. In an exemplary embodiment, the orthographic projection of the second top gate electrode 42 on the substrate at least partially overlaps with the orthographic projection of the second bottom gate electrode 22 on the substrate, and the second top gate electrode 42 and the second bottom gate electrode 22 form the second transistor T2 with a top gate-bottom gate structure.

[0235] In an exemplary embodiment, in at least one circuit unit, the first top gate electrode 41 and the second top gate electrode 42 are an integrally connected structure.

[0236] In an exemplary embodiment, the first top gate electrodes 41 of two circuit units adjacent in a partial first direction X may be an integrally connected structure. For example, the first top gate electrode 41 of the Nth unit column and the first top gate electrode 41 of the (N + 1)th unit column may be an integrally connected structure. Another example is that the first top gate electrode 41 of the (N + 2)th unit column and the first top gate electrode 41 of the (N + 3)th unit column may be an integrally connected structure.

[0237] In an exemplary embodiment, since the first top gate electrode 41 and the second top gate electrode 42 in one circuit unit are an integrally connected structure, the first top gate electrodes 41 and the second top gate electrodes 42 of two circuit units adjacent in a partial first direction X are an integrally connected structure. For example, the first top gate electrode 41 and the second top gate electrode 42 in the Nth unit column and the (N + 1)th unit column in one unit row may be an integrally connected structure. Another example is that the first top gate electrode 41 and the second top gate electrode 42 in the (N + 2)th unit column and the (N + 3)th unit column in one unit row may be an integrally connected structure.

[0238] In an exemplary embodiment, a first top gate connection block 41-1 may be provided on the first top gate electrode 41. The shape of the first top gate connection block 41-1 may be block-shaped (such as rectangular), and may be provided on a side of the first top gate electrode 41 close to the sixth top gate electrode 46 and connected to the first top gate electrode 41. The first top gate connection block 41-1 is configured to be connected to a subsequently formed first scan signal line.

[0239] In an exemplary embodiment, the first top gate connection block 41-1 may be provided at a middle position of the integrated first top gate electrode 41, that is, between two circuit units adjacent in the first direction X, such that the first top gate electrodes 41 of the two circuit units share the same first top gate connection block 41-1.

[0240] In the present disclosure, by setting the first top gate electrodes of adjacent circuit units to be an integrated structure connected to each other, the first transistors T1 of adjacent two pixel driving circuits share the same top gate electrode and top gate connection block, which can effectively reduce the occupied space of the pixel driving circuit and is beneficial to the compression of circuit units on the premise of ensuring the display resolution (PPI).

[0241] In an exemplary embodiment, the shape of the third top gate electrode 43 may be strip-shaped extending along the first direction X. The positive projection of the third top gate electrode 43 on the substrate at least partially overlaps with the positive projection of the third active layer on the substrate. The third top gate electrode 43 may serve as the gate electrode of the third transistor T3, and the third transistor T3 is a transistor with a top gate structure.

[0242] In an exemplary embodiment, the shape of the fourth top gate electrode 44 may be block-shaped (such as rectangular). The positive projection of the fourth top gate electrode 44 on the substrate at least partially overlaps with the positive projection of the fourth active layer on the substrate. The fourth top gate electrode 44 may serve as the top gate electrode of the fourth transistor T4. In an exemplary embodiment, the positive projection of the fourth top gate electrode 44 on the substrate at least partially overlaps with the positive projection of the fourth bottom gate electrode 24 on the substrate. The fourth top gate electrode 44 and the fourth bottom gate electrode 24 form the fourth transistor T4 with a top gate-bottom gate structure.

[0243] In an exemplary embodiment, the fourth top gate electrodes 44 of two circuit units adjacent in part of the first direction X may be an integrated structure connected to each other. For example, the fourth top gate electrode 44 of the Nth unit column and the fourth top gate electrode 44 of the N+1th unit column may be an integrated structure connected to each other. Another example is that the fourth top gate electrode 44 of the N+2th unit column and the fourth top gate electrode 44 of the N+3th unit column may be an integrated structure connected to each other.

[0244] In an exemplary embodiment, a fourth top gate connection block 44-1 may be provided on the fourth top gate electrode 44. The shape of the fourth top gate connection block 44-1 may be block-shaped (such as rectangular), and may be disposed on a side of the fourth top gate electrode 44 close to the sixth top gate electrode 46 and connected to the fourth top gate electrode 44. The fourth top gate connection block 44-1 is configured to be connected to a subsequently formed third scan signal line.

[0245] In an exemplary embodiment, the fourth top gate connection block 44-1 may be disposed at a middle position of the fourth top gate electrode 44 of an integrated structure, that is, between two circuit units adjacent in the first direction X, such that the fourth top gate electrodes 44 of the two circuit units share the same fourth top gate connection block 44-1.

[0246] By providing the fourth top gate electrodes of adjacent circuit units as an interconnected integrated structure, the fourth transistors T4 of adjacent two pixel driving circuits share the same top gate electrode and top gate connection block, which can effectively reduce the occupied space of the pixel driving circuit and is beneficial to the compression of circuit units on the premise of ensuring the display resolution (PPI).

[0247] In an exemplary embodiment, the shape of the sixth top gate electrode 46 may be block-shaped (such as rectangular). The positive projection of the sixth top gate electrode 46 on the substrate at least partially overlaps with the positive projection of the sixth active layer on the substrate. The sixth top gate electrode 46 may serve as the top gate electrode of the sixth transistor T6. In an exemplary embodiment, the positive projection of the sixth top gate electrode 46 on the substrate at least partially overlaps with the positive projection of the sixth bottom gate electrode 26 on the substrate. The sixth top gate electrode 46 and the sixth bottom gate electrode 26 form the sixth transistor T6 with a top gate-bottom gate structure.

[0248] In an exemplary embodiment, the sixth top gate electrodes 46 of two circuit units adjacent in part in the first direction X may be an interconnected integrated structure. For example, the sixth top gate electrode 46 of the Nth unit column and the sixth top gate electrode 46 of the N+1th unit column may be an interconnected integrated structure. Another example is that the sixth top gate electrode 46 of the N+2th unit column and the sixth top gate electrode 46 of the N+3th unit column may be an interconnected integrated structure.

[0249] In an exemplary embodiment, a sixth top gate connection block 46-1 may be provided on the sixth top gate electrode 46. The shape of the sixth top gate connection block 46-1 may be block-shaped (such as rectangular), and may be disposed on a side of the sixth top gate electrode 46 far from the first top gate electrode 41 and connected to the sixth top gate electrode 46. The sixth top gate connection block 46-1 is configured to be connected to a subsequently formed fourth scan signal line.

[0250] In an exemplary embodiment, the sixth top gate connection block 46-1 may be disposed at the middle position of the sixth top gate electrode 46 of the integrated structure, that is, between two adjacent circuit units in the first direction X, such that the sixth top gate electrodes 46 of the two circuit units share the same sixth top gate connection block 46-1.

[0251] By setting the sixth top gate electrodes of adjacent circuit units as an integrated structure connected to each other, the sixth transistors T6 of two adjacent pixel driving circuits share the same top gate electrode and top gate connection block, which can effectively reduce the occupied space of the pixel driving circuit and is beneficial to the compression of circuit units on the premise of ensuring the display resolution (PPI).

[0252] In an exemplary embodiment, the shape of the second scan signal line 62 may be a straight line or a broken line extending along the first direction X, and it may be disposed on the side of the second electrode plate 12 away from the fourth electrode plate 14. The region where the second scan signal line 62 overlaps with the seventh active layer serves as the top gate electrode of the seventh transistor T7.

[0253] In an exemplary embodiment, the second scan signal line 62 may be a non-uniform-width straight line, and the width of the overlapping position of the second scan signal line 62 and the seventh active layer may be greater than that of other positions. The orthographic projection of the second scan signal line 62 on the substrate at least partially overlaps with the orthographic projection of the first shielding line 27 on the substrate. The second scan signal line 62 and the first shielding line 27 may be connected to the same signal source, such that the first shielding line 27 can serve as the bottom gate electrode of the seventh transistor T7, and the second scan signal line 62 can serve as the top gate electrode of the seventh transistor T7, forming the seventh transistor T7 with a top gate-bottom gate structure.

[0254] In an exemplary embodiment, the shape of the light-emitting signal line 65 may be a straight line or a broken line extending along the first direction X, and it may be disposed on the side of the fourth electrode plate 14 away from the second electrode plate 12. The region where the light-emitting signal line 65 overlaps with the fifth active layer serves as the top gate electrode of the fifth transistor T5.

[0255] In an exemplary embodiment, the light-emitting signal line 65 may be a non-uniform-width straight line, and the width of the overlapping position of the light-emitting signal line 65 and the fifth active layer may be greater than that of other positions. The orthographic projection of the light-emitting signal line 65 on the substrate at least partially overlaps with the orthographic projection of the second shielding line 28 on the substrate. The light-emitting signal line 65 and the second shielding line 28 may be connected to the same signal source, such that the second shielding line 28 can serve as the bottom gate electrode of the fifth transistor T5, and the light-emitting signal line 65 can serve as the top gate electrode of the fifth transistor T5, forming the fifth transistor T5 with a top gate-bottom gate structure.

[0256] In an exemplary embodiment, in a unit row, the third conductive layers in two adjacent circuit units may be symmetrically arranged with respect to the column center line. For example, the third conductive layers of the Nth unit column and the (N + 1)th unit column may be symmetrically arranged with respect to the column center line. For another example, the third conductive layers of the (N + 1)th unit column and the (N + 2)th unit column may be symmetrically arranged with respect to the column center line.

[0257] In an exemplary embodiment, the third conductive layers in adjacent unit rows may be substantially the same.

[0258] In an exemplary embodiment, after forming the third conductive layer pattern, the third conductive layer may be used as a mask to conductivize the semiconductor layer. The semiconductor layer in the region shielded by the second conductive layer forms the channel regions of the first transistor T1 to the seventh transistor T7, and the semiconductor layer in the region not shielded by the third conductive layer is conductivized, that is, the first regions and the second regions of the first active layer to the seventh active layer are both conductivized.

[0259] Figure 12C For Figure 12A is an enlarged view of the third transistor. As Figure 12A , Figure 12B and Figure 12C shown, the overlapping region of the positive projection of the third top gate electrode 43 on the substrate and the positive projection of the third active layer on the substrate is the channel region of the third transistor T3. The channel region has a channel length L and a channel width W. The channel length L is the dimension in the second direction Y, and the channel width W is the dimension in the first direction X.

[0260] In an exemplary embodiment, the aspect ratio of the third transistor T3 as a driving transistor is the ratio of the channel width W to the channel length L, that is, W / L.

[0261] In an exemplary embodiment, the aspect ratio W / L of the third transistor T3 may be less than 1. Among them, the aspect ratio W / L of the third transistor T3 may be about 0.27 to 0.8. For example, the aspect ratio W / L may be about 6 / 10, or may be about 6 / 14, or may be about 6 / 18, or may be about 6 / 22. For another example, the aspect ratio W / L may be about 8 / 10, or may be about 8 / 14, or may be about 8 / 18, or may be about 8 / 22.

[0262] In a preferred embodiment, the aspect ratio W / L of the third transistor T3 may be about 0.44 to 0.8. For example, the aspect ratio W / L may be about 8 / 10. For another example, the aspect ratio W / L may be about 8 / 14. For still another example, the aspect ratio W / L may be about 8 / 18.

[0263] In another exemplary embodiment, the width-to-length ratio W / L of the third transistor T3 can be greater than 1. Among them, the width-to-length ratio W / L of the third transistor T3 can be approximately 1.25 to 2.67. For example, the width-to-length ratio W / L can be approximately 10 / 6, or can be approximately 12 / 6, or can be approximately 14 / 6, or can be approximately 16 / 6. Again, for example, the width-to-length ratio W / L can be approximately 10 / 8, or can be approximately 12 / 8, or can be approximately 14 / 8, or can be approximately 16 / 8.

[0264] In a preferred embodiment, the width-to-length ratio W / L of the third transistor T3 can be approximately 1.67 to 2.67. For example, the width-to-length ratio W / L can be approximately 10 / 6. Again, for example, the width-to-length ratio W / L can be approximately 12 / 6. Again, for example, the width-to-length ratio W / L can be approximately 14 / 6 or 16 / 6.

[0265] By setting the width-to-length ratio of the third transistor T3, the present disclosure can effectively improve the driving performance of the pixel driving circuit and improve the display quality.

[0266] (15) Form a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating thin film on the substrate on which the foregoing patterns are formed, and patterning the fourth insulating thin film using a patterning process to form a fourth insulating layer covering the third conductive layer, and a plurality of vias are provided on the fourth insulating layer, as Figure 13 shown.

[0267] In an exemplary embodiment, the plurality of vias of each circuit unit in the display substrate at least include: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, a seventeenth via V17, and an eighteenth via V18.

[0268] In an exemplary embodiment, the orthographic projection of the first via V1 on the substrate is within the range of the orthographic projection of the first region of the first active layer (which is also the first region of the second active layer) on the substrate. The third insulating layer and the fourth insulating layer in the first via V1 are etched away, exposing the surface of the first region of the first active layer (which is also the first region of the second active layer). The first via V1 is configured to enable a reference signal line formed subsequently to be connected to the first region of the first active layer (which is also the first region of the second active layer) through the via. In an exemplary embodiment, the first via V1 can be referred to as the first active via.

[0269] In an exemplary embodiment, the positive projection of the second via V2 on the substrate is within the range of the positive projection of the second region of the first active layer (which is also the first region of the sixth active layer) on the substrate. The third insulating layer and the fourth insulating layer in the second via V2 are etched away to expose the surface of the second region of the first active layer (which is also the first region of the sixth active layer). The second via V2 is configured to enable the first connection electrode formed subsequently to be connected to the second region of the first active layer (which is also the first region of the sixth active layer) through this via.

[0270] In an exemplary embodiment, the positive projection of the third via V3 on the substrate is within the range of the positive projection of the second region of the second active layer on the substrate. The third insulating layer and the fourth insulating layer in the third via V3 are etched away to expose the surface of the second region of the second active layer. The third via V3 is configured to enable the fourth connection electrode formed subsequently to be connected to the second region of the second active layer through this via.

[0271] In an exemplary embodiment, the positive projection of the fourth via V4 on the substrate is within the range of the positive projection of the first region of the fourth active layer on the substrate. The third insulating layer and the fourth insulating layer in the fourth via V4 are etched away to expose the surface of the first region of the fourth active layer. The fourth via V4 is configured to enable the fifth connection electrode formed subsequently to be connected to the first region of the fourth active layer through this via.

[0272] In an exemplary embodiment, the positive projection of the fifth via V5 on the substrate is within the range of the positive projection of the first region of the fifth active layer on the substrate. The third insulating layer and the fourth insulating layer in the fifth via V5 are etched away to expose the surface of the first region of the fifth active layer. The fifth via V5 is configured to enable the first power connection line formed subsequently to be connected to the first region of the fifth active layer through this via.

[0273] In an exemplary embodiment, the positive projection of the sixth via V6 on the substrate is within the range of the positive projection of the second region of the third active layer (which is also the second region of the seventh active layer) on the substrate. The third insulating layer and the fourth insulating layer in the sixth via V6 are etched away to expose the surface of the second region of the third active layer (which is also the second region of the seventh active layer). The sixth via V6 is configured to enable the third connection electrode formed subsequently to be connected to the first region of the second region of the third active layer (which is also the second region of the seventh active layer) through this via.

[0274] In an exemplary embodiment, the positive projection of the seventh via V7 on the substrate is within the range of the positive projection of the first region of the seventh active layer on the substrate. The third insulating layer and the fourth insulating layer in the seventh via V7 are etched away to expose the surface of the first region of the seventh active layer. The seventh via V7 is configured to enable the initially formed signal line to be connected to the first region of the seventh active layer through this via. In an exemplary embodiment, the seventh via V7 can be referred to as the seventh active via.

[0275] In an exemplary embodiment, the positive projection of the eighth via V8 on the substrate is within the range of the positive projection of the first bottom gate connection block 21-1 on the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer in the eighth via V8 are etched away to expose the surface of the first bottom gate connection block 21-1. The eighth via V8 is configured to enable the subsequently formed first scan signal line to be connected to the first bottom gate connection block 21-1 through this via.

[0276] In an exemplary embodiment, since the first bottom gate electrodes 21 of two circuit units share the same first bottom gate connection block 21-1, the two circuit units can share the same eighth via V8, which can effectively reduce the occupied space of the pixel driving circuit and is beneficial to the compression of the circuit units. In an exemplary embodiment, the eighth via V8 can be referred to as the first bottom gate connection via.

[0277] In an exemplary embodiment, the positive projection of the ninth via V9 on the substrate is within the range of the positive projection of the first top gate connection block 41-1 on the substrate. The fourth insulating layer in the ninth via V9 is etched away to expose the surface of the first top gate connection block 41-1. The ninth via V9 is configured to enable the subsequently formed first scan signal line to be connected to the first top gate connection block 41-1 through this via.

[0278] In an exemplary embodiment, since the first top gate electrodes 41 of two circuit units share the same first top gate connection block 41-1, the two circuit units can share the same ninth via V9, which can effectively reduce the occupied space of the pixel driving circuit and is beneficial to the compression of the circuit units. In an exemplary embodiment, the ninth via V9 can be referred to as the first top gate connection via.

[0279] In an exemplary embodiment, the positive projection of the tenth via V10 on the substrate is within the range of the positive projection of the fourth bottom gate connection block 24-1 on the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer in the tenth via V10 are etched away to expose the surface of the fourth bottom gate connection block 24-1. The tenth via V10 is configured to enable the subsequently formed third scan signal line to be connected to the fourth bottom gate connection block 24-1 through this via.

[0280] In an exemplary embodiment, since the fourth bottom gate electrodes 24 of two circuit units share the same fourth bottom gate connection block 24-1, the two circuit units can share the same tenth via V10, which can effectively reduce the occupied space of the pixel driving circuit and is beneficial to the compression of the circuit units. In an exemplary embodiment, the tenth via V10 may be referred to as the fourth bottom gate connection via.

[0281] In an exemplary embodiment, the positive projection of the eleventh via V11 on the substrate is within the range of the positive projection of the fourth top gate connection block 44-1 on the substrate. The fourth insulating layer within the eleventh via V11 is etched away to expose the surface of the fourth top gate connection block 44-1. The eleventh via V11 is configured to connect the third scanning signal line formed subsequently to the fourth top gate connection block 44-1 through this via.

[0282] In an exemplary embodiment, since the fourth top gate electrodes 44 of two circuit units share the same fourth top gate connection block 44-1, the two circuit units can share the same eleventh via V11, which can effectively reduce the occupied space of the pixel driving circuit and is beneficial to the compression of the circuit units. In an exemplary embodiment, the eleventh via V11 may be referred to as the fourth top gate connection via.

[0283] In an exemplary embodiment, the positive projection of the twelfth via V12 on the substrate is within the range of the positive projection of the sixth bottom gate connection block 26-1 on the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer within the twelfth via V12 are etched away to expose the surface of the sixth bottom gate connection block 26-1. The twelfth via V12 is configured to connect the fourth scanning signal line formed subsequently to the sixth bottom gate connection block 26-1 through this via.

[0284] In an exemplary embodiment, since the sixth bottom gate electrodes 26 of two circuit units share the same sixth bottom gate connection block 26-1, the two circuit units can share the same twelfth via V12, which can effectively reduce the occupied space of the pixel driving circuit and is beneficial to the compression of the circuit units. In an exemplary embodiment, the twelfth via V12 may be referred to as the sixth bottom gate connection via.

[0285] In an exemplary embodiment, the positive projection of the thirteenth via V13 on the substrate is within the range of the positive projection of the sixth top gate connection block 46-1 on the substrate. The fourth insulating layer within the thirteenth via V13 is etched away to expose the surface of the sixth top gate connection block 46-1. The thirteenth via V13 is configured to connect the fourth scanning signal line formed subsequently to the sixth top gate connection block 46-1 through this via.

[0286] In an exemplary embodiment, since the sixth top gate electrodes 46 of two circuit units share the same sixth top gate connection block 46-1, the two circuit units can share the same thirteenth via V13, which can effectively reduce the occupied space of the pixel driving circuit and is beneficial to the compression of the circuit units. In an exemplary embodiment, the thirteenth via V13 may be referred to as the sixth top gate connection via.

[0287] In an exemplary embodiment, the positive projection of the fourteenth via V14 on the substrate is within the range of the positive projection of the third top gate electrode 43 on the substrate. The fourth insulating layer in the fourteenth via V14 is etched away to expose the surface of the third top gate electrode 43. The fourteenth via V14 is configured to enable the subsequently formed first connection electrode 51 to be connected to the third top gate electrode 43 through this via.

[0288] In an exemplary embodiment, the positive projection of the fifteenth via V15 on the substrate is within the range of the positive projection of the fourth electrode plate 14 on the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer in the fifteenth via V15 are etched away to expose the surface of the fourth electrode plate 14. The fifteenth via V15 is configured to enable the subsequently formed second connection electrode to be connected to the fourth electrode plate 14 through this via.

[0289] In an exemplary embodiment, the positive projection of the sixteenth via V16 on the substrate is within the range of the positive projection of the electrode plate connection block 15 on the substrate. The fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer in the sixteenth via V16 are etched away to expose the surface of the electrode plate connection block 15. The sixteenth via V16 is configured to enable the subsequently formed fourth connection electrode to be connected to the electrode plate connection block 15 through this via.

[0290] In an exemplary embodiment, the positive projection of the seventeenth via V17 on the substrate is within the range of the positive projection of the second region of the fourth active layer (which is also the second region of the sixth active layer) on the substrate. The third insulating layer and the fourth insulating layer in the seventeenth via V17 are etched away to expose the surface of the second region of the fourth active layer (which is also the second region of the sixth active layer). The seventeenth via V17 is configured to enable the subsequently formed second connection electrode to be connected to the second region of the fourth active layer (which is also the second region of the sixth active layer) through this via.

[0291] In an exemplary embodiment, the positive projection of the eighteenth via V18 on the substrate is within the range of the positive projection of the second electrode plate 12 on the substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer in the eighteenth via V18 are etched away to expose the surface of the second electrode plate 12. The eighteenth via V18 is configured to enable the subsequently formed third connection electrode to be connected to the second electrode plate 12 through this via.

[0292] (16) Form a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive thin film on the substrate on which the foregoing pattern is formed, and patterning the fourth conductive thin film using a patterning process to form a fourth conductive layer disposed on the fourth insulating layer, as Figure 14A and Figure 14B shown Figure 14B is Figure 14A a schematic plan view of the fourth conductive layer in

[0293] In an exemplary embodiment, the fourth conductive layer of each circuit unit at least includes: a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55, a first scan signal line 61, a third scan signal line 63, a fourth scan signal line 64, a reference signal line 66, an initial signal line 67, and a first power connection line 68.

[0294] In an exemplary embodiment, the shapes of the first scan signal line 61, the third scan signal line 63, the fourth scan signal line 64, the reference signal line 66, the initial signal line 67, and the first power connection line 68 may be linear or polygonal lines extending along the first direction X, and are continuously arranged in one unit row. The third scan signal line 63, the fourth scan signal line 64, and the first power connection line 68 may be located on one side opposite to the second direction Y of the third top gate electrode 43, and the first scan signal line 61, the reference signal line 66, and the initial signal line 67 may be located on one side of the third top gate electrode 43 in the second direction Y.

[0295] In an exemplary embodiment, the fourth scan signal line 64 may be located on one side opposite to the second direction Y of the third top gate electrode 43, the third scan signal line 63 may be located on one side of the fourth scan signal line 64 away from the third top gate electrode 43, and the first power connection line 68 may be located on one side of the third scan signal line 63 away from the third top gate electrode 43.

[0296] In an exemplary embodiment, the first scan signal line 61 may be located on one side of the third top gate electrode 43 in the second direction Y, the reference signal line 66 may be located on one side of the first scan signal line 61 away from the third top gate electrode 43, and the initial signal line 67 may be located on one side of the reference signal line 66 away from the third top gate electrode 43.

[0297] In an exemplary embodiment, the positive projection of the first scan signal line 61 on the substrate at least partially overlaps with the positive projections of the first bottom gate electrode 21, the second bottom gate electrode 22, the first top gate electrode 41, and the second top gate electrode 42 on the substrate. On the one hand, the first scan signal line 61 is connected to the first bottom gate connection block 21-1 through the eighth via V8, and on the other hand, it is connected to the first top gate connection block 41-1 through the ninth via V9. Since the first bottom gate connection block 21-1 is respectively connected to the first bottom gate electrode 21 and the second bottom gate electrode 22, and the first top gate connection block 41-1 is respectively connected to the first top gate electrode 41 and the second top gate electrode 42, the connection of the first scan signal line 61 to the bottom gate electrode of the first transistor T1, the top gate electrode of the first transistor T1, the bottom gate electrode of the second transistor T2, and the top gate electrode of the second transistor T2 is realized. The first scan signal line 61 can control the conduction or disconnection of the first transistor T1 and the second transistor T2 simultaneously.

[0298] In an exemplary embodiment, the positive projection of the third scan signal line 63 on the substrate at least partially overlaps with the positive projections of the fourth bottom gate electrode 24 and the fourth top gate electrode 44 on the substrate. On the one hand, the third scan signal line 63 is connected to the fourth bottom gate connection block 24-1 through the tenth via V10, and on the other hand, it is connected to the fourth top gate connection block 44-1 through the eleventh via V11. Since the fourth bottom gate connection block 24-1 is connected to the fourth bottom gate electrode 24, and the fourth top gate connection block 44-1 is connected to the fourth top gate electrode 44, the connection of the third scan signal line 63 to the bottom gate electrode of the fourth transistor T4 and the top gate electrode of the fourth transistor T4 is realized. The third scan signal line 63 can control the conduction or disconnection of the fourth transistor T4.

[0299] In an exemplary embodiment, the positive projection of the fourth scan signal line 64 on the substrate at least partially overlaps with the positive projections of the sixth bottom gate electrode 26 and the sixth top gate electrode 46 on the substrate. On the one hand, the fourth scan signal line 64 is connected to the sixth bottom gate connection block 26-1 through the twelfth via V12, and on the other hand, it is connected to the sixth top gate connection block 46-1 through the thirteenth via V13. Since the sixth bottom gate connection block 26-1 is connected to the sixth bottom gate electrode 26, and the sixth top gate connection block 46-1 is connected to the sixth top gate electrode 46, the connection of the fourth scan signal line 64 to the bottom gate electrode of the sixth transistor T6 and the top gate electrode of the sixth transistor T6 is realized. The fourth scan signal line 64 can control the conduction or disconnection of the sixth transistor T6.

[0300] In an exemplary embodiment, the present disclosure effectively reduces the resistance of the scan signal lines and the voltage drop of the scan signals by disposing the first scan signal line 61, the third scan signal line 63, and the fourth scan signal line 64 in the first source-drain metal (SD1) layer, which can improve the compensation speed and the display quality.

[0301] In an exemplary embodiment, the reference signal line 66 is connected to the first region of the first active layer (which is also the first region of the second active layer) in each circuit unit through the first via V1, so that the reference signal line 66 can write the reference signal into the first pole of the first transistor T1 and the first pole of the second transistor T2 simultaneously.

[0302] In an exemplary embodiment, the orthographic projection of the reference signal line 66 on the substrate at least partially overlaps with the orthographic projection of the second scan signal line 62 on the substrate. The reference signal line 66 with a constant voltage signal can effectively shield the interference of other signals in the pixel driving circuit to the second scan signal line 62, improving the transmission quality of the second scan signal.

[0303] In an exemplary embodiment, the initial signal line 67 is connected to the first region of the seventh active layer in each circuit unit through the seventh via V7, so that the initial signal line 67 can write the initial signal into the first pole of the seventh transistor T7.

[0304] In an exemplary embodiment, the first power connection line 68 is connected to the first region of the fifth active layer through the fifth via V5. Since the first power connection line 68 is connected to the first power supply line formed subsequently, the first power supply line can write the first power supply signal into the first pole of the fifth transistor T5.

[0305] In an exemplary embodiment, a first power connection block 68-1 may be connected to the first power connection line 68, and the first power connection block 68-1 is configured to be connected to the first power supply line formed subsequently. In an exemplary embodiment, the first power connection line 68 may be disposed in each circuit unit respectively.

[0306] In an exemplary embodiment, the shape of the first connection electrode 51 may be a strip shape with the main body part extending along the first direction X. The first end of the first connection electrode 51 is connected to the second region of the first active layer (which is also the first region of the sixth active layer) through the second via V2, and the second end of the first connection electrode 51 is connected to the third top gate electrode 43 through the fourteenth via V14. In an exemplary embodiment, the first connection electrode 51 realizes the mutual connection between the second pole of the first transistor T1, the gate electrode of the third transistor T3, and the first pole of the sixth transistor T6, forming the first node N1 of the pixel driving circuit.

[0307] In an exemplary embodiment, the shape of the second connection electrode 52 may be a strip shape extending along the first direction X. The first end of the second connection electrode 52 is connected to the second region of the fourth active layer (which is also the second region of the sixth active layer) through the seventeenth via hole V17, and the second end of the second connection electrode 52 is connected to the fourth electrode plate 14 through the fifteenth via hole V15. In an exemplary embodiment, the second connection electrode 52 realizes the mutual connection between the second pole of the fourth transistor T4, the second pole of the sixth transistor T6, and the fourth electrode plate 14 of the second capacitor, forming the second node N2 of the pixel driving circuit.

[0308] In an exemplary embodiment, the shape of the third connection electrode 53 may be an "L" shape. The first end of the third connection electrode 53 is connected to the second region of the third active layer (which is also the second region of the seventh active layer) through the sixth via hole V6, and the second end of the third connection electrode 53 is connected to the second electrode plate 12 through the eighteenth via hole V18. In an exemplary embodiment, the third connection electrode 53 realizes the mutual connection between the second pole of the third transistor T3, the second pole of the seventh transistor T7, and the second electrode plate 12 (upper electrode plate) of the first capacitor, forming the third node N3 of the pixel driving circuit. In an exemplary embodiment, the third connection electrode 53 is configured to be connected to an anode connection electrode formed subsequently.

[0309] In an exemplary embodiment, the shape of the fourth connection electrode 54 may be a block shape (such as a rectangle). The first end of the fourth connection electrode 54 is connected to the second region of the second active layer through the third via hole V3, and the second end of the fourth connection electrode 54 is connected to the electrode plate connection block 15 through the sixteenth via hole V16. Since the electrode plate connection block 15 is connected to the first electrode plate 11 and the third electrode plate 13, the fourth connection electrode 54 realizes the mutual connection between the second pole of the second transistor T2, the first electrode plate 11 (lower electrode plate) of the first capacitor, and the third electrode plate 13 (lower electrode plate) of the second capacitor, forming the fourth node N4 of the pixel driving circuit.

[0310] In an exemplary embodiment, since the first electrode plate 11 and the third electrode plate 13 are connected to each other and connected to the second pole of the second transistor T2 through the fourth connection electrode 54, the first electrode plate 11 and the third electrode plate 13 have the potential of the fourth node N4 in the pixel driving circuit. Since the second electrode plate 12 is connected to the second poles of the third transistor T3 and the seventh transistor T7 through the third connection electrode 53, the second electrode plate 12 has the potential of the third node N3 in the pixel driving circuit. Since the fourth electrode plate 14 is connected to the second poles of the fourth transistor T4 and the sixth transistor T6 through the second connection electrode 52, the fourth electrode plate 14 has the potential of the second node N2 in the pixel driving circuit. In this way, the first electrode plate 11 having the potential of the fourth node N4 and the second electrode plate 12 having the potential of the third node N3 form a first capacitor, and the third electrode plate 13 having the potential of the fourth node N4 and the fourth electrode plate 14 having the potential of the second node N2 form a second capacitor.

[0311] In an exemplary embodiment, the shape of the fifth connection electrode 55 may be a strip shape in which the main body portion extends along the first direction X. The first end of the fifth connection electrode 55 is connected to the first region of the fourth active layer through the fourth via V4. The second end of the fifth connection electrode 55 extends in a direction away from the fourth transistor T4, and the second end of the fifth connection electrode 55 is configured to be connected to a data signal line formed subsequently.

[0312] In an exemplary embodiment, the fourth conductive layer of at least one circuit unit may further include a first data connection line 81. The shape of the first data connection line 81 may be a straight line shape or a broken line shape extending along the first direction X, and may be disposed in the lateral routing space between some adjacent unit rows.

[0313] In an exemplary embodiment, a first break K1 may be provided on at least one first data connection line 81. The first break K1 may cut off the first data connection line 81 so that the first data connection lines 81 on both sides of the first break K1 are insulated from each other.

[0314] In an exemplary embodiment, the first data connection line 81 may include a first connection sub-line 81-1 and a second connection sub-line 81-2 respectively located on both sides of the first break K1 in the first direction X. The first connection sub-line 81-1 is configured to be connected to the data signal line in the display area, and the second connection sub-line 81-2 is configured as a first dummy line.

[0315] In an exemplary embodiment, the first connecting sub-line 81-1 may be located on one side of the first break K1 in the first direction X, and the second connecting sub-line 81-2 may be located on the other side of the first break K1 in the opposite direction of the first direction X. In another exemplary embodiment, the first connecting sub-line 81-1 may be located on the other side of the first break K1 in the opposite direction of the first direction X, and the second connecting sub-line 81-2 may be located on one side of the first break K1 in the first direction X.

[0316] In an exemplary embodiment, at least one data connection block 83 and a data connection electrode 84 may be provided on the first connecting sub-line 81-1. The data connection block 83 may be in a strip shape extending along the second direction Y, and the data connection electrode 84 may be in a block shape (such as a rectangle). The data connection block 83 and the data connection electrode 84 may be provided on one side of the first connecting sub-line 81-1 in the second direction Y, and the data connection block 83 is provided between the first connecting sub-line 81-1 and the data connection electrode 84. The first end of the data connection block 83 is connected to the first connecting sub-line 81-1, and the second end of the data connection block 83 is connected to the data connection electrode 84. The data connection electrode 84 is configured to be connected to a second data connection line formed subsequently.

[0317] In an exemplary embodiment, the data connection block 83 and the data connection electrode 84 may be provided in a vertical routing space between some adjacent unit columns. For example, the data connection block 83 and the data connection electrode 84 may be located in the vertical routing space between the Nth unit column and the (N + 1)th unit column. Another example is that the data connection block 83 and the data connection electrode 84 may be located in the vertical routing space between the (N + 1)th unit column and the (N + 2)th unit column.

[0318] In an exemplary embodiment, the first connecting sub-line 81-1, the data connection block 83, and the data connection electrode 84 may be an integrally connected structure.

[0319] In an exemplary embodiment, the fourth conductive layer may further include at least one dummy electrode 85. The dummy electrode 85 may be in a block shape (such as a rectangle), may be provided in the vertical routing space between some adjacent unit columns, and the dummy electrode 85 is configured to be connected to a second data connection line formed subsequently. For example, the dummy electrode 85 may be located in the vertical routing space between the Nth unit column and the (N + 1)th unit column. Another example is that the dummy electrode 85 may be located in the vertical routing space between the (N + 1)th unit column and the (N + 2)th unit column.

[0320] In an exemplary embodiment, the position and shape of the dummy electrode 85 in the circuit unit may be substantially the same as the position and shape of the data connection electrode 84 in the circuit unit. The difference is that the dummy electrode 85 is isolated and is neither connected to the first data connection line 81 nor to other electrodes. In an exemplary embodiment, the dummy electrode 85 and the data connection electrode 84 have the same morphology and via connection structure. Through the same design of the transfer region, not only can the uniformity of the subsequent etching process be improved, but also the same display effect can be achieved in different regions under transmitted and reflected light, effectively achieving shadow elimination, effectively avoiding the appearance defects of the display substrate, and improving the display quality and display performance.

[0321] In an exemplary embodiment, in the first direction X, the data connection electrode 84 and the dummy electrode 85 may be disposed between two adjacent first power connection blocks 68-1 in the first direction X. In the second direction Y, the positions of the data connection electrode 84 and the dummy electrode 85 may be substantially flush with the positions of the first power connection blocks 68-1.

[0322] In an exemplary embodiment, in one unit row, the fourth conductive layers (except for the first data connection line and the data connection block) in two adjacent circuit units may be symmetrically disposed with respect to the column center line. For example, the fourth conductive layers of the Nth unit column and the (N + 1)th unit column may be symmetrically disposed with respect to the column center line. Another example is that the fourth conductive layers of the (N + 1)th unit column and the (N + 2)th unit column may be symmetrically disposed with respect to the column center line.

[0323] In an exemplary embodiment, the fourth conductive layers (except for the first data connection line and the data connection block) in adjacent unit rows may be substantially the same.

[0324] (17) Form a first planarization layer pattern. In an exemplary embodiment, forming the first planarization layer pattern may include: coating a first planarization film on the substrate on which the foregoing pattern is formed, and patterning the first planarization film using a patterning process to form a first planarization layer covering the fourth conductive layer pattern. A plurality of vias are provided on the first planarization layer, as Figure 15 shown.

[0325] In an exemplary embodiment, the plurality of vias in each circuit unit at least include: the twenty-first via V21, the twenty-second via V22, and the twenty-third via V23.

[0326] In an exemplary embodiment, the orthographic projection of the twenty-first via V21 on the substrate is located within the range of the orthographic projection of the first power connection block 68-1 on the substrate, the first flat layer in the twenty-first via V21 is removed to expose the surface of the first power connection block 68-1, and the twenty-first via V21 is configured to connect a subsequently formed first power line to the first power connection block 68-1 through the via.

[0327] In an exemplary embodiment, the orthographic projection of the twenty-second via hole V22 on the substrate is located within the range of the orthographic projection of the second end of the fifth connecting electrode 55 on the substrate, the first flat layer in the twenty-second via hole V22 is removed to expose the surface of the second end of the fifth connecting electrode 55, and the twenty-second via hole V22 is configured to connect a subsequently formed data signal line to the second end of the fifth connecting electrode 55 through the via hole.

[0328] In an exemplary embodiment, the orthographic projection of the twenty-third via hole V23 on the substrate is located within the range of the orthographic projection of the third connecting electrode 53 on the substrate, the first flat layer in the twenty-third via hole V23 is removed to expose the surface of the third connecting electrode 53, and the twenty-third via hole V23 is configured to connect a subsequently formed anode connecting electrode to the third connecting electrode 53 through the via hole.

[0329] In an exemplary embodiment, the plurality of via holes on the first planar layer may further include a twenty-fourth via hole V24 and a twenty-fifth via hole V25 .

[0330] In an exemplary embodiment, the orthographic projection of the twenty-fourth via hole V24 on the substrate is within the range of the orthographic projection of the data connection electrode 84 on the substrate, the first flat layer in the twenty-fourth via hole V24 is removed, exposing the surface of the data connection electrode 84, and the twenty-fourth via hole V24 is configured to connect the third connection sub-line in the second data connection line formed subsequently to the data connection electrode 84 through the via hole. In an exemplary embodiment, the twenty-fourth via hole V24 can be called a data transfer via hole.

[0331] In an exemplary embodiment, the orthographic projection of the twenty-fifth via hole V25 on the substrate is within the range of the orthographic projection of the dummy electrode 85 on the substrate, the first flat layer in the twenty-fifth via hole V25 is removed to expose the surface of the dummy electrode 85, and the twenty-fifth via hole V25 is configured to connect the fourth connecting sub-line in the second data connecting line formed subsequently to the dummy electrode 85 through the via hole.

[0332] In an exemplary embodiment, in the first direction X, the twenty-fourth via V24 and the twenty-fifth via V25 may be disposed between two adjacent twenty-first vias V21 in the first direction X. In the second direction Y, the positions of the twenty-fourth via V24 and the twenty-fifth via V25 may be substantially flush with the positions of the twenty-first vias V21, that is, both the twenty-fourth via V24 and the twenty-fifth via V25 are disposed within the circuit unit range. By hiding the data transfer vias in the circuit unit, the present disclosure can effectively achieve shadow elimination, effectively avoid the appearance defects of the display substrate, and improve the display quality and display performance.

[0333] (18) Form a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer may include: depositing a fifth conductive thin film on the substrate on which the foregoing pattern is formed, and patterning the fifth conductive thin film using a patterning process to form a fifth conductive layer disposed on the first flat layer, as Figure 16A and Figure 16B shown, Figure 16B is Figure 16A a plan view of the fifth conductive layer in

[0334] In an exemplary embodiment, the fifth conductive layer of each circuit unit at least includes: a first power supply line 71, a second power supply line 72, a data signal line 73, and an anode connection electrode 74.

[0335] In an exemplary embodiment, the shape of the first power supply line 71 may be a straight line or a broken line with a main body portion extending along the second direction Y, and the first power supply line 71 is connected to the first power supply connection block 68-1 through the twenty-first via V21. Since the first power supply connection block 68-1 is connected to the first power supply connection line 68, and the first power supply connection line 68 is connected to the first region of the fifth active layer, the connection between the first power supply line 71 and the first pole of the fifth transistor T5 is realized, and the first power supply line 71 can write the first power supply signal into the first pole of the fifth transistor T5.

[0336] In an exemplary embodiment, since the first power supply line 71 is connected to the first power supply connection line 68, the connection between the first power supply connection line 68 with a main body portion extending along the first direction X and the first power supply line 71 with a main body portion extending along the second direction Y is realized. The first power supply line 71 and the first power supply connection line 68 form a grid structure for transmitting the first power supply signal with a mesh-like communication structure on the display substrate, which can not only effectively reduce the resistance of the first power supply line, reduce the voltage drop of the first power supply signal, but also effectively improve the uniformity of the first power supply signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0337] In an exemplary embodiment, the first power supply connection line 68 in the fourth conductive layer may be disposed in each unit row, and the first power supply line 71 of the fifth conductive layer may be disposed in each unit column. The plurality of first power supply lines 71 are respectively connected to the plurality of first power supply connection lines 68 to form a mesh structure for transmitting the first power signal.

[0338] In an exemplary embodiment, the orthographic projection of the first power supply line 71 on the substrate at least partially overlaps with the orthographic projections of the first active layer, the fourth active layer, and the sixth active layer on the substrate. That is, the orthographic projection of the first power supply line 71 on the substrate at least partially overlaps with the orthographic projections of the first transistor T1, the fourth transistor T4, and the sixth transistor T6 on the substrate. The first power supply line 71 can block the light emission of the light-emitting device and the reflected light of the film layer from irradiating the oxide first transistor T1, the fourth transistor T4, and the sixth transistor T6, and can prevent the characteristics of the oxide transistor from drifting due to light irradiation, thereby improving the electrical characteristics of the oxide transistor.

[0339] In an exemplary embodiment, the shape of the second power supply line 72 may be linear or polygonal with a main body extending along the second direction Y, and may be disposed between the first power supply line 71 and the data signal line 73.

[0340] In an exemplary embodiment, the orthographic projection of the second power supply line 72 on the substrate at least partially overlaps with the orthographic projections of the third active layer, the fifth active layer, and the seventh active layer on the substrate. That is, the orthographic projection of the second power supply line 72 on the substrate at least partially overlaps with the orthographic projections of the third transistor T3, the fifth transistor T5, and the seventh transistor T7 on the substrate. The second power supply line 72 can block the light emission of the light-emitting device and the reflected light of the film layer from irradiating the oxide third transistor T3, the fifth transistor T5, and the seventh transistor T7, and can prevent the characteristics of the oxide transistor from drifting due to light irradiation, thereby improving the electrical characteristics of the oxide transistor.

[0341] In an exemplary embodiment, the width of the second power supply line 72 may be greater than the width of the first power supply line 71, and the width may be the dimension in the first direction X. By providing the second power supply line 72 with a wider wiring, the present disclosure not only effectively reduces the resistance of the second power supply line 72, reduces the voltage drop of the transmitted second power signal, but also effectively improves the uniformity of the second power signal in the display substrate, effectively improves the display uniformity, and improves the display quality and display performance.

[0342] In an exemplary embodiment, the data signal line 73 may be linear or zigzag with its main body extending along the second direction Y, and the data signal line 73 is connected to the second end of the fifth connection electrode 55 through the twenty-second via V22. Since the first end of the fifth connection electrode 55 is connected to the first region of the fourth active layer through a via, the data signal line 73 can write a data signal to the first pole of the fourth transistor T4.

[0343] In an exemplary embodiment, the orthographic projection of the data signal line 73 on the substrate does not overlap with the orthographic projections of the channel regions of the first transistor T1 to the seventh transistor T7 on the substrate, which can avoid signal crosstalk caused by data voltage jumps of the data signal line 73, avoid the influence of data voltage jumps on the first transistor T1 to the seventh transistor T7, improve the working stability of the pixel driving circuit, and improve the display effect.

[0344] In an exemplary embodiment, the anode connection electrode 74 may be in a block shape (such as a rectangle), the anode connection electrode 74 is connected to the third connection electrode 53 through the twenty-third via V23, and the anode connection electrode 74 is configured to be connected to an anode formed later. Since the third connection electrode 53 is connected to the second region of the third active layer (which is also the second region of the seventh active layer) through a via, the pixel driving circuit can output a driving current to the light-emitting device.

[0345] In an exemplary embodiment, the fifth conductive layer of at least one circuit unit may further include a second data connection line 82.

[0346] In an exemplary embodiment, the second data connection line 82 may be linear or zigzag with its main body extending along the second direction Y, and may be disposed in the vertical routing space between some adjacent unit columns.

[0347] In an exemplary embodiment, the second data connection line 82 may be disposed between the first power supply lines 71 of adjacent unit columns. For example, the second data connection line 82 may be disposed between the first power supply line 71 of the Nth unit column and the first power supply line 71 of the (N + 1)th unit column. Another example is that the second data connection line 82 may be disposed between the first power supply line 71 of the (N + 2)th unit column and the first power supply line 71 of the (N + 3)th unit column. By disposing the second data connection line 82 between two first power supply lines 71, the first power supply line 71 having a constant voltage signal can serve as a shield line, avoid the influence of data voltage jumps on the pixel driving circuit, improve the working stability of the pixel driving circuit, and improve the display effect.

[0348] In an exemplary embodiment, a second break K2 may be provided on at least one second data connection line 82. The second break K2 may cut off the second data connection line 82, such that the second data connection lines 82 on both sides of the second break K2 are insulated from each other.

[0349] In an exemplary embodiment, the second data connection line 82 may include a third connection sub-line 82-3 and a fourth connection sub-line 82-4 respectively located on both sides of the second direction Y of the second break K2. The third connection sub-line 82-3 is configured to be connected to a data lead in the bonding area, and the fourth connection sub-line 82-4 is configured as a second dummy line.

[0350] In an exemplary embodiment, the third connection sub-line 82-3 may be located on one side of the second direction Y of the second break K2 (the side close to the bonding area), and the fourth connection sub-line 82-4 may be located on the side opposite to the second direction Y of the second break K2 (the side far from the bonding area).

[0351] In an exemplary embodiment, the orthographic projection of at least one second break K2 on the substrate at least partially overlaps with the orthographic projection of at least one reference signal line 66 on the substrate, or the orthographic projection of at least one second break K2 on the substrate at least partially overlaps with the orthographic projection of at least one initial signal line 67 on the substrate.

[0352] In an exemplary embodiment, the orthographic projection of at least one second break K2 on the substrate may be located within the range of the orthographic projection of at least one reference signal line 66 on the substrate. The second break K2 can be padded by the reference signal line 66 to effectively eliminate the film layer difference in different regions and avoid the appearance defect of the display substrate. Alternatively, the orthographic projection of at least one second break K2 on the substrate may be located within the range of the orthographic projection of at least one initial signal line 67 on the substrate. The second break K2 can be padded by the initial signal line 67 to effectively eliminate the film layer difference in different regions and avoid the appearance defect of the display substrate.

[0353] In an exemplary embodiment, the third connection sub-line 82-3 can be connected to the data connection electrode 84 through the twenty-fourth via V24. Since the data connection electrode 84 is connected to the first connection sub-line 81-1 in the first data connection line 81 through the data connection block 83, the first data connection line 81 extending along the first direction X of the main body portion is interconnected with the second data connection line 82 extending along the second direction Y of the main body portion. Since the first connection sub-line 81-1 in the first data connection line 81 is configured to be connected to the data signal line in the display area, and the third connection sub-line 82-3 is configured to be connected to the data lead in the bonding area, the interconnection between the first connection sub-line 81-1 and the third connection sub-line 82-3 enables the data lead in the bonding area to be connected to the data signal line in the display area through the first data connection line 81 and the second data connection line 82.

[0354] In an exemplary embodiment, the fourth connection sub-line 82-4 can be connected to the dummy electrode 85 through the twenty-fifth via V25. In an exemplary embodiment, since the morphology of the dummy electrode is substantially the same as that of the data connection electrode 84, and the morphology of the twenty-fifth via V25 is substantially the same as that of the twenty-fourth via V24, the connection structure of the third connection sub-line 82-3 connected to the data connection electrode 84 through the via and the connection structure of the fourth connection sub-line 82-4 connected to the dummy electrode 85 through the via are substantially the same. This can not only improve the uniformity of the subsequent etching process, but also enable the same display effect to be achieved under transmitted and reflected light in different regions, effectively realizing shadow elimination, effectively avoiding appearance defects of the display substrate, and improving the display quality and display performance.

[0355] In an exemplary embodiment, the orthographic projection of at least one first power line 71 on the substrate at least partially overlaps with the orthographic projection of the first break K1 on the substrate, or the orthographic projection of at least one second power line 72 on the substrate can include the orthographic projection of the first break K1 on the substrate.

[0356] In an exemplary embodiment, the orthographic projection of at least one first break K1 on the substrate can be located within the range of the orthographic projection of at least one first power line 71 on the substrate, that is, the first break K1 is covered by the first power line 71. By using the first power line 71 to block the first break K1, the film layer difference between different regions can be effectively eliminated, and the appearance defect of the display substrate can be avoided. Alternatively, the orthographic projection of at least one first break K1 on the substrate can be located within the range of the orthographic projection of at least one second power line 72 on the substrate, that is, the first break K1 is covered by the second power line 72. By using the second power line 72 to block the first break K1, the film layer difference between different regions can be effectively eliminated, and the appearance defect of the display substrate can be avoided.

[0357] The subsequent fabrication process may include forming a second planar layer, on which an anode via is provided. The anode via exposes the surface of the anode connection electrode 74 and is configured to enable the subsequent formation of the anode to be connected to the anode connection electrode 74 through the via.

[0358] Thus far, the driving circuit layer of this embodiment has been fabricated on the substrate. In a plane parallel to the display substrate, the driving circuit layer may include a plurality of circuit units, and each circuit unit may include a pixel driving circuit, and a first scan signal line, a second scan signal line, a third scan signal line, a fourth scan signal line, a light-emitting signal line, a reference signal line, an initial signal line, a first power supply line, a second power supply line, and a data signal line connected to the pixel driving circuit.

[0359] In a plane perpendicular to the display substrate, the driving circuit layer may include a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, a semiconductor layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a fourth conductive layer, a first planar layer, a fifth conductive layer, and a second planar layer sequentially provided on the substrate. The first conductive layer may at least include the first electrode plate of the first capacitor and the third electrode plate of the second capacitor. The second conductive layer may at least include the second electrode plate of the first capacitor, the fourth electrode plate of the second capacitor, a first shielding line, a second shielding line, and a plurality of bottom gate electrodes. The semiconductor layer may at least include the active layers of a plurality of transistors. The third conductive layer may at least include the second scan signal line, the light-emitting signal line, and a plurality of top gate electrodes. The fourth conductive layer may at least include the first scan signal line, the third scan signal line, the fourth scan signal line, the reference signal line, the initial signal line, a first power supply connection line, and a plurality of connection electrodes. The fifth conductive layer may at least include the first power supply line, the second power supply line, and the data signal line.

[0360] In an exemplary embodiment, the fourth conductive layer may further include a first data connection line, and the fifth conductive layer may further include a second data connection line.

[0361] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may include, but is not limited to, one or more of glass and quartz. The flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on a glass carrier. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, etc. The materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the substrate. The first and second inorganic material layers are also called barrier layers. The material of the semiconductor layer may be amorphous silicon (a-si).

[0362] In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multi-layer, or a composite layer. The first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer may be made of a metal material, such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), or molybdenum (Mo), etc., or may be made of an alloy material composed of metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), etc. It may be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti, etc. The first planarization layer and the second planarization layer may be made of an organic material, such as a resin or polyimide.

[0363] In an exemplary embodiment, after the driving circuit layer is prepared, the light-emitting structure layer may be prepared on the driving circuit layer, and the encapsulation structure layer may be prepared on the light-emitting structure layer, which will not be elaborated here.

[0364] The exemplary embodiment of the present disclosure provides a display substrate, which creatively combines the oxide pixel driving circuit technology and the technology that the data connection line is located in the display area, so that the display substrate has the advantages of a narrow border and a new circuit architecture. By adopting a new pixel driving circuit of an oxide transistor, the present disclosure can effectively reduce the leakage current, which is beneficial to realizing low-frequency display. By setting a first data connection line and a second data connection line in the display area, the data lead-out line in the bonding area is connected to the data signal line through the first data connection line and the second data connection line, so that there is no need to set a fan-shaped diagonal line in the lead-out line area, effectively reducing the length of the lead-out line area, greatly reducing the width of the lower border, improving the screen-to-body ratio, and being beneficial to realizing full-screen display.

[0365] By setting the aspect ratio of the oxide driving transistor in the pixel driving circuit, the driving performance of the pixel driving circuit can be effectively improved under the corresponding process and pixel architecture, and the display quality can be effectively improved.

[0366] By setting that there is no overlap between the data signal line and the channel regions of the first transistor T1 to the seventh transistor T7, the signal crosstalk caused by the data voltage jump of the data signal line 73 can be avoided, the influence of the data voltage jump on the first transistor T1 to the seventh transistor T7 can be avoided, the working stability of the pixel driving circuit can be improved, and the display effect can be improved.

[0367] By using the first power supply line to shield the first transistor T1, the fourth transistor T4, and the sixth transistor T6, and using the second power supply line to shield the third transistor T3, the fifth transistor T5, and the seventh transistor T7, the light emission of the light-emitting device and the reflected light of the film layer can be blocked from irradiating the oxide transistor, the characteristic drift of the oxide transistor due to light irradiation can be prevented, and the electrical characteristics of the oxide transistor can be improved.

[0368] By setting the second data connection line between the two first power supply lines, the first power supply line with a constant voltage signal can be used as a shielding line to avoid the influence of the data voltage jump on the pixel driving circuit, improve the working stability of the pixel driving circuit, and improve the display effect.

[0369] By hiding the data transfer via hole connecting the first data connection line and the second data connection line in the circuit unit, the ghosting can be effectively realized, the appearance defect of the display substrate can be effectively avoided, and the display quality and display effect can be improved.

[0370] By setting the first break to overlap with the second source-drain metal layer (such as the first power supply line or the second power supply line), the second source-drain metal layer can be used to shield the first break, the film layer difference in different regions can be effectively eliminated, and the appearance defect of the display substrate can be avoided.

[0371] By setting the second break to overlap with the first source-drain metal layer (such as the reference signal line or the initial signal line), the first source-drain metal layer can be used to pad up the second break, the film layer difference in different regions can be effectively eliminated, and the appearance defect of the display substrate can be avoided.

[0372] By setting dummy electrodes in the circuit unit, the morphology and connection structure presented by the dummy electrodes are basically the same as those of the data connection electrodes, so that different circuit units have basically the same transfer connection structure, the ghosting can be effectively realized, the appearance defect of the display substrate can be effectively avoided, and the display quality and display effect can be improved.

[0373] In an embodiment of the present disclosure, a first power supply connection line with a main body portion extending along a first direction X and a first power supply line with a main body portion extending along a second direction Y are provided, and the first power supply line is connected to the first power supply connection line, so that the first power supply line and the first power supply connection line form a mesh structure for transmitting a first power signal on the display substrate. This not only effectively reduces the resistance of the first power supply line, reduces the voltage drop of the first power signal, but also effectively improves the uniformity of the first power signal in the display substrate, effectively improves the display uniformity, and improves the display quality and display performance.

[0374] In an embodiment of the present disclosure, by providing a second power supply line in the display area, a VSS in pixel structure is realized, which can greatly reduce the width of the power supply lead in the border area, greatly reduce the width of the left and right borders, improve the screen-to-body ratio, and is conducive to realizing a full-screen display. By providing a second power supply line with a wider wiring, not only the resistance of the second power supply line is effectively reduced, the voltage drop of the transmitted second power signal is reduced, but also the uniformity of the second power signal in the display substrate is effectively improved, the display uniformity is effectively improved, and the display quality and display performance are improved.

[0375] In an embodiment of the present disclosure, by arranging the first scan signal line, the third scan signal line, and the fourth scan signal line on the first source-drain metal layer, the resistance of the scan signal line is effectively reduced, the voltage drop of the scan signal is reduced, the compensation speed can be increased, and the display quality is improved.

[0376] The pixel driving circuit in an embodiment of the present disclosure uses 7 oxide transistors. Through a mirror-symmetric design, the bottom gate electrode and the top gate electrode of the transistors in adjacent circuit units are an integrated structure connected to each other, and share the same gate connection block and gate connection via. This not only effectively reduces the occupied space of the pixel driving circuit, is not only conducive to realizing a high resolution (PPI) display, but also conducive to the compression of the circuit unit. A vertical routing space for placing the second data connection line is compressed by using 2 unit columns, and a horizontal routing space for placing the first data connection line is compressed by using 4 unit rows. The circuit unit compression structure of the present disclosure can achieve a large transmittance and is applicable to sensor recognition.

[0377] The manufacturing process of the embodiment of the present disclosure can be well compatible with the existing manufacturing process, the process implementation is simple, easy to implement, has a high production efficiency, a low production cost, and a high yield rate.

[0378] In some other embodiments, the driving circuit layer of the display substrate may further include a third source-drain metal (SD3) layer. The third source-drain metal layer may be disposed on a side of the second flat layer away from the substrate, and a third flat layer may be disposed on a side of the third source-drain metal (SD3) layer away from the substrate. In an exemplary embodiment, the data signal line and the second data connection line may be disposed in the third source-drain metal layer, or the data signal line, the second data connection line, and the second power supply line may be disposed in the third source-drain metal layer. The present disclosure does not limit this here.

[0379] Figure 17 FIG. is a schematic structural diagram of another display substrate according to an exemplary embodiment of the present disclosure, and is Figure 7B an enlarged view of region A in FIG., schematically showing the structure of circuit units of one circuit row and four circuit columns. The structure of the display substrate in this embodiment is basically the same as that shown in Figure 8 FIG., the difference being that the shape of the data signal line 73 may be a broken line shape extending along the second direction Y.

[0380] In an exemplary embodiment, in at least one circuit unit, the data signal line 73 may include at least one straight segment and at least one bent segment connected to each other, and the bent segment is configured to increase the extension length of the data signal line.

[0381] As Figure 17 shown in FIG., at least one data signal line 73 may include a first straight segment 73-1, a second straight segment 73-2, and a bent segment 73-3. The first end of the bent segment 73-3 is connected to the first straight segment 73-1, and the second end of the bent segment 73-3 is connected to the second straight segment 73-2.

[0382] In an exemplary embodiment, the bent segment 73-3 may include a first bent portion 73A, a second bent portion 73B, and an extension portion 73C. The first end of the first bent portion 73A is connected to the first straight segment 73-1. After the second end of the first bent portion 73A extends toward the second power supply line 72, it is connected to the first end of the extension portion 73C. After the second end of the extension portion 73C extends along the second direction Y, it is connected to the first end of the second bent portion 73B. After the second end of the second bent portion 73B extends away from the second power supply line 72, it is connected to the second straight segment 73-2.

[0383] In an exemplary embodiment, the first bent portion 73A has a first included angle α1 with the second direction Y, and the first included angle α1 may be about 20 degrees to 60 degrees. The second bent portion 73B has a second included angle α2 with the second direction Y, and the second included angle α2 may be about 20 degrees to 60 degrees.

[0384] In an exemplary embodiment, the extension lengths of the first bending portion 73A, the second bending portion 73B, and the extension portion 73C can be set according to actual needs, and the present disclosure does not limit this here.

[0385] In an exemplary embodiment, since a part of the data signal lines in the display area (which can be referred to as FIP traces) are connected to the data lead-out lines in the bonding area through the first data connection line and the second data connection line, while another part of the data signal lines (which can be referred to as normal traces) are directly connected to the data lead-out lines in the bonding area, the data signal transmission distance of the FIP traces is greater than that of the normal traces. By providing a bending section on the data signal lines of the normal traces and compensating for the data signal transmission distance through trace bending processing, the present disclosure can make the data signal transmission distance of the FIP traces basically the same as that of the normal traces, improve the driving performance of the pixel driving circuit, and improve the display effect.

[0386] This embodiment provides a display substrate that not only has Figure 8 the technical effects of the shown display substrate, but also by providing a bending section on the data signal lines of the normal traces and compensating for the data signal transmission distance through trace bending processing, the data signal transmission distance of the FIP traces can be made basically the same as that of the normal traces, improve the driving performance of the pixel driving circuit, and improve the display effect.

[0387] Figure 18 is a schematic structural diagram of another display substrate according to an exemplary embodiment of the present disclosure, and is an Figure 7B enlarged view of area A in, showing the structure of a circuit unit with one circuit row and four circuit columns. The structure of the display substrate in this embodiment is basically the same as that shown in Figure 8 except that an auxiliary cathode is further provided on the side of the second power supply line away from the substrate.

[0388] In an exemplary embodiment, in a plane perpendicular to the display substrate, the display substrate may at least include a driving structure layer provided on the substrate and a light-emitting structure layer provided on the side of the driving structure layer away from the substrate. The driving structure layer may include a plurality of circuit units, at least one circuit unit may include a pixel driving circuit, the light-emitting structure layer may include a plurality of light-emitting units, at least one light-emitting unit may include a light-emitting device, and at least one light-emitting device may at least include an anode, an organic light-emitting layer, and a cathode, and the anode is connected to the pixel driving circuit of the corresponding circuit unit.

[0389] As Figure 18As shown, the light-emitting structure layer of this embodiment may further include at least one auxiliary cathode 90. The auxiliary cathode 90 may be disposed on the same layer as the anode. Therefore, the auxiliary cathode 90 is disposed on the side of the second power line 72 away from the substrate. The orthographic projection of the auxiliary cathode 90 on the substrate at least partially overlaps with the orthographic projection of the second power line 72 on the substrate, and the auxiliary cathode 90 is connected to the second power line 72 through an auxiliary via V30. The auxiliary cathode 90 is configured to be connected to the cathode formed subsequently.

[0390] In an exemplary embodiment, after the organic light-emitting layer is formed, a connection hole exposing the auxiliary cathode 90 may be formed by laser drilling, so that the cathode is connected to the auxiliary cathode 90 through the connection hole.

[0391] In an exemplary embodiment, a plurality of auxiliary cathodes 90 may be periodically disposed along the first direction X and the second direction Y to form a grid structure for transmitting the second power signal with a mesh connection structure on the display substrate. This can not only effectively reduce the resistance of the second power line and reduce the voltage drop of the second power signal, but also effectively improve the uniformity of the second power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0392] In an exemplary embodiment, since the width of the second power line 72 in the embodiment of the present disclosure is relatively wide, it is beneficial to arrange the position of the auxiliary cathode 90, and the voltage drop of the second power signal can be minimized. For example, in the first direction X, an auxiliary cathode 90 may be disposed every three circuit units. For another example, in the second direction Y, an auxiliary cathode 90 may be disposed every one circuit unit.

[0393] In an exemplary embodiment, the plurality of anodes in the light-emitting structure layer may be arranged in an RGBG manner or may be arranged in a real RGB manner. The present disclosure does not make a limitation herein.

[0394] In some other embodiments, the display substrate may not be provided with the auxiliary cathode 90, and the cathode in the light-emitting structure layer is directly connected to the second power line 72 through the connection hole. The present disclosure does not make a limitation herein.

[0395] Figure 19 It is a schematic structural diagram of another display substrate according to an exemplary embodiment of the present disclosure, and is Figure 7B an enlarged view of area A in the figure, showing the structure of a circuit unit of one circuit row and four circuit columns. The structure of the display substrate in this embodiment is basically the same as that shown in Figure 8 except that the second data connection line is disposed between two data signal lines.

[0396] As Figure 19As shown, the second data connection line 82 of this embodiment may be disposed between data signal lines 73 adjacent in the first direction X. For example, the second data connection line 82 may be disposed between the data signal lines 73 of the (N + 1)-th unit column and the data signal lines 73 of the (N + 2)-th unit column.

[0397] In an exemplary embodiment, the shape of the first power connection line 68 may be a straight line or a broken line extending along the first direction X, and may be discontinuously disposed in one unit row. The first power connection lines 68 of two adjacent circuit units in part of the first direction X may be an integrally connected structure.

[0398] In an exemplary embodiment, a first power connection block 68-1 may be connected to the first power connection line 68. The first power connection block 68-1 may be disposed at the middle position of the integrally connected first power connection line 68, such that the first power connection lines 68 of two circuit units share the same first power connection block 68-1.

[0399] In an exemplary embodiment, the first power lines 71 of some adjacent two circuit units may be an integrally connected structure. Therefore, the width of the first power lines 71 in this embodiment may be greater than Figure 8 the width of the first power lines 71 in the shown embodiment.

[0400] In an exemplary embodiment, the preparation process of the display substrate of this embodiment may include the following operations.

[0401] (21) Form a first conductive layer, a second conductive layer, a semiconductor layer, a third conductive layer, a fourth insulating layer, and a fourth conductive layer pattern in sequence, as Figure 20A and Figure 20B shown. Figure 20B is Figure 20A a planar schematic diagram of the fourth conductive layer in. In an exemplary embodiment, the first conductive layer, the second conductive layer, the semiconductor layer, the third conductive layer, and the fourth insulating layer pattern are substantially the same as those in the Figure 8 shown embodiment, and will not be described in detail here.

[0402] In an exemplary embodiment, the fourth conductive layer of each circuit unit at least includes: a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55, a first scan signal line 61, a third scan signal line 63, a fourth scan signal line 64, a reference signal line 66, and an initial signal line 67. The above structure is substantially the same as that in the Figure 8 shown embodiment.

[0403] In an exemplary embodiment, the fourth conductive layer of each circuit unit may further include a first power connection line 68. The shape of the first power connection line 68 may be a straight line or a broken line extending along the first direction X, and it may be discontinuously provided in the middle of a unit row. The first power connection line 68 is connected to the first region of the fifth active layer through a fifth via V5.

[0404] In an exemplary embodiment, the first power connection lines 68 of two circuit units adjacent in part of the first direction X may be an integrally connected structure. For example, the first power connection lines 68 of the Nth unit column and the (N + 1)th unit column may be an integrally connected structure, and the first power connection lines 68 of the (N + 2)th unit column and the (N + 3)th unit column may be an integrally connected structure. However, there is a gap between the first power connection lines 68 in the Nth unit column and the (N + 1)th unit column and the first power connection lines 68 in the (N + 2)th unit column and the (N + 3)th unit column.

[0405] In an exemplary embodiment, a first power connection block 68-1 may be connected to the first power connection line 68, and the first power connection block 68-1 is configured to be connected to a first power supply line formed subsequently.

[0406] In an exemplary embodiment, the first power connection block 68-1 may be provided at the middle position of the integrally formed first power connection line 68, that is, between two circuit units adjacent in the first direction X, so that the first power connection lines 68 of the two circuit units share the same first power connection block 68-1, which can effectively reduce the occupied space of the pixel driving circuit and is beneficial to the compression of the circuit unit on the premise of ensuring the display resolution (PPI).

[0407] In an exemplary embodiment, the fourth conductive layer of at least one circuit unit may further include a first data connection line 81. The shape of the first data connection line 81 may be a straight line or a broken line extending along the first direction X, and it may be provided between some adjacent unit rows. A first break K1 may be provided on the first data connection line 81, and a first connecting sub-line 81-1 and a second connecting sub-line 81-2 are formed on both sides of the first break K1.

[0408] In an exemplary embodiment, a data connection block 83 and a data connection electrode 84 may be provided on at least one first connecting sub-line 81-1. The first end of the data connection block 83 is connected to the first connecting sub-line 81-1, and the second end of the data connection block 83 is connected to the data connection electrode 84. The first connecting sub-line 81-1, the data connection block 83, and the data connection electrode 84 may be an integrally connected structure.

[0409] In an exemplary embodiment, with Figure 8Different from the illustrated embodiment, the data connection block 83 and the data connection electrode 84 of this embodiment can be disposed between the (N + 1)-th unit column and the (N + 2)-th unit column and can be located between the first power connection lines 68 that are discontinuously arranged.

[0410] In an exemplary embodiment, the fourth conductive layer may further include at least one dummy electrode 85, and the dummy electrode 85 can be located between the first power connection lines 68 that are discontinuously arranged. The position and shape of the dummy electrode 85 in the circuit unit can be substantially the same as the position and shape of the data connection electrode 84 in the circuit unit.

[0411] In an exemplary embodiment, in one unit row, the fourth conductive layers (except for the first data connection line and the data connection block) in two adjacent circuit units can be symmetrically disposed with respect to the column center line. For example, the fourth conductive layers of the N-th unit column and the (N + 1)-th unit column can be symmetrically disposed with respect to the column center line. Also, for example, the fourth conductive layers of the (N + 1)-th unit column and the (N + 2)-th unit column can be symmetrically disposed with respect to the column center line.

[0412] In an exemplary embodiment, the fourth conductive layers (except for the first data connection line and the data connection block) in adjacent unit rows can be substantially the same.

[0413] (22) Form the first planarization layer and the fifth conductive layer pattern in sequence. In an exemplary embodiment, forming the first planarization layer and the fifth conductive layer pattern in sequence may include: first forming the first planarization layer covering the fourth conductive layer pattern, with the twenty-first via V21 to the twenty-fifth via V25 disposed on the first planarization layer, and then forming the fifth conductive layer on the first planarization layer, as Figure 21A and Figure 21B shown, Figure 21B is Figure 21A a schematic plan view of the fifth conductive layer in

[0414] In an exemplary embodiment, the positions of the twenty-first via V21 to the twenty-fifth via V25 are substantially the same as those in the Figure 8 illustrated embodiment. The difference is that since the first power connection lines 68 of two adjacent circuit units adjacent in the first direction X share the same first power connection block 68-1, these two circuit units share the same twenty-first via V21.

[0415] In an exemplary embodiment, the fifth conductive layer of each circuit unit can at least include a first power line 71, a second power line 72, a data signal line 73, and an anode connection electrode 74. The above structure is the same as that in Figure 8The illustrated embodiments are substantially the same, except that the first power supply lines 71 of two adjacent circuit units can be an integrally connected structure. For example, the first power supply lines 71 of the Nth unit column and the (N + 1)th unit column can be an integrally connected structure, and the first power supply lines 71 of the (N + 2)th unit column and the (N + 3)th unit column can be an integrally connected structure.

[0416] In an exemplary embodiment, since the first power supply lines 71 of two adjacent circuit units are an integrally connected structure, the width of the first power supply lines 71 in this embodiment can be greater than Figure 8 the width of the first power supply lines 71 in the illustrated embodiment.

[0417] In an exemplary embodiment, the fifth conductive layer of at least one circuit unit may further include a second data connection line 82. The shape of the second data connection line 82 can be a straight line or a broken line with a main body portion extending along the second direction Y. It can be disposed between some adjacent unit columns. A second break K2 can be provided on the second data connection line 82, and a third connection sub-line 82-3 and a fourth connection sub-line 82-4 are formed on both sides of the second break K2.

[0418] In an exemplary embodiment, different from Figure 8 the illustrated embodiment, the second data connection line 82 in this embodiment can be disposed between some data signal lines 73 adjacent in the first direction X. For example, the second data connection line 82 can be disposed between the data signal lines 73 of the (N + 1)th unit column and the data signal lines 73 of the (N + 2)th unit column. By disposing the second data connection line 82 between two data signal lines 73, the present disclosure can make the first power supply lines 71 of two adjacent circuit units be an integrally connected structure and increase the width of the first power supply lines 71. By providing the first power supply lines 71 with a wider wiring, the present disclosure not only effectively reduces the resistance of the first power supply lines 71, reduces the voltage drop of the transmitted first power signal, but also effectively improves the uniformity of the first power signal in the display substrate, effectively improves the display uniformity, and improves the display quality and display performance.

[0419] In an exemplary embodiment, the orthographic projection of at least one first power supply line 71 on the substrate at least partially overlaps with the orthographic projection of the first break K1 on the substrate, or the orthographic projection of at least one second power supply line 72 on the substrate may include the orthographic projection of the first break K1 on the substrate.

[0420] In an exemplary embodiment, the orthographic projection of at least one second break K2 on the substrate at least partially overlaps with the orthographic projection of at least one reference signal line 66 on the substrate, or the orthographic projection of at least one second break K2 on the substrate at least partially overlaps with the orthographic projection of at least one initial signal line 67 on the substrate.

[0421] This embodiment provides a display substrate, which not only has Figure 8 the technical effects of the display substrate shown, but also by arranging the second data connection line between two data signal lines, the first power supply lines of two adjacent circuit units can be an integrally connected structure, increasing the width of the first power supply line. This not only effectively reduces the resistance of the first power supply line, reduces the voltage drop of the transmitted first power signal, but also effectively improves the uniformity of the first power signal in the display substrate, effectively improves the display uniformity, and improves the display quality and display performance.

[0422] Figure 22 is a schematic structural diagram of another display substrate according to an exemplary embodiment of the present disclosure, and is an Figure 7B enlarged view of area A in, schematically showing the structure of circuit units of one circuit row and four circuit columns. The display substrate structure of this embodiment is basically the same as that shown in Figure 8 , the difference is that some adjacent circuit units can share active vias.

[0423] As shown in Figure 22 , in this embodiment, the first active layers 31 of some adjacent circuit units in the first direction X are an integrally connected structure, and the seventh active layers 37 of some adjacent circuit units in the first direction X are an integrally connected structure.

[0424] In an exemplary embodiment, since the first active layers 31 of two adjacent circuit units in the first direction X are an integrally connected structure, these two circuit units share the same first via V1 as the first active via. For example, the first active layers 31 of the Nth unit column and the (N + 1)th unit column can be an integrally connected structure, and the circuit units of the Nth unit column and the (N + 1)th unit column share the same first via V1. Another example is that the first active layers 31 of the (N + 2)th unit column and the (N + 3)th unit column can be an integrally connected structure, and the circuit units of the (N + 2)th unit column and the (N + 3)th unit column share the same first via V1.

[0425] In an exemplary embodiment, since the seventh active layers 27 of two adjacent circuit units in the first direction X are an integrally connected structure, these two circuit units share the same seventh via V7 as the seventh active via. For example, the seventh active layers 37 of the (N + 1)th unit column and the (N + 2)th unit column can be an integrally connected structure, and the circuit units of the (N + 1)th unit column and the (N + 2)th unit column share the same seventh via V7.

[0426] In an exemplary embodiment, the manufacturing process of the display substrate of this embodiment may include the following operations.

[0427] (31) Form a first conductive layer pattern. In an exemplary embodiment, the first conductive layer pattern of each circuit unit may at least include a first electrode plate 11 of a first capacitor, a third electrode plate 13 of a second capacitor, and an electrode plate connection block 15. The above structure is substantially the same as that of the embodiment shown in Figure 8 , except that the shape of the first electrode plate 11 is different, as shown in Figure 23 .

[0428] (32) Form a second conductive layer pattern. In an exemplary embodiment, the second conductive layer pattern of each circuit unit at least includes: a second electrode plate 12 of a first capacitor, a fourth electrode plate 14 of a second capacitor, a first bottom gate electrode 21, a second bottom gate electrode 22, a fourth bottom gate electrode 24, a sixth bottom gate electrode 26, a first shielding line 27, and a second shielding line 28. The above structure is substantially the same as that of the embodiment shown in Figure 8 , except that the shape of the second electrode plate 12 is different, as shown in Figure 24 .

[0429] (33) Form a semiconductor layer pattern. In an exemplary embodiment, the semiconductor layer pattern of each circuit unit may include a first active layer 31, a second active layer 32, a third active layer 33, a fourth active layer 34, a fifth active layer 35, a sixth active layer 36, and a seventh active layer 37. The above structure is substantially the same as that of the embodiment shown in Figure 8 , except that the active layers of some adjacent circuit units are integrally connected structures, as shown in Figure 25 .

[0430] In an exemplary embodiment, the first regions 31-1 of the first active layers of some adjacent circuit units in the first direction X may be connected to each other, so that the first active layers 31 of some adjacent circuit units in the first direction X are integrally connected structures. For example, the first active layers 31 of the Nth unit column and the (N + 1)th unit column may be integrally connected structures. Another example is that the first active layers 31 of the (N + 2)th unit column and the (N + 3)th unit column may be integrally connected structures.

[0431] In an exemplary embodiment, since the first active layer 31, the second active layer 32, the fourth active layer 34, and the sixth active layer 36 in the circuit unit are integrally connected structures, the first active layer 31, the second active layer 32, the fourth active layer 34, and the sixth active layer 36 of some adjacent circuit units in the first direction X are integrally connected structures.

[0432] In an exemplary embodiment, the first regions 37-1 of the seventh active layers of adjacent circuit units in a partial first direction X may be connected to each other, such that the seventh active layers 37 of adjacent circuit units in the partial first direction X are an integrally connected structure. For example, the seventh active layers 37 of the (N+1)-th unit column and the (N+2)-th unit column may be an integrally connected structure.

[0433] In an exemplary embodiment, since the third active layer 33, the fifth active layer 35, and the seventh active layer 37 in the circuit unit are an integrally connected structure, the third active layer 33, the fifth active layer 35, and the seventh active layer 37 of adjacent circuit units in a partial first direction X are an integrally connected structure.

[0434] (34) Form a third conductive layer pattern. In an exemplary embodiment, the third conductive layer pattern of each circuit unit may at least include a first top gate electrode 41, a second top gate electrode 42, a third top gate electrode 43, a fourth top gate electrode 44, a sixth top gate electrode 46, a second scan signal line 62, and a light emission signal line 65. The above structure is substantially the same as that of the Figure 8 embodiment shown, as Figure 26 shown.

[0435] (35) Form a fourth insulating layer pattern. In an exemplary embodiment, the plurality of vias in the fourth insulating layer covering the third conductive layer may at least include a first via V1 to an eighteenth via V18. The via structure is substantially the same as that of the Figure 8 embodiment shown, except that some adjacent circuit units share the same active via, as Figure 27 shown.

[0436] In an exemplary embodiment, since the first active layers of two adjacent circuit units in a first direction X are an integrally connected structure, the two circuit units share the same first via V1 as the first active via, which can effectively reduce the occupied space of the pixel driving circuit and is beneficial to the compression of circuit units. For example, the circuit units of the N-th unit column and the (N+1)-th unit column share the same first via V1. Another example is that the circuit units of the (N+2)-th unit column and the (N+3)-th unit column share the same first via V1.

[0437] In an exemplary embodiment, since the seventh active layers of two adjacent circuit units in a first direction X are an integrally connected structure, the two circuit units share the same seventh via V7 as the seventh active via, which can effectively reduce the occupied space of the pixel driving circuit and is beneficial to the compression of circuit units. For example, the circuit units of the (N+1)-th unit column and the (N+2)-th unit column share the same seventh via V7.

[0438] (36)Form a fourth conductive layer pattern. In an exemplary embodiment, the fourth conductive layer of each circuit unit at least includes: a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55, a first scan signal line 61, a third scan signal line 63, a fourth scan signal line 64, a reference signal line 66, an initial signal line 67, and a first power connection line 68. The above structure is substantially the same as that of Figure 8 the embodiment shown, as Figure 28 shown.

[0439] In an exemplary embodiment, the reference signal line 66 is connected to the first region of the first active layer of two circuit units through a first via hole V1 shared by the two circuit units, so that the reference signal line 66 can write the reference signal into the first poles of the first transistors T1 of the two circuit units and the first poles of the second transistors T2 at the same time.

[0440] In an exemplary embodiment, the initial signal line 67 is connected to the first region of the seventh active layer in two circuit units through a seventh via hole V7 shared by the two circuit units, so that the initial signal line 67 can write the initial signal into the first poles of the seventh transistors T7 of the two circuit units.

[0441] In an exemplary embodiment, the structures such as the first data connection line 81, the first break K1, the data connection block 83, the data connection electrode 84, and the dummy electrode 85 are substantially the same as those of Figure 8 the embodiment shown.

[0442] (37)Form a first planarization layer and a fifth conductive layer pattern in sequence. The via hole structure on the first planarization layer and the structure of the fifth conductive layer are substantially the same as those of Figure 8 the embodiment shown, and will not be elaborated here.

[0443] This embodiment provides a display substrate, which not only has the technical effects of the Figure 8 display substrate shown, but also by setting the active layers of some adjacent circuit units as an interconnected integrated structure, such that two circuit units share the same active via hole, it can effectively reduce the occupied space of the pixel driving circuit and is beneficial to the compression of the circuit units.

[0444] Figure 29 is a schematic structural diagram of another display substrate according to an exemplary embodiment of the present disclosure, which is an enlarged view of region A in Figure 7B and schematically shows the structure of circuit units in one circuit row and eight circuit columns. The pixel driving circuit in the circuit unit is a non-mirror structure.

[0445] As Figure 29As shown, in an exemplary embodiment, multiple circuit units on the display substrate can compress out routing spaces in a lateral compression and a longitudinal compression manner. The routing spaces are configured to arrange a first data connection line 81 and a second data connection line 82. Among them, every four unit columns can be grouped as one set, and a vertical routing space can be compressed out through the lateral compression manner, that is, a second data connection line 82 is arranged every four unit columns. Every two unit rows can be grouped as one set, and a horizontal routing space can be compressed out through the longitudinal compression manner, that is, a first data connection line 81 is arranged every two unit rows.

[0446] In an exemplary embodiment, the manufacturing process of the display substrate in this embodiment can include the following operations.

[0447] (41) Form a first conductive layer pattern. The first conductive layer pattern of each circuit unit can at least include a first electrode plate of a first capacitor, a third electrode plate of a second capacitor, and an electrode plate connection block, as Figure 30 shown.

[0448] In an exemplary embodiment, the first conductive layers in adjacent unit columns can be substantially the same, and the first conductive layers in adjacent unit rows can be substantially the same.

[0449] (42) Form a second conductive layer pattern. The second conductive layer pattern of each circuit unit can at least include a second electrode plate of a first capacitor, a fourth electrode plate of a second capacitor, a first bottom gate electrode, a second bottom gate electrode, a fourth bottom gate electrode, a sixth bottom gate electrode, a first shielding line, and a second shielding line, as Figure 31 shown.

[0450] In an exemplary embodiment, the second conductive layers in adjacent unit columns can be substantially the same, and the second conductive layers in adjacent unit rows can be substantially the same.

[0451] (43) Form a semiconductor layer pattern. The semiconductor layer pattern of each circuit unit can at least include a first active layer, a second active layer, a third active layer, a fourth active layer, a fifth active layer, a sixth active layer, and a seventh active layer, as Figure 32 shown.

[0452] In an exemplary embodiment, the semiconductor layers in adjacent unit columns can be substantially the same, and the semiconductor layers in adjacent unit rows can be substantially the same.

[0453] (34) Form a third conductive layer pattern. The third conductive layer pattern of each circuit unit can at least include a first top gate electrode, a second top gate electrode, a third top gate electrode, a fourth top gate electrode, a sixth top gate electrode, a second scan signal line, and a light emitting signal line, as Figure 33 shown.

[0454] (35) Form a fourth insulating layer and a fourth conductive layer pattern. The fourth insulating layer of each circuit unit includes a plurality of vias, and the fourth conductive layer of each circuit unit includes at least a first connection electrode, a second connection electrode, a third connection electrode, a fourth connection electrode, a fifth connection electrode, a first scan signal line, a third scan signal line, a fourth scan signal line, a reference signal line, an initial signal line, and a first power connection line, as Figure 34 shown.

[0455] In an exemplary embodiment, the fourth conductive layer of at least one circuit unit may further include a first data connection line 81, and a data connection electrode 84 and a first break K1 may be provided on the first data connection line 81.

[0456] In an exemplary embodiment, the fourth conductive layers (except for the first data connection line and the data connection electrode) in adjacent unit columns may be substantially the same, and the fourth conductive layers (except for the first data connection line and the data connection electrode) in adjacent unit rows may be substantially the same.

[0457] (36) Form a first planarization layer and a fifth conductive layer pattern. The first planarization layer of each circuit unit includes a plurality of vias, and the fifth conductive layer may include at least: a first power line, a second power line, a data signal line, and an anode connection electrode, as Figure 29 shown.

[0458] In an exemplary embodiment, the fifth conductive layer of at least one circuit unit may further include a second data connection line 82. The second data connection line 82 may be disposed between the first power line and the data signal line adjacent in the first direction X, and the second data connection line 82 may be connected to the data connection electrode through a via.

[0459] In an exemplary embodiment, a second break K2 may be provided on at least one second data connection line 82, and the second break K2 may cut off the second data connection line 82.

[0460] In an exemplary embodiment, the positive projection of at least one second break K2 on the substrate at least partially overlaps with the positive projection of at least one reference signal line on the substrate, or the positive projection of at least one second break K2 on the substrate at least partially overlaps with the positive projection of at least one initial signal line on the substrate.

[0461] In an exemplary embodiment, the positive projection of at least one first power line on the substrate at least partially overlaps with the positive projection of the first break K1 on the substrate, or the positive projection of at least one second power line on the substrate may include the positive projection of the first break K1 on the substrate.

[0462] This embodiment provides a display substrate. The pixel driving circuit is a non-mirror structure and also has Figure 8The technical effects of the shown display substrate.

[0463] The foregoing structure shown in the present disclosure and its manufacturing process are merely an exemplary illustration. In the exemplary embodiments, the corresponding structure can be changed according to actual needs, and the lithography process can be increased or decreased. For example, the first break on the first data connection line can be disposed under the anode, and the positive projection of the first break on the substrate can be within the range of the positive projection of the anode on the substrate, using the anode to block the first break to eliminate the film layer differences in different regions. Another example is that the second break on the second data connection line can be disposed under the anode, and the positive projection of the second break on the substrate can be within the range of the positive projection of the anode on the substrate, using the anode to block the second break to eliminate the film layer differences in different regions. Still another example is that both the first break and the second break are disposed under the anode, which is not limited herein in the present disclosure.

[0464] In the exemplary embodiments, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light emitting diode display (Micro LED or Mini LED), or quantum dot light emitting diode display (QDLED), etc., which is not limited herein in the present disclosure.

[0465] The present disclosure also provides a method for manufacturing a display substrate to fabricate the display substrate provided in the above embodiments. In the exemplary embodiments, the display substrate includes a plurality of circuit units, a plurality of data signal lines extending along the second direction, a plurality of first data connection lines extending along the first direction, and a plurality of second data connection lines extending along the second direction. One end of at least one first data connection line is connected to the data signal line, and the other end is connected to the second data connection line. The first direction and the second direction intersect; the manufacturing method may include:

[0466] A pixel driving circuit is formed within at least one circuit unit. The pixel driving circuit includes at least a driving transistor, a first reset transistor, a data writing transistor, a light emitting control transistor, a first capacitor, and a second capacitor. The first capacitor includes a first electrode plate and a second electrode plate, and the second capacitor includes a third electrode plate and a fourth electrode plate. The first pole of the first reset transistor is connected to a reference signal line, the second pole of the first reset transistor is connected to the gate electrode of the driving transistor, the first pole of the light emitting control transistor is connected to a first power supply line, the second pole of the light emitting control transistor is connected to the first pole of the driving transistor, the second pole of the driving transistor is connected to the second electrode plate of the first capacitor, the first pole of the data writing transistor is connected to the data signal line, the second pole of the data writing transistor is connected to the fourth electrode plate of the second capacitor, and the first electrode plate of the first capacitor is connected to the third electrode plate of the second capacitor. The driving transistor is an oxide transistor, and the aspect ratio of the driving transistor is from 1.25 to 2.67.

[0467] The present disclosure also provides a display device, which includes the aforementioned display substrate. The display device may be: a mobile phone, a tablet computer, a television set, a monitor, a laptop computer, a digital photo frame, a navigator, or any product or component with a display function. The embodiments of the present invention are not limited thereto.

[0468] Although the embodiments disclosed in the present disclosure are as above, it should be noted that the above embodiments are merely exemplary and not restrictive. Therefore, the present disclosure is not limited to the content specifically shown and described herein. Various modifications, substitutions, or omissions can be made to the form and details of the implementation without departing from the scope of the present disclosure.

Claims

1. A display substrate, characterized in that, It includes multiple circuit units, multiple data signal lines extending along a second direction, multiple first data connection lines extending along a first direction, and multiple second data connection lines extending along the second direction. One end of at least one first data connection line is connected to the data signal line, and the other end is connected to the second data connection line. The first direction and the second direction intersect; at least one circuit unit includes a pixel driving circuit, and the pixel driving circuit at least includes a driving transistor, a first reset transistor, a data writing transistor, a light emitting control transistor, a first capacitor, and a second capacitor. The first capacitor includes a first electrode plate and a second electrode plate, and the second capacitor includes a third electrode plate and a fourth electrode plate; the first pole of the first reset transistor is connected to a reference signal line, the second pole of the first reset transistor is connected to the gate electrode of the driving transistor, the first pole of the light emitting control transistor is connected to a first power supply line, the second pole of the light emitting control transistor is connected to the first pole of the driving transistor, the second pole of the driving transistor is connected to the second electrode plate of the first capacitor, the first pole of the data writing transistor is connected to the data signal line, the second pole of the data writing transistor is connected to the fourth electrode plate of the second capacitor, and the first electrode plate of the first capacitor is connected to the third electrode plate of the second capacitor; the driving transistor is an oxide transistor, and the aspect ratio of the driving transistor is from 1.25 to 2.

67.

2. The display substrate according to claim 1, wherein The orthographic projection of the data signal line on the substrate does not overlap with the orthographic projections of the channel regions of the driving transistor, the first reset transistor, the data writing transistor, and the light emitting control transistor on the substrate.

3. The display substrate according to claim 1, characterized in that, In at least one circuit unit, the data signal line includes at least one straight segment and at least one bent segment, and the bent segment is configured to increase the extension length of the data signal line.

4. The display substrate according to claim 1, wherein At least one second data connection line is disposed between two first power supply lines adjacent in the first direction, or at least one second data connection line is disposed between two data signal lines adjacent in the first direction.

5. The display substrate according to claim 1, wherein In at least one circuit unit and the circuit unit adjacent in the first direction, the first power supply lines of the two circuit units are an integrally connected structure.

6. The display substrate according to claim 1, wherein At least one circuit unit further includes a first power supply connection line extending along the first direction. The shape of the first power supply line is a straight line or a broken line extending along the second direction, and the first power supply line is connected to the first power supply connection line to form a mesh structure for transmitting a first power signal.

7. The display substrate according to claim 1, wherein At least one circuit unit further includes a second power supply line, and the width of the second power supply line is greater than the width of the first power supply line, and the width is the dimension in the first direction.

8. The display substrate according to claim 7, wherein The display substrate further includes a plurality of auxiliary cathodes. The auxiliary cathodes are disposed on the side of the second power supply line away from the substrate. The orthographic projection of at least one auxiliary cathode on the substrate at least partially overlaps with the orthographic projection of the second power supply line on the substrate. The auxiliary cathode is connected to the second power supply line through an auxiliary via, and the auxiliary cathode is configured to be connected to the cathode of the light emitting device.

9. The display substrate according to claim 7, wherein The positive projection of the first power supply line on the substrate at least partially overlaps with the positive projections of the first reset transistor and the data writing transistor on the substrate, and the positive projection of the second power supply line on the substrate at least partially overlaps with the positive projections of the driving transistor and the light emitting control transistor on the substrate.

10. The display substrate according to claim 1, wherein At least one circuit unit further includes a data connection electrode, the data connection electrode is connected to the first data connection line, and the second data connection line is connected to the data connection electrode through a via; at least one circuit unit further includes a dummy electrode, the second data connection line is connected to the dummy electrode through a via, and the position and shape of the dummy electrode in one circuit unit are the same as the position and shape of the data connection electrode in another circuit unit.

11. The display substrate according to claim 1, wherein In a direction perpendicular to the substrate, the display substrate at least includes a first source-drain metal layer and a second source-drain metal layer sequentially arranged along a direction away from the substrate, and the first data connection line is disposed in the first source-drain metal layer; At least one first data connection line is provided with a first break, the first break truncates the first data connection line, and the positive projection of the first break on the substrate at least partially overlaps with the positive projection of the second source-drain metal layer on the substrate.

12. The display substrate according to claim 1, wherein In a direction perpendicular to the substrate, the display substrate at least includes a first source-drain metal layer and a second source-drain metal layer sequentially arranged along a direction away from the substrate, and the second data connection line is disposed in the second source-drain metal layer; At least one second data connection line is provided with a second break, the second break truncates the second data connection line, and the positive projection of the second break on the substrate at least partially overlaps with the positive projection of the first source-drain metal layer on the substrate.

13. The display substrate according to any one of claims 1 to 12, characterized in that, The pixel driving circuit further includes a second reset transistor, a third reset transistor, and a data control transistor; a first pole of the second reset transistor is connected to a reference signal line, a second pole of the second reset transistor is connected to a first electrode plate of the first capacitor and a third electrode plate of the second capacitor; a first pole of the third reset transistor is connected to an initial signal line, a second pole of the third reset transistor is connected to a second pole of the driving transistor; a first pole of the data control transistor is connected to a gate electrode of the driving transistor, a second pole of the data control transistor is connected to a second pole of the data writing transistor; the first reset transistor, the second reset transistor, the third reset transistor, the data writing transistor, the light emitting control transistor, and the data control transistor are oxide transistors.

14. The display substrate according to claim 13, wherein The first reset transistor includes at least a first bottom gate electrode and a first top gate electrode. In at least one circuit unit and a circuit unit adjacent to it in the first direction, the first bottom gate electrodes in the two circuit units are an integrally connected structure, and the first top gate electrodes in the two circuit units are an integrally connected structure; and / or, the data writing transistor includes at least a fourth bottom gate electrode and a fourth top gate electrode. In at least one circuit unit and a circuit unit adjacent to it in the first direction, the fourth bottom gate electrodes in the two circuit units are an integrally connected structure, and the fourth top gate electrodes in the two circuit units are an integrally connected structure; and / or, the data control transistor includes at least a sixth bottom gate electrode and a sixth top gate electrode. In at least one circuit unit and a circuit unit adjacent to it in the first direction, the sixth bottom gate electrodes in the two circuit units are an integrally connected structure, and the sixth top gate electrodes in the two circuit units are an integrally connected structure.

15. The display substrate according to claim 14, wherein A first bottom gate connection block is provided on the first bottom gate electrode, and a first top gate connection block is provided on the first top gate electrode. The first bottom gate connection block is configured to be connected to the first scan signal line through a first bottom gate connection via, and the first top gate connection block is configured to be connected to the first scan signal line through a first top gate connection via. In at least one circuit unit and a circuit unit adjacent to it in the first direction, the two circuit units share the first bottom gate connection via, and the two circuit units share the first top gate connection via; and / or, a fourth bottom gate connection block is provided on the fourth bottom gate electrode, and a fourth top gate connection block is provided on the fourth top gate electrode. The fourth bottom gate connection block is configured to be connected to the third scan signal line through a fourth bottom gate connection via, and the fourth top gate connection block is configured to be connected to the third scan signal line through a fourth top gate connection via. In at least one circuit unit and a circuit unit adjacent to it in the first direction, the two circuit units share the fourth bottom gate connection via, and the two circuit units share the fourth top gate connection via; and / or, a sixth bottom gate connection block is provided on the sixth bottom gate electrode, and a sixth top gate connection block is provided on the sixth top gate electrode. The sixth bottom gate connection block is configured to be connected to the fourth scan signal line through a sixth bottom gate connection via, and the sixth top gate connection block is configured to be connected to the fourth scan signal line through a sixth top gate connection via. In at least one circuit unit and a circuit unit adjacent to it in the first direction, the two circuit units share the sixth bottom gate connection via, and the two circuit units share the sixth top gate connection via.

16. The display substrate according to claim 13, characterized in that, The second reset transistor includes at least a second bottom gate electrode and a second top gate electrode. In at least one circuit unit, the first bottom gate electrode and the second bottom gate electrode are an integrally connected structure, and the first top gate electrode and the second top gate electrode are an integrally connected structure.

17. The display substrate according to claim 13, wherein The first reset transistor includes at least a first active layer. In at least one circuit unit and a circuit unit adjacent to the first direction, the first active layers in the two circuit units are integrally connected to each other.

18. The display substrate according to claim 17, wherein The reference signal line is connected to a first region of the first active layer through a first active via. In at least one circuit unit and a circuit unit adjacent to the first direction, the two circuit units share the first active via.

19. The display substrate according to claim 13, wherein The third reset transistor includes at least a seventh active layer. In at least one circuit unit and a circuit unit adjacent to the first direction, the seventh active layers in the two circuit units are integrally connected to each other.

20. The display substrate according to claim 19, wherein The initial signal line is connected to a first region of the seventh active layer through a seventh active via. In at least one circuit unit and a circuit unit adjacent to the first direction, the two circuit units share the seventh active via.

21. A display device, comprising the display substrate according to any one of claims 1 to 20.

22. A method for manufacturing a display substrate, the display substrate including a plurality of circuit units, a plurality of data signal lines extending along a second direction, a plurality of first data connection lines extending along a first direction, and a plurality of second data connection lines extending along the second direction. One end of at least one first data connection line is connected to the data signal line, and the other end is connected to the second data connection line. The first direction and the second direction intersect; the manufacturing method includes: Forming a pixel driving circuit in at least one circuit unit. The pixel driving circuit includes at least a driving transistor, a first reset transistor, a data writing transistor, a light emitting control transistor, a first capacitor, and a second capacitor. The first capacitor includes a first electrode plate and a second electrode plate, and the second capacitor includes a third electrode plate and a fourth electrode plate. A first pole of the first reset transistor is connected to a reference signal line, a second pole of the first reset transistor is connected to a gate electrode of the driving transistor, a first pole of the light emitting control transistor is connected to a first power supply line, a second pole of the light emitting control transistor is connected to a first pole of the driving transistor, a second pole of the driving transistor is connected to the second electrode plate of the first capacitor, a first pole of the data writing transistor is connected to the data signal line, a second pole of the data writing transistor is connected to the fourth electrode plate of the second capacitor, the first electrode plate of the first capacitor is connected to the third electrode plate of the second capacitor. The driving transistor is an oxide transistor, and the aspect ratio of the driving transistor is from 1.25 to 2.67.

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