Sub-pixel, display panel and method for manufacturing display panel

Abstract

The invention discloses a display panel, a sub-pixel and a method for manufacturing the display panel. The display panel comprises a silicon substrate; a first active pattern including a single crystal semiconductor layer on the silicon substrate; a first gate insulating layer covering the first active pattern; a first gate electrode on the first gate insulating layer and including at least a portion overlapping the first active pattern; a first interlayer insulating layer on the first gate electrode; a second active pattern on the first interlayer insulating layer and including a metal oxide semiconductor; a second gate insulating layer covering the second active pattern; a second gate electrode on the second gate insulating layer and including at least a portion overlapping the second active pattern; a second interlayer insulating layer covering the second gate electrode; and a source / drain electrode layer on the second interlayer insulating layer and connected to the first active pattern and the second active pattern.

Description

[0001] Cross - reference to Related Applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2024 - 0002068, filed with the Korean Intellectual Property Office on January 5, 2024, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Aspects of embodiments of the present disclosure relate to sub - pixels, a display panel including the sub - pixels, and a method of manufacturing the display panel. Background Art

[0004] With the development of information technology, the importance of display devices as a connection medium between users and information has been emphasized. Due to the importance of display devices, the use of various display devices (such as liquid crystal display devices and organic light - emitting display devices) has increased.

[0005] As display devices become smaller, methods for improving the resolution of display devices have been studied from multiple perspectives.

[0006] In addition, it may be desirable to reduce power consumption by reducing the magnitude of leakage current in a display device (e.g., in a sub - pixel of a display device), and to improve display quality by displaying images at various frequencies.

[0007] The above information disclosed in this background art section is for enhancing understanding of the background of the present disclosure, and thus, it may include information that does not constitute the prior art. Summary of the Invention

[0008] Embodiments of the present disclosure may relate to sub - pixels, a display panel including the sub - pixels, and a method of manufacturing the display panel, in which images can be displayed at various appropriate frame rates with high resolution and reduced power consumption.

[0009] According to one or more embodiments of the present disclosure, a display panel includes: a silicon substrate; a first active pattern including a single - crystal semiconductor layer on the silicon substrate; a first gate insulating layer covering the first active pattern; a first gate electrode on the first gate insulating layer and including at least a portion overlapping with the first active pattern; a first interlayer insulating layer on the first gate electrode; a second active pattern on the first interlayer insulating layer and including a metal oxide semiconductor; a second gate insulating layer covering the second active pattern; a second gate electrode on the second gate insulating layer and including at least a portion overlapping with the second active pattern; a second interlayer insulating layer covering the second gate electrode; and a source / drain electrode layer on the second interlayer insulating layer and connected to the first active pattern and the second active pattern.

[0010] In an embodiment, the silicon substrate may include a buffer layer containing silicon oxide, and the first active pattern may be located on the buffer layer.

[0011] In an embodiment, the first active pattern may be a semiconductor layer of a P-type transistor, and the second active pattern may be a semiconductor layer of an N-type transistor.

[0012] In an embodiment, the display panel may include a plurality of sub-pixels, and each of the plurality of sub-pixels may include at least one light-emitting element. At least one of the plurality of sub-pixels may further include: a driving transistor including a semiconductor layer, a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node, the driving transistor configured to control the magnitude of a current flowing through the light-emitting element based on a voltage applied to the second node; and a compensation transistor including a semiconductor layer and configured to switch an electrical connection between the first node and the second node. The semiconductor layer of the driving transistor may include the first active pattern, and the semiconductor layer of the compensation transistor may include the second active pattern.

[0013] In an embodiment, the gate electrode of the compensation transistor may be connected to the sub-gate line.

[0014] In an embodiment, the sub-gate line may include a source / drain electrode layer.

[0015] In an embodiment, the sub-gate line may be directly located on the silicon substrate, and the source / drain electrode layer may include a connection electrode configured to electrically connect the sub-gate line and the second active pattern to each other.

[0016] In an embodiment, at least one of the plurality of sub-pixels may further include an initialization transistor including a semiconductor layer, the initialization transistor configured to switch an electrical connection between the second node and a power supply line configured to be applied with an initialization voltage, and the semiconductor layer of the initialization transistor may include the second active pattern.

[0017] In an embodiment, the gate electrode of the initialization transistor may be connected to the sub-gate line.

[0018] In an embodiment, the sub-gate line may include a source / drain electrode layer.

[0019] In an embodiment, the sub-gate line may be directly located on the silicon substrate, and the source / drain electrode layer may include a connection electrode configured to electrically connect the sub-gate line and the second active pattern to each other.

[0020] In an embodiment, the source / drain electrode layer may include a first source / drain electrode layer, and the display panel may further include: a first via layer covering the first source / drain electrode layer; a second source / drain electrode layer on the first via layer and connected to the first source / drain electrode layer through a contact hole; and a second via layer covering the second source / drain electrode layer.

[0021] In an embodiment, the power line may include the second source / drain electrode layer.

[0022] In an embodiment, the power line may be directly located on the silicon substrate, and the source / drain electrode layer may include a connection electrode configured to electrically connect the power line and the second active pattern to each other.

[0023] According to one or more embodiments of the present disclosure, a sub-pixel includes a light-emitting element and a sub-pixel circuit configured to supply current to the light-emitting element. The sub-pixel circuit includes: a driving transistor including a first active pattern and a first gate electrode, the first active pattern having a single crystal structure on a silicon substrate and connected to a first node and a third node, the first gate electrode connected to a second node and including at least a part overlapping with the first active pattern, the driving transistor configured to supply a current corresponding to a voltage applied to the second node; and a compensating transistor including a second active pattern and a second gate electrode, the second active pattern including a metal oxide semiconductor layer, the second gate electrode including at least a part overlapping with the second active pattern, the compensating transistor configured to switch an electrical connection between the first node and the second node.

[0024] In an embodiment, the first active pattern may be a semiconductor layer of a P-type transistor, and the second active pattern may be a semiconductor layer of an N-type transistor.

[0025] According to one or more embodiments of the present disclosure, a method of manufacturing a display panel includes: forming a first active pattern having a single crystal structure on a silicon substrate; forming a first gate insulating layer on the first active pattern; forming a first gate electrode including at least a part overlapping with the first active pattern; forming a first interlayer insulating layer on the first gate electrode; forming a second active pattern including a metal oxide semiconductor on the first interlayer insulating layer; forming a second gate insulating layer on the second active pattern; forming a second gate electrode including at least a part overlapping with the second active pattern on the second gate insulating layer; forming a second interlayer insulating layer on the second gate electrode; and forming a source / drain electrode layer connected to the first active pattern and the second active pattern on the second interlayer insulating layer.

[0026] In an embodiment, the method may further include forming a buffer layer by implanting oxygen ions into the silicon substrate, and the first active pattern may be formed on the buffer layer.

[0027] In an embodiment, forming the first active pattern may include doping with P-type impurities, and forming the second active pattern may include doping with N-type impurities.

[0028] In an embodiment, the method may further include directly forming a power line or a sub-gate line on a silicon substrate, and forming the source / drain electrode layer may include forming at least one of the following: a connection electrode connecting the second active pattern and the power line to each other; and a connection electrode connecting the second active pattern and the sub-gate line to each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other aspects and features of the present disclosure will be more clearly understood from the following detailed description of exemplary, non-limiting embodiments with reference to the accompanying drawings.

[0030] Figure 1 is a system block diagram of a display device according to one or more embodiments of the present disclosure.

[0031] Figure 2 shows Figure 1 a block diagram of an embodiment of any one of the sub-pixels.

[0032] Figure 3 is according to Figure 2 an equivalent circuit diagram of an embodiment of the sub-pixel.

[0033] Figure 4 is according to Figure 1 a plan view of an embodiment of the display panel.

[0034] Figure 5 shows Figure 4 an exploded perspective view of a part of the display panel.

[0035] Figure 6 shows Figure 5 a plan view of an embodiment of any one of the pixels.

[0036] Figure 7 shows a cross-sectional view taken along line I-I' of Figure 6 the [relevant part].

[0037] Figures 8 to 21 shows a method of manufacturing a display panel according to one or more embodiments of the present disclosure.

[0038] Figure 22 shows Figure 7 a cross-sectional view of an embodiment of the emission structure.

[0039] Figure 23 shows Figure 7 a cross-sectional view of another embodiment of the emission structure.

[0040] Figure 24 is a plan view showing another embodiment of any one pixel of Figure 5 .

[0041] Figure 25 is a plan view showing another embodiment of any one pixel of Figure 5 .

[0042] Figure 26 is a diagram showing an example of a display system according to one or more embodiments of the present disclosure.

[0043] Figure 27 is a perspective view showing an application example of the display system of Figure 26 .

[0044] Figure 28 is a diagram showing a head-mounted display worn on a user. Detailed Embodiments

[0045] Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings, in which the same reference numerals always denote the same elements. However, the present disclosure may be implemented in various different forms and should not be construed as limited to the embodiments shown herein. On the contrary, these embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the aspects and features of the present disclosure to those skilled in the art. Therefore, processes, elements, and techniques that are not necessary for those of ordinary skill in the art to fully understand the aspects and features of the present disclosure may not be described. Unless otherwise noted, the same reference numerals denote the same elements throughout the drawings and the written description, and thus, redundant descriptions thereof may not be repeated.

[0046] When a particular embodiment can be implemented differently, the specific process order may be different from the described order. For example, two consecutively described processes may be performed simultaneously or substantially simultaneously, or may be performed in an order opposite to the described order.

[0047] In the accompanying drawings, for clarity, the relative dimensions, thicknesses, and ratios of elements, layers, and regions may be exaggerated and / or simplified. For ease of explanation, spatial relative terms such as "below", "beneath", "under", "underneath", "above", "on" etc. may be used herein to describe the relationship of one element or feature to another (other) element or feature as shown in the accompanying drawings. It will be understood that, in addition to the orientation depicted in the drawings, spatial relative terms are intended to encompass different orientations of the device during use or operation. For example, if the device in the drawings is flipped, an element described as "below" or "beneath" or "under" another element or feature will then be oriented "above" the other element or feature. Thus, the exemplary terms "below" and "beneath" can encompass both an above and a below orientation. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein should be interpreted accordingly.

[0048] In the accompanying drawings, the x-axis, y-axis, and z-axis are not limited to the three axes of a rectangular coordinate system and may be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis may be perpendicular or substantially perpendicular to each other, or may represent different directions that are not perpendicular to each other.

[0049] It will be understood that although terms such as "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, without departing from the spirit and scope of the present disclosure, a first element, first component, first region, first layer, or first section described below may be referred to as a second element, second component, second region, second layer, or second section.

[0050] It will be understood that when an element or layer is referred to as being "on", "connected to", or "coupled to" another element or layer, it can be directly on, directly connected to, or directly coupled to the other element or layer, or there may be one or more intervening elements or layers. Similarly, when a layer, region, or element is referred to as being "electrically connected" to another layer, region, or element, it can be directly electrically connected to the other layer, region, or element, and / or can be indirectly electrically connected with one or more intervening layers, regions, or elements therebetween. Additionally, it will also be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there may also be one or more intervening elements or layers.

[0051] The terms used herein are for the purpose of describing particular embodiments and are not intended to limit the disclosure. As used herein, the singular forms "a" and "an" are also intended to include the plural forms unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises," "comprising," "includes," "including," "has," "having," and "with" are used in this specification, they specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. For example, the expression "A and / or B" means A, B, or A and B. When the expression "at least one of" is used after a list of elements, it modifies the entire list of elements and not a single element in the list. For example, the expressions "at least one of a, b, and c" and "at least one selected from the group consisting of a, b, and c" mean only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0052] As used herein, the terms "substantially," "about," and similar terms are used as approximate terms and not as terms of degree, and are intended to account for the inherent variations in measured or calculated values that would be recognized by a person of ordinary skill in the art. Further, when describing embodiments of the disclosure, the use of "may" means "one or more embodiments of the disclosure." As used herein, the terms "use," "using," and "used" may be considered synonymous with the terms "utilize," "utilizing," and "utilized," respectively.

[0053] In addition, as used herein, the expression "the same" may mean "substantially the same." In other words, the expression "the same" may include the range that can be tolerated by a person skilled in the art. Other expressions may also be those from which "substantially" is omitted.

[0054] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the relevant field and / or the context of this specification, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0055] Figure 1It is a system block diagram of a display device 100 according to one or more embodiments of the present disclosure.

[0056] Referring Figure 1 , according to one or more embodiments of the present disclosure, the display device 100 may include a display panel 110, a gate driving circuit 120, a data driver 130, a voltage generator 140, a controller 150, and a temperature sensor 160.

[0057] The display panel 110 may include a plurality of sub-pixels SP. The first gate line GL1 to the m-th gate line GLm (where m is an integer greater than or equal to 2) connected to the plurality of sub-pixels SP may be disposed on the display panel 110. The first data line DL1 to the n-th data line DLn (where n is an integer greater than or equal to 2) connected to the plurality of sub-pixels SP may be disposed on the display panel 110.

[0058] The plurality of sub-pixels SP may be connected (e.g., electrically connected) to the gate driving circuit 120 through the first gate line GL1 to the m-th gate line GLm. The plurality of sub-pixels SP may be connected (e.g., electrically connected) to the data driver 130 through the first data line DL1 to the n-th data line DLn.

[0059] Each of the plurality of sub-pixels SP may include at least one light-emitting element to generate light. Each of the plurality of sub-pixels SP may generate light of a desired color (e.g., a specific or predetermined color or wavelength band) such as red, green, blue, cyan, magenta, or yellow. Two or more of the plurality of sub-pixels SP may form a pixel PXL. For example, as Figure 1 shown, three sub-pixels SP may form a pixel PXL.

[0060] The gate driving circuit 120 may be connected (e.g., electrically connected) to the plurality of sub-pixels SP (e.g., the plurality of sub-pixels SP arranged substantially along the first direction DR1) through the first gate line GL1 to the m-th gate line GLm. The first direction DR1 may be, for example, a direction from one side (e.g., the left side) of the display panel 110 to the other side (e.g., the right side) of the display panel 110. The first direction DR1 may be, for example, a row direction.

[0061] The gate driving circuit 120 may output a gate signal (e.g., a gate signal of a conductive level or a cut-off level) to the first gate line GL1 to the m-th gate line GLm in response to a gate control signal GCS. In one or more embodiments, the gate control signal GCS may include a start signal for indicating the start of each frame, a horizontal synchronization signal for outputting the gate signal in synchronization with the timing of the application data signal, and the like.

[0062] In one or more embodiments, first emission control lines EL1 to m-th emission control lines ELm connected to a plurality of sub-pixels SP may be further provided on the display panel 110. The first emission control lines EL1 to m-th emission control lines ELm may be provided to extend in a row direction on the display panel 110. The plurality of sub-pixels SP may be connected (e.g., electrically connected) to the first emission control lines EL1 to m-th emission control lines ELm. In the present embodiment, the gate driver circuit 120 may include an emission control driver to control the first emission control lines EL1 to m-th emission control lines ELm. The emission control driver may operate under the control of the controller 150.

[0063] The gate driver circuit 120 may be provided on one side of the display panel 110. However, the present disclosure is not limited thereto. For example, the gate driver circuit 120 may be divided into two or more driver circuits that are physically and / or logically distinct from each other. The driver circuits may be provided on a first side and a second side of the display panel 110 (e.g., a second side of the display panel 110 opposite to the first side). Accordingly, the gate driver circuit 120 may be provided in or around (e.g., adjacent to) the display panel 110 in various suitable forms as needed or desired.

[0064] The data driver 130 may be connected (e.g., electrically connected) to the plurality of sub-pixels SP (e.g., the plurality of sub-pixels SP arranged substantially along a second direction DR2) through first data lines DL1 to n-th data lines DLn. The second direction DR2 may be, for example, a direction that traverses from one side (e.g., the lower side) of the display panel 110 to the other side (e.g., the upper side) of the display panel 110. The second direction DR2 may intersect or cross the first direction DR1. The second direction DR2 may be, for example, a column direction.

[0065] The data driver 130 may receive image data DATA and a data control signal DCS from the controller 150. The data driver 130 may operate in response to the data control signal DCS. In one or more embodiments, the data control signal DCS may include a source start pulse, a source shift clock, a source output enable signal, and the like.

[0066] The data driver 130 may apply data signals having gray-scale voltages (e.g., gray-level voltages) corresponding to the image data DATA to the first data lines DL1 to the nth data lines DLn by using voltages (e.g., gamma voltage Vgamma) from the voltage generator 140. When a gate signal (e.g., a gate signal having an on level) is applied to each of the first gate lines GL1 to the mth gate lines GLm, the data signals corresponding to the image data DATA may be applied to the data lines DL1 to DLn. Each of the plurality of sub-pixels SP may receive the data signals applied to the plurality of sub-pixels SP in a corresponding timing in response to the gate signal (e.g., a gate signal having an on level). Each of the plurality of sub-pixels SP may generate light corresponding to the input data signals. As a result, an image may be displayed on the display panel 110.

[0067] In one or more embodiments, each of the gate driving circuit 120 and the data driver 130 may include complementary metal oxide semiconductor (CMOS) circuit elements.

[0068] The voltage generator 140 may operate in response to a voltage control signal VCS provided from the controller 150. The voltage generator 140 may generate a plurality of voltages and may provide the generated voltages to components of the display device 100. For example, the voltage generator 140 may receive an input voltage from an external device provided outside the display device 100. The voltage generator 140 may control (e.g., may reduce) the level of the received voltage and may regulate the voltage with the adjusted level. The voltage generator 140 may generate a plurality of voltages.

[0069] The voltage generator 140 may generate, for example, a first power supply voltage VDD, a second power supply voltage VSS, a gamma voltage Vgamma, etc. The generated first power supply voltage VDD and second power supply voltage VSS may be applied (e.g., commonly applied) to the plurality of sub-pixels SP. The first power supply voltage VDD may have a relatively high voltage level. The second power supply voltage VSS may have a voltage level lower than the voltage level of the first power supply voltage VDD. The generated gamma voltage Vgamma may be provided to the data driver 130. In other embodiments, the first power supply voltage VDD and / or the second power supply voltage VSS may be provided from an external device (e.g., a power management integrated circuit (PMIC)) of the display device 100.

[0070] In one or more embodiments, the voltage generator 140 may generate other voltages. For example, the voltage generator 140 may generate an initialization voltage to be applied (e.g., commonly applied) to a plurality of sub-pixels SP. For example, during a sensing operation for sensing the electrical characteristics of transistors and / or (multiple) light-emitting elements of a plurality of sub-pixels SP, a reference voltage (e.g., a specific or predetermined reference voltage) may be applied to each of the first data line DL1 to the nth data line DLn. The voltage generator 140 may generate the reference voltage.

[0071] The controller 150 may control the overall operation of the display device 100. The controller 150 may receive input image data IMG and a control signal CTRL from an external device for controlling the operation of displaying the input image data IMG. The controller 150 may provide a gate control signal GCS, a data control signal DCS, a voltage control signal VCS, etc. in response to the received control signal CTRL.

[0072] The controller 150 may convert the input image data IMG to be suitable for the display device 100 or the display panel 110, and then output image data DATA. In one or more embodiments, the controller 150 may align the input image data IMG based on rows to be suitable for the sub-pixels SP, and then output the image data DATA.

[0073] Two or more components of the data driver 130, the voltage generator 140, and the controller 150 may be mounted on a single integrated circuit. As Figure 1 shown, the data driver 130, the voltage generator 140, and the controller 150 may be included in a driver integrated circuit DIC. In this case, the data driver 130, the voltage generator 140, and the controller 150 may be components that are functionally separated from each other in a single driver integrated circuit DIC. In other embodiments, at least one of the data driver 130, the voltage generator 140, and the controller 150 may be mounted on the driver integrated circuit DIC, and the remaining one may be mounted on an integrated circuit different from the driver integrated circuit DIC.

[0074] The temperature sensor 160 may sense the temperature (e.g., the ambient temperature), and may generate temperature data TEP indicating the sensed temperature. In an embodiment, the temperature sensor 160 may be disposed on the display panel 110. In an embodiment, the temperature sensor 160 may be disposed adjacent to the display panel 110 and / or the driver integrated circuit DIC. In an embodiment, the display device 100 may include two or more temperature sensors 160.

[0075] The controller 150 may control various operations of the display device 100 in response to the temperature data TEP. In one or more embodiments, the controller 150 may adjust the brightness of an image output from the display panel 110 in response to the temperature data TEP. For example, the controller 150 may control components such as the data driver 130 and / or the voltage generator 140, and thus may adjust at least one of a data signal, a first power supply voltage VDD, and a second power supply voltage VSS to be input to the display panel 110.

[0076] Figure 2 is a block diagram showing Figure 1 an embodiment of any one sub-pixel SPij of the sub-pixels SP.

[0077] In Figure 2 , the sub-pixel SPij is shown as being provided at Figure 1 the i-th row (where i is an integer equal to or greater than 1 and less than or equal to m) and the j-th column (where j is an integer equal to or greater than 1 and less than or equal to n) among the plurality of sub-pixels SP shown in

[0078] Referring to Figure 2 , the sub-pixel SPij may include a sub-pixel circuit SPC and a light-emitting element LD.

[0079] The light-emitting element LD may be connected (e.g., electrically connected) between a first power supply voltage node VDDN and a second power supply voltage node VSSN. The first power supply voltage node VDDN may be a node to which a first power supply voltage VDD is applied (e.g., see Figure 1 ). The second power supply voltage node VSSN may be a node to which a second power supply voltage VSS is applied (e.g., see Figure 1 ).

[0080] The light-emitting element LD may include a first electrode, an emission structure EMS, and a second electrode. The first electrode may be either an anode electrode AE or a cathode electrode CE of the light-emitting element LD. The second electrode may be the other of the anode electrode AE and the cathode electrode CE of the light-emitting element LD. Hereinafter, for convenience, an example in which the first electrode of the light-emitting element LD is the anode electrode AE and the second electrode of the light-emitting element LD is the cathode electrode CE will be described in more detail.

[0081] The anode electrode AE of the light-emitting element LD can be connected (e.g., electrically connected) to the first power supply voltage node VDDN through the sub-pixel circuit SPC. The cathode electrode CE of the light-emitting element LD can be connected (e.g., electrically connected) to the second power supply voltage node VSSN. For example, the anode electrode AE of the light-emitting element LD can be connected (e.g., electrically connected) to the first power supply voltage node VDDN through one or more transistors included in the sub-pixel circuit SPC.

[0082] The sub-pixel circuit SPC of the sub-pixel SPij can be connected (e.g., electrically connected) to the first gate line GL1 to the m-th gate line GLm (e.g., see Figure 1 ) to the i-th gate line GLi. The sub-pixel circuit SPC of the sub-pixel SPij can be connected (e.g., electrically connected) to the first emission control line EL1 to the m-th emission control line ELm (e.g., see Figure 1 ) to the i-th emission control line Eli. The sub-pixel circuit SPC of the sub-pixel SPij can be connected (e.g., electrically connected) to the first data line DL1 to the n-th data line DLn (e.g., see Figure 1 ) to the j-th data line DLj. The sub-pixel circuit SPC can control the emission timing and / or emission brightness of the light-emitting element LD according to (e.g., in response to) the signal received through the signal line.

[0083] The sub-pixel circuit SPC can operate in response to the gate signal received through the i-th gate line GLi. The sub-pixel circuit SPC can operate in response to the emission control signal received through the i-th emission control line Eli.

[0084] The sub-pixel circuit SPC can receive the data signal through the j-th data line DLj. The sub-pixel circuit SPC can store the voltage of the data signal (e.g., the voltage corresponding to the data signal) in response to the gate signal (e.g., the gate signal having a conductive level) received through the i-th gate line GLi. The sub-pixel circuit SPC can adjust the timing of the current flowing to the light-emitting element LD in response to the emission control signal (e.g., the emission control signal having a conductive level) applied through the i-th emission control line Eli. The magnitude of the current flowing to the light-emitting element LD can vary according to the voltage stored in the sub-pixel circuit SPC. The light-emitting element LD can emit light having a brightness corresponding to the data signal.

[0085] Figure 3 is an equivalent circuit diagram of an embodiment of the sub-pixel SPij according to Figure 2 .

[0086] Refer to Figure 3 , the sub-pixel SPij according to one or more embodiments of the present disclosure can include a sub-pixel circuit SPC and a light-emitting element LD.

[0087] The sub-pixel circuit SPC may be connected (e.g., electrically connected) to the i-th gate line GLi (hereinafter abbreviated as "gate line GLi"), the i-th emission control line ELi (hereinafter abbreviated as "emission control line ELi"), and the j-th data line DLj (hereinafter abbreviated as "data line DLj").

[0088] The gate line GLi may include two or more sub-gate lines. Refer to Figure 3 , the gate line GLi may include the i-th first sub-gate line SGL1i (e.g., abbreviated as "first sub-gate line SGL1i"), the i-th second sub-gate line SGL2i (e.g., abbreviated as "second sub-gate line SGL2i"), the i-th third sub-gate line SGL3i (e.g., abbreviated as "third sub-gate line SGL3i"), and the i-th fourth sub-gate line SGL4i (e.g., abbreviated as "fourth sub-gate line SGL4i").

[0089] The sub-pixel circuit SPC according to one or more embodiments of the present disclosure may include a plurality of switching elements. For example, the sub-pixel circuit SPC may include a first transistor TR1 to a seventh transistor TR7. The sub-pixel circuit SPC according to one or more embodiments of the present disclosure may include at least one storage element. For example, the sub-pixel circuit SPC may include a storage capacitor Cst.

[0090] The first transistor TR1 may control the magnitude of the current (e.g., drive current) to be provided to the light-emitting element LD. The first transistor TR1 may include a first electrode connected (e.g., electrically connected) to the first node N1, a second electrode connected (e.g., electrically connected) to the third node N3, and a gate electrode connected (e.g., electrically connected) to the second node N2. According to the magnitude of the voltage applied to the second node N2, the magnitude of the current (e.g., drive current) flowing through the first transistor TR1 may be determined. The first electrode of the first transistor TR1 may be one of the source electrode and the drain electrode (e.g., such as the drain electrode), and the second electrode may be the remaining one of the source electrode and the drain electrode (e.g., such as the source electrode). The first transistor TR1 may be referred to as a driving transistor.

[0091] The second transistor TR2 may write the data voltage Vdata to the sub-pixel circuit SPC. The second transistor TR2 may switch the electrical connection between the data line DLj and the third node N3. The second transistor TR2 may include a gate electrode connected (e.g., electrically connected) to the first sub-gate line SGL1i. The second transistor TR2 may electrically connect the data line DLj and the third node N3 to each other in response to the first scan signal GW[i] (e.g., the first scan signal GW[i] having a conductive level) applied to the first sub-gate line SGL1i. The second transistor TR2 may be referred to as a scan transistor.

[0092] The third transistor TR3 can switch the electrical connection between the first node N1 and the second node N2. The third transistor TR3 can compensate for a change in the characteristic value (e.g., a change in the threshold voltage) of the first transistor TR1. The third transistor TR3 can include a gate electrode connected (e.g., electrically connected) to the second sub-gate line SGL2i. The third transistor TR3 can electrically connect the first node N1 and the second node N2 to each other in response to a second scan signal GC[i] (e.g., a second scan signal GC[i] having an on level) applied to the second sub-gate line SGL2i. When the third transistor TR3 is turned on, the first transistor TR1 can be connected in the form of a diode (e.g., can be diode-connected). The third transistor TR3 can be referred to as a compensation transistor.

[0093] The fourth transistor TR4 can switch the electrical connection between the second node N2 and the third power supply line PL3. The fourth transistor TR4 can include a gate electrode connected (e.g., electrically connected) to the third sub-gate line SGL3i. The fourth transistor TR4 can electrically connect the second node N2 and the third power supply line PL3 to each other in response to a third scan signal GI[i] (e.g., a third scan signal GI[i] having an on level) applied to the third sub-gate line SGL3i. When the fourth transistor TR4 is turned on, a first initialization voltage VINT supplied to the third power supply line PL3 can be applied to the second node N2. The fourth transistor TR4 can be referred to as a "first initialization transistor".

[0094] The fifth transistor TR5 can switch the electrical connection between the first power supply line PL1 and the third node N3. The fifth transistor TR5 can include a gate electrode connected (e.g., electrically connected) to the emission control line ELi. The fifth transistor TR5 can electrically connect the first power supply line PL1 and the third node N3 to each other in response to an emission control signal EM[i] (e.g., an emission control signal EM[i] having an on level) applied to the emission control line ELi. When the fifth transistor TR5 is turned on, a first power supply voltage VDD supplied to the first power supply line PL1 can be applied to the third node N3. The fifth transistor TR5 can be referred to as a "first emission control transistor".

[0095] The sixth transistor TR6 can switch the electrical connection between the first node N1 and the fourth node N4. The sixth transistor TR6 can include a gate electrode connected (e.g., electrically connected) to the emission control line ELi. The sixth transistor TR6 can electrically connect the first node N1 and the fourth node N4 to each other in response to an emission control signal EM[i] applied to the emission control line ELi (e.g., an emission control signal EM[i] having an on level). When the sixth transistor TR6 is turned on, the first node N1 and the fourth node N4 can be electrically connected to each other. The sixth transistor TR6 can be referred to as a "second emission control transistor".

[0096] The seventh transistor TR7 can switch the electrical connection between the fourth node N4 and the fourth power supply line PL4. The seventh transistor TR7 can include a gate electrode connected (e.g., electrically connected) to the fourth sub-gate line SGL4i. The seventh transistor TR7 can electrically connect the fourth node N4 and the fourth power supply line PL4 to each other in response to a fourth scan signal GB[i] applied to the fourth sub-gate line SGL4i (e.g., a fourth scan signal GB[i] having an on level). When the seventh transistor TR7 is turned on, a second initialization voltage VAINT supplied to the fourth power supply line PL4 can be applied to the fourth node N4. The seventh transistor TR7 can be referred to as a "second initialization transistor".

[0097] The storage capacitor Cst can hold or substantially hold the magnitude of the voltage applied to the second node N2. The storage capacitor Cst can include a first side electrode connected (e.g., electrically connected) to the first power supply line PL1 and a second side electrode connected (e.g., electrically connected) to the second node N2. The storage capacitor Cst can hold or substantially hold the potential difference between the second node N2 and the first power supply line PL1.

[0098] The light-emitting element LD can include a first electrode connected (e.g., electrically connected) to the fourth node N4, a second electrode connected (e.g., electrically connected) to the second power supply line PL2, and an emission structure EMS positioned between the first electrode and the second electrode. The first electrode can be either an anode electrode AE or a cathode electrode CE (e.g., such as the anode electrode AE). The second electrode can be the remaining one of the anode electrode AE and the cathode electrode CE (e.g., such as the cathode electrode CE). For convenience, an example in which the first electrode is the anode electrode AE and the second electrode is the cathode electrode CE will be described in more detail below. However, it should be understood that the present disclosure is not limited thereto. The first electrode (e.g., the anode electrode AE) of the light-emitting element LD can be connected (e.g., electrically connected) to the first power supply line PL1 through the sub-pixel circuit SPC. The second electrode (e.g., the cathode electrode CE) of the light-emitting element LD can be connected (e.g., electrically connected) to the second power supply line PL2.

[0099] The transistors TR1 to TR7 according to one or more embodiments of the present disclosure may include a transistor including a P-type semiconductor and a transistor including an N-type semiconductor. For example, referring to Figure 3 , each of the first transistor TR1, the second transistor TR2, and the fifth transistor TR5, the sixth transistor TR6, and the seventh transistor TR7 may be a transistor including a P-type semiconductor, and each of the third transistor TR3 and the fourth transistor TR4 may be a transistor including an N-type semiconductor.

[0100] In one or more embodiments of the present disclosure, the transistor including a P-type semiconductor may include a single-crystalline silicon semiconductor. For example, the transistor including a P-type semiconductor may be directly formed on a substrate (e.g., a silicon substrate). Since the P-type semiconductor can be directly formed on the substrate, the integration degree of the sub-pixel circuit SPC can be enhanced. For example, the P-type semiconductor may be directly formed on an epitaxial layer of a substrate (e.g., a silicon wafer substrate).

[0101] In one or more embodiments of the present disclosure, the transistor including an N-type semiconductor may include an oxide semiconductor. For example, the transistor including an N-type semiconductor may be disposed on a substrate (e.g., a silicon substrate) in the form of a thin-film transistor (TFT), and at least one insulating layer is interposed between the substrate and the transistor. In one or more embodiments of the present disclosure, each of the third transistor TR3 and the fourth transistor TR4 connected (e.g., electrically connected) to the gate electrode of the first transistor TR1 may include an oxide semiconductor. Accordingly, the magnitude of the leakage current flowing through the third transistor TR3 and the fourth transistor TR4 can be reduced. The transistor including an N-type semiconductor may be implemented using a thin-film transistor (TFT) including a metal-oxide semiconductor. According to one or more embodiments of the present disclosure, the TFT may be formed on a silicon substrate. The transistor including a metal-oxide semiconductor may have a relatively small leakage current. Accordingly, power consumption can be improved, and an image can be displayed at various frame rates.

[0102] However, it may be difficult to directly form polycrystalline silicon on a silicon substrate (e.g., a silicon wafer substrate). For example, an annealing process of irradiating an excimer laser to form polycrystalline silicon may be performed. However, in the case of directly irradiating an excimer laser onto a silicon wafer substrate, the silicon wafer substrate may be damaged. In other words, it may be difficult for those of ordinary skill in the art to form a low-temperature polycrystalline silicon (LTPO) semiconductor on a silicon substrate or to directly form an LTPO semiconductor. Accordingly, the transistor including a P-type semiconductor may be formed to include a single-crystalline silicon (Si) semiconductor.

[0103] At least one of the first transistor TR1 to the seventh transistor TR7 may be a metal-oxide-semiconductor field-effect transistor (MOSFET).

[0104] Figure 4 is a plan view of an embodiment of the display panel 110 according to Figure 1 . The display panel DP shown in

[0105] Figure 4 can be applied to the display panel 110 (for example, see Figure 1 ).

[0106] Referring to Figure 4 , the display panel DP may include a display area DA and a non-display area NDA. The display panel DP can display an image through the display area DA. The non-display area NDA can be provided around the periphery (for example, the edge area) of the display area DA.

[0107] The display panel DP may include a substrate SUB, a plurality of sub-pixels SP provided (for example, formed) on the substrate SUB, and a plurality of pads PD provided (for example, formed) on the substrate SUB.

[0108] In the case where the display panel DP according to one or more embodiments of the present disclosure is used as a display screen for a head-mounted display (HMD), a virtual reality (VR) device, a mixed reality (MR) device, an augmented reality (AR) device, etc., the display panel DP can be positioned close to (for example, very close to) the user's eyes. Therefore, in an embodiment, the sub-pixels SP can be integrated at a relatively high density. To increase the integration degree of the sub-pixels SP, the substrate SUB according to one or more embodiments of the present disclosure can be provided as a silicon substrate. The sub-pixels SP of the display panel DP can be formed on the substrate SUB which is a silicon substrate. The display device 100 including the display panel DP including the substrate SUB which is a silicon substrate (for example, referring to Figure 1 ) can be referred to as an OLED on silicon (OLEDoS) display device.

[0109] The plurality of sub-pixels SP can be provided in the display area DA on the substrate SUB. Referring to Figure 4 , the sub-pixels SP can be arranged in a matrix along a first direction DR1 and a second direction DR2 that intersects or crosses the first direction DR1. However, the present disclosure is not limited thereto. For example, the sub-pixels SP according to an embodiment of the present disclosure can be arranged in a zigzag pattern along the first direction DR1 and the second direction DR2. For example, the plurality of sub-pixels SP can be arranged in an RGGB arrangement (for example, arrangement, is a registered trademark of Samsung Display Co., Ltd.). The first direction DR1 can refer to the row direction, and the second direction DR2 can refer to the column direction. Two or more of the plurality of sub-pixels SP can form a pixel PXL.

[0110] Components for controlling sub-pixels SP can be disposed on the substrate SUB in the non-display area NDA. For example, lines such as the first gate line GL1 to the m-th gate line GLm and the first data line DL1 to the n-th data line DLn (e.g., see Figure 1 ) can be arranged to extend to at least a part of the non-display area NDA.

[0111] At least one of the gate driving circuit 120, the data driver 130, the voltage generator 140, the controller 150, and the temperature sensor 160 (e.g., see Figure 1 ) can be disposed (e.g., integrally disposed) in the non-display area NDA of the display panel DP.

[0112] In an embodiment, the gate driving circuit 120 (e.g., see Figure 1 ) can be formed on the display panel DP and disposed in the non-display area NDA. In an embodiment, the gate driving circuit 120 can be implemented as an independent integrated circuit separate from the display panel DP and installed in the non-display area NDA.

[0113] In an embodiment, the temperature sensor 160 (e.g., see Figure 1 ) can be positioned in the non-display area NDA to sense the temperature of the display panel DP. For example, the temperature sensor 160 can be disposed at the vertex of the display panel DP or a corresponding area thereof. Two or more temperature sensors 160 can be disposed on the display panel DP.

[0114] The pad PD can be disposed on the substrate SUB in the non-display area NDA. The pad PD can be electrically connected to the sub-pixel SP through a line. For example, the pad PD can be connected to the sub-pixel SP through the first data line DL1 to the n-th data line DLn.

[0115] The pad PD can connect the display panel DP to other components of the display device 100 (e.g., refer to Figure 1 ). In one or more embodiments, the voltage and signals for the operation of the components included in the display panel DP can be provided from the driver integrated circuit DIC (e.g., see Figure 1 ) through the pad PD. For example, the first data line DL1 to the n-th data line DLn (e.g., refer to Figure 1 ) can be connected to the driver integrated circuit DIC through the pad PD. For example, the first power supply voltage VDD and the second power supply voltage VSS (e.g., refer to Figure 1 ) can be received from the driver integrated circuit DIC through the pad PD. In the gate driving circuit 120 (e.g., refer to Figure 1)In an embodiment mounted on the display panel DP, the gate control signal GCS can be transmitted from the driver integrated circuit DIC to the gate driving circuit 120 through the pad PD.

[0116] In one or more embodiments, the circuit board can be electrically connected to the pad PD through a conductive adhesive component such as an anisotropic conductive film. The circuit board can be a flexible printed circuit board (FPCB) or a flexible film made of a flexible material. The driver integrated circuit DIC (e.g., refer to Figure 1 ) can be mounted on the circuit board and can be electrically connected to the pad PD.

[0117] In one or more embodiments, the display area DA can have various suitable shapes. For example, the display area DA can have a closed-loop shape including linear and / or curved edges. For example, the display area DA can have various suitable shapes such as a polygon, a circle, a semicircle, an ellipse, etc.

[0118] In one or more embodiments, the display panel DP can have a flat display surface. In one or more embodiments, the display panel DP can have at least partially rounded display surfaces. In one or more embodiments, the display panel DP can be bendable, foldable, or rollable. The display panel DP and / or the substrate SUB can include rigid or flexible materials.

[0119] Figure 5 is an exploded perspective view showing a part of the display panel DP Figure 4 .

[0120] In Figure 5 , for ease of illustration, a part of the display panel DP corresponding to the pixels PXL1 and PXL2 in the pixels PXL of Figure 4 is schematically shown. The other remaining parts of the display panel DP corresponding to other pixels can also be configured in the same or substantially the same manner.

[0121] Refer to Figure 4 and Figure 5 , the first pixel PXL1 and the second pixel PXL2 can be adjacent to each other in the second direction DR2. Each of the first pixel PXL1 and the second pixel PXL2 can include a plurality of sub-pixels. Refer to Figure 5 , each of the first pixel PXL1 and the second pixel PXL2 can include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. However, the present disclosure is not limited thereto. For example, each of the first pixel PXL1 and the second pixel PXL2 can include four sub-pixels, or can include two sub-pixels.

[0122] In Figure 5In [the figure], a case is shown in which, when viewed in a third direction DR3 that intersects or crosses (e.g., is perpendicular to) a first direction DR1 and a second direction DR2, first sub-pixels SP1 to third sub-pixels SP3 have a rectangular shape and the same or substantially the same size as each other. However, the present disclosure is not limited thereto. The first sub-pixels SP1 to third sub-pixels SP3 may be variously modified to have various suitable shapes.

[0123] The display panel DP may include a substrate SUB, a pixel circuit layer PCL, a light-emitting element layer LDL, a thin-film encapsulation layer TFE, an optical function layer OFL, an outer coating OC, and a cover window CW.

[0124] In one or more embodiments, the substrate SUB may include a silicon wafer substrate formed by a semiconductor process. The substrate SUB may include a semiconductor material suitable for forming circuit elements. For example, the semiconductor material may include silicon, germanium, and / or silicon-germanium. The substrate SUB may be provided by a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, a semiconductor-on-insulator (SeOI) layer, etc.

[0125] The pixel circuit layer PCL may be disposed on the substrate SUB. The substrate SUB and / or the pixel circuit layer PCL may include an insulating layer and conductive patterns disposed between the insulating layers. The conductive patterns of the pixel circuit layer PCL may be used as at least some of circuit components, lines, etc. The conductive patterns may include copper, but the present disclosure is not limited thereto.

[0126] The circuit elements may respectively include sub-pixel circuits SPC of the first sub-pixels SP1 to third sub-pixels SP3 (e.g., refer to Figure 2 ). The sub-pixel circuit SPC may include two or more switching elements (e.g., transistors) and one or more storage elements (e.g., capacitors). Each transistor may include a semiconductor portion including a source region, a drain region, and a channel region, and a gate electrode overlapping the semiconductor portion (e.g., the channel region of the semiconductor portion). In an embodiment, when the substrate SUB is provided using a silicon substrate, the semiconductor portions of some of the transistors may be included in the substrate SUB, and the semiconductor portions of other transistors may be disposed on the substrate SUB. The gate electrode may be included in the pixel circuit layer PCL as a conductive pattern of the pixel circuit layer PCL. The capacitor may include electrodes spaced apart from each other (e.g., facing each other). For example, each capacitor may include electrodes spaced apart from each other on a plane defined in a first direction DR1 and a second direction DR2. For example, the capacitor may include electrodes spaced apart from each other in a third direction DR3, and an insulating layer is interposed between the electrodes.

[0127] The lines of the pixel circuit layer PCL may include signal lines connected to each of the first sub-pixel SP1 to the third sub-pixel SP3, such as, for example, gate lines, emission control lines, and data lines. The lines may also include lines connected to the first power voltage node VDDN (see, for example, Figure 2 ). The lines may also include lines connected to the second power voltage node VSSN (see, for example, Figure 2 ).

[0128] The light-emitting element layer LDL may include an anode electrode AE, a pixel defining layer PDL, an emission structure EMS, and a cathode electrode CE.

[0129] The anode electrode AE may be disposed on the pixel circuit layer PCL. The anode electrode AE may be connected to (e.g., in contact with) circuit elements of the pixel circuit layer PCL. The anode electrode AE may include an opaque conductive material capable of reflecting light. However, the present disclosure is not limited thereto. In one or more embodiments, each of the anode electrodes AE may include at least one of various suitable transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), and / or indium tin zinc oxide (ITZO). However, the material of the anode electrode AE is not limited to the above examples. For example, the anode electrode AE may include titanium nitride.

[0130] The pixel defining layer PDL may be disposed on the anode electrode AE. The pixel defining layer PDL may include openings OP exposing at least a portion of each of the anode electrodes AE. The openings OP in the pixel defining layer PDL may respectively correspond to the emission regions of the first sub-pixel SP1 to the third sub-pixel SP3.

[0131] In one or more embodiments, the pixel defining layer PDL may include an inorganic material. In this embodiment, the pixel defining layer PDL may include an inorganic layer (e.g., a plurality of stacked inorganic layers). For example, the pixel defining layer PDL may include silicon oxide (SiO x ) and / or silicon nitride (SiN x ). In other embodiments, the pixel defining layer PDL may include an organic layer containing an organic material. However, the material constituting the pixel defining layer PDL according to the embodiments of the present disclosure is not limited to the above examples.

[0132] The emission structure EMS may be disposed on the anode electrode AE exposed through the opening OP in the pixel defining layer PDL. The emission structure EMS may include one or more functional layers. For example, the emission structure EMS may include one or more functional layers such as a light generation layer (e.g., an emission layer) for generating light, an electron transport layer for transporting electrons, and a hole transport layer for transporting holes.

[0133] In one or more embodiments, the opening OP in the pixel defining layer PDL may be filled with the emission structure EMS. In one or more embodiments, the emission structure EMS may be disposed over the entire surface of the pixel defining layer PDL. For example, the emission structure EMS may extend over the first sub-pixel SP1 to the third sub-pixel SP3. In the present embodiment, at least some of the functional layers in the emission structure EMS may be cut or bent at the boundary (e.g., middle or upper) between the first sub-pixel SP1 to the third sub-pixel SP3. However, the present disclosure is not limited thereto. For example, the portions of the emission structure EMS corresponding to the first sub-pixel SP1 to the third sub-pixel SP3 may be spaced apart or separated from each other, and each of these portions may be disposed in the corresponding opening OP in the pixel defining layer PDL.

[0134] The cathode electrode CE may be disposed on the emission structure EMS. The cathode electrode CE may be disposed over the first sub-pixel SP1 to the third sub-pixel SP3. The cathode electrode CE may be disposed to be commonly connected to the common electrodes of the first sub-pixel SP1 to the third sub-pixel SP3.

[0135] The cathode electrode CE may have a light-transmissive property. For example, the cathode electrode CE may be a thin film metal layer having an appropriate thickness that allows the light emitted from the emission structure EMS to pass therethrough. The cathode electrode CE may be formed of a metal material having a relatively small thickness, or may be formed of a conductive material (e.g., a transparent material) having a light-transmissive property. In one or more embodiments, the cathode electrode CE may include at least one of various suitable transparent conductive materials, including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, or gallium tin oxide. However, the material constituting the cathode electrode CE according to one or more embodiments of the present disclosure is not limited to the above examples. The cathode electrode CE may be used as a semi-reflecting mirror to partially transmit and partially reflect the light emitted from the emission structure EMS.

[0136] Any one of the anode electrodes AE, the portion of the emission structure EMS overlapping with any one of the anode electrodes AE, and the portion of the cathode electrode CE overlapping with the said portion of the emission structure EMS may be understood to constitute a light-emitting element LD (e.g., refer to Figure 2)。Each of the light-emitting elements LD of the first sub-pixel SP1 to the third sub-pixel SP3 may include an anode electrode AE, a portion of the emission structure EMS overlapping with one anode electrode AE, and a portion of the cathode electrode CE overlapping with the said portion of the emission structure EMS. In each of the first sub-pixel SP1 to the third sub-pixel SP3, holes injected from the anode electrode AE and electrons injected from the cathode electrode CE are transported into the emission structure EMS, and thus excitons are formed. When the excitons transition from the excited state to the ground state, light can be generated. The brightness of the light can be determined based on the amount of current flowing through the emission structure EMS. According to the configuration of the emission structure EMS, the wavelength range of the light to be generated from the emission structure EMS can be determined.

[0137] The thin film encapsulation layer TFE may be disposed on the cathode electrode CE. The thin film encapsulation layer TFE may cover the light-emitting element layer LDL and / or the pixel circuit layer PCL. The thin film encapsulation layer TFE may prevent or substantially prevent oxygen, water, etc. from penetrating into the light-emitting element layer LDL. In one or more embodiments, the thin film encapsulation layer TFE may include a structure formed by alternately stacking one or more inorganic layers and one or more organic layers on each other. For example, the inorganic layer may include silicon nitride, silicon oxide, silicon oxynitride (SiO x N y ), etc. For example, the organic layer may include an organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). However, the materials of the organic layer and the inorganic layer of the thin film encapsulation layer TFE are not limited to the above examples.

[0138] The thin film encapsulation layer TFE may further include a thin film such as aluminum oxide (AlO x ) to enhance the encapsulation efficiency of the thin film encapsulation layer TFE. The thin film including aluminum oxide may be positioned on the upper surface of the thin film encapsulation layer TFE facing the optical function layer OFL and / or under the lower surface of the thin film encapsulation layer TFE facing the light-emitting element layer LDL. The thin film including aluminum oxide may be formed by an atomic layer deposition (ALD) method. However, the present disclosure is not limited thereto. The thin film encapsulation layer TFE may further include a thin film formed of at least one of various suitable materials for enhancing the encapsulation efficiency.

[0139] The optical functional layer OFL may be disposed on the thin film encapsulation layer TFE. The optical functional layer OFL may include a color filter layer CFL and a lens array LA. In one or more embodiments, the optical functional layer OFL may be attached to the thin film encapsulation layer TFE through an adhesive layer. For example, the optical functional layer OFL may be manufactured through a separate process and attached to the thin film encapsulation layer TFE through an adhesive layer. The adhesive layer may further perform the function of protecting the lower layer including the thin film encapsulation layer TFE.

[0140] The color filter layer CFL may be disposed between the thin film encapsulation layer TFE and the lens array LA. The color filter layer CFL may filter the light emitted from the emission structure EMS to selectively output light in a wavelength band corresponding to each of the sub-pixels. The color filter layer CFL may include color filters CF corresponding to the first sub-pixel SP1 to the third sub-pixel SP3, respectively. Each of the color filters CF allows light in a desired wavelength band corresponding to the respective sub-pixel to pass therethrough. For example, the color filter corresponding to the first sub-pixel SP1 allows light in the first wavelength band (e.g., red) to pass therethrough. The color filter corresponding to the second sub-pixel SP2 allows light in the second wavelength band (e.g., green) to pass therethrough. The color filter corresponding to the third sub-pixel SP3 allows light in the third wavelength band (e.g., blue) to pass therethrough. The red light may be light having a wavelength of approximately 630 nanometers (nm) to approximately 750 nm. The green light may be light having a wavelength of approximately 495 nm to approximately 570 nm. The blue light may be light having a wavelength of approximately 450 nm to approximately 495 nm.

[0141] At least some of the color filters CF may be omitted according to the color of the light emitted from the emission structure EMS in each sub-pixel. In an embodiment, the color filter layer CFL may be omitted. In one or more embodiments, the color filters CF may overlap each other (e.g., partially overlap each other) in the boundary region between the first sub-pixel SP1 to the third sub-pixel SP3. In other embodiments, the color filters CF may be spaced apart from each other in the boundary region between the first sub-pixel SP1 to the third sub-pixel SP3, and a black matrix may be disposed between the color filters CF.

[0142] The lens array LA may be disposed on the color filter layer CFL. The lens array LA may include lenses LS corresponding to the first sub-pixel SP1 to the third sub-pixel SP3, respectively. Each of the lenses LS may output and guide the light emitted from the emission structure EMS along a desired path (e.g., an expected path), and thus, may enhance the light output efficiency. The lens array LA may have a relatively high refractive index. In one or more embodiments, the lens LS may include an organic material. In one or more embodiments, the lens LS may include an acrylate material. However, the material constituting the lens LS is not limited to the above examples.

[0143] In one or more embodiments, at least some of the color filters CF and / or at least some of the lenses LS may be offset compared to the position of the openings OP in the pixel definition layer PDL. For example, at least some of the color filters CF in the color filter layer CFL and at least some of the lenses LS in the lens array LA may be offset in any direction parallel to or substantially parallel to the plane defined by the first direction DR1 and the second direction DR2 from the vertical line (e.g., the center of the opening OP) of the corresponding opening OP.

[0144] More specifically, in the central region of the display area DA, the center of the color filter CF and the center of the lens LS may be aligned or overlapped with the center of the corresponding opening OP in the pixel definition layer PDL. For example, in the central region of the display area DA, the opening OP in the pixel definition layer PDL may completely overlap with the corresponding color filter CF in the color filter layer CFL and the corresponding lens LS in the lens array LA. In the region of the display area DA adjacent to the non-display area NDA, when viewed in the third direction DR3 (e.g., in a plan view), the center of the color filter CF and the center of the lens LS may be offset in the plane direction from the center of the corresponding opening OP of the pixel definition layer PDL. For example, in the region of the display area DA adjacent to the non-display area NDA, each opening OP of the pixel definition layer PDL may partially overlap with the corresponding color filter CF in the color filter layer CFL and the corresponding lens LS in the lens array LA. Therefore, the light emitted from the emission structure EMS in the central portion of the display area DA can be effectively output in the normal direction of the display surface. The light emitted from the emission structure EMS around the outer edge of the display area DA can be effectively output in a direction inclined at a certain angle (e.g., a specific or predetermined angle) with respect to the normal direction of the display surface.

[0145] The outer coating OC may be provided on the lens array LA. The outer coating OC may cover the optical functional layer OFL, the thin film encapsulation layer TFE, the emission structure EMS, and / or the pixel circuit layer PCL. The outer coating OC may include various suitable materials for protecting the lower layers from foreign substances such as dust, water, etc.

[0146] The cover window CW may be provided on the outer coating OC. The cover window CW may protect the lower layers. In one or more embodiments, the cover window CW may include light-transmitting (e.g., transparent) glass, metal, etc. However, the present disclosure is not limited thereto.

[0147] Figure 6 is a plan view showing Figure 5 an embodiment of any one pixel.

[0148] In Figure 6For ease of explanation, the first pixel PXL1 and the second pixel PXL2 are schematically depicted (e.g., see Figure 5 ). The first pixel PXL1 in Figure 5 . Other pixels may be configured in the same or substantially the same manner as the first pixel PXL1. The first pixel PXL1 may include first to third sub-pixels SP1 to SP3 arranged along a first direction DR1.

[0149] The first sub-pixel SP1 may include a first emission area EMA1 and a non-emission area NEA formed around the first emission area EMA1 (e.g., around the periphery of the first emission area EMA1). The second sub-pixel SP2 may include a second emission area EMA2 and a non-emission area NEA formed around the second emission area EMA2 (e.g., around the periphery of the second emission area EMA2). The third sub-pixel SP3 may include a third emission area EMA3 and a non-emission area NEA formed around the third emission area EMA3 (e.g., around the periphery of the third emission area EMA3).

[0150] The first emission area EMA1 may be an area that emits light from a portion of the emission structure EMS (e.g., referring to Figure 5 ). The second emission area EMA2 may be an area that emits light from a portion of the emission structure EMS corresponding to the second sub-pixel SP2. The third emission area EMA3 may be an area that emits light from a portion of the emission structure EMS corresponding to the third sub-pixel SP3. As described above with reference to Figure 5 , each emission area may be understood as a corresponding opening OP of the pixel defining layer PDL for each of the first to third sub-pixels SP1 to SP3.

[0151] Figure 7 A cross-sectional view taken along line I-I' of Figure 6 is shown.

[0152] Referring to Figure 7 , the display panel DP includes a substrate SUB and a pixel circuit layer PCL disposed on the substrate SUB.

[0153] The substrate SUB may include a silicon wafer substrate formed by a semiconductor process. For example, the substrate SUB may include silicon, germanium, and / or silicon germanium.

[0154] The buffer layer BUF can be disposed on the substrate SUB. For example, the buffer layer BUF can be formed by implanting oxygen ions into the substrate SUB. The buffer layer BUF can include an inorganic insulating material such as silicon oxide (e.g., SiO2), silicon oxynitride, or silicon nitride. The buffer layer BUF can have a single-layer structure or a multi-layer structure including one or more of the foregoing materials.

[0155] The first active pattern ACT1 can be disposed on the buffer layer BUF. The first active pattern ACT1 can be configured as, for example, a semiconductor-on-insulator (SeOI) layer. The first active pattern ACT1 can include a first source region SA1, a first drain region DA1, and a first channel region CA1. The first channel region CA1 can be located between the first source region SA1 and the first drain region DA1. The first active pattern ACT1 can be implemented as a P-type semiconductor layer. For example, the first active pattern ACT1 can be formed by doping a substrate SUB including silicon (Si) (e.g., single-crystalline silicon (Si)) with a P-type impurity (e.g., phosphorus (P), arsenic (As), etc.), and thus, the first active pattern ACT1 can have a single-crystalline structure on the silicon substrate. In an embodiment, the first source region SA1 and the first drain region DA1 can be disposed in the substrate SUB. A well formed by an ion implantation process can be disposed in the substrate SUB. The first source region SA1 and the first drain region DA1 can be disposed to be spaced apart from each other in the well. In the well, the region between the first source region SA1 and the first drain region DA1 can be defined as the first channel region CA1.

[0156] The first gate insulating layer GI1 can be disposed on the first active pattern ACT1. The first gate insulating layer GI1 can be formed of an inorganic insulating layer including an inorganic material. The first gate insulating layer GI1 can include an inorganic insulating material such as silicon dioxide (SiO2), silicon nitride (SiN x )(where x is a positive number), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium dioxide (TiO2), tantalum pentoxide (Ta2O5), hafnium dioxide (HfO2), and / or zinc peroxide (ZnO2).

[0157] The first gate electrode GAT1 can be disposed on the first gate insulating layer GI1. The first gate electrode GAT1 can overlap with the first channel region CA1 of the first active pattern ACT1. The first gate electrode GAT1 can include a metal. For example, the first gate electrode GAT1 can be made of at least one of various suitable metals such as gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), tungsten (W) or a suitable alloy of the metals. In addition, the first gate electrode GAT1 can have a single-layer structure or a multi-layer structure formed by stacking layers made of two or more of the metals and the alloys. The first gate electrode GAT1 can constitute the gate electrode of the first transistor TR1 (e.g., refer to Figure 3 ). The first gate electrode GAT1 can constitute one side electrode of the storage capacitor Cst (e.g., refer to Figure 3 ).

[0158] The second gate insulating layer GI2 can be disposed on the first gate electrode GAT1. The second gate insulating layer GI2 can be formed of an inorganic insulating layer including an inorganic material. The second gate insulating layer GI2 can include inorganic insulating materials such as silicon dioxide (SiO2), silicon nitride (SiN x )(where x is a positive number), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium dioxide (TiO2), tantalum pentoxide (Ta2O5), hafnium dioxide (HfO2) and / or zinc peroxide (ZnO2).

[0159] The second gate electrode GAT2 can be disposed on the second gate insulating layer GI2. The second gate electrode GAT2 can overlap with at least a part of the first gate electrode GAT1. The second gate electrode GAT2 can constitute one side electrode of the storage capacitor Cst (e.g., refer to Figure 3 ). Referring to Figure 3 , the second gate electrode GAT2 can constitute a part of the second node N2. The second gate electrode GAT2 can include a metal. For example, the second gate electrode GAT2 can be made of at least one of various suitable metals such as gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), tungsten (W) or a suitable alloy of the metals. In addition, the second gate electrode GAT2 can have a single-layer structure or a multi-layer structure formed by stacking layers made of two or more of the metals and the alloys.

[0160] The first interlayer dielectric layer ILD1 may be disposed on the second gate electrode GAT2. The first interlayer dielectric layer ILD1 may be an inorganic insulating layer including an inorganic material. Polysiloxane, silicon nitride, silicon oxide, silicon oxynitride, etc. may be used as the inorganic material. However, the present disclosure is not limited thereto.

[0161] The second active pattern ACT2 may be disposed on the first interlayer dielectric layer ILD1. In an embodiment, the second active pattern ACT2 may be formed of an oxide semiconductor. The second active pattern ACT2 may include a metal oxide semiconductor. For example, the second active pattern ACT2 may include indium gallium zinc oxide (IGZO), but the present disclosure is not limited thereto. The second active pattern ACT2 may be doped with an N-type impurity. For example, phosphorus (P), arsenic (As), antimony (Sb), etc. may be used as the N-type impurity. For example, the second active pattern ACT2 may be formed by depositing a metal oxide using a sputtering method and etching (e.g., dry etching) the metal oxide. However, the present disclosure is not limited thereto.

[0162] The second active pattern ACT2 may include a second source region SA2, a second drain region DA2, and a second channel region CA2. The second channel region CA2 may be located between the second source region SA2 and the second drain region DA2. The second active pattern ACT2 may be implemented as an N-type semiconductor layer.

[0163] The third gate insulating layer GI3 may be disposed on the second active pattern ACT2. The third gate insulating layer GI3 may be formed of an inorganic insulating layer including an inorganic material. The third gate insulating layer GI3 may include inorganic insulating materials such as silicon dioxide (SiO2), silicon nitride (SiN x )(where x is a positive number), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium dioxide (TiO2), tantalum pentoxide (Ta2O5), hafnium dioxide (HfO2), and / or zinc peroxide (ZnO2).

[0164] The third gate electrode GAT3 may be disposed on the third gate insulating layer GI3. The third gate electrode GAT3 may overlap with the second channel region CA2 of the second active pattern ACT2. The third gate electrode GAT3 may constitute the third transistor TR3 or the fourth transistor TR4 (e.g., refer to Figure 3) The gate electrode. The third gate electrode GAT3 may include a metal. For example, the third gate electrode GAT3 may be made of at least one of various suitable metals such as gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), tungsten (W), or a suitable alloy of the metals. In addition, the third gate electrode GAT3 may have a single-layer structure or a multi-layer structure formed by stacking layers made of two or more of the metals and the alloys.

[0165] The second interlayer insulating layer ILD2 may be disposed on the third gate electrode GAT3. The second interlayer insulating layer ILD2 may be an inorganic insulating layer including an inorganic material. Polysiloxane, silicon nitride, silicon oxide, silicon oxynitride, etc. may be used as the inorganic material. However, the present disclosure is not limited thereto.

[0166] The first source / drain electrode SD1 may be disposed on the second interlayer insulating layer ILD2. The first source / drain electrode SD1 may be connected to the corresponding first active pattern ACT1 or second active pattern ACT2. For example, the first source / drain electrode SD1 may be connected to the first source region SA1 of the first active pattern ACT1, or may be connected to the first drain region DA1. For example, the first source / drain electrode SD1 may be connected to the second source region SA2 of the second active pattern ACT2, or may be connected to the second drain region DA2.

[0167] The first source / drain electrode SD1 may include a metal. The first source / drain electrode SD1 may include a suitable material having good electrical conductivity. For example, the first source / drain electrode SD1 may include a conductive material containing molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc. The first source / drain electrode SD1 may have a single-layer structure or a multi-layer structure including one or more of the foregoing materials. For example, the first source / drain electrode SD1 may have a multi-layer structure of Ti / Al / Ti.

[0168] Reference Figure 7 , the first active pattern ACT1, the first gate electrode GAT1, and the first source / drain electrode SD1 may constitute a P-type transistor 710. The P-type transistor 710 may include a single-crystalline silicon semiconductor. Reference Figure 3 , each of the first transistor TR1, the second transistor TR2, and the fifth transistor TR5 to the seventh transistor TR7 may be implemented as a P-type transistor 710.

[0169] Reference Figure 7 , the second active pattern ACT2, the third gate electrode GAT3, and the first source / drain electrode SD1 may constitute an N-type transistor 720. The N-type transistor 720 may include a metal oxide semiconductor. Further referenceFigure 3 Each of the third transistor TR3 and the fourth transistor TR4 may be implemented as an N-type transistor 720.

[0170] The first via layer VIA1 may be disposed on the first source / drain electrode SD1. For example, the first via layer VIA1 may be formed of an organic insulating layer including an organic material. The first via layer VIA1 may include an organic insulating material such as, by way of example, a general polymer (such as polymethyl methacrylate or polystyrene), a polymer derivative including a phenolic group, an acrylic polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorinated polymer, a parylene-based polymer, a polyvinyl alcohol-based polymer, and / or a suitable blend thereof. The first via layer VIA1 may be used to planarize or substantially planarize the area on the first source / drain electrode SD1.

[0171] The second source / drain electrode SD2 may be disposed on the first via layer VIA1. The second source / drain electrode SD2 may be connected to the corresponding first source / drain electrode SD1. The second source / drain electrode SD2 may connect the first source / drain electrodes SD1 positioned to be spaced apart from each other, or may connect the corresponding first source / drain electrodes SD1 to an electrode in an upper layer (such as an anode electrode AE, etc.).

[0172] The second via layer VIA2 may be disposed on the second source / drain electrode SD2. For example, the second via layer VIA2 may be formed of an organic insulating layer including an organic material. The second via layer VIA2 may include an organic insulating material such as, by way of example, a general polymer (such as polymethyl methacrylate or polystyrene), a polymer derivative including a phenolic group, an acrylic polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorinated polymer, a parylene-based polymer, a polyvinyl alcohol-based polymer, and / or a suitable blend thereof. The second via layer VIA2 may be used to planarize or substantially planarize the area on the second source / drain electrode SD2.

[0173] The light-emitting element layer LDL may be disposed on the second via layer VIA2. The light-emitting element layer LDL may include an anode electrode AE, a pixel defining layer PDL, an emission structure EMS, a cathode electrode CE, etc.

[0174] The anode electrode AE can be disposed on the second via layer VIA2. The anode electrode AE can be connected to the second source / drain electrode SD2 through a via hole that penetrates (e.g., pierces) the second via layer VIA2. In one or more embodiments, the anode electrode AE can include a metal layer made of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a suitable alloy thereof and / or indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), etc. However, the material of the anode electrode AE is not limited to the above examples. For example, the anode electrode AE can include titanium nitride.

[0175] The pixel defining layer PDL can be disposed on the anode electrode AE. The pixel defining layer PDL can include an opening that exposes at least a portion of the anode electrode AE. The opening in the pixel defining layer PDL can define an emission region through which light is emitted from a corresponding one of the first sub-pixel SP1 to the third sub-pixel SP3 (e.g., refer to Figure 6 ). The pixel defining layer PDL can be disposed in the non-emission region NEA (e.g., see Figure 6 ). The pixel defining layer PDL can define the first emission region EMA1 to the third emission region EMA3 (e.g., see Figure 6 ). The pixel defining layer PDL can include a light absorbing material or can be coated with a light absorbent such that the pixel defining layer PDL can be used to absorb light introduced from the outside. For example, the pixel defining layer PDL can include a carbon-based black pigment. However, the present disclosure is not limited thereto. The pixel defining layer PDL can include an opaque metal having a high light absorption rate, such as chromium (Cr), molybdenum (Mo), an alloy of molybdenum and titanium (MoTi), tungsten (W), vanadium (V), niobium (Nb), tantalum (Ta), manganese (Mn), cobalt (Co), or nickel (Ni).

[0176] In one or more embodiments, the pixel defining layer PDL can include a plurality of inorganic insulating layers. Each of the inorganic insulating layers can include at least one of silicon oxide (SiO x ) and silicon nitride (SiN x ). For example, the pixel defining layer PDL can include a first inorganic insulating layer to a third inorganic insulating layer stacked on top of each other in sequence. The first inorganic insulating layer to the third inorganic insulating layer can include silicon nitride, silicon oxide, and silicon nitride, respectively. However, the present disclosure is not limited thereto. The first inorganic insulating layer to the third inorganic insulating layer can have a stepped shape in a region adjacent to each of the openings.

[0177] In an embodiment, a separator may be provided (e.g., disposed) in a boundary region between adjacent sub-pixels. In other words, the separator may be disposed in each of the boundary regions between sub-pixels SP (e.g., see Figure 1 ). The separator may form a discontinuity in the emission structure EMS in the boundary region. For example, the emission structure EMS may be cut or bent by the separator in the boundary region.

[0178] The emission structure EMS may be disposed on an anode electrode AE exposed through an opening in a pixel defining layer PDL. The emission structure EMS may fill the opening of the pixel defining layer PDL and may be disposed throughout the entire region of the first sub-pixel SP1 to the third sub-pixel SP3 (e.g., refer to Figure 6 ). As described above, at least a portion of the emission structure EMS may be partially cut or bent by the separator in the boundary region. Thus, during operation of the display panel DP, the magnitude of the current (e.g., leakage current) leaking from each of the first sub-pixel SP1 to the third sub-pixel SP3 to an adjacent (e.g., neighboring) sub-pixel through the layers included in the emission structure EMS may be reduced or eliminated.

[0179] A cathode electrode CE may be disposed on the emission structure EMS. The cathode electrode CE may be commonly provided to (e.g., disposed in) the first sub-pixel SP1 to the third sub-pixel SP3 (e.g., refer to Figure 6 ). The cathode electrode CE may serve as a semi-reflecting mirror that partially transmits and partially reflects light emitted from the emission structure EMS. The cathode electrode CE may be formed of a metal layer and / or a transparent conductive layer, the metal layer being formed of a suitable material such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a suitable alloy thereof, and the transparent conductive layer being formed of a suitable material such as ITO, IZO, ZnO, or ITZO. In an embodiment, the cathode electrode CE may have a multi-layer structure having two or more layers including a thin metal layer. For example, the cathode electrode CE may have a three-layer structure including ITO / Ag / ITO.

[0180] A thin film encapsulation layer TFE may be disposed on the cathode electrode CE. The thin film encapsulation layer TFE may prevent or substantially prevent oxygen, water, etc. from penetrating into the light emitting element layer LDL. The thin film encapsulation layer TFE may have a single-layer structure or may have a multi-layer structure. In an embodiment, the thin film encapsulation layer TFE may have a stacked structure in which an inorganic material, an organic material, and an inorganic material are deposited in the listed order. The outermost layer in the thin film encapsulation layer TFE may include an inorganic material.

[0181] The buffer layer BUF and the first active pattern ACT1 can be directly formed on the substrate SUB. The first gate insulating layer GI1, the second gate insulating layer GI2, the first interlayer insulating layer ILD1, the third gate insulating layer GI3, the second interlayer insulating layer ILD2, the first via layer VIA1, and the second via layer VIA2 can constitute the pixel circuit layer PCL. The pixel circuit layer PCL can be formed on the substrate SUB.

[0182] Figures 8 to 21 A method of manufacturing a display panel according to one or more embodiments of the present disclosure is shown.

[0183] For ease of explanation, the process of forming the first transistor TR1, the third transistor TR3, and the fourth transistor TR4 (e.g., see Figure 3 ) will be described in more detail to describe the method of manufacturing a display panel according to one or more embodiments of the present disclosure.

[0184] For example, during the process of forming the first transistor TR1, the second transistor TR2 and the fifth transistor TR5 to the seventh transistor TR7 (e.g., see Figure 3 ) may also be formed, but are not shown for convenience. Hereinafter, reference will be made to Figure 3 The process of forming transistors and lines will be described in more detail.

[0185] The method of manufacturing a display panel according to one or more embodiments of the present disclosure may include forming a first active pattern ACT1 (step S800).

[0186] When forming the first active pattern ACT1 (step S800), the first active pattern ACT1 may be formed on the buffer layer BUF on the substrate SUB. The first active pattern ACT1 may be set as a SeOI layer. The buffer layer BUF may be formed by implanting oxygen ions into the substrate SUB. The first active pattern ACT1 may be formed of a P-type semiconductor layer. When forming the first active pattern ACT1, a process of doping P-type impurities may be performed. Aluminum (Al), gallium (Ga), indium (In), etc. may be used as P-type impurities. The first active pattern ACT1 may be the semiconductor layer of the first transistor TR1 (e.g., see Figure 3 ).

[0187] The method of manufacturing a display panel according to one or more embodiments of the present disclosure may include forming a first gate insulating layer GI1 (step S900).

[0188] The first gate insulating layer GI1 may cover all of the first active pattern ACT1 and the buffer layer BUF.

[0189] A method of manufacturing a display panel according to one or more embodiments of the present disclosure may include forming a first gate electrode GAT1 (step S1000).

[0190] The first gate electrode GAT1 may be positioned to overlap at least a portion of the first active pattern ACT1 (e.g., in the third direction DR3). The first gate electrode GAT1 may form a gate electrode of the first transistor TR1.

[0191] A method of manufacturing a display panel according to one or more embodiments of the present disclosure may include forming a second gate insulating layer GI2 (step S1100).

[0192] The second gate insulating layer GI2 may cover the entire first gate electrode GAT1 and the first gate insulating layer GI1.

[0193] A method of manufacturing a display panel according to one or more embodiments of the present disclosure may include forming a second gate electrode GAT2 (step S1200).

[0194] The second gate electrode GAT2 may be connected to the first gate electrode GAT1 through a contact hole CNT. The second gate electrode GAT2 may constitute a second node N2 (e.g., see Figure 3 ).

[0195] A method of manufacturing a display panel according to one or more embodiments of the present disclosure may include forming a first interlayer insulating layer ILD1 (step S1300).

[0196] The first interlayer insulating layer ILD1 may cover the entire second gate electrode GAT2 and the second gate insulating layer GI2.

[0197] A method of manufacturing a display panel according to one or more embodiments of the present disclosure may include forming a second active pattern ACT2 (step S1400).

[0198] The second active pattern ACT2 may be formed of an N-type semiconductor layer. When forming the second active pattern ACT2, a process of doping N-type impurities may be performed. The second active pattern ACT2 may constitute a semiconductor layer of the third transistor TR3 and each of the semiconductor layers of the fourth transistor TR4 (e.g., see Figure 3 ).

[0199] A method of manufacturing a display panel according to one or more embodiments of the present disclosure may include forming a third gate insulating layer GI3 (step S1500).

[0200] The third gate insulating layer GI3 may cover the entire second active pattern ACT2 and the first interlayer insulating layer ILD1.

[0201] A method of manufacturing a display panel according to one or more embodiments of the present disclosure may include forming a third gate electrode GAT3 (step S1600).

[0202] The third gate electrode GAT3 may be positioned (e.g., in a third direction DR3) to overlap at least a portion of the second active pattern ACT2. The third gate electrode GAT3 may constitute the gate electrode of the third transistor TR3 and the gate electrode of the fourth transistor TR4.

[0203] A method of manufacturing a display panel according to one or more embodiments of the present disclosure may include forming a second interlayer insulating layer ILD2 (step S1700).

[0204] The second interlayer insulating layer ILD2 may cover the entire third gate electrode GAT3 and the third gate insulating layer GI3.

[0205] A method of manufacturing a display panel according to one or more embodiments of the present disclosure may include forming a first source / drain electrode SD1 (step S1800).

[0206] The first source / drain electrode SD1 may constitute a second sub-gate line SGL2. Herein, the second sub-gate line SGL2 may be Figure 3 the second sub-gate line SGL2i in. The first source / drain electrode SD1 constituting the second sub-gate line SGL2 may be connected to the third gate electrode GAT3 constituting the gate electrode of the third transistor TR3 through a contact hole.

[0207] The first source / drain electrode SD1 may constitute a third sub-gate line SGL3. Herein, the third sub-gate line SGL3 may be Figure 3 the third sub-gate line SGL3i in. The first source / drain electrode SD1 constituting the third sub-gate line SGL3 may be connected to the third gate electrode GAT3 constituting the gate electrode of the fourth transistor TR4 through a contact hole.

[0208] The first source / drain electrode SD1 may constitute a second node N2. The first source / drain electrode SD1 constituting the second node N2 may be connected to the second active pattern ACT2 of the semiconductor layer of the third transistor TR3, the second active pattern ACT2 of the semiconductor layer of the fourth transistor TR4, and the second gate electrode GAT2 connected to the gate electrode of the first transistor TR1 through corresponding contact holes.

[0209] The first source / drain electrode SD1 may form the first node N1. The first source / drain electrode SD1 forming the first node N1 may be connected to the second active pattern ACT2 of the semiconductor layer forming the third transistor TR3 through a contact hole. The first source / drain electrode SD1 forming the first node N1 may be connected to the first active pattern ACT1 of the semiconductor layer forming the first transistor TR1 through a contact hole.

[0210] The first source / drain electrode SD1 may form the first side electrode (e.g., the electrode to which the first initialization voltage VINT is applied) of the fourth transistor TR4. The first source / drain electrode SD1 forming the first side electrode of the fourth transistor TR4 may be connected to the second active pattern ACT2 of the semiconductor layer forming the fourth transistor TR4 through a contact hole.

[0211] In an embodiment, the second sub-gate line SGL2 and the third sub-gate line SGL3 may be directly formed on the substrate SUB. In this embodiment, the first source / drain electrode SD1 may be formed as a connection electrode connecting the second active pattern ACT2 and the second sub-gate line SGL2 and the third sub-gate line SGL3 directly formed on the substrate SUB.

[0212] The first sub-gate line SGL1i, the fourth sub-gate line SGL4i, and the emission control line ELi (e.g., see Figure 3 ) may be configured by the first source / drain electrode SD1 in the same or substantially the same manner as the configuration of the second sub-gate line SGL2 and the third sub-gate line SGL3. However, in an embodiment, at least one of the first sub-gate line SGL1i, the fourth sub-gate line SGL4i, and the emission control line ELi may be directly formed on the substrate SUB.

[0213] A method of manufacturing a display panel according to one or more embodiments of the present disclosure may include forming a first via layer VIA1 (step S1900).

[0214] The first via layer VIA1 may cover the entire first source / drain electrode SD1 and the second interlayer insulating layer ILD2.

[0215] A method of manufacturing a display panel according to one or more embodiments of the present disclosure may include forming a second source / drain electrode SD2 (step S2000).

[0216] The second source / drain electrode SD2 may form the first node N1. The second source / drain electrode SD2 forming the first node N1 may be connected to the first source / drain electrode SD1 (e.g., a plurality of first source / drain electrodes SD1) forming the first node N1 through a contact hole.

[0217] The second source / drain electrode SD2 may form a third power line PL3. The second source / drain electrode SD2 may be connected to a first source / drain electrode SD1 that forms a first side electrode of a fourth transistor TR4 through a contact hole.

[0218] In an embodiment, the third power line PL3 may be directly formed on the substrate SUB. In this embodiment, the first source / drain electrode SD1 may be formed as a connection electrode that connects the second active pattern ACT2 and the third power line PL3 directly formed on the substrate SUB. The second source / drain electrode SD2 may be formed as a connection electrode that connects the first source / drain electrode SD1 and the third power line PL3 directly formed on the substrate SUB.

[0219] The first power line PL1, the second power line PL2, the fourth power line PL4, and the data line DLj (e.g., see Figure 3 ) may be configured by the second source / drain electrode SD2 in the same or substantially the same manner as the configuration of the third power line PL3. However, in an embodiment, at least one of the first power line PL1, the second power line PL2, the fourth power line PL4, and the data line DLj may be directly formed on the substrate SUB.

[0220] A method of manufacturing a display panel according to one or more embodiments of the present disclosure may include forming a second via layer VIA2 (step S2100).

[0221] The second via layer VIA2 may cover the entire second source / drain electrode SD2 and the first via layer VIA1.

[0222] A method of manufacturing a display panel according to one or more embodiments of the present disclosure may further include forming a light-emitting element layer LDL (e.g., refer to Figure 7 ) on the second via layer VIA2.

[0223] According to a method of manufacturing a display panel according to one or more embodiments of the present disclosure, a transistor including a single-crystalline semiconductor and a transistor including a metal oxide semiconductor may be formed on the substrate SUB.

[0224] Because a transistor including a single-crystalline semiconductor is formed, the surface area of the sub-pixel circuit SPC (e.g., refer to Figure 3 ) may be reduced. Therefore, the number of sub-pixels provided per unit surface area may be increased. As a result, a high-resolution display device 100 (e.g., refer to Figure 1 ) may be provided.

[0225] Because a transistor including a metal oxide semiconductor is formed, the leakage current may be reduced. As a result, the display device 100 (e.g., refer to Figure 1) display quality.

[0226] Figure 22 shows Figure 7 A cross-sectional view of an embodiment of the emission structure EMS.

[0227] Referring Figure 22 , the emission structure EMS may have a series structure in which a first emission component EU1 and a second emission component EU2 are stacked.

[0228] Each of the first emission component EU1 and the second emission component EU2 may include at least one emission layer to generate light in response to a current applied thereto. The first emission component EU1 may include a first emission layer EML1, a first electron transport component ETU1, and a first hole transport component HTU1. The first emission layer EML1 may be disposed between the first electron transport component ETU1 and the first hole transport component HTU1. The second emission component EU2 may include a second emission layer EML2, a second electron transport component ETU2, and a second hole transport component HTU2. The second emission layer EML2 may be disposed between the second electron transport component ETU2 and the second hole transport component HTU2.

[0229] Each of the first hole transport component HTU1 and the second hole transport component HTU2 may include at least one of a hole injection layer and a hole transport layer. In an embodiment, each of the first hole transport component HTU1 and the second hole transport component HTU2 may further include a functional layer such as a hole buffer layer or an electron blocking layer. The first hole transport component HTU1 and the second hole transport component HTU2 may have the same or substantially the same configuration as each other, but the present disclosure is not limited thereto, and in some embodiments, the first hole transport component HTU1 and the second hole transport component HTU2 may have different configurations from each other.

[0230] Each of the first electron transport component ETU1 and the second electron transport component ETU2 may include at least one of an electron injection layer and an electron transport layer. In an embodiment, each of the first electron transport component ETU1 and the second electron transport component ETU2 may further include a functional layer such as an electron buffer layer or a hole blocking layer. The first electron transport component ETU1 and the second electron transport component ETU2 may have the same or substantially the same configuration as each other, but the present disclosure is not limited thereto, and in some embodiments, the first electron transport component ETU1 and the second electron transport component ETU2 may have different configurations from each other.

[0231] The connection layer can connect the first emission component EU1 and the second emission component EU2 to each other. The connection layer can be provided in the form of a charge generation layer CGL. In one or more embodiments, the charge generation layer CGL can have a stacked structure including a P-type dopant layer and an N-type dopant layer. For example, the P-type dopant layer can include a P-type dopant such as HAT-CN, TCNQ, or NDP-9. For example, the N-type dopant layer can include an alkali metal, an alkaline earth metal, a lanthanide metal, or a suitable combination thereof. However, the present disclosure is not limited thereto.

[0232] In one or more embodiments of the present disclosure, the first emission layer EML1 and the second emission layer EML2 can generate light having different colors from each other (e.g., in different wavelength bands). The light emitted from the first emission layer EML1 and the light emitted from the second emission layer EML2 can be mixed with each other to be visible to the user as white light. For example, the first emission layer EML1 can generate blue light, and the second emission layer EML2 can generate yellow light. In some embodiments, the second emission layer EML2 can include a structure in which a first sub-emission layer for generating red light and a second sub-emission layer for generating green light are stacked. The red light and the green light can be mixed with each other to allow the second emission layer EML2 to provide yellow light. In this case, an intermediate layer for performing the function of transporting holes and / or blocking electrons can be further provided between the first sub-emission layer and the second sub-emission layer.

[0233] In some embodiments, the first emission layer EML1 and the second emission layer EML2 can generate light having the same or substantially the same color as each other.

[0234] The emission structure EMS can be formed by a suitable scheme or method such as vacuum deposition, inkjet printing, etc., but the present disclosure is not limited thereto.

[0235] Figure 23 is a cross-sectional view showing Figure 7 another embodiment of the emission structure EMS.

[0236] Referring to Figure 23 , the emission structure EMS' can have a series structure in which the first emission component EU1' to the third emission component EU3' are stacked.

[0237] Each of the first emission component EU1' to the third emission component EU3' may include an emission layer to generate light in response to an electric current applied thereto. The first emission component EU1' may include a first emission layer EML1', a first electron transport component ETU1', and a first hole transport component HTU1'. The first emission layer EML1' may be disposed between the first electron transport component ETU1' and the first hole transport component HTU1'. The second emission component EU2' may include a second emission layer EML2', a second electron transport component ETU2', and a second hole transport component HTU2'. The second emission layer EML2' may be disposed between the second electron transport component ETU2' and the second hole transport component HTU2'. The third emission component EU3' may include a third emission layer EML3', a third electron transport component ETU3', and a third hole transport component HTU3'. The third emission layer EML3' may be disposed between the third electron transport component ETU3' and the third hole transport component HTU3'.

[0238] Each of the first hole transport component HTU1' to the third hole transport component HTU3' may include at least one of a hole injection layer and a hole transport layer. In an embodiment, each of the first hole transport component HTU1' to the third hole transport component HTU3' may further include at least one of a hole buffer layer and an electron blocking layer. In an embodiment, the first hole transport component HTU1' to the third hole transport component HTU3' may have the same or substantially the same configuration as each other. However, the present disclosure is not limited thereto. In some embodiments, the first hole transport component HTU1' to the third hole transport component HTU3' may have different configurations from each other.

[0239] Each of the first electron transport component ETU1' to the third electron transport component ETU3' may include at least one of an electron injection layer and an electron transport layer. In an embodiment, each of the first electron transport component ETU1' to the third electron transport component ETU3' may further include at least one of an electron buffer layer and a hole blocking layer. In an embodiment, the first electron transport component ETU1' to the third electron transport component ETU3' may have the same or substantially the same configuration as each other. However, the present disclosure is not limited thereto. In some embodiments, the first electron transport component ETU1' to the third electron transport component ETU3' may have different configurations from each other.

[0240] The first charge generation layer CGL1' may be disposed between the first emission component EU1' and the second emission component EU2'. The second charge generation layer CGL2' may be disposed between the second emission component EU2' and the third emission component EU3'.

[0241] In one or more embodiments of the present disclosure, the first emission layer EML1' to the third emission layer EML3' may generate light having different colors from each other (e.g., in different wavelength bands). The light emitted from the first emission layer EML1' to the third emission layer EML3' may be mixed with each other to be visible to the user as white light. For example, the first emission layer EML1' may generate light in the first wavelength band (e.g., blue). The second emission layer EML2' may generate light in the second wavelength band (e.g., green). The third emission layer EML3' may generate light in the third wavelength band (e.g., red).

[0242] In other embodiments, two or more of the first emission layer EML1' to the third emission layer EML3' may generate light in the same or substantially the same wavelength band (e.g., the same or substantially the same color) from each other.

[0243] Figure 24 is a plan view showing Figure 5 another embodiment of any one pixel.

[0244] Referring to Figure 24 , the first pixel PXL1' may include a first sub-pixel SP1' to a third sub-pixel SP3'.

[0245] The first sub-pixel SP1' may include a first emission area EMA1' and a non-emission area NEA' formed around the first emission area EMA1' (e.g., the periphery of the first emission area EMA1'). The second sub-pixel SP2' may include a second emission area EMA2' and a non-emission area NEA' formed around the second emission area EMA2' (e.g., the periphery of the second emission area EMA2'). The third sub-pixel SP3' may include a third emission area EMA3' and a non-emission area NEA' formed around the third emission area EMA3' (e.g., the periphery of the third emission area EMA3').

[0246] The first sub-pixel SP1' and the second sub-pixel SP2' may be arranged along the second direction DR2 (e.g., may be adjacent to each other in the second direction DR2). The third sub-pixel SP3' may be disposed in the first direction DR1 with respect to each of the first sub-pixel SP1' and the second sub-pixel SP2' (e.g., may be adjacent to each of the first sub-pixel SP1' and the second sub-pixel SP2' in the first direction DR1).

[0247] The surface area of the second sub-pixel SP2' can be larger than the surface area of the first sub-pixel SP1'. The surface area of the third sub-pixel SP3' can be larger than the surface area of the second sub-pixel SP2'. The surface area of the second emission area EMA2' that is the emission area of the second sub-pixel SP2' can be larger than the surface area of the first emission area EMA1' that is the emission area of the first sub-pixel SP1'. The surface area of the third emission area EMA3' that is the emission area of the third sub-pixel SP3' can be larger than the surface area of the second emission area EMA2' that is the emission area of the second sub-pixel SP2'. However, the present disclosure is not limited thereto. For example, the surface areas of the first sub-pixel SP1' and the second sub-pixel SP2' can be the same as or substantially the same as each other. The surface area of the third sub-pixel SP3' can be larger than the surface area of each of the first sub-pixel SP1' and the second sub-pixel SP2'. The surface area of each of the first sub-pixel SP1' to the third sub-pixel SP3' can be variously modified as needed or desired according to embodiments.

[0248] Figure 25 is a plan view showing Figure 5 another embodiment of any one pixel.

[0249] Referring Figure 25 , the first pixel PXL1" can include the first sub-pixel SP1" to the third sub-pixel SP3". The first sub-pixel SP1" can include the first emission area EMA1" and a non-emission area NEA" formed around the first emission area EMA1" (for example, the periphery of the first emission area EMA1"). The second sub-pixel SP2" can include the second emission area EMA2" and a non-emission area NEA" formed around the second emission area EMA2" (for example, the periphery of the second emission area EMA2"). The third sub-pixel SP3" can include the third emission area EMA3" and a non-emission area NEA" formed around the third emission area EMA3" (for example, the periphery of the third emission area EMA3").

[0250] When observed in one direction (for example, in the third direction DR3), each of the first sub-pixel SP1" to the third sub-pixel SP3" can have a polygonal shape. For example, the shape of each of the first sub-pixel SP1" to the third sub-pixel SP3" can be (for example, in a plan view) a hexagon, as Figure 25 shown in.

[0251] When observed in one direction (for example, in the third direction DR3), each of the first emission area EMA1" to the third emission area EMA3" can have a circular shape. However, the present disclosure is not limited thereto. For example, each of the first emission area EMA1" to the third emission area EMA3" can have a polygonal shape.

[0252] The first subpixel SP1" and the third subpixel SP3" may be arranged along the first direction DR1 (eg, may be adjacent to each other in the first direction DR1). The second subpixel SP2" may be disposed in a direction (eg, a diagonal direction) inclined at an acute angle based on the second direction DR2 relative to the first subpixel SP1".

[0253] Figure 6 , Figure 24 and Figure 25 The arrangement of the sub-pixels SP shown in FIG. 1 is illustrative, and the present disclosure is not limited thereto. Each pixel PXL may include two or more sub-pixels SP (eg, see Figure 1 ). The sub-pixels SP in the pixel PXL may be arranged in various suitable ways. Each of the sub-pixels SP may have various suitable shapes. The emission region of the sub-pixel SP may also have various suitable shapes.

[0254] Figure 26 is a diagram illustrating an example of a display system 2600 according to one or more embodiments of the present disclosure.

[0255] refer to Figure 26 , the display system 2600 may include a processor 2610 and one or more display devices 2620 and 2630 .

[0256] The processor 2610 can perform various tasks and operations. In one or more embodiments, the processor 2610 may include an application processor (AP), a graphics processing unit (GPU), a microprocessor, a central processing unit (CPU), etc. The processor 2610 can be connected to other components of the display system 2600 through a bus system to control these components.

[0257] exist Figure 26 , there is shown a case where a display system 2600 includes a first display device 2620 and a second display device 2630. The processor 2610 may be connected to the first display device 2620 through a first channel CH1, and may be connected to the second display device 2630 through a second channel CH2.

[0258] The processor 2610 may transmit the first image data IMG1 and the first control signal CTRL1 to the first display device 2620 through the first channel CH1. The first display device 2620 may display an image based on the first image data IMG1 and the first control signal CTRL1. Figure 1configured in the same or substantially the same manner as the described display device 100. In this case, the first image data IMG1 and the first control signal CTRL1 may be provided as the input image data IMG and the control signal CTRL, respectively (e.g., see Figure 1 ) provided.

[0259] The processor 2610 may transmit the second image data IMG2 and the second control signal CTRL2 to the second display device 2630 via the second channel CH2. The second display device 2630 may display an image based on the second image data IMG2 and the second control signal CTRL2. The second display device 2630 may be configured in the same or substantially the same manner as the described display device 100 with reference to Figure 1 In this case, the second image data IMG2 and the second control signal CTRL2 may be provided as the input image data IMG and the control signal CTRL, respectively (e.g., see Figure 1 ) provided.

[0260] The display system 2600 may include a system providing an image display function, such as a portable computer, a mobile phone, a smart phone, a tablet personal computer (tablet PC), a smart watch, a watch phone, a portable multimedia player, a navigation system, and an ultra-mobile personal computer (UMPC). In addition, the display system 2600 may include at least one of a head-mounted display (HMD), a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0261] Figure 27 is a perspective view showing an application example of the display system 2600 of Figure 26 .

[0262] Referring to Figure 27 , the display system 2600 (e.g., see Figure 26 ) may be applied to the head-mounted display 2700. The head-mounted display 2700 may be a wearable electronic device that can be worn on a user's head.

[0263] The head-mounted display 2700 may include a head-mounted band 2710 and a display device receiving case 2720. The head-mounted band 2710 may be connected to the display device receiving case 2720. The head-mounted band 2710 may include a horizontal band and / or a vertical band to fasten the head-mounted display 2700 to the user's head. The horizontal band may surround the sides of the user's head, and the vertical band may surround the top of the user's head. However, the present disclosure is not limited thereto. For example, the head-mounted band 2710 may be implemented in the form of a spectacle frame, a helmet, etc.

[0264] The display device receiving housing 2720 can receive the first display device 2620 and the second display device 2630 (for example, see Figure 26 ). The display device receiving housing 2720 can also receive the processor 2610 (for example, see Figure 26 ).

[0265] Figure 28 FIG. is a diagram showing a head-mounted display 2700 worn on a user USR.

[0266] Referring to Figure 28 , the first display panel DP1 of the first display device 2620 (for example, referring to Figure 26 ) and the second display panel DP2 of the second display device 2630 (for example, referring to Figure 26 ) are provided in the head-mounted display 2700. The head-mounted display 2700 may also include one or more lenses. For example, the head-mounted display 2700 may include a left-eye lens LLNS and a right-eye lens RLNS.

[0267] In the display device receiving housing 2720, the right-eye lens RLNS can be positioned between the first display panel DP1 and the right eye of the user USR. In the display device receiving housing 2720, the left-eye lens LLNS can be positioned between the second display panel DP2 and the left eye of the user USR.

[0268] The image output from the first display panel DP1 can be observed by the right eye of the user USR through the right-eye lens RLNS. The right-eye lens RLNS can refract the light emitted from the first display panel DP1 toward the right eye of the user USR. The right-eye lens RLNS can perform an optical function to adjust the viewing distance between the first display panel DP1 and the right eye of the user USR.

[0269] The image output from the second display panel DP2 can be observed by the left eye of the user USR through the left-eye lens LLNS. The left-eye lens LLNS can refract the light emitted from the second display panel DP2 toward the left eye of the user USR. The left-eye lens LLNS can perform an optical function to adjust the viewing distance between the second display panel DP2 and the left eye of the user USR.

[0270] In one or more embodiments, each of the right-eye lens RLNS and the left-eye lens LLNS may include an optical lens having a pie-shaped cross section. In one or more embodiments, each of the right-eye lens RLNS and the left-eye lens LLNS may include a multi-channel lens, and the multi-channel lens includes sub-regions having different optical characteristics. In this embodiment, the first display panel DP1 and the second display panel DP2 can respectively output images corresponding to the sub-regions of the multi-channel lens. The output images can pass through the corresponding sub-regions and be observed by the user USR.

[0271] In a subpixel, a display panel including the subpixel, and a method of manufacturing the display panel according to one or more embodiments of the present disclosure, an image can be displayed at various frame rates with high resolution and reduced power consumption.

[0272] The above is an illustration of some embodiments of the present disclosure and should not be construed as a limitation of the present disclosure. Although some embodiments have been described, those skilled in the art will readily understand that various modifications can be made to the embodiments without departing from the spirit and scope of the present disclosure. It will be understood that unless otherwise described, the description of a feature or aspect within each embodiment is generally considered applicable to other similar features or aspects in other embodiments. Thus, as will be apparent to those of ordinary skill in the art, unless otherwise specified, the features, characteristics, and / or elements described in connection with a particular embodiment can be used alone or in combination with the features, characteristics, and / or elements described in connection with other embodiments. Accordingly, it should be understood that the above is an illustration of various exemplary embodiments and should not be construed as limited to the specific embodiments disclosed herein, and that various modifications to the disclosed embodiments and other exemplary embodiments are intended to be included within the spirit and scope of the present disclosure as defined by the appended claims and their equivalents.

Claims

1. A display panel, comprising: A silicon substrate; A first active pattern, including a single-crystal semiconductor layer on the silicon substrate; A first gate insulating layer, covering the first active pattern; A first gate electrode, on the first gate insulating layer, and including at least a part overlapping with the first active pattern; A first interlayer insulating layer, on the first gate electrode; A second active pattern, on the first interlayer insulating layer, and including a metal oxide semiconductor; A second gate insulating layer, covering the second active pattern; A second gate electrode, on the second gate insulating layer, and including at least a part overlapping with the second active pattern; A second interlayer insulating layer, covering the second gate electrode; And A source / drain electrode layer, on the second interlayer insulating layer, and connected to the first active pattern and the second active pattern.

2. The display panel according to claim 1, wherein, The silicon substrate includes a buffer layer containing silicon oxide, and Wherein, the first active pattern is located on the buffer layer.

3. The display panel according to claim 1, wherein, The first active pattern is a semiconductor layer of a P-type transistor, and the second active pattern is a semiconductor layer of an N-type transistor.

4. The display panel according to claim 1, Among them, The display panel includes a plurality of sub-pixels, and each of the plurality of sub-pixels includes at least one light-emitting element, Wherein, at least one of the plurality of sub-pixels further includes: A driving transistor, including a semiconductor layer, a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node, the driving transistor configured to control the magnitude of the current flowing through the light-emitting element based on the voltage applied to the second node; and A compensation transistor, including a semiconductor layer, and configured to switch the electrical connection between the first node and the second node, and Wherein, the semiconductor layer of the driving transistor includes the first active pattern, and the semiconductor layer of the compensation transistor includes the second active pattern.

5. The display panel according to claim 4, wherein, The gate electrode of the compensation transistor is connected to a sub-gate line.

6. The display panel according to claim 5, wherein, The sub-gate line includes the source / drain electrode layer.

7. The display panel according to claim 5, Among them, The sub-gate line is directly located on the silicon substrate, and Wherein, the source / drain electrode layer includes a connection electrode configured to electrically connect the sub-gate line and the second active pattern to each other.

8. The display panel according to claim 4, Among them, At least one of the plurality of sub-pixels further includes an initialization transistor, the initialization transistor includes a semiconductor layer, and the initialization transistor is configured to switch the electrical connection between the second node and a power supply line configured to be applied with an initialization voltage, and Wherein, the semiconductor layer of the initialization transistor includes the second active pattern.

9. The display panel according to claim 8, wherein, The gate electrode of the initialization transistor is connected to a sub-gate line.

10. The display panel according to claim 9, wherein, The sub-gate line includes the source / drain electrode layer.

11. The display panel according to claim 9, Among them, The sub-gate line is directly located on the silicon substrate, and Wherein, the source / drain electrode layer includes a connection electrode configured to electrically connect the sub-gate line and the second active pattern to each other.

12. The display panel according to claim 8, Among them, The source / drain electrode layer includes a first source / drain electrode layer, and wherein, the display panel further includes: a first via layer covering the first source / drain electrode layer; a second source / drain electrode layer on the first via layer and connected to the first source / drain electrode layer through a contact hole; and a second via layer covering the second source / drain electrode layer.

13. The display panel according to claim 12, wherein, The power supply line includes the second source / drain electrode layer.

14. The display panel according to claim 8, Among them, wherein the power supply line is directly located on the silicon substrate, and wherein the source / drain electrode layer includes a connection electrode configured to electrically connect the power supply line and the second active pattern to each other.

15. A sub-pixel, including: a light-emitting element; and a sub-pixel circuit configured to supply current to the light-emitting element, wherein the sub-pixel circuit includes: a driving transistor including a first active pattern and a first gate electrode, the first active pattern having a single-crystal structure on a silicon substrate and connected to a first node and a third node, the first gate electrode connected to a second node and including at least a part overlapping with the first active pattern, the driving transistor configured to supply a current corresponding to a voltage applied to the second node; and a compensation transistor including a second active pattern and a second gate electrode, the second active pattern including a metal oxide semiconductor layer, the second gate electrode including at least a part overlapping with the second active pattern, the compensation transistor configured to switch an electrical connection between the first node and the second node.

16. The sub-pixel according to claim 15, wherein, The first active pattern is a semiconductor layer of a P-type transistor, and the second active pattern is a semiconductor layer of an N-type transistor.

17. A method of manufacturing a display panel, including: forming a first active pattern having a single-crystal structure on a silicon substrate; forming a first gate insulating layer on the first active pattern; forming a first gate electrode including at least a part overlapping with the first active pattern; forming a first interlayer insulating layer on the first gate electrode; forming a second active pattern including a metal oxide semiconductor on the first interlayer insulating layer; forming a second gate insulating layer on the second active pattern; forming a second gate electrode including at least a part overlapping with the second active pattern on the second gate insulating layer; forming a second interlayer insulating layer on the second gate electrode; and forming a source / drain electrode layer connected to the first active pattern and the second active pattern on the second interlayer insulating layer.

18. The method according to claim 17, further including forming a buffer layer by implanting oxygen ions into the silicon substrate, Among them, wherein the first active pattern is formed on the buffer layer.

19. The method according to claim 18, wherein forming the first active pattern includes doping with P-type impurities, and wherein forming the second active pattern includes doping with N-type impurities.

20. The method according to claim 18, further including directly forming a power supply line or a sub-gate line on the silicon substrate, Among them, forming the source / drain electrode layer includes forming at least one of the following: a connection electrode connecting the second active pattern and the power supply line to each other; and A connection electrode that connects the second active pattern and the sub-gate line to each other.

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