Display device

Abstract

A display device includes: a substrate including a display area having a plurality of sub-pixels; the first data lines are arranged in the display area and extend in the column direction; a first connection line disposed in the display area, electrically connected to the first data line, and extending in a row direction; the second connecting lines are arranged in the display area and extend in the column direction; a first metal pattern spaced apart from the first connection line and extending in the row direction; and a second metal pattern spaced apart from the second connecting line and extending in the column direction.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0196990, filed with the Korean Intellectual Property Office on December 29, 2023, the entire contents of which are hereby incorporated by reference in their entirety into this application. Technical field

[0003] The present invention relates to a display device, and more particularly, to a display device having a data connection structure. Background art

[0004] A display device may include a display area configured to allow an image to be displayed and a non - display area where no image is displayed. To enable the display device to perform various functions such as displaying an image, sensing a touch event, etc., various structures, circuits, lines, etc. may be provided in the non - display area (which may also be referred to as the "non - active area" or "bezel") of the display panel. Summary of the invention

[0005] To meet the market demand for a large display area, it is desirable to reduce the bezel size of the display panel. However, since the components of the display panel are provided in the non - display area, it is not easy to reduce the bezel size. In particular, link lines for transmitting data signals to data lines may be provided in the non - display area of the display panel, and thus reducing the bezel size of the display panel may become a problem.

[0006] One or more aspects of the present invention may provide a display device having a data link structure capable of reducing the bezel size of a display panel.

[0007] One or more aspects of the present invention may provide a display device having a bezel - reducing data connection structure capable of improving image quality.

[0008] One or more aspects of the present invention may provide a display device having a bezel - reducing data connection structure capable of improving the transmission performance of a common driving voltage.

[0009] One or more aspects of the present invention may provide a display device having a bezel - reducing data connection structure capable of reducing the difference in reflected light.

[0010] According to various aspects of the present invention, a display device may include: a substrate including a display area having a plurality of sub-pixels; a first data line disposed in the display area and extending in a column direction; a first connection line disposed in the display area, electrically connected to the first data line and extending in a row direction; a second connection line disposed in the display area and extending in the column direction; a first metal pattern separated from the first connection line and extending in the row direction; and a second metal pattern separated from the second connection line and extending in the column direction.

[0011] According to various aspects of the present invention, a display device may include: a substrate; a first signal line disposed on the substrate and extending in a first direction; a first power line including the same first metal as the first signal line and separated from the first signal line; a second signal line disposed on the substrate and extending in a second direction different from the first direction; and a second power line including the same second metal as the second signal line and separated from the second signal line.

[0012] According to one or more aspects of the present invention, a display device may be provided that has a data connection structure capable of reducing the bezel of a display panel.

[0013] According to one or more aspects of the present invention, a display device may be provided that has a bezel-reducing data connection structure capable of improving image quality.

[0014] According to one or more aspects of the present invention, a display device may be provided that has a bezel-reducing data connection structure capable of improving the transmission performance of a common driving voltage.

[0015] According to one or more aspects of the present invention, a display device may be provided that has a bezel-reducing data connection structure capable of reducing the difference in reflected light.

[0016] According to one or more aspects of the present invention, a display device and / or a display panel may be provided that has a reduced weight by reducing the bezel of the display panel by using an improved data connection structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate various aspects of the present invention and, together with the description, serve to explain the principles of the present invention.

[0018] Figure 1 Illustrate the system configuration of a display device according to various aspects of the present invention.

[0019] Figure 2 Illustrate a display panel according to various aspects of the present invention.

[0020] Figure 3 Is a cross-sectional view of a display panel according to various aspects of the present invention.

[0021] Figure 4 Illustrate a substrate of a display panel according to various aspects of the present invention.

[0022] Figure 5 Is a plan view of a display panel according to various aspects of the present invention, and illustrate a data connection structure disposed in the display panel.

[0023] Figure 6 Is another plan view of a display panel according to various aspects of the present invention, and illustrate an exemplary data connection structure capable of reducing the bezel of the display panel.

[0024] Figure 7 Illustrate three regions defined in a display region of a display panel according to various aspects of the present invention.

[0025] Figure 8 Illustrate some regions of a display panel according to various aspects of the present invention.

[0026] Figure 9 Is a cross-sectional view illustrating a first opening region of a first metal layer of a display panel according to various aspects of the present invention.

[0027] Figure 10 Is a cross-sectional view illustrating a second opening region of a second metal layer of a display panel according to various aspects of the present invention;

[0028] Figure 11 Illustrate a structure capable of reducing the difference in reflected light related to a bezel-reduced data connection structure in a display panel according to various aspects of the present invention.

[0029] Figures 12 to 14 Illustrate a shielding structure disposed in a first opening region of a first metal layer of a display panel according to various aspects of the present invention.

[0030] Figure 15 Illustrate a shielding structure disposed in a second opening region of a second metal layer of a display panel according to various aspects of the present invention. Detailed Description

[0031] Reference will now be made in detail to aspects of the present invention, some examples of which are illustrated in the accompanying drawings. In the following description, when a detailed description of a known method, function, structure, or construction may unnecessarily obscure aspects of the present invention, the detailed description of such known functions or constructions may be omitted for the sake of brevity. In addition, repetitive descriptions may be omitted for the sake of brevity. The processes of the described processing steps and / or operations are non-limiting examples.

[0032] The order of the steps and / or operations is not limited to those set forth herein, but may be varied to occur in a different order than that described herein, unless the steps and / or operations must occur in a particular order. In one or more examples, two consecutive operations may be performed substantially simultaneously, or, depending on the functions or operations involved, the two operations may be performed in the reverse order or a different order.

[0033] Unless otherwise indicated, like reference numerals may refer to like elements throughout, even when shown in different figures. Unless otherwise indicated, the same reference numerals may be used throughout the specification and the drawings to refer to the same or substantially the same elements. In one or more aspects, the same elements (or elements having the same name) in different figures may have the same or substantially the same functions and characteristics, unless otherwise indicated. For convenience only, the names of the corresponding elements used in the following description are selected, and thus these names may be different from those used in actual products.

[0034] The advantages and features of the present invention and the method for its implementation are illustrated by the aspects described with reference to the accompanying drawings. However, the present invention may be implemented in different forms and should not be construed as limited to the exemplary aspects set forth herein. Rather, these exemplary aspects are examples, and these exemplary aspects are provided so that the disclosure of the present invention may be thorough and complete to assist those of ordinary skill in the art in understanding the inventive concept, rather than to limit the scope of the present invention.

[0035] The shapes, sizes (e.g., dimensions, lengths, widths, heights, thicknesses, positions, radii, diameters, and areas), ratios, rates, angles, quantities, number of elements, etc. (including those shown in the figures) disclosed herein are merely examples, and thus the present invention is not limited to the details shown. However, note that the relative sizes of the components shown in the figures are part of the present invention.

[0036] When terms such as "comprising", "having", "including", "containing", or "constituting" are used with respect to one or more other elements, one or more additional elements (such as layers, films, regions, components, sections, members, parts, zones, sites, steps, and / or operations, etc.) may be added, unless terms such as "only" are used. The terms used in the disclosure of the present invention are only for describing exemplary aspects and are not intended to limit the scope of the present invention. Singular terms may include plural forms unless the context clearly indicates otherwise.

[0037] The term "exemplary" is used to mean serving as an example or illustration, unless otherwise specified. Embodiments are exemplary embodiments. Multiple aspects are exemplary aspects. In one or more embodiments, "embodiments", "aspects", "examples", etc. should not be construed as being more preferred or advantageous than other embodiments. An aspect, an example, an exemplary aspect, etc. may refer to one or more aspects, one or more examples, one or more exemplary aspects, etc., unless otherwise specified. In addition, the term "may" encompasses all meanings of the term "can".

[0038] In one or more aspects, unless otherwise explicitly specified, an element, a feature, or the corresponding information (such as level, range, size, dimension, etc.) is construed to include a range of errors or tolerances, even if no clear description of such a range of errors or tolerances is provided. Errors or tolerances may be caused by various factors (such as process factors, internal or external shocks, noise, etc.). When interpreting a numerical value, the value is construed to include a range of errors, unless otherwise explicitly specified.

[0039] When describing a positional relationship, such as when using "on", "above", "at the top of", "over", "lower", "upper", "below", "under", "near", "close to", "adjacent to", "beside", "after", "on one side", etc. to describe the positional relationship between two parts (such as layers, films, regions, components, parts, etc.), one or more other parts may be located between these two parts, unless more restrictive terms such as "immediately", "directly", or "adjacent" are used. For example, when a structure is described as being on, above, at the top of, upper, under, on top of, below, beneath, near, beside, after, on one side of, or close to, adjacent to another structure, this description should be construed to include the case where the two structures are in contact with each other and the case where one or more additional structures are disposed or interposed therebetween. In addition, terms such as "front", "rear", "back", "left", "right", "top", "bottom", "downward", "upward", "above", "below", "upper", "lower", "column", "row", "vertical", "horizontal", etc. refer to any reference system.

[0040] Spatial relative terms such as "below", "lower", "under", "above", "upper", etc. may be used to describe the relationship between various elements (such as layers, films, regions, components, parts, etc.) shown in the figures. These spatial relative terms should be understood to include terms for different orientations of the elements in addition to the orientation depicted in the figures when in use or operation. For example, if the elements shown in the figures are flipped, an element described as being "under" or "below" other elements will be oriented as being "above" the other elements. Thus, the term "below" as an exemplary term may include all directions of "above" and "below". Similarly, the exemplary terms "above" or "upper" may include all directions of "above" and "below".

[0041] When describing temporal relationships, such as when a chronological order is described as "after", "subsequently", "next", "before", "prior", "preceding", etc., discontinuous or non-sequential situations may be included, so one or more other events may occur therebetween, unless more restrictive terms such as "exactly", "immediately", or "directly" are used.

[0042] Terms such as "below", "lower", "above", "upper", etc. may be used herein to describe the relationship between the elements shown in the figures. It will be understood that these terms are spatial relative terms and are terms based on the orientation depicted in the figures.

[0043] It will be understood that although terms such as "first", "second", etc. may be used herein to describe various elements (such as layers, films, regions, components, sections, members, parts, areas, sites, steps, and / or operations, etc.), these elements should not be limited by these terms to, for example, any particular order, priority order, or number of elements. These terms are only used to distinguish one element from other elements. For example, without departing from the scope of the present invention, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. In addition, without departing from the scope of the present invention, the first element, the second element, etc. may be arbitrarily named according to the convenience of those of ordinary skill in the art. For the sake of clarity, the functions or structures of these elements (such as the first element, the second element, etc.) are not limited by the ordinal number or name in front of the element. In addition, the first element may include one or more first elements. Similarly, the second element, etc. may include one or more second elements, etc.

[0044] When describing the elements of the present invention, terms such as "first", "second", "A", "B", "(a)", or "(b)", etc. may be used. These terms are intended to identify the corresponding elements from other elements, and these terms are not used to limit the essence, basis, order, or number of the elements.

[0045] For expressions such as an element (e.g., a layer, film, region, component, part, etc.) being "connected", "joined", "attached", or "adhered" to another element, this element can not only be directly connected, joined, attached, or adhered to the other element, etc., but can also be indirectly connected, joined, attached, or adhered to the other element, etc. by means of one or more intermediate elements disposed or interposed between these elements, unless otherwise specified.

[0046] For expressions such as an element (e.g., a layer, film, region, component, part, etc.) being "overlapped" with another element, etc., this element can not only be in direct contact, overlap, etc. with the other element, but can also be indirectly overlapped, etc. with the other element by means of one or more intermediate elements disposed or interposed between these elements, unless otherwise specified.

[0047] Expressions such as an element (e.g., a layer, film, region, component, part, etc.) being "provided", "disposed", "connected", or "joined" in or on another element can be understood as at least a part of the element being provided, disposed, connected, or joined in the other element, or the whole of the element being provided, disposed, connected, or joined in the other element. Expressions such as an element (e.g., a layer, film, region, component, part, etc.) being "in contact", "overlapped", etc. with another element can be understood as at least a part of the element being in contact, overlapped, etc. with at least a part of the other element; the whole of the element being in contact, overlapped, etc. with at least a part of the other element; or at least a part of the element being in contact, overlapped, etc. with the whole of the other element.

[0048] Terms such as "line" or "direction" should not be interpreted only based on the geometric relationship that the corresponding lines or directions are parallel or perpendicular to each other. These terms can refer to a wider range of lines or directions in which the components of the present invention are functionally operable. For example, terms such as "first direction", "second direction", etc., such as directions parallel or perpendicular to the "x-axis", "y-axis", or "z-axis", should not be interpreted only based on the geometric relationship that the corresponding directions are parallel or perpendicular to each other, and can refer to directions with a wider directivity within the range in which the components of the present invention are functionally operable.

[0049] The term "at least one" should be understood to include any and all combinations of one or more of the related listed items. For example, each of the expressions "at least one of the first item, the second item, or the third item" and "at least one of the first item, the second item, and the third item" can represent: (i) a combination of items provided by one or more of the first item, the second item, and the third item; and (ii) only one of the first item, the second item, and the third item.

[0050] The expression of the first element, the second element, and / or the third element should be understood to include any one of the first element, the second element, or the third element; any one of the first element, the second element, and the third element, as well as any and all combinations of the first element, the second element, and the third element. For example, A, B, and / or C encompasses: only A; only B; only C; any one of A, B, and C (e.g., A, B, or C); some combinations of A, B, and C (e.g., A and B; A and C; or B and C); and all of A, B, and C. Additionally, the expression "A / B" can be understood as A and / or B. For example, the expression "A / B" can refer to only A; only B; A or B; or A and B.

[0051] In one or more aspects, the terms "between" and "among" may be used interchangeably for convenience only, unless otherwise specified. For example, the expression "between a plurality of elements" can be understood as among a plurality of elements. In another example, the expression "among a plurality of elements" can be understood as between a plurality of elements. In one or more examples, the number of elements can be two. In one or more examples, the number of elements can be more than two. Additionally, when an element (e.g., a layer, a film, a region, a component, a part, etc.) is said to be located between at least two elements, that element can be the only element located between at least two elements, or there can also be one or more intermediate elements.

[0052] In one or more aspects, the phrases "each other" and "one another" may be used interchangeably for convenience only, unless otherwise specified. For example, the expression "different from each other" can be understood as different from one another. In another example, the expression "different from one another" can be understood as different from each other. In one or more examples, the number of elements involved in the foregoing expressions can be two. In one or more examples, the number of elements involved in the foregoing expressions can be more than two.

[0053] In one or more aspects, the phrases "one or more of" and "one or more thereof" may be used interchangeably for convenience only, unless otherwise specified.

[0054] The term "or" means "inclusive or" rather than "exclusive or". For example, unless otherwise specified or clear from the context, an expression such as "x uses a or b" refers to any one in a natural inclusive permutation. For example, "a or b" can refer to "a", "b", or "a and b". For example, "a, b, or c" can refer to "a", "b", "c", "a and b", "b and c", "a and c", or "a, b, and c".

[0055] Features of various aspects of the present invention can be combined or assembled partially or wholly with each other, can be technically related to each other, and can be operated, connected or driven together in various ways. Multiple aspects of the present invention can be implemented or executed independently of each other, or can be implemented or executed together in a relationship of mutual dependence or association. In one or more aspects, components of each device according to aspects of the present invention are operatively engaged and configured.

[0056] Unless otherwise defined, the terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary aspects belong. It should be further understood that terms such as those defined in a commonly used dictionary should be interpreted as having a meaning consistent with the meaning in the context of the related art, and should not be idealized or interpreted overly formally, unless explicitly defined otherwise herein.

[0057] The terms used herein are selected as general terms in the relevant technical field; however, there may be other terms according to the development and / or changes of technology, customs, preferences of technicians, etc. Therefore, the terms used herein should not be construed as limiting the technical concept, but should be understood as examples of terms for describing exemplary aspects.

[0058] In addition, in specific circumstances, the terms can be arbitrarily selected by the applicant, and in such circumstances, their specific meanings are described herein. Therefore, the terms used herein should not be understood only based on the term names, but also based on the meanings and contents of the terms.

[0059] The "X-axis direction", "Y-axis direction" and "Z-axis direction" should not be interpreted only by the geometric relationship of perpendicularity to each other, but can have a broader directivity within the range where the elements of the present invention can function functionally.

[0060] In the following description, various exemplary aspects of the present invention are described in detail with reference to the accompanying drawings. Regarding the reference numerals of the elements of each figure, the same elements may be shown in other figures, and similar reference numerals may refer to similar elements, unless otherwise specified. The same or similar elements may be referred to by the same reference numerals, even if they are depicted in different figures. In addition, for the sake of convenience of description, the proportions, sizes, dimensions and thicknesses of each element shown in the drawings may be different from the actual proportions, sizes, dimensions and thicknesses, and thus, the aspects of the present invention are not limited to the proportions, sizes, dimensions and thicknesses shown in the figures.

[0061] Figure 1 Illustrate an exemplary system configuration of a display device 100 according to multiple aspects of the present invention. All components of each display device according to all aspects of the present invention are operatively engaged and configured.

[0062] Refer to Figure 1, in one or more aspects, the display device 100 may include a display panel 110, which is an element configured to display an image, and a display driving circuit. The display driving circuit may be a circuit configured to drive the display panel 110, and includes a data driving circuit 120, a gate driving circuit 130, a controller 140, and other circuit components.

[0063] The display panel 110 may include a substrate 111 and a plurality of sub-pixels SP disposed on the substrate 111.

[0064] The substrate 111 may include an active area AA that allows an image to be displayed and a non-active area NA located or disposed outside the active area.

[0065] The active area AA may also be referred to as a display area, and a plurality of sub-pixels SP configured to display an image may be disposed in the active area AA. The non-active area NA may also be referred to as a non-display area, and may include a pad area PA (see Figure 4 ). For example, the pad area PA may be a part of the non-active area NA disposed along a first direction (e.g., a column direction or a row direction) from the active area AA.

[0066] According to multiple aspects of the present invention, the display panel 110 may be configured to have a very small non-active area NA. Here, the non-active area NA may also be referred to as a "border". For example, the non-active area NA may include: a first non-active area located or disposed outside the active area AA in a first direction; a second non-active area located outside the active area AA in a second direction; a third non-active area located or disposed outside the active area AA in a direction opposite to the first direction; and a fourth non-active area located or disposed outside the active area AA in a direction opposite to the second direction. The first non-active area among the first to fourth non-active areas may include a pad area to which a driving circuit is connected or joined (or attached). Among the first to fourth non-active areas, the second to fourth non-active areas that do not include a pad area may have a very small size compared to the first non-active area.

[0067] In another example, a boundary area may be located between the active area AA and the non-active area NA. In this example, the non-active area NA may be bent at a predetermined (consistent) angle with respect to the active area AA, and thus may be disposed below the active area AA. In this embodiment, when a user views the display device 100 in front of the display device 100, all or most of the non-active area NA may be invisible to the user. However, multiple aspects of the present invention are not limited thereto.

[0068] Various signal lines configured to drive the plurality of sub-pixels SP may be disposed at the substrate 111 of the display panel 110.

[0069] In some aspects, the display device 100 herein may be a liquid crystal display device or the like, or a self-emitting display device in which the display panel 110 emits light by itself. In an example where the display device 100 is a self-emitting display device, each of the plurality of sub-pixels SP may include a light-emitting element. However, the aspects of the present invention are not limited thereto.

[0070] For example, the display device 100 according to aspects of the present invention may be an organic light-emitting display device in which a light-emitting element is implemented using an organic light-emitting diode (OLED). In another example, the display device 100 according to aspects of the present invention may be an inorganic light-emitting display device in which a light-emitting element is implemented using a light-emitting diode based on an inorganic material. In another example, the display device 100 according to aspects of the present invention may be a quantum dot display device in which a light-emitting element is implemented using a quantum dot that is a self-emitting semiconductor crystal. However, the aspects of the present invention are not limited thereto.

[0071] The structure of each of the plurality of sub-pixels SP may depend on the type of the display device 100. For example, in an example where the display device 100 is a self-emitting display device including self-emitting sub-pixels SP, each sub-pixel SP may include a self-emitting light-emitting element, one or more transistors, and one or more capacitors.

[0072] Various signal lines may include, for example: a plurality of data lines DL for transmitting data signals (which may be referred to as data voltages or image signals); a plurality of gate lines GL for transmitting gate signals (which may be referred to as scan signals); and so on.

[0073] In some aspects, the plurality of data lines DL and the plurality of gate lines GL may cross each other. Each of the plurality of data lines DL may be disposed and extend in a first direction, and each of the plurality of gate lines GL may be disposed and extend in a second direction. For example, the first direction may be a column direction, and the second direction may be a row direction. In another example, the first direction may be a row direction, and the second direction may be a column direction. Hereinafter, for the sake of convenience of explanation, the discussion may be provided based on an example in which each of the plurality of data lines DL is disposed in the column direction and each of the plurality of gate lines GL is disposed in the row direction, but the aspects of the present invention are not limited thereto.

[0074] The data driving circuit 120 may be a circuit configured to drive the plurality of data lines DL and may output data signals to the plurality of data lines DL.

[0075] The data driving circuit 120 may receive the image data DATA in digital form from the controller 140, convert the received image data DATA into an analog-form data signal, and output the converted data signal to the plurality of data lines DL.

[0076] In some aspects, the data driving circuit 120 may be connected to the display panel 110 by a tape automated bonding (TAB) method, or may be connected to conductive pads such as bonding pads of the display panel 110 by a chip on glass (COG) method or a chip on panel (COP) method, or may be connected to the display panel 110 using a chip on film (COF) method. However, aspects of the present invention are not limited thereto.

[0077] The data driving circuit 120 may be disposed on and / or electrically connected to one side or a portion (e.g., upper or lower portion) of the display panel 110, but is not limited thereto. In some aspects, the data driving circuit 120 may be disposed on and / or electrically connected to two sides or two portions (e.g., upper and lower portions) of the display panel 110, or at least two of four sides or four portions (e.g., upper, lower, left, and right portions) of the display panel 110, depending on a driving mechanism, a panel design mechanism, etc., but is not limited thereto. The terms left, right, up, and down in this context are with reference to a typical viewing position.

[0078] The data driving circuit 120 may be connected to the outside or periphery of the active area AA of the display panel 110, or may be disposed in the active area AA of the display panel 110.

[0079] The gate driving circuit 130 may be a circuit configured to drive a plurality of gate lines GL, and may output gate signals to the plurality of gate lines GL.

[0080] The gate driving circuit 130 may receive various gate driving control signals GCS, and in addition, receive a first gate voltage corresponding to a conduction level voltage and a second gate voltage corresponding to a cutoff level voltage. Thus, the gate driving circuit 130 may generate gate signals and provide the generated gate signals to the plurality of gate lines GL.

[0081] In some aspects, the gate driving circuit 130 in the display device 100 may be built into the display panel 110 by an in-panel gate (GIP) method. In an example where the gate driving circuit 130 is implemented by the in-panel gate (GIP) method, the gate driving circuit 130 may be disposed on the substrate 111 of the display panel 110 during a manufacturing process of the display panel 110 or the display device 100.

[0082] In one aspect, the gate driving circuit 130 may be disposed at a non-display area NA of the display panel 110.

[0083] In another aspect, the gate driving circuit 130 may be disposed in the active area AA of the display panel 110. In this embodiment, for example, the gate driving circuit 130 may be disposed in and / or electrically connected to a part of the first area (e.g., the left area or the right area) of the active area AA of the display panel 110, but is not limited thereto. In another example, the gate driving circuit 130 may be disposed in and / or electrically connected to a part of the first area (e.g., the left area or the right area) and a part of the second area (e.g., the right area or the left area) of the active area AA of the display panel 110, but is not limited thereto.

[0084] Here, the gate driving circuit 130 built in the display panel 110 using the gate-in-panel (GIP) method may also be referred to as a gate-in-panel circuit.

[0085] The controller 140 may be a device configured to control the data driving circuit 120 and the gate driving circuit 130, and may control the driving timings of the plurality of data lines DL and the plurality of gate lines GL.

[0086] The controller 140 may provide a data control signal DCS to the data driving circuit 120 to control the data driving circuit 120; and may provide a gate control signal GCS to the gate driving circuit 130 to control the gate driving circuit 130.

[0087] The controller 140 may receive the image data input from the host system 150, and provide the image data DATA readable by the data driving circuit 120 based on the input image data to the data driving circuit 120.

[0088] The controller 140 may be implemented in a component separate from the data driving circuit 120, or integrated with the data driving circuit 120, so that the controller 140 and the data driving circuit 120 may be implemented as a single integrated circuit.

[0089] The controller 140 may be a timing controller used in display technology, or a control device / unit capable of additionally performing other control functions in addition to the function of the timing controller. In one or more aspects, the controller 140 may be one or more other control circuits different from the timing controller, or a circuit or component in the control device / unit. The controller 140 may be implemented using various circuits or electronic components such as an integrated circuit (IC), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), and / or a processor, etc., but the various aspects of the present invention are not limited thereto.

[0090] The controller 140 may be mounted on a printed circuit board, a flexible printed circuit, etc., and may be electrically connected to the data driving circuit 120 and the gate driving circuit 130 through the printed circuit board and / or the flexible printed circuit, etc.

[0091] The controller 140 can send and receive signals to / from the data driving circuit 120 via one or more predetermined interfaces. For example, such interfaces can include a Low-Voltage Differential Signaling (LVDS) interface, an Embedded Clock Point-to-Point Interface (EPI), a Serial Peripheral Interface (SPI), etc. However, multiple aspects of the present invention are not limited thereto.

[0092] In one or more aspects, in order to provide a touch sensing function in addition to the image display function, the display device 100 can include a touch sensor and a touch sensing circuit, and the touch sensing circuit is configured to sense the touch sensor through an object such as a finger, a pen, etc. and detect the presence or absence of a touch or the touch position.

[0093] The touch sensing circuit can include: a touch driving circuit configured to drive and sense the touch sensor, generate and output touch sensing data; and a touch controller capable of detecting the presence or absence of a touch or the touch position through the touch sensing data.

[0094] The touch sensor can include a plurality of touch electrodes. The touch sensor can further include a plurality of touch lines that electrically connect the plurality of touch electrodes to the touch driving circuit.

[0095] The touch sensor can be provided outside the display panel 110 in the form of a touch panel, or can be provided inside the display panel 110. The touch sensor provided outside the display panel 110 can be referred to as an add-on type touch sensor. In an example where the add-on type touch sensor is provided in the display device 100, the touch panel and the display panel 110 can be separately manufactured and combined in an assembly process. The add-on touch panel can include a touch panel substrate and a plurality of touch electrodes provided on the touch panel substrate.

[0096] In an example where the touch sensor is provided inside the display panel 110, the touch sensor can be formed on the substrate together with signal lines and electrodes regarding display driving during the manufacturing process of the display panel 110.

[0097] The touch driving circuit can provide a touch driving signal to at least one of the plurality of touch electrodes and generate touch sensing data by sensing at least one of the plurality of touch electrodes.

[0098] The touch sensing circuit can perform touch sensing through a self-capacitance sensing method or a mutual-capacitance sensing method.

[0099] In an example where the touch sensing circuit performs touch sensing by the self - capacitance sensing method, the touch sensing circuit may perform touch sensing based on the capacitance between one or more touch electrodes and an object such as a finger and / or a pen. According to the self - capacitance sensing method, each of the plurality of touch electrodes can be used as both a driving touch electrode and a sensing touch electrode. The touch driving circuit can drive all of the plurality of touch electrodes, or one or more of them, and sense all of the plurality of touch electrodes, or one or more of them.

[0100] In an example where the touch sensing circuit performs touch sensing by the mutual - capacitance sensing method, the touch sensing circuit may perform touch sensing based on the capacitance between touch electrodes. According to the mutual - capacitance sensing method, the plurality of touch electrodes can be divided into driving touch electrodes and sensing touch electrodes. The touch driving circuit can drive the above - mentioned driving touch electrodes and sense the above - mentioned sensing touch electrodes.

[0101] In some aspects, the touch driving circuit and the touch controller included in the touch sensing circuit can be implemented as separate devices or a single device. In some aspects, the touch driving circuit and the data driving circuit can be implemented as separate devices or a single device.

[0102] The display device 100 may further include a power supply circuit configured to provide various power supplies to the display driving circuit and / or the touch sensing circuit.

[0103] In some aspects, the display device 100 can be a mobile terminal such as a smart phone and a tablet, or a display, a television (TV), etc. Such devices can be of various types, sizes, and shapes. The display device 100 according to multiple aspects of the present invention is not limited thereto, and it can include various types, sizes, and shapes configured to display information or images.

[0104] In one or more aspects, the display device 100 may further include an electronic device such as a camera (e.g., an image sensor), a sensor capable of detecting an object, etc. For example, the sensor can be a sensor capable of detecting an object or a human body by receiving light such as infrared light, ultrasonic light, ultraviolet light, etc.

[0105] Figure 2 Illustrate the structure of the display panel 110 according to multiple aspects of the present invention.

[0106] Refer to Figure 2 , the display panel 110 may include: a substrate 111 on which a plurality of sub - pixels SP are disposed; and a packaging layer 200 above the substrate 111. The packaging layer 200 can also be referred to as a packaging substrate or a packaging part, etc.

[0107] Refer to Figure 2, in an example where the display device 100 is a self-emitting display device, each of the plurality of sub-pixels SP provided on the substrate 111 may include a light-emitting element ED and a sub-pixel circuit SPC for driving the light-emitting element ED.

[0108] Referring to Figure 2 , the sub-pixel circuit SPC may include a plurality of transistors for driving the light-emitting element ED and at least one capacitor. The sub-pixel circuit SPC may drive the light-emitting element ED by supplying a driving current to the light-emitting element ED in a predetermined timing. The light-emitting element ED may emit light by being driven by the driving current.

[0109] The plurality of transistors may include: a driving transistor DT for driving the light-emitting element ED; and a scanning transistor ST configured to be turned on or off according to a scan signal SC.

[0110] The driving transistor DT may supply a driving current to the light-emitting element ED.

[0111] The scanning transistor ST may be configured to control the electrical state of a corresponding node in the sub-pixel circuit SPC, or control the state or operation of the driving transistor DT.

[0112] The at least one capacitor may include a storage capacitor Cst to maintain a constant voltage during one frame or one frame period.

[0113] To drive the sub-pixel SP, a data signal VDATA as an image signal and a scan signal SC as a gate signal may be applied to the sub-pixel SP. In addition, to drive the sub-pixel SP, a common pixel driving voltage including a first common driving voltage VDD and a second common driving voltage VSS may be applied to the sub-pixel SP.

[0114] The light-emitting element ED may include a pixel electrode PE, an intermediate layer EL, and a common electrode CE. The intermediate layer EL may be provided between the pixel electrode PE and the common electrode CE.

[0115] For example, the pixel electrode PE may be an electrode provided at each sub-pixel SP, and the common electrode CE may be an electrode commonly provided at a plurality of sub-pixels SP. For example, the pixel electrode PE may be an anode, and the common electrode CE may be a cathode. In another example, the pixel electrode PE may be a cathode, and the common electrode CE may be an anode. Hereinafter, for ease of explanation, the discussion may be provided based on an example where the pixel electrode PE is an anode and the common electrode CE is a cathode.

[0116] In an example where the light-emitting element ED is an organic light-emitting diode, the intermediate layer EL may include: a light-emitting layer EML; a first common intermediate layer COM1 located between the pixel electrode PE and the light-emitting layer EML; and a second common intermediate layer COM2 located between the light-emitting layer EML and the common electrode CE. The layer including the first common intermediate layer COM1 and the second common intermediate layer COM2 may be referred to as the common intermediate layer EL_COM.

[0117] The light-emitting layer EML may be provided at each sub-pixel SP, and the common intermediate layer EL_COM may be provided commonly across a plurality of sub-pixels SP.

[0118] The light-emitting layer EML may be provided at each light-emitting region, and the common intermediate layer EL_COM may be provided commonly across a plurality of light-emitting regions and non-light-emitting regions.

[0119] For example, the first common intermediate layer COM1 may include a hole injection layer (HIL), a hole transport layer (HTL), etc. The second common intermediate layer COM2 may include an electron transport layer (ETL), an electron injection layer (EIL), etc.

[0120] The hole injection layer may inject holes from the pixel electrode PE into the hole transport layer, the hole transport layer may transport the holes to the light-emitting layer EML, the electron injection layer may inject electrons from the common electrode CE into the electron transport layer, and the electron transport layer may transport the electrons to the light-emitting layer EML. However, multiple aspects of the present invention are not limited thereto.

[0121] For example, the common electrode CE may be electrically connected to the second common driving voltage line VSSL. As a second common driving voltage VSS of a common pixel driving voltage, the second common driving voltage VSS may be applied to the common electrode CE via the second common driving voltage line VSSL. The pixel electrode PE may be directly or indirectly (via another transistor) electrically connected to the first node N1 of the corresponding driving transistor DT of each sub-pixel SP. Here, the second common driving voltage VSS may also be referred to as a "ground voltage", and the second common driving voltage line VSSL may also be referred to as a "low power supply voltage line", a "low voltage line", or a "ground voltage line".

[0122] Each light-emitting element ED may be configured by the overlap of the pixel electrode PE, the light-emitting layer in the intermediate layer EL, and the common electrode CE. Each light-emitting element ED may form a corresponding light-emitting region. For example, the corresponding light-emitting region of each light-emitting element ED may include the overlap region of the pixel electrode PE, the light-emitting layer in the intermediate layer EL, and the common electrode CE.

[0123] In some aspects, the light-emitting element ED may be an organic light-emitting diode (OLED), an inorganic light-emitting diode (LED), or a quantum dot light-emitting element. For example, in an example where the light-emitting element ED is an organic light-emitting diode OLED, the intermediate layer EL of the light-emitting element ED may be a layer including an organic material. However, multiple aspects of the present invention are not limited thereto.

[0124] The driving transistor DT may be a transistor configured to provide a driving current to the light-emitting element ED. The driving transistor DT may be connected between the first common driving voltage line VDDL and the light-emitting element ED.

[0125] The driving transistor DT may include a first node N1, a second node N2, and a third node N3. The first node N1 may be electrically connected to the light-emitting element ED. A data signal VDATA may be applied to the second node N2. A first common driving voltage VDD provided via the first common driving voltage line VDDL may be applied to the third node N3.

[0126] In the driving transistor DT, the second node N2 may be a gate node, the first node N1 may be a source node or a drain node, and the third node N3 may be a drain node or a source node. Hereinafter, for the sake of convenience of explanation only, the discussion may be provided based on an example where the first node N1, the second node N2, and the third node N3 of the driving transistor DT are a source node, a gate node, and a drain node, respectively. However, multiple aspects of the present invention are not limited thereto.

[0127] Figure 2 The scanning transistor ST in the shown sub-pixel circuit SPC may be a switching transistor that allows a data signal VDATA, which is an image signal, to be provided to the second node N2, which is the gate node of the driving transistor DT.

[0128] The scanning transistor ST may be turned on or off by a scanning signal SC, which is a kind of gate signal, applied via a scanning line SCL, which is a kind of gate line, and controls the electrical connection between the second node N2 of the driving transistor DT and the data line DL. The drain or source of the scanning transistor ST may be electrically connected to the data line DL. The source or drain of the scanning transistor ST may be electrically connected to the second node N2 of the driving transistor DT. The gate of the scanning transistor ST may be electrically connected to the scanning line SCL.

[0129] The storage capacitor Cst may be electrically connected between the first node N1 and the second node N2 of the driving transistor DT. The storage capacitor Cst may include: a first capacitor electrode electrically connected to the first node N1 of the driving transistor DT or corresponding to the first node N1 of the driving transistor DT; and a second capacitor electrode electrically connected to the second node N2 of the driving transistor DT or corresponding to the second node N2 of the driving transistor DT.

[0130] The storage capacitor Cst can be an external capacitor specifically designed to be located or disposed outside the driving transistor DT, and thus is different from internal capacitors such as parasitic capacitors (e.g., Cgs, Cgd) that may be formed between the first node N1 and the second node N2 of the driving transistor DT.

[0131] Each of the driving transistor DT and the scanning transistor ST can be an n-type transistor or a p-type transistor.

[0132] The display panel 110 can have a top-emitting structure or a bottom-emitting structure.

[0133] In an example where the display panel 110 has a top-emitting structure, at least a part of the sub-pixel circuit SPC can overlap at least a part of the light-emitting element ED in the vertical direction. In this configuration, the area or size of the corresponding light-emitting region can be increased, and the corresponding aperture ratio can be increased.

[0134] In an example where the display panel 110 has a bottom-emitting structure, the sub-pixel circuit SPC may not overlap the light-emitting element ED in the vertical direction.

[0135] As Figure 2 shown, the sub-pixel circuit SPC can include two transistors (2T: DT and ST) and one capacitor (1C: Cst) (which can be referred to as a "2T1C structure"), and in some embodiments, can further include one or more transistors, or further include one or more capacitors.

[0136] For example, the sub-pixel circuit SPC can have an 8T1C structure including 8 transistors and 1 capacitor. In another example, the sub-pixel circuit SPC can have a 6T2C structure including 6 transistors and 2 capacitors. In yet another example, the sub-pixel circuit SPC can have a 7T1C structure including 7 transistors and 1 capacitor. Multiple aspects of the present invention are not limited to these structures.

[0137] The type and number of gate signals provided to the sub-pixel SP, and / or the type and number of gate lines connected to the sub-pixel SP can be changed according to the structure of the corresponding sub-pixel circuit SPC. In addition, the type and number of common pixel driving voltages provided to the sub-pixel SP can be changed according to the structure of the corresponding sub-pixel circuit SPC.

[0138] Since circuit elements (e.g., a light-emitting element ED such as an organic light-emitting diode (OLED) including an organic material) in each sub-pixel SP are vulnerable to external moisture or oxygen, the encapsulation layer 200 may be provided at the display panel 110 to prevent external moisture or oxygen from penetrating into the circuit elements (e.g., the light-emitting element ED). The encapsulation layer 200 may be provided in various shapes or configurations to prevent the light-emitting element ED from coming into contact with moisture or oxygen. For example, the encapsulation layer 200 may include two or more layers in which an organic layer and an inorganic layer are alternately stacked, but various aspects of the present invention are not limited thereto.

[0139] Referring to Figure 2 , in some aspects, in order to sense a user touch, the display device 100 may include: a touch sensor unit 210 including a plurality of sensor electrodes; a touch driving circuit 220 configured to sense the plurality of sensor electrodes; and a touch controller 230 configured to determine the presence or absence of a touch or touch coordinates using a sensing result (e.g., touch sensing data) of the touch driving circuit 220.

[0140] The touch sensor unit 210 may be built in the display panel 110. For example, the touch sensor unit 210 may be provided on the encapsulation layer 200 of the display panel 110.

[0141] The display panel 110 may include: a plurality of touch pads TP to which the touch driving circuit 220 is electrically connected; and a plurality of touch wirings for electrically connecting the plurality of sensor electrodes included in the touch sensor unit 210 to the plurality of touch pads TP connected to the touch driving circuit 220.

[0142] Figure 3 is a cross-sectional view of the display panel 110 according to various aspects of the present invention.

[0143] Referring to Figure 3 , in some aspects, according to a stack-up configuration, the display panel 110 may include a transistor forming portion, a light-emitting element forming portion, and an encapsulation portion.

[0144] The transistor forming portion may include: a substrate 111; various insulating layers (311, 312, 313, 321, 322, and 323) on the substrate 111; various transistors (TFT1 and TFT2); a storage capacitor Cst; and various electrodes or signal lines. The transistor forming portion may be a transistor part.

[0145] The transistors (TFT1 and TFT2) in the transistor forming portion may include a first transistor TFT1 and a second transistor TFT2.

[0146] The first transistor TFT1 may include a first active layer ACT1, a first electrode E1a, a second electrode E1b, and a third electrode E1c. The first active layer ACT1 may be a first semiconductor layer, but aspects of the present invention are not limited thereto. For example, the first active layer ACT1 may be configured with an oxide semiconductor, amorphous silicon, polysilicon, low-temperature polysilicon (LTPS), etc., but aspects of the present invention are not limited thereto. The first transistor TFT1 may be a p-channel transistor or an n-channel transistor, but aspects of the present invention are not limited thereto.

[0147] The first electrode E1a may be a gate, the second electrode E1b may be a source or a drain, and the third electrode E1c may be a drain or a source. Hereinafter, for ease of explanation, the discussion may be provided based on an example where the first electrode E1a, the second electrode E1b, and the third electrode E1c are the first gate E1a, the first source E1b, and the first drain E1c, respectively.

[0148] The second transistor TFT2 may include a second active layer ACT2, a fourth electrode E2a, a fifth electrode E2b, and a sixth electrode E2c. The second active layer ACT2 may be a second semiconductor layer, but aspects of the present invention are not limited thereto. For example, the second active layer ACT2 may be configured with an oxide semiconductor, amorphous silicon, polysilicon, low-temperature polysilicon (LTPS), etc., but aspects of the present invention are not limited thereto. The second transistor TFT2 may be a p-channel transistor or an n-channel transistor, but aspects of the present invention are not limited thereto. For example, one of the first transistor TFT1 and the second transistor TFT2 may include an active layer having an oxide semiconductor. In another example, one of the first transistor TFT1 and the second transistor TFT2 may include an active layer having low-temperature polysilicon. In yet another example, the first transistor TFT1 and the second transistor TFT2 may include an active layer having an oxide semiconductor. In another example, one or more transistors in a gate driver configured as a gate-in-panel (GIP) type may include an active layer having an oxide semiconductor or low-temperature polysilicon. In another example, all transistors disposed on a substrate and transistors included in a gate driver configured as a gate-in-panel (GIP) type may include an active layer having an oxide semiconductor.

[0149] The fourth electrode E2a may be a gate, the fifth electrode E2b may be a source or a drain, and the sixth electrode E2c may be a drain or a source. Hereinafter, for ease of explanation, the discussion may be provided based on an example where the fourth electrode E2a, the fifth electrode E2b, and the sixth electrode E2c are the second gate E2a, the second source E2b, and the second drain E2c, respectively.

[0150] Spaced apart from the substrate 111 (or based on the substrate 111), the second active layer ACT2 of the second transistor TFT2 can be set higher (farther) than the first active layer ACT1 of the first transistor TFT1.

[0151] The first buffer layer 311 can be disposed under the first active layer ACT1 of the first transistor TFT1, and the second buffer layer 321 can be disposed under the second active layer ACT2 of the second transistor TFT2. For example, the first active layer ACT1 of the first transistor TFT1 can be disposed on the first buffer layer 311, and the second active layer ACT2 of the second transistor TFT2 can be disposed on the second buffer layer 321. The second buffer layer 321 can be set higher (farther from the substrate) than the first buffer layer 311.

[0152] The storage capacitor Cst can be disposed in various metal layers in the display panel 110. For example, the storage capacitor Cst can include a first capacitor electrode CE1 and a second capacitor electrode CE2.

[0153] The light-emitting element forming portion can include a plurality of light-emitting elements ED disposed on at least one planarization layer (331 and / or 332). Each light-emitting element ED can include a pixel electrode PE, an intermediate layer EL, and a common electrode CE. The light-emitting element forming portion can be a light-emitting element portion.

[0154] The encapsulation portion can include an encapsulation layer 200 located on the plurality of light-emitting elements ED. The encapsulation layer 200 can be formed as a single layer or multiple layers. In addition to the encapsulation layer 200, the encapsulation portion can further include at least one dam DAM.

[0155] Hereinafter, reference will be made to Figure 3 The stacked structure of the display panel 110 according to various aspects of the present invention will be described in more detail.

[0156] Referring to Figure 3 , the first buffer layer 311 can be disposed on the substrate 111. The first buffer layer 311 can be formed as a single layer or multiple layers. In an example where the first buffer layer 311 has a multi-layer stack, the first buffer layer 311 can include a multi-buffer layer 311a and an active buffer layer 311b.

[0157] The first active layer ACT1 of the first transistor TFT1 can be disposed on the first buffer layer 311. The first active layer ACT1 can include: a channel region where a channel is formed; a source connection region on one side of the channel region; and a drain connection region on the other side of the channel region.

[0158] The first gate insulating layer 312 may be disposed on the first active layer ACT1 of the first transistor TFT1. The first gate E1a of the first transistor TFT1 may be disposed on the first gate insulating layer 312. The first interlayer insulating layer 313 may be disposed on the first gate E1a of the first transistor TFT1.

[0159] The second buffer layer 321 may be disposed on the first interlayer insulating layer 313.

[0160] The second active layer ACT2 of the second transistor TFT2 may be disposed on the second buffer layer 321. The second active layer ACT2 may include: a channel region in which a channel is formed; a source connection region on a first side of the channel region; and a drain connection region on a second opposite side of the channel region.

[0161] The second gate insulating layer 322 may be disposed on the second active layer ACT2 of the second transistor TFT2. The second gate E2a of the second transistor TFT2 may be disposed on the second gate insulating layer 322. The second interlayer insulating layer 323 may be disposed on the second gate E2a of the second transistor TFT2.

[0162] The first source E1b and the first drain E1c of the first transistor TFT1 and the second source E2b and the second drain E2c of the second transistor TFT2 may be disposed on the second interlayer insulating layer 323.

[0163] The first source E1b and the first drain E1c of the first transistor TFT1 may be connected to the source connection region and the drain connection region of the first active layer ACT1 respectively through holes formed in the second interlayer insulating layer 323, the second gate insulating layer 322, the second buffer layer 321, the first interlayer insulating layer 313, and the first gate insulating layer 312.

[0164] The second source E2b and the second drain E2c of the second transistor TFT2 may be connected to the source connection region and the drain connection region of the second active layer ACT2 respectively through holes in the second interlayer insulating layer 323 and the second gate insulating layer 322.

[0165] The first source E1b and the first drain E1c of the first transistor TFT1 and the second source E2b and the second drain E2c of the second transistor TFT2 may include a first metal and may be disposed in a first metal layer. The first metal and the first metal layer may be referred to as the first source-drain metal and the first source-drain metal layer respectively.

[0166] Refer to Figure 3, in one or more aspects, the storage capacitor Cst may be configured with a first capacitor electrode CE1 and a second capacitor electrode CE2. In one or more aspects, the storage capacitor Cst may include three or more capacitor electrodes, or may include two or more capacitors connected in parallel.

[0167] Each of the first capacitor electrode CE1 and the second capacitor electrode CE2 may be disposed in various metal layers in or at the display panel 110.

[0168] In one or more aspects, the first capacitor electrode CE1 may include the same first gate metal as the first gate E1a of the first transistor TFT1 on the first gate insulating layer 312, and may be disposed in or at the first gate metal layer.

[0169] In one or more aspects, the second capacitor electrode CE2 may be disposed on the first interlayer insulating layer 313.

[0170] The second source E2b of the second transistor TFT2 may be electrically connected to the second capacitor electrode CE2 through a hole in the second interlayer insulating layer 323, the second gate insulating layer 322, and the second buffer layer 321.

[0171] In one or more aspects, the first transistor TFT1 may be Figure 2 the driving transistor DT, and the second transistor TFT2 may be Figure 2 the scanning transistor ST.

[0172] The transistor forming portion may further include various metal layers (such as the first metal layer MP1, the second metal layer MP2, etc.). For example, the first metal layer MP1 may be disposed between the multiple buffer layer 311a and the active buffer layer 311b included in the first buffer layer 311. The second metal layer MP2 may include the same first gate metal as the first gate E1a of the first transistor TFT1, and may be disposed in the first gate metal layer. In one or more aspects, the first metal layer MP1 may be the first metal pattern, and the second metal layer MP2 may be the second metal pattern. However, the various aspects of the present invention are not limited thereto.

[0173] Each of the first metal layer MP1 and the second metal layer MP2 may be disposed in the active region AA or the non-active region NA.

[0174] Referring to Figure 3 , the transistor forming portion may further include a shielding layer BSM, which is disposed on the substrate 111, overlaps with the second active layer ACT2 of the second transistor TFT2, and is disposed below the second active layer ACT2 of the second transistor TFT2.

[0175] For example, the shielding layer BSM can be disposed in the same first gate metal layer as the first gate E1a of the first transistor TFT1. In another example, the shielding layer BSM can be disposed in the same metal layer as the first metal layer MP1 on the first buffer layer 311.

[0176] An additional shielding layer BSM can be disposed under and overlapping the first active layer ACT1 of the first transistor TFT1. In this embodiment, the shielding layer BSM can be disposed in the same metal layer as the first metal layer MP1.

[0177] Referring Figure 3 , the transistor forming portion may further include a common driving voltage pattern CVP to which a common driving voltage is applied. The common driving voltage applied to the common driving voltage pattern CVP can be a power supply signal. For example, it can be Figure 2 the first common driving voltage VDD or the second common driving voltage VSS in . The first common driving voltage VDD can be referred to as a high power supply voltage (or a high potential power supply signal), and the second common driving voltage VSS can be referred to as a low power supply voltage (or a low potential power supply signal) or a ground voltage.

[0178] The common driving voltage pattern CVP can be disposed in the active area AA or the non-active area NA.

[0179] At least one planarization layer can be disposed on the first transistor TFT1 and the second transistor TFT2. Figure 3 For example, two planarization layers (the first planarization layer 331 and the second planarization layer 332) are shown disposed on the first transistor TFT1 and the second transistor TFT2. In one or more aspects, three or more planarization layers can be disposed on the first transistor TFT1 and the second transistor TFT2 according to design requirements. However, multiple aspects of the present invention are not limited thereto.

[0180] Referring Figure 3 , the first planarization layer 331 can be disposed on the first source E1b and the first drain E1c of the first transistor TFT1 and the second source E2b and the second drain E2c of the second transistor TFT2. In one or more aspects, the first planarization layer 331 can be disposed on both the first transistor TFT1 and the second transistor TFT2 and cover both the first transistor TFT1 and the second transistor TFT2.

[0181] Referring Figure 3 , a relay electrode RE (or a connection electrode) can be disposed on the first planarization layer 331. The relay electrode RE can be electrically connected to the first source E1b of the first transistor TFT1 via a hole in the first planarization layer. The relay electrode RE can also be referred to as a connection electrode.

[0182] The relay electrode RE may be disposed in a second metal layer on the first planarization layer 331 and include a second metal. The second metal and the second metal layer may be referred to as a second source-drain metal and a second source-drain metal layer, respectively.

[0183] A second planarization layer 332 may be disposed on the relay electrode RE.

[0184] Refer to Figure 3 , a light-emitting element forming portion may be disposed on the second planarization layer 332. A light-emitting element ED may be formed on the second planarization layer 332. The light-emitting element ED may include a pixel electrode PE, an intermediate layer EL, and a common electrode CE. A light-emitting region of the light-emitting element ED may be formed in a region where the pixel electrode PE, the intermediate layer EL, and the common electrode CE overlap and contact each other.

[0185] The pixel electrode PE may be disposed on the second planarization layer 332, and a bank portion 333 may be disposed on the pixel electrode PE. An opening of the bank portion 333 may expose a part of the pixel electrode PE to form a light-emitting region. For example, the opening of the bank portion 333 may overlap a part of the pixel electrode PE.

[0186] The intermediate layer EL of the light-emitting element ED may be disposed on a part of the pixel electrode PE and the bank portion 333. The common electrode CE may be disposed on the intermediate layer EL.

[0187] Refer to Figure 3 , an encapsulation portion may be disposed on the light-emitting element forming portion and on the common electrode CE. The encapsulation portion may include an encapsulation layer 200 disposed on the common electrode CE.

[0188] The encapsulation layer 200 may prevent moisture or oxygen from penetrating into the light-emitting element ED. For example, the encapsulation layer 200 may prevent moisture or oxygen from penetrating into the organic material included in the intermediate layer EL of the light-emitting element ED. In one or more aspects, the encapsulation layer 200 may be formed as a single layer or multiple layers, but the aspects of the present invention are not limited thereto.

[0189] Refer to Figure 3 , for example, the encapsulation layer 200 may include a first encapsulation layer 341, a second encapsulation layer 342, and a third encapsulation layer 343. The first encapsulation layer 341 and the third encapsulation layer 343 may include an inorganic layer, and the second encapsulation layer 342 may include an organic layer, for example.

[0190] In one or more aspects, a touch sensor may be built into the display panel 110. In these aspects, the display panel 110 may include a touch sensor portion 210 disposed on the encapsulation layer 200.

[0191] Refer to Figure 3, the touch sensor unit 210 may include a plurality of touch electrodes TE, and may include a bridging electrode BRG and a touch sensor electrode TSM for forming the plurality of touch electrodes TE. The touch sensor electrode TSM may also be referred to as a touch sensor layer TSM. The bridging electrode BRG may also be referred to as a bridging layer BRG.

[0192] The touch sensor unit 210 may further include one or more insulating layers, such as a buffer layer 351 on the encapsulation layer 200, an interlayer insulating layer 352 on the buffer layer 351, and / or a protective layer 353 on the interlayer insulating layer 352. The bridging layer BRG may be disposed between the buffer layer 351 and the interlayer insulating layer 352, and the touch sensor layer TSM may be disposed between the interlayer insulating layer 352 and the protective layer 353.

[0193] Each of the plurality of touch electrodes TE may include a touch sensor layer TSM. Each of the plurality of touch electrodes TE may be a mesh-type electrode having a plurality of openings.

[0194] The plurality of touch electrodes TE may include one or more first touch electrodes TE1 and one or more second touch electrodes TE2. The touch sensor layers TSM included in the first touch electrodes TE1 may be electrically connected via at least one bridging layer BRG.

[0195] The buffer layer 351 may be disposed on the encapsulation layer 200, the bridging layer BRG may be disposed on the buffer layer 351, and the interlayer insulating layer 352 may be disposed on the bridging layer BRG.

[0196] The touch sensor layer TSM may be disposed on the interlayer insulating layer 352. Corresponding portions of the touch sensor layer TSM may be connected to corresponding bridging layers BRG via holes formed in the interlayer insulating layer 352.

[0197] Refer to Figure 3 , the touch sensor layer TSM and the bridging layer BRG may be arranged such that the touch sensor layer TSM and the bridging layer BRG may overlap each other. The touch sensor layer TSM and the bridging layer BRG may overlap with the dam portion 333.

[0198] In one or more aspects, a plurality of touch sensor layers TSM may be included in one touch electrode TE, and may be arranged in a mesh pattern and electrically connected to each other. In one or more aspects, one or more touch sensor layers TSM and another or more touch sensor layers TSM may be electrically connected to each other via one or more bridging layers BRG to form one touch electrode TE.

[0199] The sensor protective layer 353 may be disposed on the touch sensor layer TSM and the bridging layer BRG, and cover the touch sensor layer TSM and the bridging layer BRG.

[0200] Reference Figure 3 As shown in Figure 3 , the touch line TL can electrically connect the touch electrode TE to the touch pad TP. The touch line TL can include at least one of the touch sensor layer TSM and the bridging layer BRG.

[0201] In an example where the display panel 110 is a display panel with a built-in touch sensor, the touch line TL can extend along the outer slope SLP_ENCAP of the encapsulation layer 200 and the upper part of at least one dam DAM, and extend to the touch pad TP located or disposed in the non-active area NA.

[0202] Figure 4 Illustrate an exemplary substrate (e.g., Figure 3 substrate 111) of the display panel 110 according to various aspects of the present invention.

[0203] Reference Figure 4 As shown in Figure 4 , in one or more aspects, the substrate 111 of the display panel 110 can include an active area AA where an image can be displayed and a non-active area NA where no image is displayed.

[0204] The non-active area NA can include a first non-active area NA1, a second non-active area NA2, a third non-active area NA3, and a fourth non-active area NA4. However, various aspects of the present invention are not limited thereto. There may be additional non-active areas or a smaller number of non-active areas.

[0205] The first non-active area NA1 can be located or disposed in a first direction from the active area AA. The second non-active area NA2 can be located or disposed in a second direction from the active area AA. The third non-active area NA3 can be located or disposed in a third direction from the active area AA. The fourth non-active area NA4 can be located or disposed in a fourth direction from the active area AA.

[0206] For example, the first non-active area and the third non-active area (NA1, NA3) can be areas opposite to each other in the column direction. The second non-active area and the fourth non-active area (NA2, NA4) can be areas opposite to each other in the row direction. In another example, the first non-active area and the third non-active area (NA1, NA3) can be areas opposite to each other in the row direction. The second non-active area and the fourth non-active area (NA2, NA4) can be areas opposite to each other in the column direction. Hereinafter, for the sake of explanation, the discussion may be provided based on an example where the first non-active area and the third non-active area (NA1, NA3) are areas opposite to each other in the column direction and the second non-active area and the fourth non-active area (NA2, NA4) are areas opposite to each other in the row direction.

[0207] For example, the column direction may be the direction in which the data line DL extends, and the row direction may be the direction in which the gate line GL extends. In another example, the column direction may be the direction in which the gate line GL extends, and the row direction may be the direction in which the data line DL extends. Hereinafter, for the sake of easy explanation, the discussion may be provided based on the example in which the column direction is the direction in which the data line DL extends and the row direction is the direction in which the gate line GL extends. However, various aspects of the present invention are not limited thereto.

[0208] Referring to Figure 4 , the first non-active region NA1 may include a pad region PA. A plurality of pads to which at least one driving circuit or a printed circuit board is electrically connected may be provided in the pad region PA. In one or more aspects, a plurality of data lines DL, a first common driving voltage line VDDL, and a second common driving voltage line VSSL may be electrically connected to the plurality of pads.

[0209] The first non-active region NA1 may further include a bending region BA. In this embodiment, the substrate 111 may be a flexible substrate. In one or more aspects, the first non-active region NA1 may not include the bending region BA.

[0210] The display panel 110 may further include a ground line provided in the non-active region NA of the substrate 111. The ground line may be provided to extend from a point of the pad region PA through the second non-active region NA2, the third non-active region NA3, and the fourth non-active region NA4 to another point of the pad region PA.

[0211] In one or more aspects, the encapsulation layer 200 provided in the display panel 110 may have a structure in which at least one inorganic layer and at least one organic layer are stacked, but various aspects of the present invention are not limited thereto. In these aspects, the edge of the encapsulation layer 200 may be the edge of the organic layer. The encapsulation layer 200 may extend from the display region AA to a part of the non-active region NA.

[0212] In one or more aspects, in order to prevent the overflow of the organic layer in the encapsulation layer 200, the display panel 110 may further include at least one dam or at least one stopper provided outside the organic layer included in the encapsulation layer 200. The at least one dam or the at least one stopper may include an organic layer, but various aspects of the present invention are not limited thereto.

[0213] Figure 5 is an exemplary plan view of the display panel 110 according to various aspects of the present invention and illustrates a data connection structure configured in the display panel 110.

[0214] Referring to Figure 5, in one or more aspects, the display panel 110 may include: a plurality of data lines DL for transmitting a data voltage VDATA; and a plurality of pads PD, which are provided in a pad region PA and allow electrical connection of the data driver circuit 120.

[0215] In one or more aspects, the display panel 110 may include a data connection structure for electrically connecting the plurality of data lines DL to the plurality of pads PD. In one or more aspects, the data connection structure may include a plurality of data connection lines LINK. The data connection lines may also be referred to as link lines.

[0216] The plurality of data connection lines LINK may be provided in a non-active region NA. For example, the plurality of data connection lines LINK may be provided in a first non-active region NA1 including the pad region PA.

[0217] In addition to the pad region PA and the bending region BA, the first non-active region NA1 may further include a connection region LA.

[0218] For example, each of the plurality of data connection lines LINK may be disposed across the pad region PA, the bending region BA, and the connection region LA. Each of the plurality of data connection lines LINK may include: a first end (or first side), which is electrically connected to the pad PD provided in the pad region PA; and a second end (or second side), which is electrically connected to the data line DL provided in the active region AA. A portion between both ends (i.e., the first end and the second end, or the first side and the second side) of each of the plurality of data connection lines LINK may be disposed across the bending region BA and the connection region LA.

[0219] For example, each of the plurality of data connection lines LINK may be formed from one line or two or more lines. Each of the plurality of data connection lines LINK may be provided in one metal layer, or two or more metal layers.

[0220] The bending region BA may be bent during the manufacturing process of the display panel 110. Therefore, when the user views the display device 100 in front of the display device 100, the bending region BA and the pad region PA may be invisible to the user.

[0221] However, when the user views the display device 100 in front of the display device 100, the connection region LA may be recognized as a border even if it is covered by a case or a cover member. Therefore, in order to achieve a narrow border, it is desirable to reduce the area or size of the connection region LA.

[0222] Refer to Figure 5 , since all of the plurality of data connection lines LINK in the connection region LA of the first non-active region NA1 need to be electrically connected to the plurality of data lines DL, the connection region LA requires a large area.

[0223] For example, when the length of the pad region PA in the second direction (row direction) is less than the length of the active region AA in the second direction (row direction), each of the plurality of data connection lines LINK in the left region LBZ and the right region RBZ of the connection region LA needs to extend at a predetermined (consistent) angle with respect to the row direction or the column direction, and then is electrically connected to a corresponding one of the plurality of data lines DL. This configuration causes the connection region LA to have an increased length in the first direction (column direction), and the connection region LA has an increased area.

[0224] Therefore, as Figure 5 shown, in an example of a data connection structure in which a plurality of data connection lines LINK are provided in the first non-active region NA1 of the display panel 110, the connection region LA of the first non-active region NA1 may require a larger area. In this embodiment, when the user views the display device 100 in front of the display device 100, the connection region LA may be recognized as a wide border.

[0225] Therefore, in order to achieve a narrow border, a data connection structure capable of reducing the area of the connection region LA needs to be provided. To meet this requirement, as discussed below, a data connection structure capable of achieving a narrow border is provided.

[0226] Hereinafter, a data connection structure capable of achieving a narrow border according to various aspects of the present invention will be described.

[0227] Figure 6 is an exemplary plan view of a display panel 110 according to various aspects of the present invention, and illustrates an exemplary data connection structure (border reduction data connection structure) capable of reducing the border of the display panel 110. Figure 7 Illustrates an example of three regions (region A, region B, and region C) in the active region AA through the border reduction data connection structure of the display panel 110 according to various aspects of the present invention. In one or more aspects, the data connection structure may be a border reduction data connection structure.

[0228] Referring to Figure 6 the non-active region NA may include a first non-active region NA1 provided in the column direction from the active region AA. The first non-active region NA1 may include a pad region PA and a connection region LA provided in the column direction from the active region AA.

[0229] In one or more aspects, the display panel 110 may include a data connection structure that can reduce the border of the display panel 110 and allows a data voltage VDATA to be provided to a plurality of sub-pixels SP provided in the active region AA.

[0230] Referring to Figure 6, in one or more aspects, this border-reducing data connection structure may include a plurality of data connection lines LINK configured to electrically connect a plurality of data lines DL to a plurality of pads PD.

[0231] The plurality of data lines DL may be disposed in the active region AA, extend in the column direction, and be connected to a plurality of sub-pixels SP disposed in the active region AA.

[0232] The plurality of pads PD may be disposed in a pad region PA included in the first non-active region NA1.

[0233] The plurality of data connection lines LINK may electrically connect the plurality of pads PD disposed in the pad region PA in the first non-active region NA1 to the plurality of data lines DL disposed at the active region AA.

[0234] Referring to Figure 6 , in one or more aspects, each of the plurality of data connection lines LINK in the data connection structure for a narrow border may include a portion LIA of the active region AA disposed therein.

[0235] In the border-reducing data connection structure according to multiple aspects of the present invention, the plurality of data connection lines LINK and the plurality of data lines DL may be electrically connected to each other in the active region AA. For example, in the border-reducing data connection structure according to multiple aspects of the present invention, the connection point CNT_DL between the plurality of data connection lines LINK and the plurality of data lines DL may be located or disposed in the active region AA.

[0236] Therefore, each of the plurality of data connection lines LINK may not need to extend at a predetermined (consistent) angle with respect to the row direction or the column direction in the left region and the right region of the connection region LA, and each of the plurality of data connection lines LINK may pass through the connection region LA in the column direction with a shorter length and enter the active region AA to be connected to the corresponding data line DL in the active region AA.

[0237] As Figure 6 shown, in an example where the display panel 110 has a border-reducing data connection structure, the length of the connection region LA in the column direction may be very short or zero. Therefore, the first non-active region NA1 seen by the user in front of the display panel 110 may become very small.

[0238] Referring to Figure 6 , in the border-reducing data connection structure according to multiple aspects of the present invention, each of the plurality of data connection lines LINK may include a connection line LIA (which may be referred to as an active region connection line LIA) of the active region AA that may be disposed in the active region AA.

[0239] The active region connection line LIA can be disposed in the active region AA, and includes a horizontal connection line HLIA extending in the row direction (i.e., the horizontal direction) and a vertical connection line VLIA extending in the column direction (i.e., the vertical direction). The horizontal connection line HLIA can be denoted as the first connection line, the third connection line, etc., but multiple aspects of the present invention are not limited thereto. The vertical connection line VLIA can be denoted as the second connection line, the fourth connection line, etc., but multiple aspects of the present invention are not limited thereto.

[0240] Each vertical connection line VLIA can electrically connect the corresponding pad PD to the corresponding horizontal connection line HLIA. Each horizontal connection line HLIA can electrically connect the corresponding vertical connection line VLIA to the corresponding data line DL.

[0241] The horizontal connection line HLIA and the vertical connection line VLIA can be electrically connected to each other at the connection point CNT_LIA. The horizontal connection line HLIA and the data line DL can be electrically connected to each other at the connection point CNT_DL.

[0242] Referring to Figure 6 , each of the multiple data connection lines LINK can further include a connection line LIN (which can be referred to as a non-active region connection line LIN) of the non-active region NA that can be disposed in the first non-active region NA1 of the non-active region NA.

[0243] For example, the non-active region connection line LIN and the vertical connection line VLIA can be formed as a single line. In another example, the non-active region connection line LIN can be electrically connected to the vertical connection line VLIA and can be disposed in a metal layer different from the metal layer in which the vertical connection line VLIA is disposed. In yet another example, the non-active region connection line LIN can include a line that is electrically connected to the vertical connection line VLIA and is disposed in a metal layer different from the metal layer in which the vertical connection line VLIA is disposed.

[0244] In the example where the display panel 110 has Figure 6 the border-reducing data connection structure shown, the horizontal connection line HLIA included in each of the multiple data connection lines LINK can be parallel to the multiple gate lines GL disposed in the active region AA and extend in the row direction (horizontal direction).

[0245] In addition, in the example where the display panel 110 has Figure 6 the border-reducing data connection structure shown, the horizontal connection line HLIA included in each of the multiple data connection lines LINK can overlap at least one gate line GL in the vertical direction.

[0246] Referring to Figure 6, among the plurality of vertical connection lines VLIA, the vertical connection line VLIA electrically connected to the data line DL placed or disposed closer to the center of the active region AA may have a relatively short length. Among the plurality of vertical connection lines VLIA, the vertical connection line VLIA electrically connected to the data line DL farther from the center of the active region AA may have a greater length than the vertical connection line VLIA electrically connected to the data line DL placed or disposed closer to the center of the active region AA. Among the plurality of vertical connection lines VLIA, the vertical connection line VLIA electrically connected to the data line DL placed or disposed closer to the center of the active region AA may have a shorter length than the vertical connection line VLIA electrically connected to the data line DL farther from the center of the active region AA. However, various aspects of the present invention are not limited thereto.

[0247] , among the plurality of horizontal connection lines HLIA, the horizontal connection line HLIA electrically connected to the data line DL placed or disposed closer to the center of the active region AA may have a relatively short length. Among the plurality of horizontal connection lines HLIA, the horizontal connection line HLIA electrically connected to the data line DL farther from the center of the active region AA may have a greater length than the horizontal connection line HLIA electrically connected to the data line DL placed or disposed closer to the center of the active region AA. Among the horizontal connection lines HLIA, the horizontal connection line HLIA electrically connected to the data line DL placed or disposed closer to the center of the active region AA may have a shorter length than the horizontal connection line HLIA electrically connected to the data line DL farther from the center of the active region AA. However, various aspects of the present invention are not limited thereto.

[0248] , among the plurality of horizontal connection lines HLIA, the horizontal connection line HLIA closer to the pad region PA may have a relatively short length. Among the plurality of horizontal connection lines HLIA, the horizontal connection line HLIA farther from the pad region PA may have a relatively greater length. Among the plurality of horizontal connection lines HLIA, the horizontal connection line HLIA closer to the pad region PA may have a shorter length than the horizontal connection line HLIA farther from the pad region PA. However, various aspects of the present invention are not limited thereto.

[0249] The first data connection line LINK1 may include an active region connection line LIA1 and a non-active region connection line LIN1. The active region connection line LIA1 included in the first data connection line LINK1 may include a first connection line HLIA1 as a horizontal connection line and a second connection line VLIA1 as a vertical connection line.

[0250] The second data connection line LINK2 may include an active region connection line LIA2 and a non-active region connection line LIN2. The active region connection line LIA2 included in the second data connection line LINK2 may include a third connection line HLIA2 as a horizontal connection line and a fourth connection line VLIA2 as a vertical connection line.

[0251] Among the second connection line VLIA1 and the fourth connection line VLIA2 which are vertical connection lines, the fourth connection line VLIA2 may have a greater length than the second connection line VLIA1 that is electrically connected to the first data line DL1 which is placed or disposed more outwardly among the first data line DL1 and the second data line DL2.

[0252] In addition, among the first connection line HLIA1 and the third connection line HLIA2 which are horizontal connection lines, the third connection line HLIA2 may have a greater length than the first connection line HLIA1 that is electrically connected to the first data line DL1 which is placed or disposed more outwardly among the first data line DL1 and the second data line DL2.

[0253] Since the first connection line HLIA1 has a greater length than the third connection line HLIA2, a first dimension of a region where the first connection line HLIA1 overlaps with at least one gate line GL may be greater than a second dimension of a region where the third connection line HLIA2 overlaps with at least one gate line GL.

[0254] As Figure 6 shown, a point CNT_DL where the data line DL and the horizontal connection line HLIA are connected may form two first slant lines SLT_DL. In addition, a point CNT_LIA where the vertical connection line VLIA and the horizontal connection line HLIA are connected may form two second slant lines SLT_LIA when connected by an imaginary line.

[0255] As Figure 6 shown, two triangles may be formed by the two first slant lines SLT_DL and the two second slant lines SLT_LIA (shown as 2 shaded triangles in Figure 6 . In each of the two triangles, one of the three sides may be a horizontal side parallel to the horizontal connection line HLIA, and a vertex facing this horizontal side may be located or disposed in a boundary between the active region AA and the first non-active region NA1, or at a position near the boundary.

[0256] Referring to Figure 6 , the active region AA may include a central region Ac, a first region A1 on a first side of the central region Ac, and a second region A2 on a second opposite side of the central region Ac.

[0257] The data lines DL provided in the first region A1 and the second region A2 can be connected to the non-active region connection line LIN through the active region connection line LIA.

[0258] In an embodiment, at least one data line DL provided in the central region Ac can be directly connected to the corresponding non-active region connection line LIN without the active region connection line LIA.

[0259] In the display panel 110 having Figure 6 In the example of the border reduction data connection structure shown, the corresponding horizontal connection line HLIA in the plurality of data connection lines LINK can be parallel to the plurality of gate lines GL provided in the active region AA, and extend in the row direction (horizontal direction), and the corresponding horizontal connection line HLIA included in the plurality of data connection lines LINK can overlap at least one gate line GL in the vertical direction.

[0260] Referring to Figure 7 , according to the above border reduction data connection structure, the active region AA can include three regions (A, B, and C).

[0261] The first region (region A) can be a region where the border reduction data connection structure is not configured. The second region (region B) and the third region (region C) can be regions where the border reduction data connection structure is configured. The second region (region B) can be a region where the horizontal connection line HLIA is provided, and the third region (region C) can be a region where the vertical connection line VLIA is provided.

[0262] Among the first to fourth non-active regions (NA1 to NA4) included in the non-active region NA, the first non-active region NA1 including the pad region PA can contact one side of each third region (region C).

[0263] The second region (region B) can have an inverted triangle or an isosceles triangle, but various aspects of the present invention are not limited thereto. The active region AA can include two second regions (region B). The two second regions (region B) can be respectively located or provided on both sides of the first region (region A, which is located or provided in the central region of the active region AA).

[0264] The third region (region C) can have a right triangle, but various aspects of the present invention are not limited thereto. The active region AA can include two third regions (region C). The two third regions (region C) can be respectively located or provided on both sides of the first region (region A, which is located in the central region of the active region AA). A right triangle can also be referred to as a triangle with a right angle, an orthogonal triangle, or a rectangular triangle.

[0265] The first region (Region A) can be located on (or on top of) two second regions (Region B), can also be located or disposed between two third regions (Region C), or can be located outside two second regions (Region B). The first region (Region A) located or disposed between two third regions (Region C) can correspond to Figure 6 the central region Ac.

[0266] Referring to Figure 6 and Figure 7 , in other embodiments of the present invention, the first region (Region A), the second region (Region B), and the third region (Region C) can be arranged differently and / or each can have a shape different from that shown in Figure 6 and 7 . For example, Figure 7 shows that the adjacent third regions (Region C) have a portion overlapping with the central region Ac (see Figure 6 ) of the first region (Region A) interposed therebetween. However, the active region AA does not need to have a portion overlapping or coinciding with the central region Ac of the first region (Region A). Instead, the adjacent third regions (Region C) can be combined to form a single third region (Region C) in the form of an isosceles triangle.

[0267] In addition, referring to Figure 6 and Figure 7 , the shape of the second region (Region B) does not need to be the isosceles triangle shown, but can be a polygon, such as a trapezoid, a parallelogram, or other shapes. When the second region (Region B) is a parallelogram, the lengths of the first connection line HLIA1 or the second connection line HLIA2 can be the same.

[0268] Referring to Figure 6 and 7 , the boundary between the first region (Region A) and each of the two second regions (Region B) can correspond to the point CNT_DL where the horizontal connection line HLIA is connected to the data line DL, and form the first diagonal line SLT_DL.

[0269] The boundary between each second region (Region B) and each third region (Region C) can correspond to the point CNT_LIA where the vertical connection line VLIA is connected to the horizontal connection line HLIA, and form the second diagonal line SLT_LIA.

[0270] As shown in Figure 7 , the first diagonal line SLT_DL and the second diagonal line SLT_LIA are inclined in different directions. However, many aspects of the present invention are not limited thereto. For example, the first diagonal line SLT_DL and the second diagonal line SLT_LIA can be parallel, or inclined in the same direction.

[0271] Figure 8Region of the display panel 110 having a data connection structure (e.g., the bezel-reduced data connection structure discussed above) according to various aspects of the present invention is illustrated. Figure 8 is a magnified plan view of region 600 which is configured with a data connection structure (i.e., the bezel-reduced data connection structure). Figure 6 Figure 9 is an exemplary cross-sectional view of the first opening region OA1 of the first metal layer ML1 of the display panel 110 according to various aspects of the present invention. Figure 9 is Figure 8 a cross-sectional view of region 810 including the first opening region OA1 of the first metal ML1. Figure 10 is an exemplary cross-sectional view of the second opening region OA2 of the second metal layer ML2 of the display panel 110 according to various aspects of the present invention. Reference will be made to Figure 6 and Figure 8 、 9 and 10 for the discussion below.

[0272] Referring to Figure 8 , the first non-active region NA1 may include a pad region PA provided with a plurality of data pads (DP1, DP2, DP3, and / or DP4). The plurality of data pads (DP1, DP2, DP3, and / or DP4) may include a first data pad DP1, a second data pad DP2, a third data pad DP3, and a fourth data pad DP4. However, various aspects of the present invention are not limited thereto, and additional data pads may be employed.

[0273] A plurality of data lines DL may be provided in or at the active region AA, and include a first data line DL1, a second data line DL2, a third data line DL3, and a fourth data line DL4. Each of the first data line DL1, the second data line DL2, the third data line DL3, and the fourth data line DL4 may be provided in the active region AA and extend in the column direction. Corresponding data voltages may be applied to each of the first data line DL1, the second data line DL2, the third data line DL3, and the fourth data line DL4.

[0274] Referring to Figure 8 and 6 , a data connection structure (e.g., the bezel-reduced data connection structure discussed above) may be configured in a part of the active region AA adjacent to the first non-active region NA1. Thus, the bezel-reduced data connection structure discussed with reference to Figure 6 may be configured for Figure 8 the data connection structure.

[0275] Referring to Figure 8 and 6 ​, the data connection structure may include an active region connection region LIA. The active region connection region LIA may include a horizontal connection line HLIA and a vertical connection line VLIA.

[0276] Each horizontal connection line HLIA may be disposed in the active region AA. All or at least a part of each vertical connection line VLIA may be disposed in the active region AA.

[0277] Referring to Figure 8 , the horizontal connection line HLIA may include a first connection line HLIA1 and a third connection line HLIA2. The first connection line HLIA1 may be electrically connected to the first data line DL1. The first connection line HLIA1 may be disposed in the active region AA. The first connection line HLIA1 may extend in the row direction. The first connection line HLIA1 may be disposed in the first metal layer ML1.

[0278] The third connection line HLIA2 may be electrically connected to the second data line DL2. The third connection line HLIA2 may be located in the active region AA. The third connection line HLIA2 may extend in the row direction. The third connection line HLIA2 may be disposed in the first metal layer ML1.

[0279] Referring to Figure 8 , the vertical connection line VLIA may include a second connection line VLIA1 and a fourth connection line VLIA2. The second connection line VLIA1 may electrically connect the first connection line HLIA1 to the first data pad DP1. The second connection line VLIA1 may extend in the column direction. The second connection line VLIA1 may be disposed in a second metal layer ML2 different from the first metal layer ML1. All or at least a part of the second connection line VLIA1 may be disposed in the active region AA.

[0280] The fourth connection line VLIA2 may electrically connect the third connection line HLIA2 to the second data pad DP2. The fourth connection line VLIA2 may extend in the column direction. The fourth connection line VLIA2 may be located or disposed in the second metal layer ML2 different from the first metal layer ML1. All or at least a part of the fourth connection line VLIA2 may be disposed in or at the active region AA.

[0281] Referring to Figure 8 , in one or more aspects, the display panel 110 may further include a first metal pattern HLIA1_DC, which is separated from the first connection line HLIA1 and extends in the row direction. The first metal pattern HLIA1_DC may be disposed in the first metal layer ML1. The first metal pattern HLIA1_DC and the first connection line HLIA1 may be parallel to each other or may be disposed in the same row direction.

[0282] In one or more aspects, the display panel 110 may further include a second metal pattern VLIA1_DC, which is separated from the second connection line VLIA1 and extends in the column direction. The second metal pattern VLIA1_DC may be located or disposed in the second metal layer ML2.

[0283] In one or more aspects, the display panel 110 may further include a third metal pattern HLIA2_DC, which is separated from the third connection line HLIA2 and extends in the row direction. The third metal pattern HLIA2_DC may be disposed in the first metal layer ML1.

[0284] In one or more aspects, the display panel 110 may further include a fourth metal pattern VLIA2_DC, which is separated from the fourth connection line VLIA2 and extends in the column direction. The fourth metal pattern VLIA2_DC may be disposed in the second metal layer ML2.

[0285] If the first metal pattern HLIA1_DC and the third metal pattern HLIA2_DC are not provided in an area where the first connection line HLIA1 and the third connection line HLIA2 are not provided, the light reflection characteristics in the area where the first connection line HLIA1 and the third connection line HLIA2 are provided may be different from the light reflection characteristics in the area where the first connection line HLIA1 and the third connection line HLIA2 are not provided. Here, the light reflection characteristics may also refer to the degree of light reflection, the amount of light reflection, or the light reflectance. For example, the degree of light reflection in the area where the first connection line HLIA1 and the third connection line HLIA2 are provided may be greater than the degree of light reflection in the area where the first connection line HLIA1 and the third connection line HLIA2 are not provided. Due to this configuration, the corresponding light reflection characteristics at each position inside the display panel 110 may become significantly different, which results in display artifacts such as image abnormalities, brightness differences, color differences, etc. For example, the deviation of the light reflection characteristics in the area where the first connection line HLIA1 and the third connection line HLIA2 are not provided from the light reflection characteristics in the area where the first connection line HLIA1 and the third connection line HLIA2 are provided may be significantly changed, thereby display artifacts such as image abnormalities, brightness differences, color differences, etc. may occur. The light may include at least a part of the light (or internal light) emitted from one or more light-emitting elements ED and the external light introduced from the outside into the display panel 110.

[0286] If the second metal pattern VLIA1_DC and the fourth metal pattern VLIA2_DC are not provided in the region where the second connection line VLIA1 and the fourth connection line VLIA2 are not provided, the light reflection characteristics in the region where the second connection line VLIA1 and the fourth connection line VLIA2 are provided may be different from the light reflection characteristics in the region where the second connection line VLIA1 and the fourth connection line VLIA2 are not provided. Here, the light reflection characteristics may also refer to the degree of light reflection, the amount of light reflection, or the light reflectance. For example, the degree of light reflection in the region where the second connection line VLIA1 and the fourth connection line VLIA2 are provided may be greater than the degree of light reflection in the region where the second connection line VLIA1 and the fourth connection line VLIA2 are not provided. Due to this configuration, the corresponding characteristics of the reflected light at each position inside the display panel 110 may become significantly different, resulting in display artifacts such as image abnormalities, brightness differences, color differences, etc. For example, the deviation of the light reflection characteristics in the region where the second connection line VLIA1 and the fourth connection line VLIA2 are not provided from the light reflection characteristics in the region where the second connection line VLIA1 and the fourth connection line VLIA2 are provided may change significantly, thereby display artifacts such as image abnormalities, brightness differences, color differences, etc. may occur.

[0287] By placing the first metal pattern HLIA1_DC and the third metal pattern HLIA2_DC in the region where the first connection line HLIA1 and the third connection line HLIA2 are not provided, the difference between the light reflection characteristics in the region where the first connection line HLIA1 and the third connection line HLIA2 are provided and the light reflection characteristics in the region where the first connection line HLIA1 and the third connection line HLIA2 are not provided can be reduced. By placing the second metal pattern VLIA1_DC and the fourth metal pattern VLIA2_DC in the region where the second connection line VLIA1 and the fourth connection line VLIA2 are not provided, the difference between the light reflection characteristics in the region where the second connection line VLIA1 and the fourth connection line VLIA2 are provided and the light reflection characteristics in the region where the second connection line VLIA1 and the fourth connection line VLIA2 are not provided can be reduced. Therefore, the display artifacts caused by the presence or absence of one or more metal layers can be reduced by the first metal pattern HLIA1_DC and the third metal pattern HLIA2_DC, and the second metal pattern VLIA1_DC and the fourth metal pattern VLIA2_DC.

[0288] In one or more aspects, the display panel 110 may further include a metal pattern VLIA_DC adjacent to the first data line DL1 and extending in the column direction, and a metal pattern VLIA_DC adjacent to the second data line DL2 and extending in the column direction.

[0289] The first metal pattern HLIA1_DC, the third metal pattern HLIA2_DC, the second metal pattern VLIA1_DC, and the fourth metal pattern VLIA2_DC can be used as lines to which a low power supply voltage VSS, which is applied as a second common driving voltage, is applied.

[0290] Each of the first metal pattern HLIA1_DC and the third metal pattern HLIA2_DC can extend in the row direction, and each of the second metal pattern VLIA1_DC and the fourth metal pattern VLIA2_DC can extend in the column direction. Thus, the first metal pattern HLIA1_DC, the third metal pattern HLIA2_DC, the second metal pattern VLIA1_DC, and the fourth metal pattern VLIA2_DC can be configured as a mesh pattern and cross each other. By applying this configuration, the area for providing the low power supply voltage VSS as the second common driving voltage can be significantly increased by the first metal pattern HLIA1_DC, the third metal pattern HLIA2_DC, the second metal pattern VLIA1_DC, and the fourth metal pattern VLIA2_DC. Accordingly, the transmission characteristics of the low power supply voltage VSS can also be significantly improved.

[0291] In addition, the length and area of the path for transmitting the data voltage can be reduced because the first connection line HLIA1 and the first metal pattern HLIA1_DC, which extend in the same direction, are separated from each other, and the second connection line VLIA1 and the second metal pattern VLIA1_DC, which extend in the same direction, are separated from each other. By applying this configuration, the parasitic capacitance associated with the first data line DL1 can be reduced.

[0292] In addition, the length and area of the path for transmitting the data voltage can be reduced because the third connection line HLIA2 and the third metal pattern HLIA2_DC, which extend in the same direction, are separated from each other, and the fourth connection line VLIA2 and the fourth metal pattern VLIA2_DC, which extend in the same direction, are separated from each other. By applying this configuration, the parasitic capacitance associated with the second data line DL2 can be reduced.

[0293] The reduction of the parasitic capacitance associated with the first data line DL1 and the second data line DL2 can contribute to improving the image quality.

[0294] Refer to Figure 8 and 9, a reflection light difference caused by reflection of light inside the display panel 110 may occur between a first opening region OA1 where a first connection line HLIA1 and a first metal pattern HLIA1_DC are disconnected and a region where the first connection line HLIA1 and the first metal pattern HLIA1_DC are provided. The light may include light (or internal light) emitted from one or more light-emitting elements ED and at least a part of external light introduced from the outside into the display panel 110. The reflection light may be the reflected light among the light (or internal light) and the external light.

[0295] Referring to Figure 8 and 9 , the first connection line HLIA1 and the first metal pattern HLIA1_DC may be provided in a first metal layer ML1 and arranged in the same row. Accordingly, the first opening region OA1 where the first connection line HLIA1 and the first metal pattern HLIA1_DC are disconnected may also be referred to as the first opening region OA1 of the first metal layer ML1.

[0296] Referring to Figure 8 and 10 , a reflection light difference caused by reflection of light inside the display panel 110 may occur between a second opening region OA2 where a second connection line VLIA1 and a second metal pattern VLIA1_DC are disconnected and a region where the second connection line VLIA1 and the second metal pattern VLIA1_DC are provided. The light may include light (or internal light) emitted from one or more light-emitting elements ED and at least a part of external light introduced from the outside into the display panel 110. The reflection light may be the reflected light among the light (or internal light) and the external light.

[0297] Referring to Figure 8 and 10 , the second connection line VLIA1 and the second metal pattern VLIA1_DC may be provided in a second metal layer ML2 and arranged in the same column. Accordingly, the second opening region OA2 where the second connection line VLIA1 and the second metal pattern VLIA1_DC are disconnected may also be referred to as the second opening region OA2 of the second metal layer ML2.

[0298] Referring to Figure 7 , by reducing the data connection structure through the border, the first opening region OA1 of the first metal layer ML1 may exist at a boundary between a first region (region A) and a second region (region B) among three regions (A, B, and C) in the active region AA. Accordingly, a plurality of first opening regions OA1 may be positioned along a first diagonal line SLT_DL.

[0299] In addition, by reducing the data connection structure through the border, the first opening region OA1 of the first metal layer ML1 and the second opening region OA2 of the second metal layer ML2 can be present at the boundary between the second region (region B) and the third region (region C) among the three regions (A, B, and C) in the active region AA. Therefore, a plurality of first opening regions OA1 and / or a plurality of second opening regions OA2 can be positioned along the second slant line SLT_LIA.

[0300] Referring to Figure 9 and 10 , the first connection line HLIA1 and the first metal pattern HLIA1_DC can be disposed on the second interlayer insulating layer 323 (e.g., Figure 3 the second interlayer insulating layer 323), and are separated from each other.

[0301] The first planarization layer 331 (e.g., Figure 3 the first planarization layer 331) can be disposed on the first connection line HLIA1 and the first metal pattern HLIA1_DC.

[0302] Referring to Figure 9 and 10 , the second connection line VLIA1, the second metal pattern VLIA1_DC, and one or more other vertical lines (e.g., the data line DL3, etc.) can be disposed on the first planarization layer 331.

[0303] Referring to Figure 9 and 10 , the second connection line VLIA1 can be connected to the first connection line HLIA1 through a hole formed in the first planarization layer 331.

[0304] Referring to Figure 9 and 10 , the second planarization layer 332 (e.g., Figure 3 the second planarization layer 332) can be disposed on the second connection line VLIA1, the second metal pattern VLIA1_DC, and one or more other vertical lines (e.g., the data line DL3, etc.). The dam portion 333 (e.g., Figure 3 the dam portion 333) can be disposed on the second planarization layer 332.

[0305] Referring to Figure 9 , the first connection line HLIA1 and the first metal pattern HLIA1_DC can be disposed in the first metal layer ML1. The reflected light reflected by the metal can be reduced in the first opening region OA1 between the first connection line HLIA1 and the first metal pattern HLIA1_DC. Due to this structure, a difference in reflected light that may occur between the first opening region OA1 and the region around the first opening region OA1 can be obtained.

[0306] Referring to Figure 10, the second connection line VLIA1 and the second metal pattern VLIA1_DC may be disposed in the second metal layer ML2. The reflected light reflected by the metal may be reduced in the second opening region OA2 between the second connection line VLIA1 and the second metal pattern VLIA1_DC. Due to this configuration, a difference in reflected light may occur between the second opening region OA2 and the region around the second opening region OA2.

[0307] The difference in reflected light caused by light reflection through the first opening region OA1 in the first metal layer ML1 and the second opening region OA2 in the second metal layer ML2 may cause display artifacts such as image abnormalities, brightness differences, color differences, etc. The light may include at least a part of the light (or internal light) emitted from one or more light-emitting elements ED and the external light introduced from the outside into the display panel 110. The reflected light may be the amount of the reflected light among the light (or internal light) and the external light.

[0308] In the case where neither the first opening region OA1 in the first metal layer ML1 nor the second opening region OA2 in the second metal layer ML2 is adopted or present, since the first opening region OA1 in the first metal layer ML1 and the second opening region OA2 in the second metal layer ML2 are removed, the lengths of the active region connection line LIA and the data line DL connected to the active region connection line LIA become larger. Accordingly, the parasitic capacitance caused by the active region connection line LIA and the data line DL may increase, which may cause deterioration of image quality such as display artifacts. In addition, in the case where neither the first opening region OA1 in the first metal layer ML1 nor the second opening region OA2 in the second metal layer ML2 is adopted or present, since the first opening region OA1 in the first metal layer ML1 and the second opening region OA2 in the second metal layer ML2 are removed, the first metal pattern HLIA1_DC and the second metal pattern VLIA1_DC cannot be used as power supply lines (low power supply voltage lines VSSL) for transmitting the low power supply voltage VSS, which may cause a large voltage drop of the low power supply voltage VSS. Therefore, considering the voltage drop of the low power supply voltage VSS, a relevant power supply circuit may be required to output an increased low power supply voltage VSS. For example, such a case where neither the first opening region OA1 in the first metal layer ML1 nor the second opening region OA2 in the second metal layer ML2 is adopted may cause an increase in the rising of the low power supply voltage VSS.

[0309] When the first metal pattern HLIA1_DC, the third metal pattern HLIA2_DC, the second metal pattern VLIA1_DC, and the fourth metal pattern VLIA2_DC are provided, image abnormalities caused by the presence or absence of the metal layer can be reduced, and the transmission characteristics of the low-potential power supply voltage can be improved. However, when the first metal pattern HLIA1_DC, the third metal pattern HLIA2_DC, the second metal pattern VLIA1_DC, and the fourth metal pattern VLIA2_DC are provided, there are a first opening region OA1 in the first metal layer ML1 and a second opening region OA2 in the second metal layer ML2, and there are differences in reflected light due to the first opening region OA1 and the second opening region OA2. Therefore, it is desirable to reduce the differences in reflected light caused by the first opening region OA1 in the first metal layer ML1 and the second opening region OA2 in the second metal layer ML2.

[0310] Accordingly, in one or more aspects, the display device 100 and the display panel 110 may have a structure for reducing light reflection differences related to a data connection structure (e.g., a bezel reduction data connection structure). Hereinafter, a structure for reducing light reflection differences related to a data connection structure according to various aspects of the present invention will be described in detail with reference to Figures 11 to 15 A structure for reducing light reflection differences related to a data connection structure according to various aspects of the present invention will be described in detail.

[0311] Figure 11 Illustrates an exemplary structure (light reflection difference reduction structure) capable of reducing reflected light differences related to a bezel reduction data connection structure in a display panel 110 according to various aspects of the present invention. Figures 12 to 14 Illustrates an exemplary shielding structure disposed in a first opening region OA1 of a first metal layer ML1 in a display panel 110 according to various aspects of the present invention. Figure 15 Illustrates an exemplary shielding structure disposed in a second opening region OA2 of a second metal layer ML2 of a display panel 110 according to various aspects of the present invention.

[0312] Similar to Figure 8 is an enlarged plan view of a region 600 configured with a bezel reduction data connection structure. Figure 11 is a cross-sectional view of a region 1110 including a first opening region OA1 of a first metal layer ML1 including Figure 6 of a display panel 110 according to various aspects of the present invention. Figure 12 and Figure 11 Illustrate other exemplary shielding structures of a first opening region OA1 of a first metal layer ML1. Figure 13 and 14 Illustrate other exemplary shielding structures of a first opening region OA1 of a first metal layer ML1. Figure 15 is a cross-sectional view of a region 1120 including a second opening region OA2 of a second metal layer ML2 including Figure 11 of a display panel 110 according to various aspects of the present invention. In the following description, for the sake of simplicity, those discussions substantially the same as the discussions of Figures 8 to 10 will be omitted. Therefore, the discussion will focus on different features.

[0313] Referring to Figures 11 to 15 , in one or more aspects, the display device 100 may include a substrate 111, a first signal line HLIA1 (also referred to as a first connection line), a second signal line VLIA1 (also referred to as a second connection line), a first power line HLIA1_DC (also referred to as a first metal pattern), and a second power line VLIA1_DC (also referred to as a second metal pattern).

[0314] The first signal line HLIA1 may be disposed on the substrate 111. The first signal line HLIA1 may extend in a first direction (e.g., a row direction or a horizontal direction). The first signal line HLIA1 may be disposed in an active area AA where an image is allowed to be displayed.

[0315] The second signal line VLIA1 may be disposed on the substrate 111. The second signal line VLIA1 may extend in a second direction different from the first direction (e.g., a column direction or a vertical direction). All or at least a part of the second signal line VLIA1 may be disposed in the active area AA.

[0316] For example, the first signal line HLIA1 may be the first connection line HLIA1, and the second signal line VLIA1 may be the second signal line VLIA1.

[0317] The first signal line HLIA1 and the second signal line VLIA1 may be electrically connected.

[0318] The first power line HLIA1_DC may include the same first metal as the first signal line HLIA1 and may be disposed in the same row as the first signal line HLIA1. The first power line HLIA1_DC may be disposed such that the first power line HLIA1_DC is disconnected or separated from the first signal line HLIA1.

[0319] The second power line VLIA1_DC may include the same second metal as the second signal line VLIA1 and may be disposed in the same column as the second signal line VLIA1. The second power line VLIA1_DC may be disposed such that the second power line VLIA1_DC is disconnected or separated from the second signal line VLIA1.

[0320] The first power line HLIA1_DC may be the first metal pattern HLIA1_DC. The second power line VLIA1_DC may be the second metal pattern VLIA1_DC.

[0321] The first power line HLIA1_DC may extend in the first direction. The second power line VLIA1_DC may extend in the second direction.

[0322] The first power line HLIA1_DC and the second power line VLIA1_DC may be a low power supply voltage line VSSL to which a low power supply voltage VSS, which is the second common voltage, is applied.

[0323] The first signal line HLIA1 and the second signal line VLIA1 may be a first connection line HLIA1 and a second connection line VLIA1 electrically connected to the first data line DL1, respectively. The first power line HLIA1_DC and the second power line VLIA1_DC may be a low power supply voltage line VSSL to which a low power supply voltage VSS, which is the second common voltage, is applied.

[0324] For example, a voltage level may be applied to the first signal line HLIA1 and the second signal line VLIA1 in accordance with at least one or more frames or a signal that varies over time (e.g., a data voltage), and a voltage level that does not vary in accordance with at least one or more frames or a power signal that does not change over time (e.g., a low power supply voltage VSS) may be applied to the first power line HLIA1_DC and the second power line VLIA1_DC.

[0325] The first signal line HLIA1 may be disposed in the first metal layer ML1, and the second signal line VLIA1 may be disposed in the second metal layer ML2. For example, relative to the substrate 111, the second signal line VLIA1 may be placed or disposed higher (or farther) than the first signal line HLIA1. That is, the second signal line VLIA1 may be located or disposed above the first signal line HLIA1.

[0326] Referring to Figures 12 to 14 , in one or more aspects, the display device 100 may further include a first shielding pattern SHD1 overlapping with a first opening region OA1 that is disconnected from the first signal line HLIA1 and the first power line HLIA1_DC. The first opening region OA1 may be a region located between the first signal line HLIA1 and the first power line HLIA1_DC. The first signal line HLIA1 and the first power line HLIA1_DC may be separated from each other and disposed in the first metal layer ML1. In this case, the first opening region OA1 may be a region where the first metal layer ML1 is disconnected, broken, or cut. At least a portion of the first shielding pattern SHD1 may overlap with the first opening region OA1.

[0327] Referring to Figures 12 to 14 , the first signal line HLIA1 and the first power line HLIA1_DC may be disposed in the first metal layer ML1, and the first shielding pattern SHD1 may be disposed in at least one of the second metal layer ML2 and the pixel electrode layer PEL.

[0328] Referring to Figure 15, in one or more aspects, the display device 100 may further include a second shielding pattern SHD2 overlapping a second opening region OA2 where the second signal line VLIA1 and the second power supply line VLIA1_DC are disconnected. The second opening region OA2 may be an area located between the second signal line VLIA1 and the second power supply line VLIA1_DC. The second signal line VLIA1 and the second power supply line VLIA1_DC may be separated from each other and disposed in the second metal layer ML2. In this case, the second opening region OA2 may be an area where the second metal layer ML2 is disconnected, broken, or cut off. At least a portion of the second shielding pattern SHD2 may overlap the second opening region OA2.

[0329] Referring Figure 15 , the second signal line VLIA1 and the second power supply line VLIA1_DC may be disposed in the second metal layer ML2, and the second shielding pattern SHD2 may be disposed in the pixel electrode layer PEL.

[0330] As Figure 12 shown, the metal pattern disposed on the first planarization layer 331 may be a data line DL3 or another vertical line. For example, the another vertical line may be a first common driving voltage line VDDL for transmitting the first common driving voltage VDD, but various aspects of the present invention are not limited thereto.

[0331] Hereinafter, the display panel 110 having a light reflection difference reduction structure related to a bezel-reduced data connection structure according to various aspects of the present invention will be described in more detail.

[0332] Referring Figure 11 , in one or more aspects, the display panel 110 may include a substrate 111 having an active area AA and a non-active area NA, a first data pad DP1, and a first data line DL1.

[0333] The active area AA of the display panel 110 may include a plurality of sub-pixels SP. The non-active area NA may be located or disposed outside the active area AA. The non-active area NA may include a pad area PA. The first data pad DP1 may be disposed in the pad area PA. The first data line DL1 may be located or disposed in the active area AA. The first data line DL1 may extend in the column direction, and a data voltage may be applied to the first data line DL1.

[0334] The display panel 110 according to various aspects of the present invention may have a bezel-reduced data connection structure. The display panel 110 may include a first connection line HLIA1 and a second connection line VLIA1 electrically connected to the first data line DL1.

[0335] The first connection line HLIA1 can be electrically connected to the first data line DL1 and extends in the row direction. The second connection line VLIA1 can electrically connect the first connection line HLIA1 to the first data pad DP1 and extends in the column direction.

[0336] The first connection line HLIA1 can be located or disposed in the active area AA that allows an image to be displayed. All or at least a part of the second connection line VLIA1 can be disposed in the active area AA. By applying these configurations, since all or most of the data connection structure can be not disposed in the non-active area NA, the size of the border can be significantly reduced.

[0337] The first data line DL1 can be disposed in the second metal layer ML2. The first connection line HLIA1 can be located or disposed in the first metal layer ML1, and the second connection line VLIA1 can be located or disposed in the second metal layer ML2 different from the first metal layer ML1.

[0338] According to this configuration, a horizontal line (such as the first connection line, the first metal pattern, etc.) extending in the horizontal direction (row direction) can be disposed in the first metal layer ML1, and a vertical line (such as the second connection line, the second metal pattern, etc.) extending in the vertical direction (column direction) can be disposed in the second metal layer ML2.

[0339] Spaced apart from the substrate 111, the second metal layer ML2 can be placed or disposed higher than the first metal layer ML1. For example, the first metal layer ML1 can be the first source-drain metal layer, and the second metal layer ML2 can be the second source-drain metal layer farther from the substrate than the first metal layer ML1.

[0340] In one or more aspects, in relation to the border-reducing data connection structure, the display panel 110 can further include: a first metal pattern HLIA1_DC, which is separated from the first connection line HLIA1, extends in the row direction, and is disposed in the same row as the first connection line HLIA1; and a second metal pattern VLIA1_DC, which is separated from the second connection line VLIA1, extends in the column direction, and is disposed in the same column as the second connection line VLIA1.

[0341] For example, the first metal pattern HLIA1_DC can be located or disposed in the first metal layer ML1. The second metal pattern VLIA1_DC can be located or disposed in the second metal layer ML2.

[0342] Since the first metal pattern HLIA1_DC and the first connection line HLIA1 are set to have the same shape and arrangement, and the second metal pattern VLIA1_DC and the second connection line VLIA1 are set to have the same shape and arrangement, the display panel 110 can have the advantage of reducing display artifacts such as image anomalies, brightness differences, color differences, and the like.

[0343] In one aspect, the first metal pattern HLIA1_DC and the second metal pattern VLIA1_DC can be electrically floating.

[0344] In another aspect, the low power supply voltage VSS, which is the second common driving voltage, can be applied to the first metal pattern HLIA1_DC and the second metal pattern VLIA1_DC.

[0345] The horizontal metal pattern including the first metal pattern HLIA1_DC and the vertical metal pattern including the second metal pattern VLIA1_DC can be configured as a mesh pattern in the active region AA. The horizontal metal pattern and the vertical metal pattern can be signal transmission paths for the low power supply voltage VSS in the active region AA. The horizontal metal pattern and the vertical metal pattern can supply the low power supply voltage VSS to a plurality of sub-pixels distributed in the active region AA. Arranging the horizontal metal pattern and the vertical metal pattern in a mesh shape can mean that the total width of the signal transmission path for the low power supply voltage VSS can be enlarged, and the resistance of the signal transmission path for the low power supply voltage VSS can be reduced. Thereby, the voltage drop of the low power supply voltage VSS can be reduced, and the transmission characteristics of the low power supply voltage VSS can be significantly improved.

[0346] In one or more aspects, the display panel 110 can include a low power supply voltage line VSSL (see Figure 2 ) for supplying the low power supply voltage VSS corresponding to the common driving voltage to a plurality of sub-pixels SP.

[0347] The low power supply voltage line VSSL can be configured to include the horizontal metal pattern including the first metal pattern HLIA1_DC and the vertical metal pattern including the second metal pattern VLIA1_DC. The horizontal metal pattern and the vertical metal pattern can cross each other to form a power supply line structure in a mesh pattern. The horizontal metal pattern and the vertical metal pattern can be electrically connected to each other.

[0348] In one or more aspects, each of the plurality of sub-pixels SP can include a light-emitting element ED, which includes a pixel electrode PE, an intermediate layer EL, and a common electrode CE. The first metal pattern HLIA1_DC and the second metal pattern VLIA1_DC can be electrically connected to the common electrode CE to which the low power supply voltage VSS is applied. The low power supply voltage line VSSL can be electrically connected to at least one of the first metal pattern HLIA1_DC and the second metal pattern VLIA1_DC.

[0349] In addition, a low power supply voltage VSS as a signal having a constant voltage level may be applied to the first metal pattern HLIA1_DC and the second metal pattern VLIA1_DC.

[0350] In one or more aspects, the display panel 110 may include a third connection line HLIA2 and a fourth connection line VLIA2 electrically connected to the second data line DL2 as a data connection structure of the second data line DL2.

[0351] The third connection line HLIA2 may be electrically connected to the second data line DL2 and extend in the row direction. The fourth connection line VLIA2 may electrically connect the third connection line HLIA2 to the second data pad DP2 and extend in the column direction.

[0352] The third connection line HLIA2 may be disposed in or at the active area AA configured to display an image. All or at least a part of the fourth connection line VLIA2 may be disposed in or at the active area AA. By applying these configurations, the border size required for the data connection structure can be reduced.

[0353] The third connection line HLIA2 may be disposed in the first metal layer ML1. The fourth connection line VLIA2 may be disposed in a second metal layer ML2 different from the first metal layer ML1.

[0354] In one or more aspects, in relation to the border-reduced data connection structure, the display panel 110 may further include: a third metal pattern HLIA2_DC, which is separated from the third connection line HLIA2, extends in the row direction, and is disposed in the same row as the third connection line HLIA2; and a fourth metal pattern VLIA2_DC, which is separated from the fourth connection line VLIA2, extends in the column direction, and is disposed in the same column as the fourth connection line VLIA2.

[0355] The third metal pattern HLIA2_DC may be disposed in the first metal layer ML1. The fourth metal pattern VLIA2_DC may be disposed in the second metal layer ML2.

[0356] Since the third metal pattern HLIA2_DC and the third connection line HLIA2 are set to the same shape and arrangement, and the fourth metal pattern VLIA2_DC and the fourth connection line VLIA2 are set to the same shape and arrangement, the display panel 110 may have the advantage of reducing display artifacts such as image anomalies, brightness differences, color differences, and the like.

[0357] In one aspect, the third metal pattern HLIA2_DC and the fourth metal pattern VLIA2_DC may be electrically floating.

[0358] In another aspect, a low power supply voltage VSS, which is a second common driving voltage, may be applied to the third metal pattern HLIA2_DC and the fourth metal pattern VLIA2_DC.

[0359] The horizontal metal pattern including the third metal pattern HLIA2_DC and the vertical metal pattern including the fourth metal pattern VLIA2_DC may be configured as a mesh pattern in the active region AA. The horizontal metal pattern and the vertical metal pattern may be signal transmission paths for the low power supply voltage VSS in the active region AA. The horizontal metal pattern and the vertical metal pattern may supply the low power supply voltage VSS to a plurality of sub-pixels distributed in the active region AA. Arranging the horizontal metal pattern and the vertical metal pattern in a mesh shape may mean that the total width of the signal transmission paths for the low power supply voltage VSS may be enlarged, and the resistance of the signal transmission paths for the low power supply voltage VSS may be reduced. Accordingly, the voltage drop of the low power supply voltage VSS may be reduced, and the transmission characteristics of the low power supply voltage VSS may be significantly improved.

[0360] In one or more aspects, the display panel 110 may include one or more low power supply voltage lines VSSL (see Figure 2 ) configured to supply a low power supply voltage VSS corresponding to a common driving voltage to a plurality of sub-pixels SP.

[0361] The low power supply voltage line VSSL may be electrically connected to the third metal pattern HLIA2_DC and the fourth metal pattern VLIA2_DC.

[0362] In one or more aspects, each of the plurality of sub-pixels SP may include a light-emitting element ED, which includes a pixel electrode PE, an intermediate layer EL, and a common electrode CE, and the third metal pattern HLIA2_DC and the fourth metal pattern VLIA2_DC may be electrically connected to the common electrode CE to which the low power supply voltage VSS is applied.

[0363] In one or more aspects, a low power supply voltage VSS, which is a signal having a constant voltage level, may be applied to the third metal pattern HLIA2_DC and the fourth metal pattern VLIA2_DC.

[0364] The display panel 110 according to multiple aspects of the present invention may include a light reflection difference reduction structure related to a border reduction data connection structure.

[0365] The light reflection difference reduction structure related to the border reduction data connection structure may be used to reduce the reflected light difference caused by the first opening region OA1 in the first metal layer ML1 and the second opening region OA2 in the second metal layer ML2.

[0366] The light reflection difference reduction structure related to the border reduction data connection structure may be referred to as a shielding structure.

[0367] Reference Figures 11 to 14 ,In one or more aspects, the display panel 110 may further include a first shielding pattern SHD1 overlapping with a first opening area OA1 in which the first metal pattern HLIA1_DC and the first connection line HLIA1 are separated from each other.

[0368] Reference Figure 12 and 13 ,The first shielding pattern SHD1 may be disposed in the pixel electrode layer PEL and overlap with the first opening area OA1 in which the first metal pattern HLIA1_DC and the first connection line HLIA1 are separated from each other.

[0369] Reference Figure 12 and 13 ,The first shielding pattern SHD1 may be disposed in the pixel electrode layer PEL and may be the pixel electrode PE in the light-emitting element ED or may include the same material as the pixel electrode PE. For example, the first shielding pattern SHD1 may include the same pixel electrode material as the pixel electrode PE.

[0370] Reference Figure 12 and 13 ,The first metal pattern HLIA1_DC and the first connection line HLIA1 may be disposed in the first metal layer ML1, and the pixel electrode layer PEL may be a metal layer and may be disposed higher than the first metal layer ML1. That is, the pixel electrode layer PEL may be farther from the substrate than the first metal layer ML1.

[0371] Reference Figure 14 ,In one aspect, according to the position of the first opening area OA1 in which the first metal pattern HLIA1_DC and the first connection line HLIA1 are separated from each other in the display panel 110, the first shielding pattern SHD1 may be a metal pattern VLP disposed in the second metal layer ML2. The first opening area OA1 may be an area located between the first metal pattern HLIA1_DC and the first connection line HLIA1. The first metal pattern HLIA1_DC and the first connection line HLIA1 may be separated from each other and disposed in the first metal layer ML1. In this case, the first opening area OA1 may be an area where the first metal layer ML1 is disconnected, broken, or cut off. At least a part of the first shielding pattern SHD1 may overlap with the first opening area OA1.

[0372] Reference Figure 14 ,The first shielding pattern SHD1 may be disposed in the same metal layer as a vertical line extending in the column direction. This vertical line may include the first data line DL1, the second connection line VLIA1, the first common driving voltage line VDDL, etc.

[0373] In another aspect, according to the position of the first opening region OA1 where the first metal pattern HLIA1_DC and the first connection line HLIA1 are separated from each other in the display panel 110, the first shielding pattern SHD1 may include the metal pattern VLP in the second metal layer ML2 and all of the metal patterns provided in the pixel electrode layer PEL. The metal patterns provided in the pixel electrode layer PEL may include all of the pixel electrodes PE and the pixel electrode material patterns.

[0374] The first opening region OA1 where the first metal pattern HLIA1_DC and the first connection line HLIA1 are separated from each other may be one of the plurality of first opening regions OA1 located or provided in the first metal layer ML1. The plurality of first shielding patterns SHD1 may be provided such that the plurality of first shielding patterns SHD1 overlap with the plurality of first opening regions OA1 in the first metal layer ML1.

[0375] As described above, referring to Figures 11 to 15 and Figure 7 , the first opening region OA1 of the first metal layer ML1 may exist at the boundary between the first region (region A) and the second region (region B) among the three regions (A, B, and C) defined in the active region AA by reducing the data connection structure through the border.

[0376] Therefore, the plurality of first shielding patterns SHD1 overlapping with the plurality of first opening regions OA1 existing in the first metal layer ML1 may be provided in the boundary direction (e.g., the diagonal direction) between the first region (region A) and the second region (region B) extending at a predetermined (consistent) angle with respect to the row direction or the column direction. The plurality of first shielding patterns SHD1 may be provided at a predetermined angle with respect to the column direction or the row direction. Therefore, the plurality of first shielding patterns SHD1 may be positioned along and aligned with the first diagonal line SLT_DL.

[0377] Referring to Figure 11 and 15 , in one or more aspects, the display panel 110 may further include a second shielding pattern SHD2 overlapping with a second opening region OA2 where the second metal pattern VLIA1_DC and the second connection line VLIA1 are separated from each other. The second opening region OA2 may be the region between the second metal pattern VLIA1_DC and the second connection line VLIA1. The second metal pattern VLIA1_DC and the second connection line VLIA1 may be separated from each other and provided in the second metal layer ML2. In this case, the second opening region OA2 may be the region where the second metal layer ML2 is disconnected, broken, or cut off. At least a part of the second shielding pattern SHD2 may overlap with the second opening region OA2.

[0378] Referring to Figure 15, the second shielding pattern SHD2 may include a metal pattern disposed in the pixel electrode layer PEL. Such a metal pattern disposed in the pixel electrode layer PEL may be the pixel electrode PE or may include the same material as the pixel electrode PE. For example, the second shielding pattern SHD2 may include the same pixel electrode material as the pixel electrode PE.

[0379] The second opening region OA2 where the second metal pattern VLIA1_DC and the second connection line VLIA1 are separated from each other may be one of a plurality of second opening regions OA2 located or disposed in the second metal layer ML2. A plurality of second shielding patterns SHD2 may be arranged such that the plurality of second shielding patterns SHD2 overlap with the plurality of second opening regions OA2 in the second metal layer ML2.

[0380] Referring to Figures 11 to 15 and Figure 7 , the first opening region OA1 of the first metal layer ML1 and the second opening region OA2 of the second metal layer ML2 may be present at the boundary between the second region (region B) and the third region (region C) among the three regions (A, B, and C) defined in the active region AA by reducing the data connection structure through the border.

[0381] Therefore, a plurality of second shielding patterns SHD2 overlapping with the plurality of second opening regions OA2 present in the second metal layer ML2 may be arranged in the boundary direction (e.g., diagonal direction) between the second region (region B) and the third region (region C) extending at a predetermined (consistent) angle with respect to the row direction or the column direction. The plurality of second shielding patterns SHD2 may be arranged at a predetermined angle with respect to the column direction or the row direction. Therefore, the plurality of second shielding patterns SHD2 may be positioned along the second diagonal line SLT_LIA and aligned with the second diagonal line SLT_LIA.

[0382] Referring to Figure 3 The first metal layer ML1 and the second metal layer ML2 in the display panel 110 will be briefly described.

[0383] In the display panel 110, a horizontal line extending in the horizontal direction (row direction) may be provided in the first metal layer ML1, and a vertical line extending in the vertical direction (column direction) may be provided in the second metal layer ML2.

[0384] Referring to Figure 3 , each of the plurality of sub-pixels SP may include a light-emitting element ED and two or more transistors (TFT1 and TFT2). The two or more transistors (TFT1 and TFT2) may include source electrodes (E1b and E2b) and drain electrodes (E1c and E2c).

[0385] The source electrodes (E1b and E2b) and the drain electrodes (E1c and E2c) may include the first metal in the first connection line HLIA1 and the first metal pattern HLIA1_DC, or may include the metal layer in which the first connection line HLIA1 and the first metal pattern HLIA1_DC are provided. The first metal may be the metal constituting the first metal layer ML1. The first connection line HLIA1 and the first metal pattern HLIA1_DC may be included in the horizontal line. As described above, the first connection line HLIA1 and the first metal pattern HLIA1_DC may be provided in the first metal layer ML1 together with the source electrodes (E1b and E2b) and the drain electrodes (E1c and E2c). During the panel manufacturing process, the first connection line HLIA1 and the first metal pattern HLIA1_DC may be formed together when forming the source electrodes (E1b and E2b) and the drain electrodes (E1c and E2c). Therefore, no separate process needs to be added to form the first connection line HLIA1 and the first metal pattern HLIA1_DC.

[0386] Referring to Figures 11 to 15 and Figure 3 , the light-emitting element ED may include a pixel electrode PE, an intermediate layer EL, and a common electrode CE, and the relay electrode RE may electrically connect the pixel electrode PE to the source electrode E1b or the drain electrode E1c of the first transistor TFT1 among two or more transistors (TFT1 and TFT2).

[0387] The relay electrode RE may include the second metal in the second connection line VLIA1 and the second metal pattern VLIA1_DC, or may include the metal layer in which the second connection line VLIA1 and the second metal pattern VLIA1_DC are provided. The second metal may be the metal constituting the second metal layer ML2. The second connection line VLIA1 and the second metal pattern VLIA1_DC may be included in the vertical line. As described above, the second connection line VLIA1 and the second metal pattern VLIA1_DC may be provided in the second metal layer ML2 together with the relay electrode RE. During the panel manufacturing process, the second connection line VLIA1 and the second metal pattern VLIA1_DC may be formed together when forming the relay electrode RE. Therefore, no separate process needs to be added to form the second connection line VLIA1 and the second metal pattern VLIA1_DC.

[0388] The first data line DL1, which is one of the vertical lines, may also be provided in the second metal layer ML2.

[0389] The display device according to various aspects of the present invention is described below.

[0390] According to various aspects of the present invention, a display device may be provided, including: a substrate including a display area having a plurality of sub-pixels; a first data line disposed in the display area and extending in a column direction; a first connection line disposed in the display area, electrically connected to the first data line and extending in a row direction; a second connection line disposed in the display area and extending in the column direction; a first metal pattern separated from the first connection line and extending in the row direction; and a second metal pattern separated from the second connection line and extending in the column direction.

[0391] In one or more aspects, the first connection line may be disposed in the display area. All or at least a part of the second connection line may be disposed in the display area.

[0392] In one or more aspects, the first connection line and the first metal pattern may be disposed in a first metal layer. The second connection line and the second metal pattern may be disposed in a second metal layer different from the first metal layer.

[0393] In one or more aspects, the second metal layer may be disposed farther from the substrate than the first metal layer.

[0394] In one or more aspects, the display device may further include a low power voltage line configured to supply a low power voltage to the plurality of sub-pixels. The low power voltage line may be electrically connected to the first metal pattern and the second metal pattern. For example, the low power voltage may correspond to a common driving voltage.

[0395] In one or more aspects, each of the plurality of sub-pixels may include a light-emitting element including a pixel electrode, an intermediate layer, and a common electrode. The first metal pattern and the second metal pattern may be electrically connected to the common electrode.

[0396] In one or more aspects, the display device may further include: a first opening area located between the first metal pattern and the first connection line; and a first shielding pattern overlapping with the first opening area.

[0397] In one or more aspects, the first shielding pattern may be the pixel electrode or include the same material as the pixel electrode.

[0398] In one or more aspects, the first shielding pattern may be a metal pattern disposed in the second metal layer. For example, the first shielding pattern may be a metal pattern disposed in the second metal layer in which the second connection line and the second metal pattern are disposed. The first shielding pattern may be a metal pattern disposed in the metal layer in which the second connection line and the second metal pattern are disposed.

[0399] In one or more aspects, the first shielding pattern may be disposed in the same metal layer as the vertical line extending in the column direction.

[0400] In one or more aspects, the first opening region may be one of a plurality of first opening regions disposed in the first metal layer. For example, the first opening region may be one of a plurality of first opening regions disposed in the metal layer in which the first connection line and the first metal pattern are disposed.

[0401] In one or more aspects, a plurality of first shielding patterns including the first shielding pattern may overlap with the plurality of first opening regions.

[0402] In one or more aspects, the plurality of first shielding patterns may be disposed at a predetermined angle (e.g., along an oblique line direction) with respect to the column direction or the row direction.

[0403] In one or more aspects, the display device may further include: a second opening region located between the second metal pattern and the second connection line; and a second shielding pattern overlapping with the second opening region.

[0404] In one or more aspects, each of the plurality of sub-pixels may include a light-emitting element, the light-emitting element may include a pixel electrode, an intermediate layer, and a common electrode, and the second shielding pattern may be the pixel electrode or include the same material as the pixel electrode.

[0405] In one or more aspects, the second opening region may be one of a plurality of second opening regions disposed in the second metal layer. For example, the second opening region may be one of a plurality of second opening regions disposed in the metal layer in which the second connection line and the second metal pattern are disposed.

[0406] In one or more aspects, a plurality of second shielding patterns including the second shielding pattern may overlap with the plurality of second opening regions.

[0407] In one or more aspects, the plurality of second shielding patterns may be disposed at a predetermined angle (e.g., in an oblique line direction) with respect to the column direction or the row direction.

[0408] In one or more aspects, the first data line may be disposed in a metal layer. For example, the first data line may be disposed in a metal layer (second metal layer) in which the second connection line and the second metal pattern are disposed.

[0409] In one or more aspects, each of the plurality of sub-pixels may include a light-emitting element and two or more transistors. The light-emitting element may include a pixel electrode, an intermediate layer, and a common electrode. Each of the two or more transistors may include a source or a drain.

[0410] In one or more aspects, the corresponding source or drain included in the two or more transistors may include a metal layer. For example, the corresponding source or drain included in the two or more transistors may include a metal layer in which the first connection line and the first metal pattern are disposed.

[0411] In one or more aspects, the display device may further include a connection electrode (relay electrode) configured to electrically connect the pixel electrode to a source or a drain of a first transistor among the two or more transistors.

[0412] In one or more aspects, the connection electrode may include a metal layer. For example, the connection electrode may include a metal layer in which the second connection line and the second metal pattern are disposed.

[0413] In one or more aspects, the substrate may include a non-display area outside the display area. The non-display area may include a pad area having pads. The second connection line may electrically connect the first connection line to the pad.

[0414] In one or more aspects, the display area may include: a first area in which no horizontal connection line extending in the row direction and no vertical connection line extending in the column direction are provided; a second area including the horizontal connection line; and a third area including the vertical connection line. The horizontal connection line may include the first connection line (first signal line), and the vertical connection line may include the second connection line (second signal line).

[0415] In one or more aspects, the display device may further include a first opening area between the first metal pattern and the first connection line. The first opening area may be present at a boundary between the first area and the second area.

[0416] In one or more aspects, the display device may further include a second opening area between the second metal pattern and the second connection line. The first opening area and the second opening area may be present at a boundary between the second area and the third area.

[0417] In one or more aspects, the first metal pattern may be set to the same shape as the first connection line. The second metal pattern may be set to the same shape as the second connection line.

[0418] In one or more aspects, the low power supply voltage line may be configured to include a horizontal metal pattern including the first metal pattern and a vertical metal pattern including the second metal pattern.

[0419] In one or more aspects, the display device may further include: a third connection line provided in the first metal layer; a fourth connection line provided in the second metal layer; a third metal pattern separated from the third connection line, extending in the row direction, and provided in the same row as the third connection line; and a fourth metal pattern separated from the fourth connection line, extending in the column direction, and provided in the same column as the fourth connection line.

[0420] In one or more aspects, a display device may include: a substrate; a first signal line provided on the substrate and extending in a first direction; and a first power supply line including the same first metal as the first signal line and separated from the first signal line. The display device may further include: a second signal line provided on the substrate and extending in a second direction different from the first direction; and a second power supply line including the same second metal as the second signal line and separated from the second signal line.

[0421] In one or more aspects, the first signal line may be provided in a display area configured to display an image. All or a part of the second signal line may be provided in the display area.

[0422] In one or more aspects, the first signal line may be electrically connected to the second signal line.

[0423] In one or more aspects, the first power supply line may extend in the first direction. The second power supply line may extend in the second direction.

[0424] In one or more aspects, a signal whose voltage level varies with time (e.g., according to at least one or more frames) may be applied to the first signal line and the second signal line.

[0425] In one or more aspects, a power supply signal whose voltage level does not change with time (e.g., according to at least one or more frames) may be applied to the first power supply line and the second power supply line.

[0426] In one or more aspects, the second signal line may be disposed farther from the substrate than the first signal line.

[0427] In one or more aspects, the display device may further include a first shielding pattern overlapping with a first opening area, wherein in the first opening area, the first signal line and the first power line are disconnected.

[0428] In one or more aspects, the display device may further include a second shielding pattern overlapping with a second opening area, wherein in the second opening area, the second signal line and the second power line are disconnected.

[0429] In one or more aspects, the first signal line may be disposed in a display area configured to display an image, and all or a part of the second signal line may be disposed in the display area.

[0430] In one or more aspects, the first signal line may be electrically connected to the second signal line.

[0431] In one or more aspects, the first power line may extend along the first direction, and the second power line may extend along the second direction.

[0432] In one or more aspects, the first signal line and the first power line may be disposed in a first metal layer. The second signal line and the second power line may be disposed in a second metal layer different from the first metal layer.

[0433] In one or more aspects, the display device may further include a first shielding pattern overlapping with a first opening area between the first signal line and the first power line. The first shielding pattern may be disposed in at least one of the second metal layer and the layer in which the pixel electrode is disposed.

[0434] In one or more aspects, the display device may further include a second shielding pattern overlapping with a second opening area between the second signal line and the second power line. The second shielding pattern may be disposed in the layer in which the pixel electrode is disposed.

[0435] In one or more aspects, a display device may include: a substrate including a display area having a plurality of sub-pixels; a first data line disposed in the display area and extending in a column direction; a first connection line disposed in the display area, electrically connected to the first data line, and extending in a row direction; a second connection line disposed in the display area, electrically connected to the first connection line, and extending in the column direction; and a first metal pattern separated from and collinear with the first connection line. At least one of the plurality of sub-pixels may overlap a position where the first connection line is connected to the second connection line.

[0436] According to various aspects described herein, a display device may be provided having a data connection structure capable of reducing a border size of a display panel.

[0437] According to various aspects, a display device may be provided having a border-reducing data connection structure capable of improving image quality.

[0438] According to various aspects, a display device may be provided having a border-reducing data connection structure capable of improving transmission performance of a common driving voltage.

[0439] According to various aspects, a display device may be provided having a border-reducing data connection structure capable of reducing a difference in reflected light.

[0440] According to various aspects, a display device and / or a display panel may be provided having a reduced weight by reducing a border size of the display panel by using an improved data connection structure.

[0441] The display device according to various aspects of the present invention may be applied to a mobile device, a video phone, a smart watch, a watch phone, a wearable device, a foldable device, a rollable device, a bendable device, a flexible device, a stretchable device, a curved device, a sliding device, a variable device, an electronic notebook, an e-book, a portable multimedia player (PMP), a personal digital assistant (PDA), an MP3 player, a mobile medical device, a desktop PC, a laptop PC, a netbook, a workstation, a navigation device, an in-vehicle navigation device, a vehicle display device, a vehicle device, a cinema device, a cinema display device, a television, a wallpaper device, a signage device, a gaming device, a notebook computer, a monitor, a camera, a camcorder, and household appliances, etc.

[0442] It will be apparent to those of ordinary skill in the art that various modifications and variations can be made in the present invention without departing from the scope of the invention. Accordingly, the invention is intended to cover modifications and variations that fall within the scope of the appended claims and their equivalents.

Claims

1. A display device, comprising: a substrate including a display area having a plurality of sub-pixels; a first data line disposed in the display area and extending in a column direction; a first connection line disposed in the display area, electrically connected to the first data line and extending in a row direction; a second connection line disposed in the display area and extending in the column direction; a first metal pattern separated from the first connection line and extending in the row direction; and a second metal pattern separated from the second connection line and extending in the column direction.

2. The display device according to claim 1, wherein the first connection line and the first metal pattern are disposed in a first metal layer, and the second connection line and the second metal pattern are disposed in a second metal layer different from the first metal layer.

3. The display device according to claim 2, wherein the second metal layer is disposed farther from the substrate than the first metal layer.

4. The display device according to claim 1, further comprising a low power supply voltage line configured to supply a low power supply voltage to the plurality of sub-pixels, wherein the low power supply voltage line is electrically connected to at least one of the first metal pattern and the second metal pattern.

5. The display device according to claim 1, wherein each of the plurality of sub-pixels includes a light-emitting element, and the light-emitting element includes a pixel electrode, an intermediate layer, and a common electrode, wherein the first metal pattern and the second metal pattern are electrically connected to the common electrode.

6. The display device according to claim 1, further comprising: a first opening area located between the first metal pattern and the first connection line; and a first shielding pattern overlapping with the first opening area.

7. The display device according to claim 6, wherein each of the plurality of sub-pixels includes a light-emitting element, and the light-emitting element includes a pixel electrode, an intermediate layer, and a common electrode, wherein the first shielding pattern is the pixel electrode or includes a material the same as that of the pixel electrode.

8. The display device according to claim 6, wherein the first shielding pattern is a metal pattern disposed in the metal layer in which the second connection line and the second metal pattern are disposed.

9. The display device according to claim 6, wherein the first shielding pattern is disposed in the same metal layer as a vertical line extending in the column direction.

10. A display device, comprising: a substrate; a first signal line disposed on the substrate and extending in a first direction; a first power supply line including the same first metal as the first signal line and separated from the first signal line; a second signal line disposed on the substrate and extending in a second direction different from the first direction; and a second power supply line including the same second metal as the second signal line and separated from the second signal line.

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