Air conditioning system

Abstract

An air conditioning system comprises a first bus, a second bus, a main control chip, a first alternating current coupling circuit and a second alternating current coupling circuit. And the first alternating current coupling circuit is electrically connected with the main control chip, the first bus and the second bus. And the second alternating current coupling circuit is electrically connected with the main control chip, the first bus and the second bus. The main control chip is configured to receive a first communication signal from the load, analyze the first communication signal, and receive the first communication signal under the condition that the first communication signal meets a first preset condition; and analyzing a second communication signal, and sending the second communication signal to the load under the condition that the second communication signal meets a second preset condition.

Description

Air conditioning system

[0001] This application claims priority to Chinese patent application No. 202310512637.8 filed on May 8, 2023, priority to Chinese patent application No. 202321090907.2 filed on May 8, 2023, and priority to Chinese patent application No. 202310512631.0 filed on May 8, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to the technical field of air conditioning equipment, and in particular to an air conditioning system. Background Art

[0003] With the continuous advancement of technology and the improvement of people's living standards, central air conditioning systems have become an indispensable feature of modern buildings and residences. Central air conditioning systems are highly efficient air control systems that provide comfortable indoor temperatures and air quality throughout the building. Central air conditioning systems use a home bus to communicate between indoor and outdoor units, between wired controllers and indoor units, and between outdoor units.

[0004] Summary of the Invention

[0005] An air conditioning system is provided, comprising a first bus, a second bus, and a communication circuit. The communication circuit is configured to be electrically connected to a load. The communication circuit comprises a main control chip, a first AC coupling circuit, and a second AC coupling circuit. The first AC coupling circuit is electrically connected to the main control chip, the first bus, and the second bus. The second AC coupling circuit is electrically connected to the main control chip, the first bus, and the second bus. The main control chip is configured to: receive a first communication signal from the load via the first AC coupling circuit, parse the first communication signal, and receive the first communication signal if the first communication signal meets a first preset condition; and generate a second communication signal, parse the second communication signal, and send the second communication signal to the load via the second AC coupling circuit if the second communication signal meets a second preset condition. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] FIG1 is a structural diagram of an air conditioning system according to some embodiments;

[0007] FIG2 is a circuit diagram of a communication loop according to some embodiments;

[0008] FIG3 is a circuit diagram of a signal analysis component according to some embodiments;

[0009] FIG4 is another circuit diagram of a communication loop according to some embodiments;

[0010] FIG5 is a circuit diagram of a first clamping circuit according to some embodiments;

[0011] FIG6 is a circuit diagram of yet another communication loop according to some embodiments;

[0012] FIG7 is a circuit diagram of a first anti-backflow circuit according to some embodiments;

[0013] FIG8 is a circuit diagram of a balancing circuit according to some embodiments;

[0014] FIG9 is a circuit diagram of yet another communication loop according to some embodiments;

[0015] FIG10 is a circuit diagram of yet another communication loop according to some embodiments;

[0016] FIG11 is a circuit diagram of yet another communication loop according to some embodiments;

[0017] FIG12 is a circuit diagram of yet another communication loop according to some embodiments;

[0018] FIG13 is a circuit diagram of yet another communication loop according to some embodiments;

[0019] FIG14 is a circuit diagram of a main control chip according to some embodiments;

[0020] FIG15 is a circuit diagram of a first output subassembly according to some embodiments;

[0021] FIG16 is a circuit diagram of another first output subassembly according to some embodiments;

[0022] FIG17 is a circuit diagram of yet another first output subassembly according to some embodiments;

[0023] FIG18 is a circuit diagram of yet another first output subassembly according to some embodiments;

[0024] FIG19 is a circuit diagram of yet another first output subassembly according to some embodiments;

[0025] FIG20 is a circuit diagram of another main control chip according to some embodiments;

[0026] FIG21 is a circuit diagram of another main control chip according to some embodiments;

[0027] FIG22 is a circuit diagram of another main control chip according to some embodiments;

[0028] FIG23 is a circuit diagram of another air conditioning system according to some embodiments;

[0029] FIG24 is a circuit diagram of a second controller and a load according to some embodiments;

[0030] FIG25 is a circuit diagram of another second controller and a load according to some embodiments;

[0031] FIG26 is a circuit diagram of a third clamping circuit according to some embodiments;

[0032] FIG27 is a circuit diagram of yet another second controller and a load according to some embodiments;

[0033] FIG28 is a circuit diagram of yet another second controller and a load according to some embodiments;

[0034] FIG29 is a circuit diagram of a fourth clamping circuit according to some embodiments;

[0035] FIG30 is a circuit diagram of a fifth clamping circuit according to some embodiments;

[0036] FIG31 is a circuit diagram of yet another second controller and a load according to some embodiments. DETAILED DESCRIPTION

[0037] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0038] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0039] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly specifying the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of some embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0040] When describing some embodiments, the word "connected" and its derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" can mean fixed connection, detachable connection, or integration; it can be directly connected or indirectly connected through an intermediate medium.

[0041] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0042] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0043] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0044] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0045] Typically, air conditioning systems (such as central air conditioning systems) use a home bus to communicate between indoor and outdoor units, between wired controllers and indoor units, and between outdoor units. The air conditioning system's communication circuit includes a communication chip, which is a communication protocol conversion chip.

[0046] However, the indoor unit, outdoor unit and wired controller in the air-conditioning system all need to communicate with each other. Therefore, if communication chips are provided in the indoor unit, outdoor unit and wired controller, the cost of the air-conditioning system will increase.

[0047] Based on this, some embodiments of the present disclosure provide an air conditioning system 1000. Air conditioning system 1000 includes a main control chip connected to a communication circuit of air conditioning system 1000. In air conditioning system 1000, the parsing function of the communication chip is integrated into the main control chip, enabling communication between indoor and outdoor units and a wired controller within the communication circuit of air conditioning system 1000 without requiring a communication chip.

[0048] It should be noted that parsing can be understood as the interpretation of signals, that is, converting one form of communication protocol into another form of protocol conversion.

[0049] In some embodiments, as shown in Figures 1 and 2, an air conditioning system 1000 includes at least one indoor unit 1001, at least one outdoor unit 1002, at least one wired controller 1003, a first controller 1004, a first bus A, and a second bus B. The first controller 1004 includes a communication circuit 1005, which includes a main control chip 1.

[0050] The main control chip 1 is provided in at least one of at least one indoor unit 1001, at least one outdoor unit 1002, and at least one wired controller 1003. The at least one indoor unit 1001, at least one outdoor unit 1002, and at least one wired controller 1003 are communicatively connected via a first bus A and a second bus B. For example, the first bus A and the second bus B are home buses (HB).

[0051] It should be noted that FIG1 is merely an example of the main control chip 1 being disposed in the wired controller 1003, and this should not be considered as limiting the embodiments of the present disclosure. In some embodiments, the main control chip 1 may also be disposed in the indoor unit 1001, or the main control chip 1 may also be disposed in the outdoor unit 1002.

[0052] The air conditioning system 1000 provided in some embodiments of the present disclosure may be an air conditioning system consisting of one indoor unit and one outdoor unit, or a multi-split air conditioning system. For ease of description, different types of air conditioning systems are described using the air conditioning system shown in FIG1 as an example.

[0053] In some embodiments, as shown in FIG2 , the communication circuit 1005 further includes a first AC coupling circuit 2 and a second AC coupling circuit 3. For example, the first AC coupling circuit 2 is a signal receiving-side AC coupling circuit, i.e., the first AC coupling circuit 2 is located on the signal receiving side of the main control chip 1. The second AC coupling circuit 3 is a signal transmitting-side AC coupling circuit, i.e., the second AC coupling circuit 3 is located on the signal transmitting side of the main control chip 1.

[0054] The air conditioning system 1000 further includes a load 1006. The first bus A is electrically connected to one end of the load 1006, and the second bus B is electrically connected to the other end of the load 1006. In some embodiments, the load 1006 includes at least one of a device including the indoor unit 1001, the outdoor unit 1002, the wired controller 1003, or a centralized controller that supports differential communication.

[0055] The main control chip 1 includes a first port 11, a second port 12, a third port 13, and a fourth port 14. The first AC coupling circuit 2 includes a fifth port 21, a sixth port 22, a seventh port 23, and an eighth port 24. The second AC coupling circuit 3 includes a ninth port 31, a tenth port 32, an eleventh port 33, and a twelfth port 34.

[0056] The first port 11 and the second port 12 of the main control chip 1 are electrically connected to the fifth port 21 and the sixth port 22 of the first AC coupling circuit 2, respectively. The third port 13 and the fourth port 14 of the main control chip 1 are electrically connected to the ninth port 31 and the tenth port 32 of the second AC coupling circuit 3, respectively. The seventh port 23 and the eighth port 24 of the first AC coupling circuit 2 are electrically connected to the first bus A and the second bus B, respectively. The eleventh port 33 and the twelfth port 34 of the second AC coupling circuit 3 are electrically connected to the first bus A and the second bus B, respectively.

[0057] In some embodiments, as shown in Figure 3, the main control chip 1 also includes a signal analysis component 100, and the main control chip 1 is configured to: receive a first communication signal from the first AC coupling circuit 2, analyze the received first communication signal through the signal analysis component 100, and receive the first communication signal when the first communication signal meets a first preset condition.

[0058] For example, the first preset condition includes that the voltage of the first communication signal is any value between -5V and 5V.

[0059] In some embodiments, the main control chip 1 is further configured to: generate a second communication signal, parse the generated second communication signal through the signal parsing component 100, and transmit the second communication signal to the second AC coupling circuit 3 when the second communication signal meets a second preset condition.

[0060] For example, the second preset condition includes that the voltage of the second communication signal is any value between -5V and 5V.

[0061] It should be noted that the first preset condition and the second preset condition may be the same or different, and this disclosure does not limit this.

[0062] In some embodiments, as shown in FIG3 , the signal analysis component 100 includes: a first output subassembly 110, a second output subassembly 120, a first pin 130, and a second pin 140. The signal analysis component 100 is electrically connected to other components in the main control chip 1 via the first pin 130 and the second pin 140. The first output subassembly 110 is electrically connected to the first pin 130, and the second output subassembly 120 is electrically connected to the second pin 140.

[0063] For example, at least one of the first output subassembly 110 and the second output subassembly 120 acts on at least one corresponding one of the first pin 130 and the second pin 140 .

[0064] At least one of the first output subassembly 110 and the second output subassembly 120 includes a logic control component 150 and a level conversion circuit 160 .

[0065] It should be noted that FIG3 is an illustration of an example in which the first output subassembly 110 and the second output subassembly 120 respectively include a logic control component 150 and a level conversion circuit 160 , and it cannot be regarded as a limitation of the present disclosure.

[0066] The logic control element 150 includes a first control terminal K1, a second control terminal K2, and a third control terminal K3. The level conversion circuit 160 includes a first transistor Q1, a second transistor Q2, a third transistor Q3, a first resistor R1, and a second resistor R2.

[0067] The control electrode of the first transistor Q1 is electrically connected to the first control terminal K1, the first electrode of the first transistor Q1 is electrically connected to the second end of the first resistor R1, the second electrode of the first transistor Q1 is electrically connected to the output terminal OUT of the level conversion circuit 160, and the first end of the first resistor R1 is electrically connected to the first voltage terminal VCC of the level conversion circuit 160.

[0068] The control electrode of the second transistor Q2 is electrically connected to the second control terminal K2 , the first electrode of the second transistor Q2 is electrically connected to the output terminal OUT of the level conversion circuit 160 , and the second electrode of the second transistor Q2 is electrically connected to the second voltage terminal GND of the level conversion circuit 160 .

[0069] The control electrode of the third transistor Q3 is electrically connected to the third control terminal K3, the first electrode of the third transistor is electrically connected to the second end of the second resistor R2, the second electrode of the third transistor Q3 is electrically connected to the second voltage terminal GND of the level conversion circuit 160, and the first end of the second resistor R2 is electrically connected to the output terminal OUT of the level conversion circuit 160.

[0070] In some embodiments, the transistors (e.g., the first transistor Q1, the second transistor Q2, and the third transistor Q3) are NPN transistors. The first control signal of the NPN transistor has an on-level and is high, and the second control signal of the NPN transistor has an off-level and is low.

[0071] In some embodiments, the transistor is a PNP transistor, the first control signal of the PNP transistor has an on level and is low, and the second control signal of the PNP transistor has an off level and is high.

[0072] For example, as shown in FIG3 , the first transistor Q1 , the second transistor Q2 , and the third transistor Q3 are all NPN transistors. In this case, when the first transistor Q1 (or the second transistor Q2 ) is turned on, the first voltage terminal VCC (or the second voltage terminal GND) and the output terminal OUT can be considered as a wire.

[0073] If the first transistor Q1 is turned on and the second transistor Q2 is turned off, the output terminal OUT outputs the voltage of the first voltage terminal VCC. If the first transistor Q1 is turned off and the second transistor Q2 is turned on, the output terminal OUT outputs the voltage of the second voltage terminal GND.

[0074] In some embodiments, the logic control unit 150 is configured to output a first control signal having an on level to the first transistor Q1 , output a second control signal having an off level to the second transistor Q2 , and output a third control signal having an on level to the third transistor Q3 .

[0075] It is understood that the first control signal can control the first transistor Q1 to be turned on, the third control signal can control the third transistor Q3 to be turned on, and the second control signal can control the second transistor Q2 to be turned off. In this case, the first transistor Q1 and the third transistor Q3 are connected, and the voltage across the second resistor R2 is transmitted to the output terminal OUT.

[0076] In some embodiments, the voltage of the first voltage terminal VCC is 5V, the voltage of the second voltage terminal GND is 0V, and the resistance value of the first resistor R1 is the same as the resistance value of the second resistor R2. It can be understood that the voltage output by the output terminal OUT is the voltage across the second resistor R2. Therefore, when the resistance value of the first resistor R1 is the same as the resistance value of the second resistor R2, the voltage output by the output terminal OUT is 2.5V.

[0077] If the ratio of the resistance value of the first resistor R1 to the resistance value of the second resistor R2 is 4:1, the voltage outputted by the output terminal OUT is 1V.

[0078] It can be understood that the voltage output by the output terminal OUT is the voltage across the second resistor R2, and the voltage across the second resistor R2 is related to the ratio of the resistance value of the first resistor R1 to the resistance value of the second resistor R2. Therefore, by changing the ratio between the resistance value of the first resistor R1 and the resistance value of the second resistor R2, the voltage output by the output terminal OUT can be adjusted.

[0079] For ease of description, the three transistors in the second output subassembly 120 are referred to as a fourth transistor Q4, a fifth transistor Q5, and a sixth transistor Q6 to distinguish them from the first transistor Q1, the second transistor Q2, and the third transistor Q3 in the first output subassembly 110. The two resistors in the second output subassembly 120 are referred to as a third resistor R3 and a fourth resistor R4 to distinguish them from the first resistor R1 and the second resistor R2 in the first output subassembly 110.

[0080] In some embodiments, at least one of the first resistor R1 , the second resistor R2 , the third resistor R3 , and the fourth resistor R4 is an adjustable resistor.

[0081] In some embodiments, as shown in Figure 2, the first communication signal emitted by the load 1006 is transmitted to the seventh port 23 and the eighth port 24 of the first AC coupling circuit 2 via the first bus A and the second bus B. The first AC coupling circuit 2 receives the first communication signal and transmits the AC signal that meets the first preset condition via the fifth port 21 and the sixth port 22 of the first AC coupling circuit 2 to the first port 11 and the second port 12 of the main control chip 1, thereby transmitting it to the main control chip 1. The main control chip 1 parses the first communication signal.

[0082] In some embodiments, the main control chip 1 parses and calibrates the second communication signal, and transmits the second communication signal to the ninth port 31 and the tenth port 32 of the second AC coupling circuit 3 through the third port 13 and the fourth port 14. The second AC coupling circuit 3 receives the second communication signal and transmits the AC signal that meets the second preset condition to the first bus A and the second bus B via the eleventh port 33 and the twelfth port 34 of the second AC coupling circuit 3, so that the second communication signal is transmitted to the load 1006, completing the communication between the main control chip 1 and the load 1006.

[0083] For example, the main control chip 1 performs self-transmission and self-reception calibration on the signal.

[0084] In some embodiments, as shown in FIG. 2 , the first bus A is electrically connected to the seventh port 23 of the first AC coupling circuit 2 , and the second bus B is electrically connected to the eighth port 24 of the first AC coupling circuit 2 .

[0085] For example, a first communication signal emitted by the load 1006 is transmitted via the first bus A to the seventh port 23 of the first AC coupling circuit 2. The first AC coupling circuit 2 receives the first communication signal and transmits an AC signal that meets the first preset condition via the fifth port 21 to the first port 11 of the main control chip 1, thereby transmitting the AC signal to the main control chip 1. The main control chip 1 parses the first communication signal.

[0086] The main control chip 1 sends a second communication signal through the third port 13 and transmits the second communication signal to the tenth port 32 of the second AC coupling circuit 3. The second AC coupling circuit 3 receives the second communication signal and transmits an AC signal that meets the second preset condition to the second bus B through the twelfth port 34. The second communication signal is transmitted to the load 1006 via the second bus B, thereby completing the communication between the main control chip 1 and the load 1006.

[0087] In some embodiments, the first communication signal emitted by the load 1006 is transmitted to the eighth port 24 of the first AC coupling circuit 2 via the second bus B. The first AC coupling circuit 2 receives the first communication signal and transmits an AC signal that meets the first preset condition to the second port 12 of the main control chip 1 via the sixth port 22. The main control chip 1 receives the first communication information through the second port 12 and parses the first communication signal.

[0088] The main control chip 1 sends a second communication signal through the fourth port 14 and transmits the second communication signal to the ninth port 31 of the second AC coupling circuit 3. The second AC coupling circuit 3 receives the second communication signal and transmits an AC signal that meets the second preset condition to the first bus A through the eleventh port 33. The second communication signal is transmitted to the load 1006 via the first bus A, thereby completing the communication between the main control chip 1 and the load 1006.

[0089] It is understood that in some embodiments of the present disclosure, air conditioning system 1000 integrates the parsing function into main control chip 1, enabling main control chip 1 to perform the parsing function of the communication chip. Furthermore, by using multiple circuits to protect the pins of main control chip 1, the communication chip can be eliminated from air conditioning system 1000, thereby reducing the cost of the air conditioning system.

[0090] In some embodiments, as shown in FIG4 , the communication circuit 1005 further includes a first clamping circuit 4 and a second clamping circuit 5 . The first clamping circuit 4 is electrically connected to the main control chip 1 and the first AC coupling circuit 2 and is configured to clamp the voltage of the signals from the first port 11 and the second port 12 of the main control chip 1 to within a first preset range. The second clamping circuit 5 is electrically connected to the main control chip 1 and the second AC coupling circuit 3 and is configured to clamp the voltage of the signals from the third port 13 and the fourth port 14 of the main control chip 1 to within a second preset range. This protects the ports of the main control chip 1 and helps improve the operational stability of the main control chip 1.

[0091] For example, the first clamp circuit 4 includes a thirteenth port 41 , a fourteenth port 42 , a fifteenth port 43 , and a sixteenth port 44 . The second clamp circuit 5 includes a seventeenth port 51 , an eighteenth port 52 , a nineteenth port 53 , and a twentieth port 54 .

[0092] The thirteenth and fourteenth ports 41 and 42 of the first clamping circuit 4 are electrically connected to the first and second ports 11 and 12 of the main control chip 1, respectively. The fifteenth and sixteenth ports 43 and 44 of the first clamping circuit 4 are electrically connected to the fifth and sixth ports 21 and 22 of the first AC coupling circuit 2, respectively. The seventeenth and eighteenth ports 51 and 52 of the second clamping circuit 5 are electrically connected to the third and fourth ports 13 and 14 of the main control chip 1, respectively. The nineteenth and twentieth ports 53 and 54 of the second clamping circuit 5 are electrically connected to the ninth and tenth ports 31 and 32 of the second AC coupling circuit 3, respectively.

[0093] For example, the first clamping circuit 4 and the second clamping circuit 5 are Schottky diodes, or they may also be switching diodes.

[0094] In some embodiments, as shown in FIG5 , the first clamping circuit 4 includes a third diode D3 and a fourth diode D4. The communication circuit 1005 also includes a first signal line C1 and a second signal line C2. The first signal line C1 and the second signal line C2 are connecting lines between any two components in the communication circuit 1005 (e.g., the main control chip 1 and the first clamping circuit 4 ), and are configured to communicatively connect the two components to transmit signals between the two components.

[0095] The cathode of the third diode D3 is electrically connected to the first signal line C1 , the anode of the third diode D3 and the anode of the fourth diode D4 are electrically connected to the ground terminal GND of the first clamping circuit 4 , and the cathode of the fourth diode D4 is electrically connected to the second signal line C2 .

[0096] For example, if the voltage of load 1006 is lower than the voltage of ground terminal GND of first clamping circuit 4, third diode D3 conducts, clamping the voltage of load 1006 to a preset value (e.g., -0.3V), thereby preventing the voltage at the port of main control chip 1 from being too low. Similarly, in this case, fourth diode D4 conducts, clamping the voltage of load 1006 to a preset value (e.g., -0.3V), thereby preventing the voltage at the port of main control chip 1 from being too low. It should be noted that the aforementioned "too low voltage" refers to a voltage below 0V.

[0097] In this way, when the load 1006 is at an abnormally low voltage, the first clamping circuit 4 can utilize the unidirectional conductivity of the third diode D3 and the fourth diode D4, as well as the voltage drop characteristics when the diodes are turned on, to clamp the voltage across the load 1006 at a preset value, thereby protecting the port of the main control chip 1 and improving the stability of the operation of the main control chip 1.

[0098] In some embodiments, the ports of the main control chip 1 are pins of the main control chip 1 .

[0099] It should be noted that the abnormally low voltage mentioned above refers to a negative voltage below a preset range value, which can be set according to the ability of the pins of the main control chip to withstand negative voltage.

[0100] For example, the preset range value is -3 V. That is, a voltage lower than -3 V is an abnormally low voltage, and a voltage higher than -3 V is not an abnormally low voltage.

[0101] It should be noted that the structure and function of the second clamping circuit 5 are substantially the same as those of the first clamping circuit 4 , and will not be described in detail here.

[0102] In some embodiments, as shown in Figure 6, the communication circuit 1005 also includes a first anti-backflow circuit 6 and a balancing circuit 7. The first anti-backflow circuit 6 is electrically connected to the main control chip 1 and the balancing circuit 7. The balancing circuit 7 is also electrically connected to the second clamping circuit 5. The first anti-backflow circuit 6 is configured to prevent the signals on the first bus A and the second bus B from being transmitted to the main control chip 1 through the second AC coupling circuit 3. The balancing circuit 6 is configured to balance the voltage in the communication circuit 1005 when there is no signal transmission in the communication circuit 1005, so that the voltage in the communication circuit 1005 tends to be stable. For example, the balancing circuit 6 is configured to control the voltage in the communication circuit to fluctuate within a third preset range when there is no signal transmission in the communication circuit 1005. The third preset range is 2.4V to 2.6V.

[0103] For example, the first backflow prevention circuit 6 includes a twenty-first port 61 , a twenty-second port 62 , a twenty-third port 63 , and a twenty-fourth port 64 . The balancing circuit 7 includes a twenty-fifth port 71 , a twenty-sixth port 72 , a twenty-seventh port 73 , and a twenty-eighth port 74 .

[0104] The twenty-first port 61 and the twenty-second port 62 of the first backflow prevention circuit 6 are electrically connected to the third port 13 and the fourth port 14 of the main control chip 1, respectively. The twenty-third port 63 and the twenty-fourth port 64 of the first backflow prevention circuit 6 are electrically connected to the twenty-fifth port 71 and the twenty-sixth port 72 of the balancing circuit 7, respectively. The twenty-seventh port 73 and the twenty-eighth port 74 of the balancing circuit 7 are electrically connected to the seventeenth port 51 and the eighteenth port 52 of the second clamping circuit 5, respectively.

[0105] In some embodiments, as shown in FIG7 , the first backflow prevention circuit 6 includes a first diode D1 and a second diode D2. The anode of the first diode D1 is electrically connected to the twenty-first port 61 of the first backflow prevention circuit 6, and the cathode of the first diode D1 is electrically connected to the twenty-third port 63 of the first backflow prevention circuit 6. The anode of the second diode D2 is electrically connected to the twenty-second port 62 of the first backflow prevention circuit 6, and the cathode of the second diode D2 is electrically connected to the twenty-fourth port 64 of the first backflow prevention circuit 6.

[0106] For example, when the voltage at the first end or the second end of the load 1006 is greater than the voltage at the port of the main control chip 1 (such as the fourth port 14 or the third port 13), due to the unidirectional conductivity of the diode (such as the first diode D1 or the second diode D2), the voltage of the load 1006 cannot reach the main control chip 1, thereby preventing the port of the main control chip 1 from being impacted by a large voltage, which is beneficial to improving the stability of the operation of the main control chip 1.

[0107] In this way, when the load 1006 is at an abnormally high voltage, the first anti-backflow circuit 6 can use the unidirectional conductivity of the first diode D1 and the second diode D2 to prevent the port of the main control chip 1 from being impacted by the abnormally high voltage, thereby protecting the port of the main control chip 1.

[0108] It should be noted that the abnormally high voltage mentioned above refers to the voltage across the load 1006 being greater than the voltage at the third port 13 and the fourth port 14 of the main control chip.

[0109] In some embodiments, the first diode D1 and the second diode D2 are Schottky diodes, or switching diodes.

[0110] It should be noted that both Schottky diodes and switching diodes can achieve unidirectional conduction and are suitable for rectification applications. The difference between switching diodes and Schottky diodes is that switching diodes have a higher withstand voltage, while Schottky diodes have a faster recovery speed and are suitable for high-frequency applications.

[0111] In some embodiments, as shown in FIG8 , the balancing circuit 7 includes a fifth resistor R5 , a sixth resistor R6 , a seventh resistor R7 , and an eighth resistor R8 .

[0112] A first end of the fifth resistor R5 is electrically connected to the power supply VCC of the balancing circuit 7 , a second end of the fifth resistor R5 is electrically connected to the first end of the sixth resistor R6 and to the first signal line C1 , and a second end of the sixth resistor R6 is electrically connected to the ground GND of the balancing circuit 7 .

[0113] A first end of the seventh resistor R7 is electrically connected to the power supply terminal VCC of the balancing circuit 7. A second end of the seventh resistor R7 is electrically connected to a first end of the eighth resistor R8 and to the second signal line C2. A second end of the eighth resistor R8 is electrically connected to the ground terminal GND of the balancing circuit 7.

[0114] In some embodiments, when the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, and the eighth resistor R8 have the same resistance value, the voltage level on the first signal line C1 is the first voltage level VCC / 2, and the voltage level on the second signal line A is also the first voltage level VCC / 2. In this case, a differential signal is obtained by differentiating the voltage level on the first signal line C1 from the voltage level on the second signal line C2, and the voltage level of the differential signal is 0. It will be understood that a differential signal voltage level of 0 is a stable state. Thus, when the first signal line C1 and the second signal line C2 are idle, the differential signal is at a stable low level, thereby improving communication quality.

[0115] It can be understood that when no signal is transmitted on the first signal line C1 and the second signal line C2, the level on the first signal line C1 and the level on the second signal line C2 are clamped to the first level, and the level of the differential signal is made to be 0 after differentiation, so that the ratio of the resistance values ​​of the seventh resistor R7 and the eighth resistor R8 can be equal to the ratio of the resistance values ​​of the fifth resistor R5 and the sixth resistor R6.

[0116] For example, when the resistance of the fifth resistor R5 is 10kΩ and the resistance of the sixth resistor R6 is 30kΩ, the voltage level of the first signal line C1 is VCC / 4. When the resistance of the seventh resistor R7 is 20kΩ and the resistance of the eighth resistor R8 is 60kΩ, the voltage level of the second signal line C2 is also VCC / 4. In this case, the resistance ratio of the seventh resistor R7 to the eighth resistor R8 is equal to the resistance ratio of the fifth resistor R5 to the sixth resistor R6, resulting in the voltage levels of the first signal line C1 and the second signal line C2 being clamped at VCC / 4.

[0117] In some embodiments, the resistance of the fifth resistor R5 , the sixth resistor R6 , the seventh resistor R7 , and the eighth resistor R8 is greater than 1 kΩ.

[0118] In some embodiments, as shown in FIG9 , the communication circuit 1005 further includes a negative voltage protection circuit 8 and a bus drive circuit 9. The negative voltage protection circuit 8 is electrically connected to the bus drive circuit 9 and the second AC coupling circuit 3 and is configured to prevent abnormal negative voltage surges on the first bus A and the second bus B. The bus drive circuit 9 is electrically connected to the second clamping circuit 5, the negative voltage protection circuit 8, and the main control chip 1 and is configured to increase the drive capability of the communication circuit 1005 when the communication circuit 1005 is at a low level.

[0119] For example, the bus drive circuit 9 includes a ground terminal. When the communication circuit 1005 is at a low level (such as 0 level), the bus drive circuit 9 can introduce the current in the communication circuit 1005 into the ground terminal to improve the driving capability of the communication circuit 1005 and protect the pins of the main control chip 1.

[0120] It is understood that the maximum current that the pins of the main control chip 1 can withstand is 20mA. When the communication circuit 1005 is at a low level (e.g., level 0), the current in the communication circuit 1005 is much greater than 20mA (e.g., 100mA to 500mA). In this case, the current is directed to the ground terminal through the bus drive circuit 9, thereby protecting the pins of the main control chip.

[0121] For example, the maximum current that the bus driving circuit 9 can withstand is 1A.

[0122] For example, the negative voltage protection circuit 8 includes a twenty-ninth port 81 (i.e., the first port of the negative voltage protection circuit) and a thirtieth port 82 (i.e., the second port of the negative voltage protection circuit). The bus drive circuit 9 includes a thirty-first port 91, a thirty-second port 92, a thirty-third port 93, a thirty-fourth port 94, a thirty-fifth port 95, and a thirty-sixth port 96. The main control chip 1 also includes a thirty-seventh port 15 and a thirty-eighth port 16.

[0123] The twenty-ninth and thirtieth ports 81 and 82 of the negative voltage protection circuit 8 are electrically connected to the thirty-third and thirty-fourth ports 93 and 94 of the bus driver circuit 9, respectively. The twenty-ninth and thirtieth ports 81 and 82 of the negative voltage protection circuit 8 are also electrically connected to the ninth and tenth ports 31 and 32 of the second AC coupling circuit 3, respectively. The thirty-first and thirty-second ports 91 and 92 of the bus driver circuit 9 are electrically connected to the nineteenth and twentieth ports 53 and 54 of the second clamping circuit 5, respectively. The thirty-third and thirty-fourth ports 93 and 94 of the bus driver circuit 9 are electrically connected to the ninth and tenth ports 31 and 32 of the second AC coupling circuit 3, respectively. The thirty-fifth and thirty-sixth ports 95 and 96 of the bus driver circuit 9 are electrically connected to the thirty-seventh and thirty-eighth ports 15 and 16 of the main control chip 1, respectively.

[0124] It should be noted that the two main control chips 1 shown in FIG23 are the same main control chip, and the schematic diagram in the figure is for better showing the ports of the main control chip 1 and the connection method with other circuits.

[0125] In some embodiments, the bus driving circuit 9 is further configured to operate to improve the driving capability of the communication circuit 1005 when the communication circuit is in a low voltage state.

[0126] In some embodiments, the negative voltage protection circuit 8 is a Schottky diode or a switching diode, and the bus driving circuit 9 is a transistor.

[0127] It is understandable that communication signals (such as the first communication signal and the second communication signal) can be transmitted between the load 1006 and the main control chip 1 through multiple paths. Below, in combination with Figure 9, the various transmission methods and transmission paths of the communication signals in the communication loop 1005 are introduced in detail.

[0128] In some embodiments, the process of the load 1006 transmitting the first communication signal to the main control chip 1 includes:

[0129] The first communication signal sent by the load 1006 is transmitted to the seventh port 23 and the eighth port 24 of the first AC coupling circuit 2 via the first bus A and the second bus B.

[0130] The first AC coupling circuit 2 receives the first communication signal, and transmits the AC signal meeting the first preset condition to the fifteenth port 43 and the sixteenth port 44 of the first clamping circuit 4 via the fifth port 21 and the sixth port 22 .

[0131] The first clamping circuit 4 receives the first communication signal, transmits the first communication signal to the first port 11 and the second port 12 of the main control chip 1 via the thirteenth port 41 and the fourteenth port 42, and clamps the voltage of the first port 11 and the second port 12 of the main control chip 1 to within a first preset range, thereby transmitting the first communication signal to the main control chip 1.

[0132] The main control chip 1 analyzes the first communication signal.

[0133] In some embodiments, if the voltage in the communication circuit 1005 is not an abnormally low voltage, the process of the main control chip 1 transmitting the second communication signal to the load 1006 includes:

[0134] The main control chip 1 generates a second communication signal, analyzes and calibrates the second communication signal, and transmits the second communication signal to the twenty-first port 61 and the twenty-second port 62 of the first backflow prevention circuit 6 through the third port 13 and the fourth port 14 .

[0135] The first backflow prevention circuit 6 receives the second communication signal, and transmits the second communication signal to the twenty-fifth port 71 and the twenty-sixth port 72 of the balancing circuit 7 via the twenty-third port 63 and the twenty-fourth port 64 .

[0136] The balancing circuit 7 receives the second communication signal, and transmits the second communication signal to the seventeenth port 51 and the eighteenth port 52 of the second clamping circuit 5 via the twenty-seventh port 73 and the twenty-eighth port 74 .

[0137] The second clamping circuit 5 receives the second communication signal, and transmits the second communication signal to the ninth port 31 and the tenth port 32 of the second AC coupling circuit 3 via the nineteenth port 53 and the twentieth port 54 .

[0138] The second AC coupling circuit 3 receives the second communication signal and transmits the AC signal that meets the second preset condition to the first bus A and the second bus B via the eleventh port 33 and the twelfth port 34, so that the second communication signal is transmitted to the load 1006, completing the communication work between the main control chip 1 and the load 1006.

[0139] In some embodiments, if the voltage in the communication circuit 1005 is abnormally low, the process in which the main control chip 1 transmits the second communication signal to the load 1006 includes:

[0140] The main control chip 1 generates a second communication signal, analyzes and calibrates the second communication signal, and transmits the second communication signal to the twenty-first port 61 and the twenty-second port 62 of the first backflow prevention circuit 6 through the third port 13 and the fourth port 14 .

[0141] The first backflow prevention circuit 6 receives the second communication signal, and transmits the second communication signal to the twenty-fifth port 71 and the twenty-sixth port 72 of the balancing circuit 7 via the twenty-third port 63 and the twenty-fourth port 64 .

[0142] The balancing circuit 7 receives the second communication signal, and transmits the second communication signal to the seventeenth port 51 and the eighteenth port 52 of the second clamping circuit 5 via the twenty-seventh port 73 and the twenty-eighth port 74 .

[0143] The second clamping circuit 5 receives the second communication signal, and transmits the second communication signal to the thirty-first port 91 and the thirty-second port 92 of the bus driving circuit 9 via the nineteenth port 53 and the twentieth port 54 .

[0144] The bus driving circuit 9 receives the second communication signal and transmits the second communication signal to the ninth port 31 and the tenth port 32 of the second AC coupling circuit 3 via the thirty-third port 93 and the thirty-fourth port 94 .

[0145] The second AC coupling circuit 3 receives the second communication signal and transmits the AC signal that meets the second preset condition to the first bus A and the second bus B via the eleventh port 33 and the twelfth port 34, so that the second communication signal is transmitted to the load 1006, completing the communication work between the main control chip 1 and the load 1006.

[0146] In some embodiments, if the voltage in the communication circuit 1005 is abnormally low, the process of the load 1006 transmitting the first communication signal to the main control chip 1 includes:

[0147] The first communication signal is transmitted via the first bus A to the seventh port 23 of the first AC coupling circuit 2 .

[0148] The first AC coupling circuit 2 receives the first communication signal, and transmits the AC signal meeting the first preset condition to the fifteenth port 43 of the first clamping circuit 4 via the fifth port 21 .

[0149] The first clamping circuit 4 receives the first communication signal and transmits the first communication signal to the first port 11 of the main control chip 1 via the thirteenth port 41 , thereby transmitting the first communication signal to the main control chip 1 . The main control chip 1 analyzes the first communication signal.

[0150] In this case, the process of transmitting the second communication signal sent by the main control chip to the load 1006 includes:

[0151] The main control chip 1 generates a second communication signal, analyzes and calibrates the second communication signal, and transmits the second communication signal to the twenty-second port 62 of the first backflow prevention circuit 6 through the third port 13 .

[0152] The first backflow prevention circuit 6 receives the second communication signal, and transmits the second communication signal to the twenty-sixth port 72 of the balancing circuit 7 via the twenty-fourth port 64 .

[0153] The balancing circuit 7 receives the second communication signal, and transmits the second communication signal to the eighteenth port 52 of the second clamping circuit 5 via the twenty-eighth port 74 .

[0154] The second clamping circuit 5 receives the second communication signal, and transmits the second communication signal to the 32nd port 92 of the bus driving circuit 9 via the 20th port 54 of the second clamping circuit 5 .

[0155] The bus driving circuit 9 receives the second communication signal, and transmits the second communication signal to the tenth port 32 of the second AC coupling circuit 3 via the thirty-fourth port 94 .

[0156] The second AC coupling circuit 3 receives the second communication signal and transmits the AC signal that meets the second preset condition to the second bus B via the twelfth port 34 , thereby transmitting the second communication signal to the load 1006 , completing the communication work between the main control chip 1 and the load 1006 .

[0157] In some embodiments, if the voltage in the communication circuit 1005 is not an abnormally low voltage, the process of the load 1006 transmitting the first communication signal to the main control chip 1 includes:

[0158] The load 1006 sends a first communication signal, and transmits the first communication signal to the seventh port 23 of the first AC coupling circuit 2 via the first bus A.

[0159] The first AC coupling circuit 2 receives the first communication signal, and transmits the AC signal meeting the first preset condition to the fifteenth port 43 of the first clamping circuit 4 via the fifth port 21 .

[0160] The first clamping circuit 4 receives the first communication signal and transmits the first communication signal to the first port 11 of the main control chip 1 via the thirteenth port 41 , thereby transmitting the first communication signal to the main control chip 1 . The main control chip 1 analyzes the first communication signal.

[0161] In this case, the process of transmitting the second communication signal sent by the main control chip to the load 1006 includes:

[0162] The main control chip 1 generates a second communication signal, analyzes and calibrates the second communication signal, and transmits the second communication signal to the twenty-second port 62 of the first backflow prevention circuit 6 via the third port 13 .

[0163] The first backflow prevention circuit 6 receives the second communication signal, and transmits the second communication signal to the twenty-sixth port 72 of the balancing circuit 7 via the twenty-fourth port 64 .

[0164] The balancing circuit 7 receives the second communication signal, and transmits the second communication signal to the eighteenth port 52 of the second clamping circuit 5 via the twenty-eighth port 74 .

[0165] The second clamping circuit 5 receives the second communication signal, and transmits the second communication signal to the tenth port 32 of the second AC coupling circuit 3 via the twentieth port 54 .

[0166] The second AC coupling circuit 3 receives the second communication signal and transmits the AC signal satisfying the second preset condition to the second bus B through the twelfth port 34 , thereby transmitting the second communication signal to the load 1006 , completing the communication between the main control chip 1 and the load 1006 .

[0167] In some embodiments, if the voltage in the communication circuit 1005 is abnormally low, the process of the load 1006 transmitting the first communication signal to the main control chip 1 includes:

[0168] The load 1006 sends a first communication signal, and transmits the first communication signal to the eighth port 24 of the first AC coupling circuit 2 via the second bus B.

[0169] The first AC coupling circuit 2 receives the first communication signal, and transmits the AC signal meeting the first preset condition to the sixteenth port 44 of the first clamping circuit 4 via the sixth port 22 .

[0170] The first clamp circuit 4 receives the first communication signal and transmits the first communication signal to the second port 12 of the main control chip 1 via the fourteenth port 42, thereby transmitting the first communication signal to the main control chip 1. The main control chip 1 analyzes the first communication signal.

[0171] In this case, the process of transmitting the second communication signal sent by the main control chip to the load 1006 includes:

[0172] The main control chip 1 generates a second communication signal, analyzes and calibrates the second communication signal, and transmits the second communication signal to the twenty-first port 61 of the first backflow prevention circuit 6 through the fourth port 14 .

[0173] The first backflow prevention circuit 6 receives the second communication signal, and transmits the second communication signal to the twenty-fifth port 71 of the balancing circuit 7 via the twenty-third port 63 .

[0174] The balancing circuit 7 receives the second communication signal, and transmits the second communication signal to the seventeenth port 51 of the second clamping circuit 5 via the twenty-seventh port 73 .

[0175] The second clamping circuit 5 receives the second communication signal, and transmits the second communication signal to the thirty-first port 91 of the bus driving circuit 9 via the nineteenth port 53 .

[0176] The bus driving circuit 9 receives the second communication signal, and transmits the second communication signal to the ninth port 31 of the second AC coupling circuit 3 via the thirty-third port 93 .

[0177] The second AC coupling circuit 3 receives the second communication signal and transmits the AC signal that meets the second preset condition to the first bus A via the eleventh port 33, thereby transmitting the second communication signal to the load 1006, completing the communication work between the main control chip 1 and the load 1006.

[0178] In some embodiments, if the voltage in the communication circuit 1005 is not an abnormally low voltage, the process of the load 1006 transmitting the first communication signal to the main control chip 1 includes:

[0179] The load 1006 sends a first communication signal, and transmits the first communication signal to the eighth port 24 of the first AC coupling circuit 2 via the second bus B.

[0180] The first AC coupling circuit 2 receives the first communication signal, and transmits the AC signal meeting the first preset condition to the sixteenth port 44 of the first clamping circuit 4 via the sixth port 22 .

[0181] The first clamping circuit 4 receives the first communication signal and transmits the first communication signal to the second port 12 of the main control chip 1 via the fourteenth port 42 , thereby transmitting the first communication signal to the main control chip 1 , and the main control chip 1 analyzes the first communication signal.

[0182] In this case, the process of transmitting the second communication signal sent by the main control chip to the load 1006 includes:

[0183] The main control chip 1 generates a second communication signal, analyzes and calibrates the second communication signal, and transmits the second communication signal to the twenty-first port 61 of the first backflow prevention circuit 6 through the fourth port 14 .

[0184] The first backflow prevention circuit 6 receives the second communication signal, and transmits the second communication signal to the twenty-fifth port 71 of the balancing circuit 7 via the twenty-third port 63 .

[0185] The balancing circuit 7 receives the second communication signal, and transmits the second communication signal to the seventeenth port 51 of the second clamping circuit 5 via the twenty-seventh port 73 .

[0186] The second clamping circuit 5 receives the second communication signal, and transmits the second communication signal to the ninth port 31 of the second AC coupling circuit 3 via the nineteenth port 53 .

[0187] The second AC coupling circuit 3 receives the second communication signal and transmits the AC signal that meets the second preset condition to the first bus A via the eleventh port 33, thereby transmitting the second communication signal to the load 1006, completing the communication work between the main control chip 1 and the load 1006.

[0188] In some embodiments, as shown in FIG. 10 , the communication circuit 1005 further includes a terminal resistor 111 and an overvoltage protection circuit 112 .

[0189] A first end of the terminal resistor 111 is electrically connected to the first bus A, and a second end of the terminal resistor 111 is electrically connected to the second bus B. The terminal resistor 111 is configured to reduce a transmission delay of a communication waveform in the communication loop 1005 .

[0190] A first end of the overvoltage protection circuit 112 is electrically connected to the first bus A, and a second end of the overvoltage protection circuit 112 is electrically connected to the second bus B. The overvoltage protection circuit 112 is configured to filter out abnormal spike voltages on the first bus A or the second bus B.

[0191] In some embodiments, the overvoltage protection circuit 112 is a varistor, or the overvoltage protection circuit 112 includes a varistor and a diode, and the varistor and the diode are connected in series.

[0192] 11 to 13 , the communication circuit 1005 further includes at least one of a first fuse 113 or a second fuse 114. The first fuse 113 or the second fuse 114 is configured to protect components in the communication circuit 1005 from damage caused by current overload or short circuit.

[0193] 11 , the communication circuit 1005 includes a first fuse 113 . A first end of the first fuse 113 is electrically connected to a first end of the overvoltage protection circuit 112 , and a second end of the first fuse 113 is connected to the first bus A.

[0194] 12 , the communication circuit 1005 includes a second fuse 114. A first end of the second fuse 114 is electrically connected to a second end of the overvoltage protection circuit 112, and a second end of the second fuse 114 is connected to the second bus B.

[0195] For example, referring to FIG13 , the communication circuit 1005 includes a first fuse 113 and a second fuse 114. A first end of the first fuse 113 is electrically connected to a first end of the overvoltage protection circuit 112, and a second end of the first fuse 113 is connected to a first bus A. A first end of the second fuse 114 is electrically connected to a second end of the overvoltage protection circuit 112, and a second end of the second fuse 114 is connected to a second bus B.

[0196] 14 and 15 , the first pins 130 are electrically connected to the first bus A, and the second pins 140 are electrically connected to the second bus B. The first output subassembly 110 is electrically connected to the first pins 130 , and the second output subassembly 120 is electrically connected to the second pins 140 .

[0197] The logic control element 150 includes a first control terminal K1 and a first control terminal K2. The level conversion circuit 160 is electrically connected to the logic control element 150, the first voltage terminal VCC, and the second voltage terminal GND. The output terminal of the level conversion circuit 160 is electrically connected to the first pin 130 or the second pin 140.

[0198] The logic control unit 150 is configured to output a control signal. The level shifter circuit 160 is configured to output a voltage signal at the first voltage terminal VCC to a target pin (e.g., the first pin or the second pin) electrically connected to the level shifter circuit 160, or to output a voltage signal at the second voltage terminal GND to the target pin (e.g., the first pin or the second pin) electrically connected to the level shifter circuit 160, under the control of the control signal.

[0199] It should be noted that the voltage signal of the first voltage terminal VCC is a power supply voltage with a high level. The voltage range of the first voltage terminal VCC is set according to the voltage tolerance range of the pins of the main control chip 1. In other words, the maximum voltage of the first voltage terminal VCC is less than or equal to the maximum voltage that the pins of the main control chip 1 can withstand. The voltage signal of the second voltage terminal GND is a ground voltage with a low level. For example, the voltage output of the second voltage terminal GND is zero.

[0200] It can be understood that, under the control of the logic control component 150, the level conversion circuit 160 can selectively output the high voltage of the first voltage terminal VCC or the low voltage of the second voltage terminal GND to the pin of the main control chip 1, thereby preventing the voltage outside the tolerance range of the pin of the main control chip from being output to the pin, causing damage or failure of the pin, and thus helping to improve the stability and reliability of the main control chip 1 during operation.

[0201] Below, the structure of the first output subassembly 110 will be described in detail with reference to Figures 15 to 19. It should be noted that the structure and function of the second output subassembly 120 are roughly the same as those of the first output subassembly 110, and this disclosure will not go into details.

[0202] In some embodiments, as shown in FIG15 , the level shifting circuit 160 includes a first sub-circuit 161 and a second sub-circuit 162. The first sub-circuit 161 is electrically connected to the first control terminal K1, the first voltage terminal VCC, and the output terminal OUT. The first sub-circuit 161 is configured to transmit the voltage signal at the first voltage terminal VCC to the output terminal OUT. The second sub-circuit 162 is electrically connected to the first control terminal K2, the second voltage terminal GND, and the output terminal OUT. The second sub-circuit 162 is configured to transmit the voltage signal at the second voltage terminal GND to the output terminal OUT.

[0203] In some embodiments, the first control terminal K1 is configured to output a first control signal, and the first control terminal K2 is configured to output a second control signal.

[0204] In some embodiments, the logic control component 150 is configured to output control signals (such as a first control signal and a second control signal) to control the first sub-circuit 161 to be turned on or off, and to control the second sub-circuit 162 to be turned on or off.

[0205] For example, when the logic control element 150 outputs a first control signal having an on-level and a second control signal having an off-level, the first sub-circuit 161 receives and responds to the first control signal to be turned on (e.g., turned on), and the second sub-circuit 162 receives and responds to the second control signal to be turned off. It will be understood that when the first sub-circuit 161 is turned on and the second sub-circuit 162 is turned off, the voltage signal at the first voltage terminal VCC can be transmitted to the output terminal OUT and output to the pin via the output terminal OUT.

[0206] For example, when the logic control element 150 outputs a first control signal having an off level and a second control signal having an on level, the first sub-circuit 161 receives and responds to the first control signal to be turned off, and the second sub-circuit 162 receives and responds to the second control signal to be turned on. When the first sub-circuit 161 is turned off and the second sub-circuit 162 is turned on, the voltage signal at the second voltage terminal GND can be transmitted to the output terminal OUT and output to the pin through the output terminal OUT.

[0207] In some embodiments, as shown in FIG16 , the first sub-circuit 161 includes a first transistor Q1 , a control electrode of the first transistor Q1 being electrically connected to the first control terminal K1 , a first electrode of the first transistor Q1 being electrically connected to the first voltage terminal VCC, and a second electrode of the first transistor Q1 being electrically connected to the output terminal OUT.

[0208] In some embodiments, as shown in FIG17 , the second sub-circuit 162 includes a second transistor Q2 , a control electrode of which is electrically connected to the first control terminal K2 , a first electrode of which is electrically connected to the output terminal OUT, and a second electrode of which is electrically connected to the second voltage terminal.

[0209] In some embodiments, the first transistor Q1 and the second transistor Q2 are NPN transistors. In this case, when the first transistor Q1 is turned on, the first voltage terminal VCC and the output terminal OUT can be considered as a wire. When the second transistor Q2 is turned on, the second voltage terminal GND and the output terminal OUT can be considered as a wire.

[0210] Therefore, if the first transistor Q1 is on and the second transistor Q2 is off, the output terminal OUT outputs the voltage of the first voltage terminal VCC. If the first transistor Q1 is off and the second transistor Q2 is on, the output terminal OUT outputs the voltage of the second voltage terminal GND. If both the first transistor Q1 and the second transistor Q2 are on, the level shifter circuit 160 is short-circuited and does not output any voltage.

[0211] In some embodiments, the level shifter circuit 160 is further configured to, under the control of the control signal, output a set voltage signal to the target pin electrically connected to the level shifter circuit 160. The voltage of the set voltage signal is any voltage between the voltage of the first voltage terminal and the voltage of the second voltage terminal, thereby improving the operational stability of the first pin 130 or the second pin 140.

[0212] 18 , the logic control element 150 further includes a third control terminal K3 configured to output a third control signal. The level conversion circuit 160 further includes a third sub-circuit 163 , a first voltage dividing sub-circuit 164 , and a second voltage dividing sub-circuit 165 .

[0213] The first voltage divider sub-circuit 164 is electrically connected between the first voltage terminal VCC and the first sub-circuit 161. The first end of the second voltage divider sub-circuit 165 is electrically connected to the first sub-circuit 161 and the output terminal OUT. The third sub-circuit 163 is electrically connected to the third control terminal K3, the second voltage terminal GND, and the second end of the second voltage divider sub-circuit 165.

[0214] In this case, the logic control unit 150 is further configured to output a first control signal and a third control signal having an on-level, and a second control signal having an off-level, to control the first sub-circuit 161 and the third sub-circuit 163 to be on, and to control the second sub-circuit 162 to be off. The level conversion circuit 160 is configured to output a set voltage signal to the output terminal OUT.

[0215] For example, when the logic control element 150 outputs a first control signal and a third control signal at an on-level, and a second control signal at an off-level, the first sub-circuit 161 receives and responds to the first control signal to turn on, the second sub-circuit 162 receives and responds to the second control signal to turn off, and the third sub-circuit 163 receives and responds to the third control signal to turn on. When the first sub-circuit 161 is on, the second sub-circuit 162 is off, and the third sub-circuit 163 is on, any voltage between the voltage at the first voltage terminal VCC and the voltage at the second voltage terminal GND is output to the output terminal OUT. This prevents the voltage outputted from the output terminal OUT from being too high (e.g., close to the voltage at the first voltage terminal VCC) or too low (e.g., close to the voltage at the second voltage terminal GND), thereby improving the operational stability and reliability of the first pin 130 and the second pin 140.

[0216] In some embodiments, as shown in Figures 19 and 20, the third sub-circuit 163 includes a third transistor Q3. The control electrode of the third transistor Q3 is electrically connected to the third control terminal K1, the first electrode of the third transistor Q3 is electrically connected to the second terminal of the second voltage divider sub-circuit 165, and the second electrode of the third transistor Q3 is electrically connected to the second voltage terminal GND.

[0217] The first voltage divider sub-circuit 164 includes a first resistor R1, and the second voltage divider sub-circuit 165 includes a second resistor R2. A first end of the first resistor R1 is electrically connected to the first voltage terminal VCC, and a second end of the first resistor R1 is electrically connected to the first electrode of the first transistor Q1. A first end of the second resistor R2 is electrically connected to the second electrode of the first transistor Q1, and a second end of the second resistor R2 is electrically connected to the first electrode of the third transistor Q3.

[0218] It is understood that the voltage at the output terminal is the voltage across the second resistor R2, and the voltage across the second resistor R2 depends on the ratio of the resistance values ​​of the first resistor R1 to the second resistor R2. Therefore, by providing the first resistor R1 and the second resistor R2 in the level conversion circuit 160 and adjusting the ratio of the resistance values ​​of the first resistor R1 to the resistance values ​​of the second resistor R2, the voltage at the output terminal OUT can be adjusted so that the voltage at the output terminal OUT is any voltage between the voltage of the first voltage terminal VCC and the voltage of the second voltage terminal GND, thereby ensuring the stable operation of the main control chip 1 and improving the reliability of the operation of the main control chip 1.

[0219] For ease of description, the second output subassembly 120 includes a fourth transistor Q4, a fifth transistor Q5, and a sixth transistor Q6, which correspond to the first transistor Q1, the second transistor Q2, and the third transistor Q3 in the first output subassembly 110. The second output subassembly 120 includes a third resistor R3 and a fourth resistor R4, which correspond to the first resistor R1 and the second resistor R2 in the first output subassembly 110.

[0220] In some embodiments, at least one of the first resistor R1 or the second resistor R2 is an adjustable resistor, and at least one of the third resistor R3 or the fourth resistor R4 is an adjustable resistor. The logic control unit 150 further includes a fourth control terminal K4 and a fifth control terminal K5.

[0221] The fourth control terminal K4 in the first output subassembly 110 is configured to output a control signal to the first resistor R1 to adjust the resistance of the first resistor R1. The fourth control terminal K4 in the second output subassembly 120 is configured to output a control signal to the third resistor R3 to adjust the resistance of the third resistor R3.

[0222] Similarly, the fifth control terminal K5 in the first output subassembly 110 is configured to output a control signal to the second resistor R2 to adjust the resistance of the second resistor R2. The fifth control terminal K5 in the second output subassembly 120 is configured to output a control signal to the fourth resistor R4 to adjust the resistance of the fourth resistor R4.

[0223] In some embodiments, as shown in FIG21 , the first resistor R1 and the fourth resistor R4 are adjustable resistors. The logic control component 150 of the first output subassembly 110 further includes a fourth control terminal K4 electrically connected to the first resistor R1. The logic control component 150 of the second output subassembly 120 further includes a fifth control terminal K5 electrically connected to the fourth resistor R4.

[0224] In the first output subcomponent 110, the logic control component 150 outputs a first control signal and a third control signal with an on level, and a second control signal with a cut-off level. The first transistor Q1 is turned on under the control of the first control signal, the third transistor Q3 is turned on under the control of the third control signal, and the second transistor Q2 is cut off under the control of the second control signal.

[0225] In this case, the first transistor Q1 and the third transistor Q3 are connected, and the voltage across the second resistor R2 is the voltage output by the output terminal OUT. The fourth control terminal K4 is configured to output a control signal to the first resistor R1 to adjust the resistance value of the first resistor R1, thereby adjusting the resistance ratio of the first resistor R1 to the second resistor R2, thereby adjusting the voltage of the output terminal OUT, and further adjusting the voltage of the first pin 130.

[0226] In the second output subcomponent 120, the logic control component 150 outputs a first control signal and a third control signal with an on level, and a second control signal with a cut-off level, the fourth transistor Q4 is turned on under the control of the first control signal, the fifth transistor Q5 is turned on under the control of the third control signal, and the sixth transistor Q6 is cut off under the control of the second control signal.

[0227] In this case, the fourth transistor Q4 and the sixth transistor Q6 are connected, and the voltage across the fourth resistor R4 is the voltage output by the output terminal OUT. The fifth control terminal K5 is configured to output a control signal to the fourth resistor R4 to adjust the resistance value of the fourth resistor R4, thereby adjusting the resistance ratio of the third resistor R3 to the fourth resistor R4, thereby adjusting the voltage of the output terminal OUT, and further adjusting the voltage of the second pin 140.

[0228] In some embodiments, as shown in FIG22 , the first resistor R1, the third resistor R3, and the fourth resistor R4 are adjustable resistors. The logic control component 150 of the first output subassembly 110 further includes a fourth control terminal K4 electrically connected to the first resistor R1. The logic control component 150 of the second output subassembly 120 further includes a fourth control terminal K4 and a fifth control terminal K5. The fourth control terminal K4 is electrically connected to the third resistor R3, and the fifth control terminal K5 is electrically connected to the fourth resistor R4.

[0229] In the first output subcomponent 110, the logic control component 150 outputs a first control signal and a third control signal with an on level, and a second control signal with a cut-off level. The first transistor Q1 is turned on under the control of the first control signal, the third transistor Q3 is turned on under the control of the third control signal, and the second transistor Q2 is cut off under the control of the second control signal.

[0230] In this case, the first transistor Q1 and the third transistor Q3 are connected, and the voltage across the second resistor R2 is the voltage output by the output terminal OUT. The fourth control terminal K4 is configured to output a control signal to the first resistor R1 to adjust the resistance value of the first resistor R1, thereby adjusting the resistance ratio of the first resistor R1 to the second resistor R2, thereby adjusting the voltage of the output terminal OUT, and further adjusting the voltage of the first pin 130.

[0231] In the second output subcomponent 120, the logic control component 150 outputs a first control signal and a third control signal with an on level, and a second control signal with a cut-off level, the fourth transistor Q4 is turned on under the control of the first control signal, the fifth transistor Q5 is turned on under the control of the third control signal, and the sixth transistor Q6 is cut off under the control of the second control signal.

[0232] In this case, the fourth transistor Q4 and the sixth transistor Q6 are connected, and the voltage across the fourth resistor R4 is the voltage output by the output terminal OUT. The fourth control terminal K4 is configured to output a control signal to the third resistor R3 to adjust the resistance value of the third resistor R3. The fifth control terminal K5 is configured to output a control signal to the fourth resistor R4 to adjust the resistance value of the fourth resistor R4, thereby adjusting the resistance ratio of the third resistor R3 to the fourth resistor R4, thereby adjusting the voltage of the output terminal OUT, and further adjusting the voltage of the second pin 140.

[0233] It should be noted that the above only uses the main control chip 1 in Figures 21 and 22 as an example to introduce the circuit structure of the first output subassembly 110 and the second output subassembly 120, but it cannot be regarded as a limitation of the present disclosure.

[0234] In some embodiments, the first resistor R1 is an adjustable resistor. In this case, the logic control component 150 in the first output subassembly 110 may include the fourth control terminal K4 but not the fifth control terminal K5.

[0235] In some embodiments, the second resistor R2 is an adjustable resistor. In this case, the logic control component 150 in the first output subassembly 110 may include the fifth control terminal K5 but not the fourth control terminal K4.

[0236] In some embodiments, the first resistor R1 and the second resistor R2 are both adjustable resistors. In this case, the logic control component 150 in the first output subassembly 110 may include a fourth control terminal K4 and a fifth control terminal K5.

[0237] In some embodiments, the third resistor R3 is an adjustable resistor. In this case, the logic control component 150 in the second output subassembly 120 may include the fourth control terminal K4 but not the fifth control terminal K5.

[0238] In some embodiments, the fourth resistor R4 is an adjustable resistor. In this case, the logic control component 150 in the second output subassembly 120 may include the fifth control terminal K5 but not the fourth control terminal K4.

[0239] In some embodiments, the third resistor R3 and the fourth resistor R4 are both adjustable resistors. In this case, the logic control component 150 in the second output subassembly 120 may include a fourth control terminal K4 and a fifth control terminal K5.

[0240] It is understood that in some of the above embodiments, depending on whether the resistance is adjustable, the first output subassembly 110 can be constructed into three circuit structures, and the second output subassembly 120 can also be constructed into three circuit structures. When any of the three first output subassemblies 110 is used in conjunction with any of the three second output subassemblies 120, the voltage at the first pin 130 and the second pin 140 can be adjusted, thereby preventing the first pin and the second pin from being affected by abnormal voltage, thereby facilitating improved operational stability and reliability of the main control chip 1.

[0241] Some embodiments of the present disclosure provide another air conditioning system 1000 , as shown in FIG23 , which includes a second controller 1007 and a load 1006 , but does not include the first controller 1004 . The second controller 1007 is in communication with the load 1006 .

[0242] As described above, the load 1006 may include at least one of the devices including the indoor unit 1001 , the outdoor unit 1002 , the wired controller 1003 , or the centralized controller, etc., which include differential communication.

[0243] In some embodiments, as shown in FIG23 , the second controller 1007 includes a main control chip 1 and a second backflow prevention circuit 20. The main control chip 1 is electrically connected to the second backflow prevention circuit 20. The main control chip 1 is configured to output a communication signal to the load 1006. The second backflow prevention circuit 20 is configured to be cut off when the voltage at the port of the load 1006 is greater than the voltage at the pin of the main control chip, thereby preventing the abnormal voltage at the load 1006 from being transmitted to the pin of the main control chip 1, thereby improving the operational stability of the main control chip 1.

[0244] In some embodiments, as shown in FIG23 , the main control chip 1 includes a third pin 17 and a fourth pin 18. The second backflow prevention circuit 20 includes a first terminal 201, a second terminal 202, a third terminal 203, and a fourth terminal 204. The load 1006 includes a fifth terminal T1 (i.e., the first terminal of the load) and a sixth terminal T2 (i.e., the second terminal of the load).

[0245] For example, the third pin 17 and the fourth pin 18 are output pins, and the main control chip 1 is further configured to output a communication signal to the load 1006 through the third pin 17 and the fourth pin 18 .

[0246] The first end 201 of the second anti-backflow circuit 20 is electrically connected to the third pin 17 of the main control chip 1, the second end 202 of the second anti-backflow circuit 20 is electrically connected to the fourth pin 18 of the main control chip 1, the third end 203 of the second anti-backflow circuit 20 is electrically connected to the fifth end T1 of the load 1006, and the fourth end 204 of the second anti-backflow circuit 20 is electrically connected to the sixth end T2 of the load 1006.

[0247] The second anti-backflow circuit 20 is also configured to be cut off when the voltage of the fifth terminal T1 of the load 1006 is greater than the voltage of the third pin 17 of the main control chip 1, and to be cut off when the voltage of the sixth terminal T2 of the load 1006 is greater than the voltage of the fourth pin 18 of the main control chip 1.

[0248] It should be noted that when the second anti-backflow circuit 20 is turned off, at least one device in the second anti-backflow circuit 20 is turned off. When the second anti-backflow circuit 20 is turned on, all devices in the second anti-backflow circuit 20 are turned on.

[0249] It is understandable that when the voltage of the communication signal transmitted to the third pin 17 and the fourth pin 18 is an abnormal voltage, the third pin 17 and the fourth pin 18 may be affected, or even fail and stop working.

[0250] For example, when the voltage of the fifth end of the load 1006 is greater than the voltage of the third pin 17 of the main control chip 1, and when the voltage of the sixth end T2 of the load 1006 is greater than the voltage of the fourth pin 18 of the main control chip 1, it is considered that the voltage received by the third pin 17 and the fourth pin 18 of the main control chip 1 is an abnormal voltage. In this case, the second anti-backflow circuit 20 is cut off, thereby preventing the abnormal voltage from being transmitted to the third pin 17 and the fourth pin 18 of the main control chip 1, which is beneficial to improving the stability of the operation of the main control chip 1.

[0251] In some embodiments, as shown in FIG24 , the second backflow prevention circuit 20 includes a seventh diode D7 and an eighth diode D8. The anode of the seventh diode D7 is electrically connected to the third pin 17 of the main control chip 1, and the cathode of the seventh diode D7 is electrically connected to the fifth terminal T1 of the load 1006. The anode of the eighth diode D8 is electrically connected to the fourth pin 18 of the main control chip 1, and the cathode of the eighth diode D8 is electrically connected to the sixth terminal T2 of the load 1006.

[0252] For example, if the voltage at the port of the load 1006 is greater than the voltage at the pin of the main control chip 1, due to the unidirectional conductivity of the seventh diode D7, the voltage at the fifth terminal T1 of the load 1006 cannot pass through the seventh diode D7 to reach the main control chip 1, thereby preventing the third pin 17 from being affected by the abnormal voltage. Similarly, due to the unidirectional conductivity of the eighth diode D8, the voltage at the sixth terminal T2 of the load 1006 cannot pass through the eighth diode D8 to reach the main control chip 1, thereby preventing the fourth pin 18 from being affected by the abnormal voltage.

[0253] In some embodiments, the seventh diode D7 and the eighth diode D8 are Schottky diodes or switching diodes.

[0254] In some embodiments, as shown in FIG25 , the second controller 1007 further includes a third clamping circuit 30. The third clamping circuit 30 is electrically connected to the second backflow prevention circuit 20 and the load 1006, respectively, and the third clamping circuit 30 is configured to be turned on when the voltage at the fifth terminal T1 and the sixth terminal T2 of the load 1006 is less than the voltage at the third ground terminal GND3 of the third clamping circuit 30, so as to clamp the voltage at the third pin 17 and the fourth pin 18 of the main control chip 1 to an allowable range.

[0255] For example, the third clamping circuit 30 includes a seventh terminal 301, an eighth terminal 302, and a ninth terminal 303. The seventh terminal 301 of the third clamping circuit 30 is electrically connected to the third terminal 203 of the second anti-backflow circuit 20, the eighth terminal 302 of the third clamping circuit 30 is electrically connected to the fourth terminal 204 of the second anti-backflow circuit 20, and the ninth terminal 303 of the third clamping circuit 30 is electrically connected to the third ground terminal GND3 of the third clamping circuit 30.

[0256] It should be noted that the voltage of the third ground terminal GND3 is zero. That is, when the voltages of the fifth terminal T1 and the sixth terminal T2 of the load 1006 are less than zero, the third clamping circuit 30 is turned on, and the voltages of the third pin 17 and the fourth pin 18 of the main control chip 1 can be clamped to within an allowable range, thereby protecting the third pin 17 and the fourth pin 18 of the main control chip 1, and improving the stability and reliability of the operation of the main control chip 1.

[0257] In some embodiments, as shown in FIG. 26 and FIG. 27 , the third clamping circuit 30 includes a fifth diode D5 and a sixth diode D6 .

[0258] 26 and 27 , the cathode of the fifth diode D5 is electrically connected to the cathode of the seventh diode D7 , the anode of the fifth diode D5 and the anode of the sixth diode D6 are electrically connected to the third ground terminal GND3 , and the cathode of the sixth diode D6 is electrically connected to the cathode of the eighth diode D8 .

[0259] The fifth diode D5 is configured to be turned on when the voltage of the fifth terminal T1 of the load 1006 is less than the voltage of the third ground terminal GND3, so that the voltage of the fifth terminal T1 of the load 1006 is clamped at a preset value (such as -0.3V), so that an excessively low voltage will not appear on the third pin 17 of the main control chip 1.

[0260] The sixth diode D6 is configured to be turned on when the voltage of the sixth terminal T2 of the load 1006 is less than the voltage of the third ground terminal GND3, so that the voltage of the sixth terminal T2 of the load 1006 is clamped at a preset value (such as -0.3V), so that an excessively low voltage will not appear on the fourth pin 18 of the main control chip 1.

[0261] It should be noted that the low voltage refers to a voltage lower than 0V.

[0262] It can be understood that when the load is at an abnormally low voltage, the third clamping circuit 30 can utilize the unidirectional conductivity of the fifth diode D5 and the sixth diode D6 and the voltage drop effect of the diode conduction to clamp the voltage across the load 1006 at a preset value, thereby protecting the pins of the main control chip 1 and helping to improve the stability and reliability of the operation of the main control chip 1.

[0263] It should be noted that the preset value can be adjusted according to actual conditions and is related to the abnormally low voltage tolerance of the pins of the main control chip 1. The stronger the abnormally low voltage tolerance of the pins of the main control chip 1 is, the lower the preset value can be set.

[0264] For example, for the main control chip provided in some embodiments of the present disclosure, -3V is an abnormally low voltage, while -0.2V is not an abnormally low voltage. Whether it is an abnormal negative pressure can be determined based on the ability of the main control chip pins to withstand negative pressure.

[0265] In some embodiments, at least one of the fifth diode D5 and the sixth diode D6 may be a Schottky diode or a switching diode.

[0266] In some embodiments, as shown in FIG28 , the second controller 1007 further includes a third signal line C3 and a fourth signal line C4. The third signal line C3 and the fourth signal line C4 are configured to transmit differential signals. The third terminal 203 of the second anti-backflow circuit 20 is electrically connected to the fifth terminal T1 of the load 1006 via the third signal line C3, and the fourth terminal 204 of the second anti-backflow circuit 20 is electrically connected to the sixth terminal T2 of the load 1006 via the fourth signal line C4.

[0267] For example, the third signal line C3 and the fourth signal line C4 are a home communication bus.

[0268] In some embodiments, as shown in FIG28 , the second controller 1007 further includes a fourth clamping circuit 40 and a fifth clamping circuit 50. Both the fourth clamping circuit 40 and the fifth clamping circuit 50 are midpoint level clamping circuits. The fourth clamping circuit 40 is electrically connected to the third signal line C3 and is configured to clamp the voltage level on the third signal line C3 to the first voltage level when no signal is transmitted on the third signal line C3. The fifth clamping circuit 50 is electrically connected to the fourth signal line C4 and is configured to clamp the voltage level on the fourth signal line C4 to the first voltage level when no signal is transmitted on the fourth signal line C4.

[0269] For example, the tenth terminal 401 of the fourth clamping circuit 40 is electrically connected to the third terminal 203 of the second backflow prevention circuit 20 , the seventh terminal 301 of the third clamping circuit 30 , and the fifth terminal T1 of the load 1006 , respectively.

[0270] It is understood that when the fourth clamping circuit 40 and the fifth clamping circuit 50 clamp the levels on the third signal line C3 and the fourth signal line C4 to the first level, a differential signal is obtained by differentiating the levels on the third signal line C3 and the fourth signal line C4, and the level of the differential signal is 0. It is understood that a differential signal level of 0 is a stable state. Thus, when the third signal line C3 and the fourth signal line C4 are idle, the differential signal is at a stable low level, thereby improving communication quality.

[0271] 28 , the tenth terminal 401 of the fourth clamp circuit 40 is electrically connected to the third signal line C3 , the eleventh terminal 402 of the fourth clamp circuit 40 is electrically connected to the first power supply terminal VCC1 , and the twelfth terminal 403 of the fourth clamp circuit 40 is electrically connected to the first ground terminal GND1 .

[0272] The thirteenth terminal 501 of the fifth clamping circuit 50 is electrically connected to the fourth signal line C4; the fourteenth terminal 502 of the fifth clamping circuit 50 is electrically connected to the second power supply terminal VCC2; and the fifteenth terminal 503 of the fifth clamping circuit 50 is electrically connected to the second ground terminal GND2.

[0273] In some embodiments, the first power terminal VCC1 of the fourth clamping circuit 40 and the second power terminal VCC2 of the fifth clamping circuit 50 are the same power terminal. The first ground terminal GND1 of the fourth clamping circuit 40 and the second ground terminal GND2 of the fifth clamping circuit 50 are the same ground terminal.

[0274] In some embodiments, as shown in FIG29 and FIG31 , the fourth clamping circuit 40 includes a ninth resistor R9 and a tenth resistor R10. A first end of the ninth resistor R9 is electrically connected to the first power supply terminal VCC1, a second end of the ninth resistor R9 is electrically connected to the first end of the tenth resistor R10 and the third signal line C3, and a second end of the tenth resistor R10 is electrically connected to the first ground terminal GND1.

[0275] In some embodiments, as shown in Figures 30 and 31, the fifth clamping circuit 50 includes an eleventh resistor R11 and a twelfth resistor R12. A first end of the eleventh resistor R11 is electrically connected to the second power supply terminal VCC2, a second end of the eleventh resistor R11 is electrically connected to a first end of the twelfth resistor R12 and the fourth signal line C4, and a second end of the twelfth resistor R12 is electrically connected to the second ground terminal GND2.

[0276] In some embodiments, if the ninth resistor R9, the tenth resistor R10, the eleventh resistor R11, and the twelfth resistor R12 have the same resistance value, the voltage level on the third signal line C3 is VCC / 2, and the voltage level on the fourth signal line C4 is also VCC / 2. In other words, the voltage levels on the third signal line C3 and the fourth signal line C4 are both the first voltage level VCC / 2.

[0277] In some embodiments, the ratio of the resistances of the eleventh resistor R11 to the twelfth resistor R12 is equal to the ratio of the resistances of the ninth resistor R9 to the tenth resistor R10 .

[0278] For example, if the resistance of the ninth resistor R9 is 10 kΩ and the resistance of the tenth resistor R10 is 30 kΩ, the level of the third signal line C3 is VCC / 4. If the resistance of the eleventh resistor R11 is 20 kΩ and the resistance of the twelfth resistor R12 is 60 kΩ, the level of the fourth signal line C4 is also VCC / 4. In this case, the ratio of the resistances of the eleventh resistor R11 and the twelfth resistor R12 is equal to the ratio of the resistances of the ninth resistor R9 and the tenth resistor R10. At the same time, the levels of the third signal line C3 and the fourth signal line C4 are both clamped at VCC / 4, meeting the aforementioned differential requirement.

[0279] Those skilled in the art will understand that the scope of the present invention is not limited to the above specific embodiments, and that certain elements of the embodiments may be modified and replaced without departing from the spirit of the present invention. The scope of the present invention is limited by the appended claims.

Claims

1. An air conditioning system, comprising: First bus; Second bus; as well as A communication circuit is configured to be electrically connected to a load; the communication circuit comprises: Main control chip; A first AC coupling circuit is electrically connected to the main control chip, the first bus and the second bus; and a second AC coupling circuit, electrically connected to the main control chip, the first bus and the second bus; Wherein, the main control chip is configured as: receiving a first communication signal from the load through a first AC coupling circuit, parsing the first communication signal, and receiving the first communication signal if the first communication signal satisfies a first preset condition; and, A second communication signal is generated, the second communication signal is analyzed, and when the second communication signal meets a second preset condition, the second communication signal is sent to the load through the second AC coupling circuit.

2. The air conditioning system according to claim 1, wherein: The main control chip includes a first port and a second port; The communication loop also includes a first clamping circuit; the first clamping circuit is electrically connected to the first port and the second port of the main control chip; the first clamping circuit is electrically connected to the first AC coupling circuit; the first clamping circuit is configured to clamp the voltage of the signal at the first port and the second port of the main control chip to within a first preset range.

3. The air conditioning system according to claim 1 or 2, wherein: The main control chip includes a third port and a fourth port; The communication loop includes a second clamping circuit; the second clamping circuit is electrically connected to the third port and the fourth port of the main control chip, and the second AC coupling circuit; the second clamping circuit is configured to clamp the voltage of the signal at the third port and the fourth port of the main control chip to within a second preset range.

4. The air conditioning system according to claim 3, wherein: The communication loop also includes a first anti-backflow circuit; the first anti-backflow circuit is electrically connected to the third port and the fourth port of the main control chip, and the second clamping circuit; the first anti-backflow circuit is configured to prevent signals on the first bus and the second bus from being transmitted to the main control chip through the second AC coupling circuit.

5. The air conditioning system according to claim 4, wherein: The communication loop also includes a balancing circuit; the balancing circuit is electrically connected to the first anti-backflow circuit and the second clamping circuit; the balancing circuit is configured to control the voltage in the communication loop to fluctuate within a third preset range when there is no signal transmission in the communication loop.

6. The air conditioning system according to claim 5, wherein: The communication circuit further includes a negative voltage protection circuit; the negative voltage protection circuit includes a first port and a second port; the first port and the second port of the negative voltage protection circuit are electrically connected to the second clamping circuit, and the first port and the second port of the negative voltage protection circuit are also electrically connected to the second AC coupling circuit; The negative voltage protection circuit is configured to prevent the negative voltage on the first bus and the second bus from impacting the main control chip.

7. The air conditioning system according to claim 6, wherein: The communication circuit also includes a bus driving circuit; the bus driving circuit is electrically connected to the second clamping circuit, the second AC coupling circuit and the main control chip respectively; the bus driving circuit is configured to introduce the current in the communication circuit into the ground terminal of the bus driving circuit when the communication circuit is at a low level.

8. The air conditioning system according to any one of claims 1 to 7, wherein: The communication loop also includes a terminal resistor; a first end of the terminal resistor is electrically connected to the first bus, and a second end of the terminal resistor is electrically connected to the second bus; the terminal resistor is configured to reduce the transmission delay of the communication waveform in the communication loop.

9. The air conditioning system according to claim 8, wherein: The communication circuit also includes an overvoltage protection circuit; a first end of the overvoltage protection circuit is electrically connected to the first bus, and a second end of the overvoltage protection circuit is electrically connected to the second bus; the overvoltage protection circuit is configured to filter out peak voltages on the first bus or the second bus.

10. The air conditioning system according to claim 9, wherein: The communication circuit further includes at least one of a first fuse or a second fuse; The first end of the first fuse is electrically connected to the first end of the overvoltage protection circuit, and the second end of the first fuse is connected to the first bus; The first end of the second fuse is electrically connected to the second end of the overvoltage protection circuit, and the second end of the second fuse is connected to the second bus.

11. The air conditioning system according to any one of claims 1 to 10, wherein: The main control chip also includes: A first pin, electrically connected to the first bus; a second pin, electrically connected to the second bus; a first output subassembly electrically connected to the first pin; and a second output subassembly, electrically connected to the second pin; Wherein, at least one of the first output subassembly and the second output subassembly comprises: a first voltage terminal; a second voltage terminal; a logic control element electrically connected to the level conversion circuit and configured to output a control signal to the level conversion circuit; and A level conversion circuit is electrically connected to the first voltage terminal and the second voltage terminal respectively; the output terminal of the level conversion circuit is electrically connected to a target pin; the target pin is the first pin or the second pin; the level conversion circuit is configured to output the voltage signal of the first voltage terminal to the target pin, or output the voltage signal of the second voltage terminal to the target pin under the control of the control signal.

12. The air conditioning system according to claim 11, wherein: The logic control element comprises: a first control terminal; and A second control terminal; The level conversion circuit comprises: a first sub-circuit electrically connected to the first control terminal, the first voltage terminal and the output terminal of the level conversion circuit; a second sub-circuit, electrically connected to the second control terminal, the second voltage terminal and the output terminal of the level conversion circuit; Wherein, the logic control element satisfies one of the following: The logic control element is configured to: output a first control signal having an on level to the first sub-circuit through the first control terminal to control the first sub-circuit to be on; and output a second control signal having an off level to the second sub-circuit through the second control terminal to control the second sub-circuit to be off; the first sub-circuit is configured to transmit the voltage signal of the first voltage terminal to the output terminal; or The logic control element is configured to: output a first control signal with a cut-off level to the first sub-circuit through the first control terminal to control the first sub-circuit to be turned off; and output a second control signal with an on-level to the second sub-circuit through the second control terminal to control the second sub-circuit to be turned on; the second sub-circuit is configured to transmit the voltage signal of the second voltage terminal to the output terminal.

13. The air conditioning system according to claim 12, wherein: The first subcircuit includes a first transistor; a control electrode of the first transistor is electrically connected to the first control terminal, a first electrode of the first transistor is electrically connected to the first voltage terminal, and a second electrode of the first transistor is electrically connected to the output terminal.

14. The air conditioning system according to claim 13, wherein: The second subcircuit includes a second transistor; a control electrode of the second transistor is electrically connected to the second control terminal, a first electrode of the second transistor is electrically connected to the output terminal, and a second electrode of the second transistor is electrically connected to the second voltage terminal.

15. The air conditioning system according to any one of claims 12 to 14, wherein: The level conversion circuit is further configured to output a set voltage signal to the target pin under the control of the control signal; The voltage of the setting voltage signal is any voltage between the voltage of the first voltage terminal and the voltage of the second voltage terminal.

16. The air conditioning system according to claim 15, wherein: The logic control unit also includes a third control terminal; The level conversion circuit also includes: a first voltage dividing sub-circuit, electrically connected between the first voltage terminal and the first sub-circuit; a second voltage dividing sub-circuit, electrically connected to the first sub-circuit and the output end respectively; and a third sub-circuit, connected to the third control terminal, the second voltage terminal and the second voltage dividing sub-circuit respectively; Wherein, the logic control element is further configured as: Outputting a first control signal having an on level to the first sub-circuit through the first control terminal to control the first sub-circuit to be turned on; outputting a second control signal having a cut-off level to the second sub-circuit through the second control terminal to control the second sub-circuit to be turned off; and A third control signal having an on level is output to the third sub-circuit through the third control terminal to control the third sub-circuit to be turned on.

17. The air conditioning system according to claim 16, wherein: The third subcircuit includes a third transistor; the control electrode of the third transistor is electrically connected to the third control terminal, the first electrode of the third transistor is electrically connected to the second voltage divider subcircuit, and the second electrode of the third transistor is electrically connected to the second voltage terminal.

18. The air conditioning system according to claim 17, wherein: The first voltage dividing subcircuit includes a first resistor, and the second voltage dividing subcircuit includes a second resistor; Wherein, at least one of the first resistor or the second resistor is an adjustable resistor.

19. The air conditioning system according to any one of claims 1 to 18, wherein: The main control chip further includes a third pin and a fourth pin; the load includes a first end and a second end; The air conditioning system further includes a second backflow prevention circuit; the second backflow prevention circuit is electrically connected to the third pin, the fourth pin, and the first end and the second end of the load respectively; The second anti-backflow circuit is configured as follows: Cutting off when the voltage of the first end of the load is greater than the voltage of the third pin; Cutting off when the voltage of the second end of the load is greater than the voltage of the fourth pin; and The load is turned off when the voltage at the first end of the load is greater than the voltage at the third pin, and the voltage at the second end of the load is greater than the voltage at the fourth pin.

20. The air conditioning system according to claim 19, wherein: The second anti-backflow circuit comprises: a third diode, an anode of the third diode being electrically connected to the third pin, and a cathode of the third diode being electrically connected to the first end of the load; and a fourth diode; an anode of the fourth diode is electrically connected to the fourth pin, and a cathode of the fourth diode is electrically connected to the second end of the load.

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