Pin electronic device, testing device and testing method

Abstract

Provided is a pin electronic device for testing an element to be tested, the pin electronic device comprising: a test circuit connected to the element to be tested for testing the element to be tested; a power supply circuit for supplying power to a circuit in the pin electronic device; and a monitoring circuit that, in response to the detection of a malfunction of the pin electronic device, records malfunction information related to the malfunction to a recording medium that is readable without receiving the power supply from the power supply circuit.

Description

Technical Field

[0001] The present invention relates to a pin electronic device, a test device and a method. Background Art

[0002] Patent Document 1 describes: "It is possible to easily confirm an abnormality in the internal voltage supplied to the internal circuit of the semiconductor integrated circuit device in the combustion test" (paragraph 0010); "The semiconductor integrated circuit device 100D includes internal step-down power supplies 3(1), 3(2),..., 3(n), an abnormality detection circuit 5D, and a logic circuit 9" (paragraph 0076); "In the internal memory 10, in addition to the information indicating an abnormality, information indicating in which internal step-down power supply 3 the abnormality has occurred is also stored" (paragraph 0079).

[0003] Patent Document 2 describes: "The storage element 106 is a non-volatile rewritable memory in which the stored content does not disappear even without power supply, and the use of a flash memory is assumed" (paragraph 0018); "According to the operation described above, in the storage element 106 in the semiconductor integrated circuit 100 of the present invention, the time exceeding the warning temperature in the "warning temperature exceeding time" region during operation is recorded as the number of times per unit time, and the temperature value at the highest temperature during operation in the "highest detected temperature" region is also recorded. When a malfunction occurs in the semiconductor integrated circuit 100 and causes poor operation, the information in the "warning temperature exceeding time" or "highest detected temperature" region of the storage element 106 is read via the input / output unit 104 by the control circuit 103." (paragraph 0022).

[0004] Patent Document 3 describes: " Figure 1FIG. 0 shows an example of the abnormality notification system 1 of the present invention. The abnormality notification system 1 includes a bus 2, an upper module 3, and N (N is an integer of 2 or more) lower modules 4-1 to 4-N (collectively referred to as the lower module 4).” (Paragraph 0025); “Examples of the abnormality detected by the abnormality detection circuit 20 include an abnormality in the power supply voltage or an abnormality in the circuit temperature. For the pin electronic card of the lower module 4, there is a circuit for power supply or testing (for example, a Field Programmable Gate Array (FPGA)). When the output voltage of the power supply becomes abnormal or the temperature of the circuit becomes abnormal, etc., the abnormality detection circuit 20 performs abnormality detection.” (Paragraph 0033); “The abnormality information storage unit 22 is connected to M abnormality detection circuits 20 and inputs abnormality detection information indicating that the abnormality detection circuit 20 has detected an abnormality. The abnormality detection information is 1-bit information, and the total abnormality detection information is M bits. The abnormality information storage unit 22 stores the M-bit abnormality detection information as abnormality information” (Paragraph 0035).

[0005] Patent Document 4 describes: “The circuit component self-test system 10 (here, the test system 10) located on the circuit component 18 includes a microprocessor 20, a non-volatile memory 30 (here, the NVM 30), a volatile memory 42, a circuit 52 to be tested (on the circuit component 18), and an interface circuit 60.” (Paragraph 0019); “For example, in the case where a specific test program fails to be completed due to a failure or an error, this failure condition is immediately recorded in the non-volatile memory 30 so that this information can be used by maintenance personnel. This information is not lost due to a power outage or a power reset and is permanent in nature.” (Paragraph 0035).

[0006] Patent Document 5 describes: "The present invention is an abnormality processing device for an IC test device. When an abnormality that may develop into a fire occurs in an Integrated Circuit (IC) test device, an abnormality sensor operates, and the output of an abnormality monitoring circuit that processes the abnormality detection output is inserted into a control computer. The control computer displays the cause of the abnormality on a terminal and causes a power control circuit to operate to cut off the power supply of the IC test device and its control device. The abnormality processing device of the IC test device includes: various abnormality sensors for the IC test device and the control device, which are classified according to the type of cause of the abnormality; an abnormality monitoring circuit that processes the abnormality detection output and inserts it into the control computer; an uninterruptible power supply device that monitors the abnormality of the power supply to the control device, supplies power to the control device for a specified time when the abnormality occurs, and notifies the abnormality monitoring circuit whether it is in operation; a control computer that reads the cause of the abnormality and whether the uninterruptible power supply device is in operation from the abnormality monitoring circuit, and judges whether the IC test device can be restored to an operating state; and a component that causes the power control circuit to operate by the output of the control computer, keeps the power supply of the control device in an operating state and only cuts off the power supply of the IC test device, and starts the power supply of the IC test device from a stopped state." (Paragraph 0009).

[0007] Patent Document 6 describes: " Figure 1 The semiconductor test device 1 of the present invention is shown. The semiconductor test device 1 is composed of cards 2A to 2F (collectively referred to as card 2), a tester controller 3, a hard disk 4, and a connection path 5." (Paragraph 0030); "A diagnosis unit 11 is provided on each card 2. As the diagnosis unit 11, a diagnosis (self-diagnosis) of whether a failure has occurred in its own card 2 or a diagnosis (connection diagnosis) of whether a failure has occurred in the connection path 5 as a connection unit to which it is connected is performed." (Paragraph 0035); "The diagnosis data storage unit 25 stores the diagnosis data generated by the diagnosis data generation unit 24 Figure 4 as shown in the diagnosis data." (Paragraph 0055).

[0008] Patent Document 7 describes: "The semiconductor test device applies a signal to the DUT and compares and determines the output signal from the DUT with an expected value, thereby discriminating between good and defective products of the DUT." (Paragraph 0002); "As a result, when a failure occurs during the diagnosis of the failure memory unit 51, information on the failure area is stored in the information storage unit 61 of the address allocation unit, and an offset address is set in the offset setting unit 63." (Paragraph 0042).

[0009] [Prior Art Documents]

[0010] [Patent Documents]

[0011] [Patent Document 1] Japanese Patent Laid-Open No. 2021-052122

[0012] [Patent Document 2] Japanese Patent Laid-Open No. 2014-003078

[0013] [Patent Document 3] Japanese Patent Laid-Open No. 2012-063837

[0014] [Patent Document 4] Japanese Patent Laid-Open No. 2000-221238

[0015] [Patent Document 5] Japanese Patent Laid-Open No. 7-074224

[0016] [Patent Document 6] Japanese Patent Laid-Open No. 2012-117932

[0017] [Patent Document 7] Japanese Patent Laid-Open No. 2009-020934 SUMMARY OF THE INVENTION

[0018] In a first embodiment of the present invention, there is provided a pin electronic device that tests a device under test. The pin electronic device includes: a test circuit connected to the device under test to test the device under test; a power supply circuit that supplies power to the circuits within the pin electronic device; and a monitoring circuit that, in the case where a failure of the pin electronic device is detected, records failure information related to the failure in a recording medium that can be read without receiving power supply from the power supply circuit.

[0019] In the pin electronic device described above, the recording medium can be read by short-range wireless communication.

[0020] The pin electronic device may include: an antenna provided on the outer surface of the pin electronic device that is exposed to the outside when the pin electronic device is mounted on a test head, and the recording medium can be read by short-range wireless communication using the antenna.

[0021] In any one of the pin electronic devices described above, the antenna may be provided on the outer surface of the pin electronic device where a connector connected to the device under test is mounted.

[0022] Any one of the pin electronic devices may include: an antenna at an edge of the upper surface of the pin electronic device where a connector connected to the device under test is mounted, and the recording medium can be read by short-range wireless communication using the antenna.

[0023] In any one of the pin electronic devices described above, the recording medium receives power supply to read the failure information by short-range wireless power supply from a terminal device that reads the failure information via the antenna, and supplies the failure information to the terminal device by short-range wireless communication via the antenna.

[0024] In any of the above-described pin electronic devices, the monitoring circuit may include a microcontroller. The microcontroller monitors for faults and writes to a recording medium by executing a monitoring program. The microcontroller receives power supply through short-range wireless power supply via an antenna from a terminal device that reads fault information, reads the fault information from the recording medium, and supplies the fault information to the terminal device via the antenna through short-range wireless communication.

[0025] In any of the above-described pin electronic devices, the monitoring circuit may include a microcontroller. The microcontroller monitors for faults and writes to a recording medium by executing a monitoring program. The pin electronic device has a monitoring connector for connecting a terminal device that reads fault information to the microcontroller. The microcontroller receives power supply from the terminal device via the monitoring connector, reads the fault information from the recording medium, and supplies the fault information to the terminal device via the monitoring connector.

[0026] In any of the above-described pin electronic devices, when a fault of a component of the pin electronic device is detected, the monitoring circuit may record fault information including component identification information for identifying the faulty component to the recording medium.

[0027] In any of the above-described pin electronic devices, when a fault of the pin electronic device is detected, the monitoring circuit may record the fault detection date and time associated with the fault information to the recording medium.

[0028] In any of the above-described pin electronic devices, the monitoring circuit may include: an internal clock; a clock setting circuit that sets the current date and time received from an external device of the pin electronic device to the internal clock; and a writing circuit that, when a fault of the pin electronic device is detected, writes the date and time represented by the internal clock as the fault detection date and time associated with the fault information to the recording medium.

[0029] In any of the above-described pin electronic devices, the monitoring circuit may encrypt at least a part of the fault information and record it to the recording medium.

[0030] In any of the above-described pin electronic devices, the monitoring circuit may encrypt the component identification information contained in the fault information for identifying the faulty component.

[0031] Any of the above-described pin electronic devices may include: a main board; and a plurality of sub-boards mounted on the main board, with a monitoring circuit and a recording medium mounted on each sub-board.

[0032] In a second embodiment of the present invention, a test device is provided, including: one or more pin electronic devices; a control device for controlling the one or more pin electronic devices; and a connection device for connecting between the one or more pin electronic devices and one or more devices under test.

[0033] In a third embodiment of the present invention, a method is provided, including: a pin electronic device connected to a device under test tests the device under test; and in a case where the pin electronic device detects a fault, the pin electronic device records fault information related to the fault in a recording medium that can be read without receiving power supply from a power circuit within the pin electronic device.

[0034] In addition, the above description of the invention does not list all features of the present invention. Moreover, sub-combinations of these feature groups can also form an invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 shows the structure of the test device 1 of this embodiment.

[0036] Figure 2 shows the structure of the pin electronic device 110 of this embodiment.

[0037] Figure 3 shows the power supply monitoring process of the pin electronic device 110 of this embodiment.

[0038] Figure 4 shows the fault monitoring process of the pin electronic device 110 of this embodiment.

[0039] Figure 5 shows the structure of the test head 100 of this embodiment as viewed from the mounting surface side of the connection device 120.

[0040] Figure 6 shows the structure of the pin electronic device 610 of the first modification.

[0041] Figure 7 shows the structure of the pin electronic device 710 of the second modification.

[0042] Figure 8 shows the structure of the pin electronic device 810 of the third modification.

[0043] Figure 9 shows an example of a computer 2200 in which multiple forms of the present invention can be embodied as a whole or in part. DETAILED DESCRIPTION OF THE INVENTION

[0044] ​​​​​​​​​Hereinafter, the present invention will be described by way of embodiments of the invention. However, the following embodiments do not limit the invention claimed. Moreover, not all combinations of the features described in the embodiments are necessarily required for the solution of the invention.

[0045] Figure 1 The structure of the test device 1 of the present embodiment and the device under test (DUT) 10 are shown together. The DUT 10 is an element in which a circuit that is the object of testing of the test device 1 is formed. The DUT 10 may be a wafer in which a circuit is formed, an integrated circuit / large-scale integration (IC / LSI) chip obtained by singulating the wafer, or an IC / LSI package formed by packaging the IC / LSI chip. In the example of this figure, the test device 1 mounts one DUT 10. However, instead of this, the test device 1 may mount a plurality of DUTs 10 to perform tests simultaneously.

[0046] The test device 1 performs electrical tests on the DUT 10. Instead of this or in addition to this, the test device 1 may also perform optical input / output tests on the DUT 10. In the present embodiment, the case where the test device 1 performs electrical tests on the DUT 10 will be described as an example. In the case where the test device 1 performs optical input / output tests on the DUT 10, the test device 1 and the DUT 10 are connected by optical connection instead of electrical connection.

[0047] The test device 1 includes a test head 100, a plurality of pin electronics 110, a connection device 120, and a main frame 150. The test head 100 is a housing that can mount a plurality of pin electronics 110. In the example of this figure, the test head 100 has a plurality of slots for inserting a plurality of pin electronics 110.

[0048] The plurality of pin electronics 110 are respectively inserted into the slots of the test head 100, so as to be detachably connected to the backplane of the test head 100. The pin electronics 110 may also be referred to as "pin electronic cards", "test boards", or "test modules", etc. Each pin electronics 110 is electrically connected to the DUT 10 via the connection device 120. Each pin electronics 110 inputs / outputs signals to / from the DUT 10, and tests the DUT 10 by checking the signals input from the DUT 10.

[0049] The connection device 120 is mounted on the test head 100 and electrically connected to a plurality of pin electronic devices 110. The connection device 120 mounts the DUT 10 and is electrically connected to a plurality of terminals of the DUT 10. The connection device 120 functions as an interface between the terminals of the plurality of pin electronic devices 110 and the DUT 10, and electrically connects the respective terminals of one or more DUTs 10 and the corresponding terminals of the plurality of pin electronic devices 110 through signal cables or substrate wirings, etc.

[0050] The main frame 150 controls each part in the test device 1 to test the DUT 10. In the present embodiment, the main frame 150 is a frame independent of the frame provided with the test head 100, etc. Instead, each structure in the main frame 150 may also be provided in the same frame as the test head 100. The main frame 150 has a main power supply device 160 and a control device 170.

[0051] The main power supply device 160 receives power supply from a commercial power supply, etc., and supplies power to each device and circuit, etc. in the test device 1. The control device 170 is connected to the main power supply device 160 and receives power supply from the main power supply device 160. The control device 170 controls the test of the DUT 10. When the control device 170 is implemented by a computer, it can control the test of the DUT 10 by executing a test control program. The control device 170 supplies a test program to each pin electronic device 110 and causes each pin electronic device 110 to execute it, thereby testing the DUT 10. The control device 170 collects the test results of the DUT 10 from each pin electronic device 110 and records them.

[0052] Figure 2 Shows the structure of the pin electronic device 110 of the present embodiment. The pin electronic device 110 includes a power supply circuit 200, a test circuit 210, a test control circuit 220, a monitoring circuit 230, a capacitor 250, a recording medium 260, and an antenna 270.

[0053] The power supply circuit 200 receives power supply from the main power supply device 160 and generates power to be supplied to each circuit in the pin electronic device 110, and supplies the power to each circuit in the pin electronic device 110. The power supply circuit 200 may have a plurality of power supplies 205a to 205d (also denoted as "power supply 205"). The plurality of power supplies 205 may output powers such as rated voltages or rated currents that are different from each other. Moreover, when the same rated voltage or rated current, etc. of power is frequently used in the pin electronic device 110, the same rated voltage or rated current, etc. of power may be output by two or more power supplies 205.

[0054] The test circuit 210 is connected to the DUT 10 via the connection device 120 to test the DUT 10. The test circuit 210 for the operation test of the DUT 10 may include various circuits for transmitting and receiving signals with the DUT 10 to determine the quality of the DUT 10. The various circuits include a pattern generator for generating a test pattern, a timing generator for generating a timing, a waveform shaper for shaping the test pattern using the timing generated by the timing generator and outputting a test signal, a driver circuit for amplifying the test signal and outputting it to the DUT 10, a comparator for comparing the response signal from the DUT 10 with a target value, or a determiner for determining the quality of the DUT 10 using the comparison result obtained by the comparator. Moreover, the test circuit 210 for the parameter test of the DUT 10 may include various circuits, and the various circuits include at least one of a voltage generator for generating a voltage supplied to the DUT 10, a current generator for generating a current supplied to the DUT 10, a voltage measurer for measuring the voltage output by the DUT 10, a current measurer for measuring the current output by the DUT 10, a frequency measurer for measuring the frequency of the signal output by the DUT 10, etc.

[0055] The test control circuit 220 controls the test of the DUT 10 by the test circuit 210. The test control circuit 220 may also be referred to as a "site controller". The test control circuit 220 executes a test program supplied from the control device 170 to control each part in the test circuit 210, whereby the test circuit 210 performs tests such as an operation test or a parameter test of the DUT 10.

[0056] The monitoring circuit 230 is connected to the power supply circuit 200, the test circuit 210, and the test control circuit 220. The monitoring circuit 230 monitors each component, and the components include various electronic components (such as Application Specific Integrated Circuit (ASIC), LSI, or IC, etc.) in the pin electronic device 110, such as the power supply circuit 200, the test circuit 210, and the test control circuit 220 in the pin electronic device 110, each circuit, discrete components, and mechanical components, etc. When the monitoring circuit 230 detects a fault in the pin electronic device 110, it records fault information related to the fault in the recording medium 260. When the monitoring circuit 230 detects a fault in the power supply circuit 200, that is, an abnormality in the power supply from the power supply circuit 200, before the power supply to the monitoring circuit 230 is blocked, it records fault information including power supply identification information in the recording medium 260. Here, the monitoring circuit 230 records fault information including power supply identification information for identifying the power supply 205 with an abnormal power supply detected among the multiple power supplies 205 in the recording medium 260.

[0057] In addition, in this specification, the so-called "abnormality in power supply" may include two cases: the output of the power supply circuit 200 (or each power supply 205) does not meet the power specifications (such as voltage specifications, current specifications, etc.) and the temperature of the power supply circuit 200 (or each power supply 205) does not meet the temperature specifications (such as the upper limit temperature, etc.).

[0058] The monitoring circuit 230 includes a voltage detection circuit 235, a temperature detection circuit 240, and a microcontroller 245. The voltage detection circuit 235 is connected to each of the multiple power supplies 205. For each power supply 205 among the multiple power supplies 205a to 205d, the voltage detection circuit 235 detects whether the output voltage of the power supply 205 is outside the reference voltage range specified in advance for each power supply 205. The voltage detection circuit 235 may include a comparison circuit that compares the output voltage of the power supply 205 with each of the rated upper limit voltage and the rated lower limit voltage of the output voltage of the power supply 205. The voltage detection circuit 235 can detect an abnormality in the power supply 205 when the output voltage of the power supply 205 deviates from the reference voltage range from the rated lower limit voltage to the rated upper limit voltage.

[0059] The temperature detection circuit 240 is connected to the power supply circuit 200. The temperature detection circuit 240 detects whether the temperature associated with each power supply 205 exceeds a preset reference temperature. The temperature detection circuit 240 can detect an abnormality in the power supply 205 when the temperature indicated by the temperature detection signal from a temperature sensor such as a thermistor provided near each power supply 205 exceeds the rated upper limit temperature.

[0060] Moreover, the temperature detection circuit 240 can detect whether the temperature of each component within the pin electronic device 110 has exceeded a pre-specified reference temperature. Such a reference temperature can be specified individually for each component, or can be specified jointly for two or more components.

[0061] The microcontroller 245 is connected to various circuits or components to be monitored such as the power supply circuit 200, the test circuit 210, and the test control circuit 220, the voltage detection circuit 235, and the temperature detection circuit 240. The microcontroller 245 may include a control or general-purpose central processing unit (Central Processing Unit, CPU). The microcontroller 245 monitors the faults (including temperature monitoring) of each component within the pin electronic device 110, monitors the multiple power supplies 205, and writes the fault information to the recording medium 260 by executing a monitoring program.

[0062] The microcontroller 245 includes an internal clock 246, a clock setting circuit 247, and a writing circuit 248. The internal clock 246 outputs the current date and time. For example, the internal clock 246 can be set to a certain date and time, and the internal time is updated whenever a pre-specified time has elapsed from this date and time, thereby representing the current time. Moreover, the internal clock 246 can have a timing counter that is reset at a certain date and time and incremented whenever a pre-specified time has elapsed, and the current date and time is calculated using the elapsed time counted from the reset date and time indicated by the timing counter.

[0063] The clock setting circuit 247 sets the current date and time received from an external device of the pin electronic device 110 to the internal clock 246. The clock setting circuit 247 can receive the writing of the current date and time from the control device 170 at the startup of the test device 1 or periodically to set the current date and time. Additionally, the microcontroller 245 may not include the internal clock 246 and the clock setting circuit 247 if the fault detection date and time is not associated with the fault information and recorded to the recording medium 260.

[0064] The writing circuit 248 records the fault information related to the fault to the recording medium 260 in case a fault of the pin electronic device 110 is detected. In case an abnormality in the power supply from the power supply circuit 200 is detected by the voltage detection circuit 235 or the temperature detection circuit 240, the writing circuit 248 includes the power supply identification information for identifying the power supply 205 where the abnormality is detected in the fault information and records it to the recording medium 260. Moreover, in case a fault of the test circuit 210, the test control circuit 220, or other components of the pin electronic device 110 is detected, the writing circuit 248 records the fault information including the component identification information for identifying the component where the fault has occurred to the recording medium 260.

[0065] In addition, the monitoring circuit 230 may also have dedicated hardware to replace the microcontroller 245, and the dedicated hardware implements the operations that the microcontroller 245 should perform through dedicated circuits. Moreover, the monitoring circuit 230 may also perform only one or two of the fault detection of each component within the pin electronics 110, the fault detection of each power supply 205 by the voltage detection circuit 235, and the fault detection of each power supply 205 by the temperature detection circuit 240. When the monitoring circuit 230 does not perform the fault detection of each power supply 205 by the voltage detection circuit 235, it may not have the voltage detection circuit 235. When the monitoring circuit 230 does not perform the fault detection of each power supply 205 by the temperature detection circuit 240, it may not have the temperature detection circuit 240.

[0066] The capacitor 250 is connected to the power supply circuit 200. The capacitor 250 stores the power from at least one of the multiple power supplies 205. The capacitor 250 may have a capacitor for storing power or a small rechargeable battery.

[0067] The capacitor 250 may store the power from the power supply 205 that supplies power to the monitoring circuit 230 among the multiple power supplies 205 and supply it to the monitoring circuit 230. Thus, the monitoring circuit 230 can record the power supply identification information to the non-volatile recording medium 260 after the power supply from the power supply circuit 200 is interrupted and before the power supply from the capacitor 250 is interrupted.

[0068] The recording medium 260 is connected to the monitoring circuit 230. The recording medium 260 receives a write request for the fault information from the monitoring circuit 230 and stores the fault information. The recording medium 260 can store a set of fault information and can also store multiple sets of fault information. The recording medium 260 may be a non-volatile recording medium such as a flash memory so that the stored fault information will not be lost even after the power supply from the power supply circuit 200 is interrupted.

[0069] Moreover, the recording medium 260 can be a recording medium that can be read without receiving power supply from a power source such as the power supply circuit 200 provided in the pin electronic device 110. For example, the recording medium 260 can also be implemented using a Radio Frequency Identification (RFID) that is connected to the antenna 270 and can be read through short-range wireless communication. The antenna 270 is used to access the information (data) recorded in the recording medium 260 through short-range wireless communication. The antenna 270 can receive the power for operating the recording medium 260 from an external terminal or the like through wireless power supply and supply it to the recording medium 260, and operate the recording medium 260 with this power. Also, according to the protocol of short-range wireless communication, the antenna 270 supplies a read request from an external terminal or the like to the recording medium 260, and returns the information read from the recording medium 260 to the external terminal or the like.

[0070] In addition, the recording medium 260 can also be built into the monitoring circuit 230. Moreover, the microcontroller 245 can also use at least a part of the non-volatile memory built into the microcontroller 245 as the recording medium 260.

[0071] Figure 3 This shows the power supply monitoring process of the pin electronic device 110 of the present embodiment. The pin electronic device 110 starts the power supply monitoring process of this figure in a state where the power supply circuit 200 normally supplies power to each circuit in the pin electronic device 110.

[0072] In S300, the microcontroller 245 in the monitoring circuit 230 monitors the state of the power supply circuit 200. In S310, the microcontroller 245 determines whether an abnormality in the power supply performed by the power supply circuit 200 is detected. The microcontroller 245 detects an abnormality in the power supply 205 corresponding to the case where the output voltage of each power supply 205 is outside the reference voltage range specified for this power supply 205, or the case where the temperature of each power supply 205 exceeds the reference temperature specified for this power supply 205. When the microcontroller 245 detects an abnormality in the power supply, it acquires the date and time indicated by the internal clock 246 as the failure detection date and time.

[0073] When the power supply is normal, the microcontroller 245 advances the process to S300 and continues to monitor the state of the power supply circuit 200 ("No" in S310). When the power supply is abnormal, the microcontroller 245 advances the process to S320 ("Yes" in S310).

[0074] In S320, when the monitoring circuit 230 corresponds to a situation where the power supply from the power supply circuit 200 is blocked and power is received from the capacitor 250, it shifts to a power-saving mode with less power consumption than during normal operation. For example, the monitoring circuit 230 can reduce power consumption by stopping the power supply to at least one of the voltage detection circuit 235 or the temperature detection circuit 240, or by shifting the microcontroller 245 to the power-saving mode to block the power supply to a part of the circuits within the microcontroller 245, or by changing the operating frequency of the microcontroller 245, etc. Additionally, even in the normal operation mode, but when the power supply from the power supply circuit 200 is blocked and the monitoring circuit 230 can write the fault information to the recording medium 260 before the power supply to the monitoring circuit 230 is blocked, the monitoring circuit 230 may not execute S320.

[0075] In S330, the monitoring circuit 230 collects power supply abnormality information used as fault information in the case of a power supply abnormality. The power supply abnormality information as the fault information may include power supply identification information as part identification information, and may include fault type information indicating the type of fault, or detailed part information (product model number, serial number, manufacturing date, manufacturer, etc.) of the part (power supply circuit 200, power supply 205, etc.) where the fault occurred, the output voltage of each power supply 205 or the faulty power supply 205 measured by the voltage detection circuit 235, the temperature of each power supply 205 or the faulty power supply 205 detected by the temperature detection circuit 240, and various other information related to the fault. Additionally, the part identification information may include more detailed information in addition to information sufficient to identify the part where the fault occurred within the pin electronic device 110 (for example, a unique part ID within the pin electronic device 110), and the more detailed information includes at least one of the product model number, serial number, manufacturing date, or manufacturer, etc.

[0076] In S340, before the power supply to the monitoring circuit 230 is blocked, the monitoring circuit 230 records the power supply abnormality information including the power supply identification information as fault information to the recording medium 260. The monitoring circuit 230 may record the fault detection date and time to the recording medium 260 in association with the power supply abnormality information.

[0077] The monitoring circuit 230 may encrypt at least a part of the fault information and record it to the recording medium 260. For example, the monitoring circuit 230 may encrypt at least one of the power supply identification information contained in the fault information, the detailed part information of the faulty power supply circuit 200 or power supply 205, or the fault type information, etc. Thereby, the monitoring circuit 230 can prevent further damage to the pin electronic device 110 caused by an inappropriate part replacement by a third party who is not familiar with the pin electronic device 110.

[0078] After the power supply from the power supply circuit 200 is interrupted, in S350, the recording medium 260 is read by short-range wireless communication or the like without the power supply from the power supply circuit 200. Further, in the case of a power supply abnormality to the extent that the power supply 205 supplying power to the monitoring circuit 230 does not need to be cut off, or in the case where the test device 1 has been restarted or the like, the control device 170 can read the recording medium 260 to obtain the failure detection date and time and the failure information.

[0079] According to the pin electronic device 110 shown above, the recording medium 260 can maintain the written failure information and the like even when the power supply from the power supply circuit 200 is interrupted due to a failure of the power supply circuit 200. Therefore, the pin electronic device 110 can provide failure information and the like to a user such as a maintenance person of the test device 1 or an external device such as the control device 170 even after the test device 1 is shut down or the power supply from the power supply circuit 200 is interrupted.

[0080] Moreover, the recording medium 260 records the failure information including the power supply identification information for identifying the power supply 205 in which an abnormality in the power supply is detected in the recording medium 260, so that it is possible to easily determine the power supply 205 in which a failure has occurred among the plurality of power supplies 205. Further, even in the case where the power supply 205 intermittently has an abnormality, or in the case where the power supply 205 has an abnormality only under certain conditions, the pin electronic device 110 records the detected abnormal power supply 205 in an identifiable manner in the recording medium 260, so that the repairability, product quality, or mean time to repair (MTTR) of the pin electronic device 110 can be improved. Moreover, the pin electronic device 110 records the failure detection date and time in association with the failure information in the recording medium 260, whereby information that makes it easier for the user of the test device 1 to identify the cause of a permanent failure, an intermittent abnormality, or a temporary abnormality caused by external noise such as lightning in the parts within the pin electronic device 110 can be provided.

[0081] Further, the control device 170 or the pin electronic device 110 can be configured to control the power supply circuit 200 to interrupt the power supply of the pin electronic device 110 in a predetermined power interruption sequence. At this time, the power supply circuit 200 interrupts the plurality of power supplies 205a to 205d in the order of the predetermined power interruption sequence in response to the detection of an abnormality in the power supply. In such a configuration, the monitoring circuit 230 can also receive power supply from the power supply 205 to be interrupted after at least one other power supply 205 among the plurality of power supplies 205a to 205d is interrupted.

[0082] For example, in the case where the power supply circuit 200 cuts off power supply every 400 ms in the order of power supply 205d, power supply 205c, power supply 205b, and power supply 205a, there is a delay of 1200 ms from when the power supply from power supply 205d is cut off until the power supply from power supply 205a is cut off. The monitoring circuit 230 starts writing fault information to the recording medium 260 after the start of the interruption of the power supply by receiving power supply from power supply 205a, and can complete the writing of the fault information before the power supply from power supply 205a is cut off. In this way, the monitoring circuit 230 can be configured to receive power supply from the power supply 205 that cuts off the power supply only after the writing of the fault information is completed after detecting an abnormality in the power supply. The monitoring circuit 230 can also receive power supply from the power supply 205 that is the last to be cut off in the power supply cut-off sequence among the plurality of power supplies 205.

[0083] Figure 4 FIG. shows the fault monitoring process of the pin electronic device 110 of the present embodiment. The pin electronic device 110 starts the fault monitoring process of this figure when each circuit in the pin electronic device 110 is operating normally. The pin electronic device 110 can also start the fault monitoring process of this figure in self-diagnosis performed when the power supply of the test device 1 is turned on or the like. In addition, since the fault of the power supply circuit 200 is a kind of part fault in the pin electronic device 110, Figure 3 the power supply monitoring process shown can be a form or subset of the fault monitoring process of this figure.

[0084] In S400, the microcontroller 245 in the monitoring circuit 230 monitors the states of the respective parts in the pin electronic device 110. In S410, the microcontroller 245 determines whether an abnormality in the parts in the pin electronic device 110 is detected. Each part in the pin electronic device 110 has various error detectors for detecting abnormalities such as parity / error correcting code (ECC) errors, queue overflow / underflow, or detection of undefined instructions. The microcontroller 245 detects an abnormality in the part having this error detector in response to receiving an error detection signal indicating the occurrence of an abnormality from the error detector. The microcontroller 245 can detect an abnormality in a certain part in response to the temperature detection circuit 240 detecting that the temperature of the part exceeds the reference temperature specified for this part.

[0085] Moreover, in the self-diagnosis of the test device 1, the pin electronic device 110 performs self-diagnosis tests on internal components. The microcontroller 245 can detect component abnormalities corresponding to the results of the self-diagnosis tests. When the microcontroller 245 detects a failure of the pin electronic device 110, it obtains the date and time represented by the internal clock 246 as the failure detection date and time.

[0086] When all components are normal, the microcontroller 245 advances the process to S400 and continues to monitor the status of each component ("No" in S410). When any component is abnormal, the microcontroller 245 advances the process to S420 ("Yes" in S410).

[0087] In S420, in response to detecting an abnormality in a component, the monitoring circuit 230 switches to a power-saving mode with lower power consumption than during normal operation. For example, the monitoring circuit 230 can reduce power consumption by stopping the power supply to at least one of the voltage detection circuit 235 or the temperature detection circuit 240, or by switching the microcontroller 245 to the power-saving mode to block the power supply to a part of the circuits inside the microcontroller 245, or by decreasing the operating frequency of the microcontroller 245. Additionally, when a severe abnormality such as a power short circuit or a mechanical failure that requires an emergency shutdown of the test device 1 occurs and the power supply to the monitoring circuit 230 is cut off, the monitoring circuit 230 switches to the power-saving mode. In the case of a minor abnormality where the test device 1 can continue to operate, S420 may not be executed.

[0088] In S430, the monitoring circuit 230 collects fault information. The fault information can include component identification information and can also include various information related to the fault such as fault type information, detailed component information, status values or internal data of each component or the component where the fault occurred.

[0089] In S440, before the power supply to the monitoring circuit 230 is cut off, the monitoring circuit 230 records the fault information to the recording medium 260. The monitoring circuit 230 can record the fault detection date and time associated with the fault information to the recording medium 260.

[0090] The monitoring circuit 230 can encrypt at least a part of the fault information and record it to the recording medium 260. For example, the monitoring circuit 230 can encrypt at least one of the component identification information identifying the component where the fault occurred, the detailed component information of the component where the fault occurred, or the fault type information.

[0091] In the event of a severe abnormality, in S450, the test device 1 shuts down. Accordingly, the power supply circuit 200 within the pin electronic device 110 stops supplying power to each circuit within the pin electronic device 110. After the power supply from the power supply circuit 200 is stopped, in S460, the recording medium 260 is read through short-range wireless communication or the like without power supply from the power supply circuit 200. In the case of a power supply abnormality to the extent that power supply to the monitoring circuit 230 does not need to be interrupted, or in the case where the test device 1 has been restarted or the like, the control device 170 can read the recording medium 260 to obtain the failure detection date and time and failure information.

[0092] According to the pin electronic device 110 shown above, the recording medium 260 can maintain the written failure information even when the test device 1 shuts down due to a failure in a circuit or component within the pin electronic device 110. Therefore, the pin electronic device 110 can provide failure information to an external device such as a user of the test device 1 or the control device 170 even after the test device 1 shuts down or after the power supply from the power supply circuit 200 is interrupted.

[0093] Moreover, since the recording medium 260 records failure information including component identification information for identifying a failed component to the recording medium 260, it is possible to easily identify the failed component among multiple components. For example, an ASIC / LSI / IC within the pin electronic device 110 may sometimes be equipped with a heat sink for cooling, or may be enclosed in a water jacket for liquid cooling. When the recording medium 260 records at least one of the product model, serial number, manufacturing date, or manufacturer of such a component as component identification information, a user of the test device 1 can obtain detailed component identification information without removing the heat sink or the like.

[0094] Moreover, according to the pin electronic device 110 shown above, by using a recording medium that can be read without receiving power supply from the power supply circuit 200 as the recording medium 260, it is possible to provide failure information to a user of the test device 1 or an external device without turning on the power supply of the pin electronic device 110 even after the test device 1 shuts down or after the power supply from the power supply circuit 200 is interrupted.

[0095] In addition, before detecting an abnormality in the power supply or a failure of the pin electronic device 110, the monitoring circuit 230 can pre-write part information about each of the multiple parts mounted on the pin electronic device 110 in association with part identification information to the recording medium 260. Moreover, before detecting an abnormality in the power supply or a failure of the pin electronic device 110, the monitoring circuit 230 can pre-write other information that can be pre-written to the recording medium 260 to the recording medium 260. By pre-writing as much information as possible to the recording medium 260 before detecting an abnormality in the power supply or a failure of the pin electronic device 110, it is possible to reduce the size of the information written to the recording medium 260 by the monitoring circuit 230 after detecting the abnormality in the power supply or the failure of the pin electronic device 110, and thus reduce the writing time to the recording medium 260.

[0096] Figure 5 shows the structure of the test head 100 of the present embodiment as viewed from the mounting surface side of the connection device 120 ( Figure 1 the upper surface side of the test head 100 in the test device 1). The multiple pin electronic devices 110 are respectively inserted into the slots of the test head 100, and the connection device 120 and the edges on the DUT 10 side are exposed on the outer surface of the test head 100. The pin electronic device 110 has one or more connectors 520a to 520c (also denoted as "connector 520") and an antenna 270 at the edges on the connection device 120 and DUT 10 sides.

[0097] Each connector 520 is connected to a corresponding connector on the surface of the connection device 120 on the test head 100 side. Thus, the pin electronic device 110 is electrically connected to the DUT 10 via the connection device 120.

[0098] The antenna 270 is provided on the outer surface of the pin electronic device 110 that is exposed to the outside when the pin electronic device 110 is mounted on the test head 100. In the example of this figure, the antenna 270 is provided on the outer surface of the pin electronic device 110 where the connectors 520a to 520c electrically connected to the DUT 10 are mounted. Thus, by removing the connection device 120 mounted on the test head 100, even if the pin electronic device 110 is not removed from the test head 100, the antenna 270 will be exposed to the outside. In this state, the recording medium 260 can be read by using the near-field wireless communication of the antenna 270.

[0099] The recording medium 260 can receive power supply by short-range wireless power supply via the antenna 270 from a terminal device that reads failure information to read the failure information, and supply the failure information to the terminal device via short-range wireless communication via the antenna 270. The recording medium 260 can receive power supply by short-range wireless power supply via the antenna 270 from the terminal device to operate, and supply the failure information to the terminal device by short-range wireless communication.

[0100] Therefore, by bringing the terminal carried by the user of the test device 1 close to the antenna 270 of each pin electronic device 110, the user can read the failure occurrence date and time and failure information recorded in the recording medium 260 in each pin electronic device 110 for confirmation. The user can confirm the failure information read from each pin electronic device 110 to determine the pin electronic device 110 in which an abnormality has occurred among the plurality of pin electronic devices 110, and thus can remove the pin electronic device 110 in which an abnormality has occurred from the test head 100 for inspection or replacement.

[0101] Moreover, a terminal that reads the failure information of the pin electronic device 110 via the antenna 270 can upload the failure information etc. to a server device (such as a cloud server) on the Internet or an intranet via a wireless communication network. Thereby, the server device can centrally manage the failure information etc. of the pin electronic devices 110 mounted in the plurality of test devices 1 installed in various places, and the manufacturer or maintenance management company of the test device 1 can confirm the status of each test device 1.

[0102] In addition, the recording medium 260 can also be read under the control of the microcontroller 245 without receiving power supply from the power supply circuit 200. At this time, the microcontroller 245 receives power supply by short-range wireless power supply via the antenna 270 from the terminal device that reads the failure information, and reads the failure information from the recording medium 260. And the microcontroller 245 supplies the failure information to the terminal device via short-range wireless communication via the antenna 270.

[0103] More specifically, when the microcontroller 245 starts power supply and starts up, and receives power supply by short-range wireless power supply without receiving power supply from the power supply circuit 200, it migrates to a mode of processing a read request for the recording medium 260 from the outside. In this mode, when the microcontroller 245 receives a read request for the recording medium 260 via the antenna 270, it reads the requested information (data) from the recording medium 260 and returns it via short-range wireless communication via the antenna 270.

[0104] Figure 6 Shows the structure of the pin electronic device 610 representing the first modification. The test device 1 can also replace Figures 1 to 5The pin electronic device 110 shown includes a pin electronic device 610. The pin electronic device 610 is a modified example of the pin electronic device 110, so the following description is omitted except for the differences.

[0105] The pin electronic device 610 has a main board 615 and one or more connectors 620a to 620c (also denoted as "connector 620"). The main board 615 is mounted Figure 2 The various circuits and components shown. This figure shows the structure of the pin electronic device 610 when viewed from the component mounting surface side of the main board 615. Here, the component mounting surface side of the pin electronic device 610 becomes the upper surface side when the pin electronic device 610 taken out from the test head 100 is placed on a table or the like. The antenna 270 is provided at the edge of the upper surface of the pin electronic device 610 where one or more connectors 620 connected to the DUT 10 are mounted. The antenna 270 may also be provided at a corner on the side of the upper surface of the pin electronic device 610 where one or more connectors 620 are mounted. One or more connectors 620 and Figure 5 The one or more connectors 520 shown are the same, so the description is omitted.

[0106] The pin electronic device 610 has the antenna 270 at the edge of the upper surface where the respective connectors 620 are mounted, so that it is not necessary to bring the terminal close to the central part of the various circuits densely mounted in the pin electronic device 110, etc., and the recording medium 260 can be read by using the short-range wireless communication of the antenna 270. Thus, the pin electronic device 610 can reduce the risk of damage to the pin electronic device 610 caused by dropping of the terminal or the like.

[0107] Moreover, the main board 615 may have the following structure, that is, at the edge where the respective connectors 620 are mounted, the wiring is concentrated to the respective connectors 620, and it is easy to ensure a region without a wiring pattern outside the vicinity of the respective connectors 620. In this case, the main board 615 can avoid having other wiring patterns in the layer where the antenna 270 is provided and its upper and lower layers by having the antenna pattern of the antenna 270 at the edge where the respective connectors 620 are mounted, thereby being able to suppress interference with the short-range wireless communication. In addition, the antenna 270 may also be provided at other parts of the upper surface of the pin electronic device 110 corresponding to the arrangement of the components or wiring patterns of the main board 615.

[0108] Figure 7 Shows the structure of the pin electronic device 710 which is a second modified example. The test device 1 may also replace Figures 1 to 5 The pin electronic device 110 shown and Figure 6The pin electronic device 610 shown includes a pin electronic device 710. The pin electronic device 710 is a modified example of the pin electronic device 110 and the pin electronic device 610. Therefore, the following description is omitted except for the differences.

[0109] The pin electronic device 710 has a main board 715, one or more connectors 720a to 720c (also denoted as "connector 720"), and a monitoring connector 730. The main board 715 mounts Figure 2 the various circuits and components shown. This figure shows the structure of the pin electronic device 710 when viewed from the component mounting surface side of the main board 715. Here, the component mounting surface side of the pin electronic device 710 becomes the upper surface side when the pin electronic device 710 taken out from the test head 100 is placed on a table or the like. One or more connectors 720 are Figure 5 the same as one or more connectors 520 shown or Figure 6 one or more connectors 620 shown, and thus the description is omitted.

[0110] The monitoring connector 730 is provided in place of the antenna 270 and is used to wire-connect a terminal 790 for reading failure information to the recording medium 260. The recording medium 260 can receive power supply from the terminal 790 via the monitoring connector 730. The recording medium 260 reads the failure information according to a read request from the terminal 790 and supplies the failure information to the terminal 790 through wired communication via the monitoring connector 730.

[0111] The monitoring connector 730 can be provided on the outer surface of the pin electronic device 710 where the connectors 720a to 720c electrically connected to the DUT 10 are mounted. Thus, by disassembling the connecting device 120 mounted on the test head 100, even if the pin electronic device 110 is not disassembled from the test head 100, the monitoring connector 730 is exposed to the outside. In this state, the recording medium 260 can be read through wired communication using the monitoring connector 730.

[0112] Alternatively, the monitoring connector 730 can also be provided at the edge or the like of the upper surface of the pin electronic device 710 where one or more connectors 720 connected to the DUT 10 are mounted. At this time, the monitoring connector 730 can be accessed in a state where the pin electronic device 710 is disassembled from the test head 100 and placed on a table or the like.

[0113] In addition, the recording medium 260 can also be read under the control of the microcontroller 245 without receiving power supply from the power supply circuit 200. At this time, the microcontroller 245 receives power supply from the terminal 790 via the monitoring connector 730, reads the failure information from the recording medium 260, and supplies the failure information to the terminal device via the monitoring connector 730.

[0114] Figure 8 The structure of the pin electronic device 810 showing the third modification example. The test device 1 can also replace Figures 1 to 5 the pin electronic device 110 shown in Figure 6 the pin electronic device 610 shown in Figure 7 and the pin electronic device 710 shown in and include the pin electronic device 810. Since the pin electronic device 810 is a modification example of the pin electronic device 110, the pin electronic device 610, and the pin electronic device 710, the following description is omitted except for the differences.

[0115] The pin electronic device 810 includes a main board 815, one or more daughter boards 825a to 825c (also denoted as "daughter board 825"), and one or more connectors 820a to 820c (also denoted as "connector 820"). The main board 815 mounts one or more daughter boards 825. This figure shows the structure of the pin electronic device 810 when viewed from the side of the main board 815 on which the daughter board 825 is mounted. Here, the side of the main board 815 on which the daughter board 825 is mounted becomes the upper surface side when the pin electronic device 810 taken out from the test head 100 is placed on a table or the like.

[0116] One or more daughter boards 825 are mounted on the main board 815. Each daughter board 825 can be respectively installed with Figure 2 each circuit or component included in the pin electronic device 110 shown in. Along with this, one or more daughter boards 825 can mount a monitoring circuit 827 and an antenna 830 on each daughter board 825. Therefore, the pin electronic device 810 includes one or more monitoring circuits 827a to 827c (also denoted as "monitoring circuit 827") and one or more antennas 830a to 830c (also denoted as "antenna 830") mounted on the respectively corresponding daughter boards 825. Here, each monitoring circuit 827 can have the same function and structure as Figure 1 the monitoring circuit 230 shown in Figure 1 and each antenna 830 can have the same function and structure as

[0117] By providing a monitoring circuit 827 and an antenna 830 on each daughter board 825, the pin electronic device 810 can read out failure information and the like recorded in the recording medium 260 on each of one or more daughter boards 825 through short-range wireless communication. Therefore, the user of the test device 1 can read out the failure occurrence date and time and the failure information recorded in the recording medium 260 within each daughter board 825 by bringing the terminal carried by himself / herself close to the antenna 830 of each daughter board 825 for confirmation. The user can confirm the failure information read out from each daughter board 825 and determine the daughter board 825 in which an abnormality has occurred from one or more daughter boards 825, and thus can disassemble the daughter board 825 in which an abnormality has occurred from the pin electronic device 810 for inspection or replacement.

[0118] Various embodiments of the present invention can be described with reference to flowcharts and block diagrams. Here, a block can represent (1) a stage of a process that performs an operation or (2) a part of a device that has a function of performing an operation. A specific stage and part can be implemented by a dedicated circuit, a programmable circuit provided together with computer-readable instructions stored on a computer-readable medium, and / or a processor provided together with computer-readable instructions stored on a computer-readable medium. The dedicated circuit can include digital and / or analog hardware circuits and can include integrated circuits (ICs) and / or discrete circuits. The programmable circuit can include a reconfigurable hardware circuit, and the reconfigurable hardware circuit includes memory elements such as logical AND (AND), logical OR (OR), Exclusive OR (XOR), Not AND (NAND), Not OR (NOR), and other logical operations, flip-flops, registers, Field Programmable Gate Arrays (FPGAs), Programmable Logic Arrays (PLAs), and the like.

[0119] A computer-readable medium may include any tangible element capable of storing instructions to be executed by appropriate components. As a result, a computer-readable medium having instructions stored therein will include the products described below, i.e., this product contains instructions that may be executed for fabricating components for performing the operations specified in a flowchart or block diagram. As examples of computer-readable media, it may include electronic storage media, magnetic storage media, optical storage media, electromagnetic storage media, semiconductor storage media, etc. As more specific examples of computer-readable media, it may include floppy (registered trademark) disks, diskettes, hard disks, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (electrically programmable read only memory (EPROM) or flash memory), electronically erasable programmable read only memory (EEPROM), static random access memory (SRAM), compact disc read only memory (CD-ROM), digital versatile disc (DVD), Blu-ray (registered trademark) disc, memory sticks, integrated circuit cards, etc.

[0120] Computer-readable instructions may include either source code or object code described in any combination of one or more programming languages, the one or more programming languages including assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, or object-oriented programming languages such as Smalltalk (registered trademark), JAVA (registered trademark), C++, etc., and legacy procedural programming languages such as the "C" programming language or the like.

[0121] Computer-readable instructions may be provided locally or to a processor or programmable circuit of a programmable data processing apparatus such as a general-purpose computer, a special-purpose computer, or other computers via a local area network (LAN), a wide area network (WAN) such as the Internet, etc., and the computer-readable instructions are executed to fabricate components for performing operations specified by a flowchart or block diagram. As examples of the processor, a computer processor, a processing unit, a microprocessor, a digital signal processor, a controller, a microcontroller, etc. are included.

[0122] Figure 9 This is an example of the computer 2200 in which multiple aspects of the present invention may be implemented in whole or in part. The program installed in the computer 2200 may cause the computer 2200 to function as an operation associated with the apparatus of an embodiment of the present invention or one or more parts of the apparatus, or may cause the computer 2200 to execute the operation or the one or more parts, and / or may cause the computer 2200 to execute a process of an embodiment of the present invention or a stage of the process. Such a program may be executed by the CPU 2212 to cause the computer 2200 to perform specific operations associated with some or all of the blocks in the flowcharts and block diagrams described in this specification.

[0123] The computer 2200 of this embodiment includes a CPU 2212, a RAM 2214, a graphics controller 2216, and a display element 2218, which are interconnected by a main controller 2210. The computer 2200 also includes input / output units such as a communication interface 2222, a hard disk drive 2224, a digital versatile disc read only memory (DVD-ROM) drive 2226, and an IC card drive, which are connected to the main controller 2210 via an input / output controller 2220. The computer also includes conventional input / output units such as a ROM 2230 and a keyboard 2242, which are connected to the input / output controller 2220 via an input / output chip 2240.

[0124] The CPU 2212 operates according to programs stored in the ROM 2230 and the RAM 2214, thereby controlling each unit. The graphics controller 2216 acquires image data generated by the CPU 2212 in a frame buffer or the like provided in the RAM 2214 or itself, and displays the image data on the display element 2218.

[0125] The communication interface 2222 communicates with other electronic components via a network. The hard disk drive 2224 stores programs and data used by the CPU 2212 within the computer 2200. The DVD-ROM drive 2226 reads programs or data from the DVD-ROM 2201 and provides the programs or data to the hard disk drive 2224 via the RAM 2214. The IC card drive reads programs and data from an IC card and / or writes programs and data to an IC card.

[0126] The ROM 2230 stores therein a boot program and the like executed by the computer 2200 at activation and / or a program dependent on the hardware of the computer 2200. The input / output chip 2240 can also connect various input / output units to the input / output controller 2220 via a parallel port, a serial port, a keyboard port, a mouse port, etc.

[0127] The program is provided via a computer-readable medium such as the DVD-ROM 2201 or an IC card. The program is read from the computer-readable medium and installed in the hard disk drive 2224, the RAM 2214, or the ROM 2230, which are also examples of computer-readable media, and is executed by the CPU 2212. The information processing described within these programs is read by the computer 2200, bringing about the linkage between the program and the various types of hardware resources. The device or method can be configured to implement the operation or processing of information according to the use of the computer 2200.

[0128] For example, when performing communication between the computer 2200 and an external component, the CPU 2212 can execute a communication program loaded into the RAM 2214 and instruct the communication interface 2222 to perform communication processing based on the processing described in the communication program. Under the control of the CPU 2212, the communication interface 2222 reads the transmission data stored in the transmission buffer processing area provided in a recording medium such as the RAM 2214, the hard disk drive 2224, the DVD-ROM 2201, or an IC card, transmits the read transmission data to the network, or writes the received data from the network to the reception buffer processing area provided on the recording medium, etc.

[0129] Moreover, the CPU 2212 can read all or a required part of a file or database stored in an external recording medium such as the hard disk drive 2224, the DVD-ROM drive 2226 (DVD-ROM 2201), an IC card, etc. into the RAM 2214 and perform various types of processing on the data on the RAM 2214. Next, the CPU 2212 writes the processed data back to the external recording medium.

[0130] Various types of information such as various types of programs, data, tables, and databases can be stored in a recording medium and undergo information processing. The CPU 2212 can perform various types of processing on the data read from the RAM 2214 and write the results back to the RAM 2214. The various types of processing include various types of operations, information processing, conditional judgments, conditional branches, unconditional branches, retrieval / replacement of information, etc. described throughout this disclosure and specified by the instruction sequences of programs. Moreover, the CPU 2212 can retrieve information in files, databases, etc. within the recording medium. For example, if there are a plurality of entries each having an attribute value of a first attribute associated with an attribute value of a second attribute in the recording medium, the CPU 2212 can retrieve an entry that matches the condition specifying the attribute value of the first attribute from the plurality of entries, and read the attribute value of the second attribute stored in the entry, thereby obtaining the attribute value of the second attribute associated with the first attribute that satisfies a pre-specified condition.

[0131] The programs or software modules described above can be stored in a computer-readable medium on or near the computer 2200. Moreover, a recording medium such as a hard disk or RAM provided within a server system connected to a dedicated communication network or the Internet can be used as a computer-readable medium, whereby the program is provided to the computer 2200 via the network.

[0132] As described above, the present invention has been illustrated using embodiments, but the technical scope of the present invention is not limited to the scope described in the embodiments. Those skilled in the art will clearly understand that various changes or improvements can be made to the embodiments. It is clear from the description in the claims that such forms with changes or improvements can also be included within the technical scope of the present invention.

[0133] It should be noted that regarding the execution order of each process such as actions, flows, steps, and stages in the devices, systems, programs, and methods shown in the claims, the description, and the drawings, unless specifically stated as "before", "prior to", etc., and the output of the pre-processing is used in the post-processing, it can be implemented in any order. Regarding the action flows in the claims, the description, and the drawings, even if described using "firstly", "next", etc. for convenience, it does not mean that it must be implemented in this order.

[0134] Explanation of reference numerals

[0135] 1: Test device

[0136] 10: DUT

[0137] 100: Test head

[0138] 110: Pin electronic device

[0139] 120: Connecting device

[0140] 150: Main frame

[0141] 160: Main power supply device

[0142] 170: Control device

[0143] 200: Power circuit

[0144] 205a - 205d: Power supply

[0145] 210: Test circuit

[0146] 220: Test control circuit

[0147] 230: Monitoring circuit

[0148] 235: Voltage detection circuit

[0149] 240: Temperature detection circuit

[0150] 245: Microcontroller

[0151] 246: Internal clock

[0152] 247: Clock setting circuit

[0153] 248: Writing circuit

[0154] 250: Accumulator

[0155] 260: Recording medium

[0156] 270: Antenna

[0157] 520a - 520c: Connector

[0158] 610: Pin electronic device

[0159] 615: Motherboard

[0160] 620a - 620c: Connector

[0161] 710: Pin electronic device

[0162] 715: Motherboard

[0163] 720a - 720c: Connector

[0164] 730: Monitoring connector

[0165] 790: Terminal

[0166] 810: Pin electronic device

[0167] 815: Motherboard

[0168] 820a - 820c: Connector

[0169] 825a - 825c: Daughter board

[0170] 827a - 827c: Monitoring circuit

[0171] 830a - 830c: Antenna

[0172] 2200: Computer

[0173] 2201: DVD-ROM

[0174] 2210: Main controller

[0175] 2212: CPU

[0176] 2214: RAM

[0177] 2216: Graphics controller

[0178] 2218: Display component

[0179] 2220: Input / output controller

[0180] 2222: Communication interface

[0181] 2224: Hard disk drive

[0182] 2226: DVD-ROM drive

[0183] 2230: ROM

[0184] 2240: Input / output chip

[0185] 2242: Keyboard

Claims

1. A pin electronic device for testing a device under test, the pin electronic device comprising: A test circuit connected to the device under test for testing the device under test; A power supply circuit for supplying power to the circuits within the pin electronic device; And A monitoring circuit that, in the case of detecting a failure of the pin electronic device, records failure information related to the failure to a recording medium that can be read without receiving power supply from the power supply circuit.

2. The pin electronic device according to claim 1, wherein The recording medium can be read by short-range wireless communication.

3. The pin electronic device according to claim 2, comprising: An antenna provided on the outer surface of the pin electronic device that is exposed to the outside when the pin electronic device is mounted on a test head, The recording medium can be read by short-range wireless communication using the antenna.

4. The pin electronic device according to claim 3, wherein The antenna is provided on the outer surface of the pin electronic device where a connector connected to the device under test is mounted.

5. The pin electronic device according to claim 2, comprising: An antenna provided at an edge of the upper surface of the pin electronic device where a connector connected to the device under test is mounted, The recording medium can be read by short-range wireless communication using the antenna.

6. The pin electronic device according to claim 2, wherein The recording medium receives power supply by short-range wireless power supply via the antenna from a terminal device that reads the failure information to read the failure information, and supplies the failure information to the terminal device via the antenna by short-range wireless communication.

7. The pin electronic device according to claim 2, wherein The monitoring circuit has a microcontroller that monitors the failure and writes to the recording medium by executing a monitoring program, The microcontroller receives power supply by short-range wireless power supply via the antenna from a terminal device that reads the failure information, reads the failure information from the recording medium, and supplies the failure information to the terminal device via the antenna by short-range wireless communication.

8. The pin electronic device according to claim 1, wherein The monitoring circuit has a microcontroller that monitors the failure and writes to the recording medium by executing a monitoring program, The pin electronic device has a monitoring connector for connecting a terminal device that reads the failure information to the microcontroller, The microcontroller receives power supply from the terminal device via the monitoring connector, reads the failure information from the recording medium, and supplies the failure information to the terminal device via the monitoring connector.

9. The pin electronic device according to claim 1, wherein The monitoring circuit, in the case of detecting a failure of a component of the pin electronic device, records the failure information including component identification information for identifying the failed component to the recording medium.

10. The pin electronic device according to claim 1, wherein in a case where the monitoring circuit detects a failure of the pin electronic device, the failure detection date and time is associated with the failure information and recorded in the recording medium.

11. The pin electronic device according to claim 10, wherein the monitoring circuit includes: an internal clock; a clock setting circuit that sets the current date and time received from an external device of the pin electronic device to the internal clock; and a writing circuit that, at the timing of detecting a failure of the pin electronic device, writes the date and time represented by the internal clock as the failure detection date and time in association with the failure information to the recording medium.

12. The pin electronic device according to claim 1, wherein the monitoring circuit encrypts at least a part of the failure information and records it in the recording medium.

13. The pin electronic device according to claim 12, wherein the monitoring circuit encrypts the part identification information included in the failure information for identifying the part in which the failure has occurred.

14. The pin electronic device according to claim 1, comprising: a main board; and a plurality of daughter boards mounted on the main board, wherein the monitoring circuit and the recording medium are mounted on each daughter board.

15. A test device, comprising: one or more pin electronic devices according to any one of claims 1 to 14; a control device that controls the one or more pin electronic devices; and a connection device that connects between the one or more pin electronic devices and one or more devices under test.

16. A method, comprising: a pin electronic device connected to a device under test tests the device under test; and in a case where the pin electronic device detects a failure of the pin electronic device, the pin electronic device records failure information related to the failure in a recording medium that can be read without receiving power supply from a power supply circuit in the pin electronic device.

Images