Clock architecture for transmitting clock signal over communication interface

Abstract

An integrated circuit (IC) device includes a first IC chip (110), a second IC chip (120), and a chip-to-chip interface (112) connected between the first IC chip (110) and the second IC chip (120). The chip-to-chip interface (120) transmits an interface clock signal and a logic clock signal between the first IC chip (110) and the second IC chip (120). The interface clock signal is synchronized with a data signal received by one of the first IC chip (110) and the second IC chip (120). The logic clock signal is asynchronous with the data signal.

Description

Technical Field

[0001] Examples of the present disclosure generally relate to clock interfaces for high-speed integrated circuit chip-to-integrated circuit chip communication interfaces. Background Art

[0002] As computer systems become more tightly integrated, integrated circuit (IC) chip-to-IC chip (C2C) interfaces are used more widely. One such computing system is an anchor IC chip (e.g., a processor, application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or system-on-chip (SOC)) or another anchor IC chip that uses a C2C interface to communicate with one or more die (e.g., high-speed I / O or high-bandwidth memory (HBM)). The C2C interface is limited by the area of the edge region (e.g., the side of the anchor chip), which limits the number of signals and wires that can pass through the interface. Therefore, the required bandwidth is achieved by running the interface at a high data rate.

[0003] The C2C interface uses multiple clock signals to transfer parallel data between IC chips. Generally, the C2C interface implements clock techniques to support the communication of parallel data between IC chips. However, such C2C interfaces are specific to a particular implementation and do not support multiple different C2C modes. Summary of the Invention

[0004] In one example, an integrated circuit (IC) device includes a first IC chip, a second IC chip, and a chip-to-chip interface connected between the first IC chip and the second IC chip. The chip-to-chip interface transfers an interface clock signal and a logic clock signal between the first IC chip and the second IC chip. The interface clock signal is synchronized with a data signal received by one of the first IC chip and the second IC chip. The logic clock signal is asynchronous with the data signal.

[0005] In one example, a chip-to-chip interface transfers an interface clock signal between a first IC chip and a second IC chip. The first IC chip and the second IC chip are connected to each other via the chip-to-chip interface. The interface clock signal is synchronized with the data signal. The data signal is received by one of the first IC chip and the second IC chip. The chip-to-chip interface also transfers a logic clock signal between the first IC chip and the second IC chip. The logic clock signal is asynchronous with the data signal.

[0006] In one example, an IC chip includes a chip-to-chip interface circuit connected to a second IC chip. The chip-to-chip interface circuit is configured to transmit an interface clock signal to the second IC chip. The interface clock signal is synchronized with a data signal received by the IC chip. The chip-to-chip interface also transmits a logic clock signal to the second IC chip. The logic clock signal is asynchronous with the data signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] To enable a more particular understanding of the manner of the above-described features, a more specific description may be obtained by reference to example embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings illustrate only typical example embodiments and are therefore not to be considered limiting of their scope.

[0008] Figure 1 is a block diagram of a multi-integrated circuit (IC) chip device according to an example.

[0009] Figure 2 is a block diagram of a multi-IC chip device according to an example.

[0010] Figure 3 is a block diagram of a multi-IC chip device configured as a receiver of a transceiver device according to an example.

[0011] Figure 4 is a block diagram of a multi-IC chip device configured as a transmitter of a transceiver device according to an example.

[0012] Figure 5 is a block diagram of a multi-IC chip device configured as a receiver of a transceiver device according to an example.

[0013] Figure 6 is a block diagram of a multi-IC chip device configured as a transmitter of a transceiver device according to an example.

[0014] Figure 7 Illustrates control signals of a multi-IC chip device according to an example.

[0015] Figure 8 is a block diagram of a multi-IC chip device including a plurality of anchor IC chips according to an example.

[0016] Figure 9 is a block diagram of a multi-IC chip device in which the interface circuit is bypassed.

[0017] Figure 10 is a block diagram of a clock generation circuit according to an example. DETAILED DESCRIPTION

[0018] The various features are described below with reference to the accompanying drawings. It should be noted that the drawings may or may not be drawn to scale, and elements with similar structures or functions are denoted by like reference numerals in all the drawings. It should be noted that the drawings are only intended to facilitate the description of the features. They are not intended to be an exhaustive description of the features nor a limitation on the scope of the claims. Additionally, the illustrated examples need not have all the aspects or advantages shown. The aspects or advantages described in connection with a particular example are not necessarily limited to that example and may be practiced in any other example even if not so illustrated or explicitly described.

[0019] Embodiments herein describe clock techniques for a chip-to-chip (C2C) interface. The clock techniques described herein can be used for various different C2C interface modes. For example, the C2C interface employs a low-latency streaming mode, a flow control mode, and a low-latency synchronous communication mode.

[0020] The C2C interface includes wires that connect two or more integrated circuit (IC) chips to each other. The wires may be referred to as modules or DWORDs. In one example, a module is the basic unit of the C2C interface. A module includes one or more wires that serve as an interface between the IC chips. In the full-module mode, all the wires of the C2C interface are used for communication. Further, in the full-module mode, all the wires of the C2C interface are driven with the same clock signal. In the half-module mode, fewer than all the wires of the C2C interface are used.

[0021] In many cases, both the clock signal used to send data through the C2C interface and the clock signal used by the functional circuits of the IC chips are generated from a data signal. Thus, when the data signal is no longer received, the control signal for sending the clock signal for the functional circuits is aborted, and the clock signal for the functional circuits becomes unavailable. Below, a process for sending multiple different clock signals via the C2C interface is described. As will be described in detail below, at least one clock signal is generated independently of the data signal and is used as the clock signal for the functional circuits of the IC chips. For example, a first portion of the wires of the C2C interface is driven based on a first clock signal, and a second portion of the wires is driven based on a second clock signal. The second clock signal is different from the first clock signal. Different clock signals are used to send data signals and control signals. Using two clock signals allows the control signal to continue to be sent when an error occurs within the data signal, thereby improving the reliability and performance of the C2C interface.

[0022] In one or more examples, multiple anchored IC chips (e.g., IC chips including programmable structured logic) are interconnected via a C2C interface. The anchored chips may also be referred to as master IC chips. In such examples, instead of each anchored IC chip locally generating a different clock signal, the C2C interface is used to convey clock signals between the IC chips. In this mode of operation, the fabric logic clock signal associated with one IC chip is conveyed via the C2C interface to another IC chip. The fabric logic clock signal is conveyed via a portion of the wires of the C2C interface (e.g., the sideband), thereby synchronizing the IC chips with each other, reducing data errors within the multiple IC chips, and improving the performance of the multiple IC chips.

[0023] Figure 1 FIG. 4 is a block diagram of a multi-(integrated circuit) chip device 100 including an IC chip 110 and an IC chip 120. The IC chip 110 and the IC chip 120 may be mounted to an interposer (not shown) or another substrate.

[0024] In one example, the IC chip 110 is a master IC chip or an anchored IC chip. The IC chip 110 includes circuitry that includes one or more data processing blocks, such as a processing system or subsystem (PS), a memory system (e.g., including a memory controller), etc. Additionally, the IC chip 110 includes a C2C interface circuit 112. The IC chip 110 is an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a central processing unit (CPU), or a memory, etc.

[0025] In one or more examples, the IC chip 120 is a die or an auxiliary IC chip. In such examples, the IC chip 120 includes a dedicated logic device or device type configured to serve a particular purpose or provide a particular functionality, such as a data processing engine (DPE) or a hardware accelerator IC chip configured to provide artificial intelligence (AI), machine learning (ML) functionality, Ethernet communication, memory functionality, etc. In one or more examples, using a die or an auxiliary IC chip as the IC chip 120 can decouple the development cycle of the IC chip 110 from that of the IC chip 120. For example, the IC chip 110 is developed and manufactured independently of the development of the IC chip 120. In other examples, the IC chip 120 is configured similar to the configuration of the IC chip 110. For example, both the IC chip 110 and the IC chip 120 are master IC chips or anchored IC chips. In such examples, the IC chip 120 is an ASIC, an FPGA, a CPU, or a memory, etc.

[0026] In one example, the IC chip 120 is a die or a helper IC chip and is part of an overall IC design framework that performs one or more specific functions, but requires an external entity (i.e., the IC chip 110) to make these functions useful. For example, the IC chip 120 can perform the acceleration of machine learning functions, but requires the IC chip 110 to program registers, provide an interface to memory, etc.

[0027] The IC chip 120 includes a C2C interface circuit 122. The C2C interface circuit 122 of the IC chip 120 is connected to the C2C interface circuit 112 of the IC chip 110 via the interface 130. The interface 130 includes one or more wires. For example, the interface 130 can include N wires. N is a number equal to or greater than one. In one or more examples, the C2C interface circuit 112, the C2C interface circuit 122, and the interface 130 form a C2C interface system 140. In one example, each wire of the interface 130 is driven based on the same clock signal. In other examples, at least two wires of the interface 130 are driven with a clock signal whose frequency is less than the frequency of the clock signal driving the other wires of the interface 130. In one or more examples, the C2C interface system 140 operates at approximately 8 gigabits per second (Gbps) per wire.

[0028] In one example, the C2C interface circuit 112 and the C2C interface circuit 122 include one or more programmable elements (e.g., via a programming software model that employs a programming interface for end users). In some embodiments, the C2C interface circuit 112 and the C2C interface circuit 122 include digital and / or analog components that implement communication between the IC chip 110 and the IC chip 120.

[0029] In one or more examples, the multi-IC chip device 100 includes more than two IC chips. For example, the multi-IC chip device 100 includes the IC chip 110 and two or more IC chips 120. In such an example, the IC chips 120 can be configured to perform common functions and / or different functions.

[0030] The C2C interface system 140 enables communication between the IC chip 110 and the IC chip 120. The C2C interface system 140 provides flexibility in creating the multi-IC chip device 100. In one or more examples, the C2C interface system 140 allows different combinations of IC chips (e.g., the IC chips 110 and 120) to be interconnected to form the multi-IC chip device 100.

[0031] Figure 2 A block diagram of the IC chip 110 and the IC chip 120 is illustrated. As Figure 2As illustrated, the C2C interface circuit 112 of the IC chip 110 includes an application circuit 210, a protocol layer circuit 212, a link layer circuit 214, and a physical (PHY) layer circuit 216.

[0032] The application circuit 210 is a circuit that executes user- and / or design-specified functions. In one example, the application circuit 210 includes non-programmable (hardened) circuits such as a processor core, a DPE, a graphics processing unit, transceiver circuits (e.g., a transmitter circuit and a receiver circuit), etc. In another example, the application circuit 210 includes programmable circuits (e.g., programmable structure circuits) such as configurable logic blocks (CLBs) or other types of programmable logic that can be customized on the fly. The application circuit 210 generates data that is delivered to the IC chip 120 via the interface 130 and processes the data received from the IC chip 120.

[0033] In one or more examples, the application circuit 210 uses a specific protocol to send data to other hardware elements (e.g., the protocol layer circuit 212) in the IC chip 110. This protocol is typically different from the protocol used to send data through the interface 130. In such an example, the application circuit 210 outputs a protocol word (or control signal) that is received by the protocol layer circuit 212. The protocol layer circuit 212 receives the protocol word and converts the protocol word into a data signal (e.g., a data word (DW)) that is compatible with the interface 130. The protocol word includes control data and a data signal. Converting the protocol word includes separating the control data from the data signal. The control data is transmitted via the interface 130 as a packet separated from the data signal.

[0034] In other examples, the application circuit 210 outputs a data signal that is compatible with the interface 130. In such an example, the protocol layer circuit 212 is bypassed and does not process the data signal output by the application circuit 210. In Figure 3 、 Figure 4 、 Figure 6 and Figure 7 's examples, as described below, the protocol layer is bypassed. A similar method can be applied to examples where the protocol layer is not bypassed.

[0035] In one example, the link layer circuit 214 generates a framing pattern from the data signal, and the framing pattern is transmitted along the interface 130 together with the data signal. The framing pattern indicates the start of the data within the data signal. The PHY layer circuit 216 transmits the data signal and the framing pattern along the interface 130. In addition, the PHY layer circuit 216 receives the data signal and the framing pattern from the interface 130. In such an example, the received data signal and the framing pattern are provided to the link layer circuit 214. The link layer circuit 214 detects the framing pattern and identifies the start of the data signal. The data signal is output to the application circuit 210.

[0036] In one example, a data signal is sent together with a framing signal. The framing signal defines a valid data region within the data signal. In one example, the framing signal is used to mask invalid data within the data signal.

[0037] The C2C interface circuit 122 of the IC chip 120 includes an application circuit 220, a protocol layer circuit 222, a link layer circuit 224, a PHY layer circuit 226, and a reducer circuitry 228. The application circuit 220, the protocol layer circuit 222, the link layer circuit 224, and the PHY layer circuit 226 are configured in a manner similar to the application circuit 210, the protocol layer circuit 212, the link layer circuit 214, and the PHY layer circuit 216, respectively.

[0038] The C2C interface circuit 122 also includes a reducer circuitry 228. The reducer circuitry 228 receives an output from the application circuit 220 (e.g., a protocol word or a data signal) and adjusts the output by reducing the data rate (e.g., frequency) and increasing the bit size of the data signal. In one example, the reducer circuitry 228 converts a data signal with 80 bits and a frequency of 1.45 GHz into a data signal with 160 bits and a frequency of 725 MHz. In one example, the factor by which the frequency is reduced is the same as the factor by which the number of bits of the data signal is increased. Thus, after processing the output of the application circuit 220 using the reducer circuitry 228, the same amount of data is transmitted in the same amount of time.

[0039] In one or more examples, the protocol layer circuit 222 converts the output of the reducer circuitry 228 between protocols, as described above for the protocol layer circuit 212. In other examples, the protocol layer circuit 222 is bypassed, and the output of the reducer circuitry 228 is transmitted to the link layer circuit 224.

[0040] In one or more examples, the C2C interface system 140 supports various different communication modes. In one or more examples, the application circuit 210 and / or 220 is a transceiver circuit that can be configured as a transmitter circuit and a receiver circuit, respectively. For example, the application circuit 210 and / or 220 includes a serializer / deserializer (SERDES) circuit or other transceiver circuits.

[0041] In the low-latency streaming mode, the protocol layer circuits (e.g., protocol layer circuits 212 and 222) and / or the link layer circuits (e.g., link layer circuits 214 and 224) are bypassed. In the low-latency streaming mode, all or part of the wires of the interface 130 can be used.

[0042] In one or more examples, application circuit 210, link layer circuit 214, and PHY layer circuit 216 each include sideband circuits 230, 232, and 234, respectively. Additionally, application circuit 220, link layer circuit 224, and PHY layer circuit 226 each include sideband circuits 240, 242, and 244, respectively. Sideband circuits 230, 232, and 234 and sideband circuits 240, 242, and 244 communicate via a portion of interface 130 (e.g., the sideband). In such an example, interface 130 transmits data via the mainband and transmits sideband information via the sideband of interface 130. The sideband corresponds to M wires of the interface, and the mainband corresponds to P wires of the interface. P and M are numbers greater than or equal to one. Additionally, P can be greater than M. In one or more examples, the frequency used to transmit data via the mainband (e.g., the mainband or data path clock signal frequency) is greater than the frequency used to transmit data via the sideband (e.g., the sideband or control signal clock signal frequency). In one example, the sideband can be used to transmit control data as sideband information between IC chips.

[0043] In one example, using all the wires of interface 130 is referred to as full module mode, and using a portion of the wires is referred to as half module mode. In full module mode, all the wires of interface 130 are clocked with the same clock signal. The clock signal is generated by a PHY interface circuit (e.g., PHY layer circuits 216 and / or 226).

[0044] In one or more examples, IC chip 110 and IC chip 120 are connected via a data path and a sideband. In such examples, the data path is a synchronous, low-latency data path. As described in more detail below, the data path uses a data path clock signal generated from a clock generation circuit based on a data signal.

[0045] In one or more examples, the data path clock signal may stop due to auto-negotiation and link training (ANLT), dynamic rate change, or link data loss within IC chip 110 and / or 120. Stopping the data path clock signal stops data transmission between IC chip 110 and 120. In such an implementation, to maintain communication of control data between IC chip 110 and 120, the sideband connection is used to transmit control data between IC chip 110 and 120. To ensure the proper functionality of IC chip 110 and 120, control data is continuously transmitted even when the first clock signal stops. To support continuous communication of control data, the sideband connection uses a sideband clock signal independent of the data path clock signal.

[0046] In one example, the sideband circuits 230 - 234 and the sideband circuits 240 - 244 are used to transmit control data via the sideband of the interface 130. In another example, in the half - module mode, one or more of the wires in the interface 130 are used to transmit control data as a sideband connection, and the remaining wires of the interface 130 are used to transmit data signals (e.g., data paths). In the half - module mode, the sideband circuits 230 - 234 and the sideband circuits 240 - 244 are used to transmit clock signals or information defining the attributes of the clock signals (e.g., the frequency of the clock signal). In one or more examples, the sideband connection uses a clock signal different from the clock signal of the data bus (or main band).

[0047] In one or more examples, the interface 130 transmits an interface clock signal (e.g., a first clock signal or a main - band clock signal) between the IC chip 110 and the IC chip 120. The interface clock signal is synchronized with the data signal received by one of the IC chips 110 and 120. The interface 130 also transmits a logic clock signal (e.g., a second clock signal, a sideband clock signal, or a control clock signal) between the IC chip 110 and the IC chip 120. The logic clock signal is asynchronous with the data signal received by one of the IC chips 110 and 120. The logic clock signal is generated independently of the interface clock signal. In addition, the interface 130 transmits data signals between the IC chips 110 and 120. The frequency of the data signal is greater than the frequency of the interface clock signal. The interface 130 also transmits control signals (e.g., protocol signals) between the IC chips 110 and 120. The control signal has the frequency of the data signal.

[0048] In one or more examples, the interface 130 transmits an interface clock signal and a logic clock signal between the IC chip 110 and the IC chip 120. The frequency of the interface clock signal is a multiple of the frequency of the logic clock signal. In one example, the frequency of the interface clock signal is at least twice the frequency of the logic clock signal. In one or more examples, the interface transmits data signals between the IC chips 110 and 120. The data signal is synchronized with the interface signal. The framing mode is transmitted together with the data signal. In one example, the interface clock signal is generated at the rising edge of the logic clock signal. In one example, the framing signal is transmitted together with the data signal and is used to define the valid data within the data signal.

[0049] Figure 3 is a block diagram of the multi - IC chip device 300. The multi - IC chip device 300 includes the IC chip 310 and the IC chip 350. The IC chip 310 is connected to the IC chip 350 via the interface 302. The IC chip 310 is configured in a manner similar to Figure 1 the IC chip 110, and the IC chip 350 is configured in a manner similar to Figure 1configured in a manner similar to that of the IC chip 120, and the interface 302 is configured in a manner similar to that of Figure 1 the interface 130. In Figure 3 the example of, the IC chip 310 is the main IC chip, and the IC chip 350 is the auxiliary IC chip or the die.

[0050] The multi-IC chip device 300 is configured such that data and control data (or other sideband information) are transmitted between the IC chip 310 and the IC chip 350 using both a data path and a sideband connection.

[0051] The IC chip 350 includes an application circuit 352 and a C2C interface circuit 360. The C2C interface circuit 360 includes a PHY layer circuit 362, a link layer circuit 364, a protocol layer circuit 366, and a reducer circuit 368. The C2C interface circuit 360 is configured in a manner similar to that of Figure 1 the C2C interface circuit 122, the PHY layer circuit 362 is configured in a manner similar to that of Figure 2 the PHY layer circuit 216, the C2C link layer circuit 364 is configured in a manner similar to that of Figure 2 the C2C link layer circuit 214, the protocol layer circuit 366 is configured in a manner similar to that of Figure 2 the protocol layer circuit 212, and the reducer circuit 368 is configured in a manner similar to that of Figure 2 the reducer circuit 228. The application circuit 352 is configured in a manner similar to that of Figure 2 the application circuit 220.

[0052] The IC chip 350 further includes an application circuit 354 and a C2C interface circuit 370. The C2C interface circuit 370 includes a PHY layer circuit 372, a link layer circuit 374, and a protocol layer circuit 376. The C2C interface circuit 370 is configured in a manner similar to that of Figure 1 the C2C interface circuit 122, the PHY layer circuit 372 is configured in a manner similar to that of Figure 2 the PHY layer circuit 216, the C2C link layer circuit 374 is configured in a manner similar to that of Figure 2 the C2C link layer circuit 214, and the protocol layer circuit 376 is configured in a manner similar to that of Figure 2 the protocol layer circuit 212. The application circuit 354 is configured in a manner similar to that of Figure 2 the application circuit 220.

[0053] In addition, the IC chip 350 includes a clock circuit 380 and a clock circuit 390. The clock circuit 380 generates a data path clock signal (e.g., the clock signal 305), and the clock circuit 390 generates a sideband clock signal (e.g., the clock signal 307).

[0054] In one example, the IC chip 350 is configured as a receiver circuit in a transceiver circuit. The IC chip 350 receives a data signal 351.

[0055] The clock circuit 380 includes a clock generation circuit 382, a frequency divider circuit 384, a multiplication delay locked loop (MDLL) circuit 386, and a frequency divider circuit 388. The clock circuit 390 is a frequency divider circuit.

[0056] The IC chip 310 includes an application circuit 312 and a C2C interface circuit 320. The C2C interface circuit 320 includes a PHY layer circuit 322, a link layer circuit 324, and a protocol layer circuit 326. The C2C interface circuit 320 is configured in a manner similar to that of Figure 1 the C2C interface circuit 112, the PHY layer circuit 322 is configured in a manner similar to that of Figure 2 the PHY layer circuit 216, the C2C link layer circuit 324 is configured in a manner similar to that of Figure 2 the C2C link layer circuit 214, and the protocol layer circuit 326 is configured in a manner similar to that of Figure 2 the protocol layer circuit 212. The application circuit 312 is configured in a manner similar to that of Figure 2 the application circuit 210.

[0057] The IC chip 310 further includes an application circuit 314 and a C2C interface circuit 330. The C2C interface circuit 330 includes a PHY layer circuit 332, a link layer circuit 334, and a protocol layer circuit 336. The C2C interface circuit 330 is configured in a manner similar to that of Figure 1 the C2C interface circuit 112, the PHY layer circuit 332 is configured in a manner similar to that of Figure 2 the PHY layer circuit 216, the C2C link layer circuit 334 is configured in a manner similar to that of Figure 2 the C2C link layer circuit 214, and the protocol layer circuit 336 is configured in a manner similar to that of Figure 2 the protocol layer circuit 212. The application circuit 314 is configured in a manner similar to that of Figure 2 the application circuit 210.

[0058] In addition, the IC chip 310 includes a clock circuit 340 and a clock circuit 346. The clock circuit 340 receives a clock signal 305 (e.g., a data path clock signal) from the IC chip 350, and the clock circuit 346 receives a clock signal 307 (e.g., a sideband clock signal) from the IC chip 350. The clock signal 307 is transmitted as a differential signal.

[0059] The clock circuit 340 includes a frequency divider circuit 342 and an MDLL circuit 344. The clock circuit 346 includes a frequency divider circuit.

[0060] In one example, the IC chip 350 transmits data signal 304, clock signal 305, control signal word 306, and clock signal 307 via interface 302. The IC chip 350 generates data signal 304 and clock signal 305 based on data signal 351. For example, clock circuit 380 generates clock signal 305 based on data signal 351. Clock generation circuit 382 generates clock signal 383 from data signal 351. For example, clock generation circuit 382 generates clock signal 383 based on the received data signal 351. Further, the frequency of clock signal 383 corresponds to the frequency of data signal 351 generated by application circuit 352 from data signal 353. In one example, the frequency of clock signal 383 is 1.45 GHz, and the frequency of data signal 353 is 1.45 GHz. Clock signal 383 is received by application circuit 352 and divider circuit 384. Clock signal 383 is used as the clock signal for application circuit 352. Divider circuit 384 divides the frequency of clock signal 383 by two or a larger number to determine divided clock signal 385a. Divider circuit 384 also receives divided clock signal 389a from divider circuit 388. Divider circuit 384 divides the frequency of clock signal 389a by two or a larger number to determine divided clock signal 385b. In one example, the frequencies of clock signals 385a and 385b are 725 MHz. Divided clock signal 385a and divided clock signal 385b are received by MDLL circuit 386.

[0061] MDLL circuit 386 reduces the delay of clock signals 385a and 385b. Further, MDLL circuit 386 generates clock signal 387 from clock signals 385a and 385b. For example, MDLL circuit 386 multiplies the frequencies of clock signals 385a and 385b by two or a larger number. In one example, MDLL circuit 386 multiplies the frequencies of clock signals 385a and 385b by five. In this example, the frequency of clock signal 387 is 3.625 GHz. Clock signal 387 is output by driver circuit 356 via interface 302 as clock signal 305. In one example, clock signal 305 is transmitted as a differential signal via two wires of interface 302.

[0062] The clock signal 387 is also received by a frequency divider circuit 388. The frequency divider circuit 388 outputs clock signals 389a, 389b, and 389c. The frequency divider circuit 388 generates the clock signal 389a by reversing the processes applied by the frequency divider circuit 384 and the MDLL circuit 386. For example, the frequency divider circuit 388 divides the frequency of the clock signal 387 by two or a larger number, and multiplies the frequency of the clock signal by two or a larger number. In addition, the frequency divider circuit 388 generates the clock signal 389b by dividing the frequency of the clock signal 387 by two or a larger number. In addition, the clock signal 389c is passed through the frequency divider circuit 388 without being processed or changed. The frequency of the clock signal 389c is the same as the frequency of the clock signal 387.

[0063] The clock signal 389a is received by a reducer circuit 368 that processes the data signal 353 using the clock signal 389a. The reducer circuit 368 reduces the frequency of the data signal 353 to one-half or less of its original value, and increases the number of bits of the data signal to twice or more than its original value, to generate a data signal 363. In one example, the data signal 353 has 80 bits and a frequency of 1.45 GHz. In such an example, when the frequency is reduced to one-half of its original value and the number of bits is increased to twice its original value, the data signal 363 has 160 bits and a frequency of 725 MHz. Reducing the frequency of the data signal 353 to generate the data signal 363 places the data signal 363 within the operating range of the link layer circuit 364 and the PHY layer circuit 362.

[0064] The protocol layer circuit 366 is bypassed because the data signal 363 is compatible with the link layer circuit 364 and the PHY layer circuit 362. The link layer circuit 364 receives the clock signal 389b, and generates a framing pattern indicating the start of the data signal 363. The framing pattern, together with the data signal 363, is transmitted to the PHY layer circuit 362. In one example, the data signal 363 is transmitted together with a framing signal that defines a valid data region within the data signal 363. The framing signal masks invalid data within the data signal 363.

[0065] The PHY layer circuit 362 receives the clock signals 389b and 389c, and generates the data signal 304 from the data signal 363. The PHY layer circuit 362 increases the frequency of the data signal 363 to two times or more than two times the original, and reduces the bit size to one - half or less than one - half of the original to generate the data signal 304. In one or more examples, the PHY layer circuit 362 increases the frequency of the data signal 363 to 5 times, 10 times, 15 times, 20 times or more than 20 times the original, and reduces the bit size to 1 / 5, 1 / 10, 1 / 15 or 1 / 20 or less than 1 / 20 of the original. In an example where the PHY layer circuit 362 increases the frequency of the data signal 363 to two times or more than two times the original and reduces the bit size to one - half or less than one - half of the original. When the data signal 363 has a bit size of 160 bits and a frequency of 725 MHz, the data signal 304 has a bit size of 16 bits and a frequency of 7.25 GHz. In one example, the PHY layer circuit 362 has a multiplication ratio of sixteen to one. In another example, the PHY layer circuit 362 has other multiplication ratios. In one example, the data signal 304 has a frequency of 7.25 GHz and 16 bits. In another example, the data signal 304 has a frequency greater than or less than 7.25 GHz.

[0066] In one or more examples, the link layer circuit 364 includes a buffer 365. The buffer 365 can be a first - in - first - out (FIFO) buffer. Although a single buffer 365 is illustrated Figure 3 here, in other examples, the link layer circuit 364 may include multiple buffers 365. The buffer 365 receives a write clock signal and a read clock signal. The write clock signal and the read clock signal are in different clock domains (e.g., having different frequencies). The buffer 365 may include an array of memory elements addressed via a write pointer or a read pointer. During a write operation, data is written to the address of the write pointer. During a read operation, data is read from the address of the read pointer. In one example, the read pointer is offset from the write pointer to ensure that the data read based on the read pointer does not change when read.

[0067] The control signal 306 and the clock signal 308 are transmitted from the IC chip 350 to the IC chip 310 via the interface 302. The control signal 306 is generated based on the control signal 355 generated by the application circuit 354. The control signal 306 can be a protocol word. The protocol layer circuit 376 is bypassed, and the control signal 355 is received by the link layer circuit 374. The link layer circuit 374 generates a framing pattern for the control signal 355 and outputs the control signal and the framing pattern to the PHY layer circuit 372. In one example, the control signal 355 is sent together with a framing signal. The framing signal defines the valid data area within the control signal 355. In one example, the framing signal is used to mask the invalid data within the control signal 355.

[0068] The PHY layer circuit 372 increases the frequency of the control signal 355 to two times or more of the original, and reduces the bit size of the control signal 355 to one - half or less of the original to generate the control signal 306. In a specific example, the PHY layer circuit 372 increases the frequency of the control signal 355 to 16 times of the original, and reduces the bit size of the control signal 355 to 1 / 16 of the original. In such examples, the frequency of the control signal 355 is 200 MHz, and the bit size of the control signal 355 is 320 bits. Therefore, the control signal 306 has a bit size of 16 bits and a frequency of 8 GHz.

[0069] The side - band clock signal 308 is based on a clock signal generated by the IC chip 350 independently of the data signal 351. For example, the side - band clock signal 308 is generated by the clock generation circuit 392 of the IC chip 350. The IC chip 350 also includes a clock generation circuit 394 that generates a clock signal 395. The clock signal 395 is used internally by the application circuit 354, the link layer circuit 374, and the PHY layer circuit 372. The clock circuit 390 acts as a through - circuit that outputs the clock signal 308 without changing it. The clock signal 308 is output by the clock circuit 390 to the driver circuit 396, which drives the clock signal on the interface 302. In addition, the clock circuit 390 outputs the clock signal 308 to the PHY layer circuit 372. The clock circuit 390 further divides the clock signal 308 by two or a larger number. The clock signal 391 is output to the link layer circuit 374 and the PHY layer circuit 372.

[0070] IC chip 310 receives data signal 304, clock signal 305, control signal 306, and sideband clock signal 308 from IC chip 350. Receiver circuit 348 receives clock signal 305. Receiver circuit 348 outputs the received clock signal 305 as clock signal 349 to frequency divider circuit 342. Frequency divider circuit 342 reduces the frequency of clock signal 349 by two times or more. In a specific example, frequency divider circuit 342 reduces the frequency of clock signal 349 by ten times. In such an example, when the frequency of clock signal 305 is 3.625 GHz, frequency divider circuit 342 divides the frequency of clock signal 349 by ten to generate a clock signal 343 with a frequency of 362.5 MHz. Frequency divider circuit 342 also outputs clock signal 349 to be used as a through circuit so that clock signal 349 is not changed by frequency divider circuit 342. Clock signal 349 is output to PHY layer circuit 322.

[0071] Clock signal 343 is output to PHY layer circuit 332 and link layer circuit 334. In addition, clock signal 343 is output to MDLL circuit 344. MDLL circuit 344 generates clock signal 345 based on clock signal 343 and a feedback signal (e.g., clock signal 315) received from application circuit 312. Clock signal 343 is output to application circuit 312. In one example, buffer 313 of application circuit 312 receives clock signal 343 and generates clock signal 315. In one example, clock signal 315 is the capture clock signal of flip-flop 317 of application circuit 312. Thus, clock signal 315 is generated based on data signal 353, and this clock signal is the clock signal for application circuit 312.

[0072] In one or more examples, the feedback signal (e.g., clock signal 315) is used by MDLL circuit 344 to deskew clock signal 343 and for phase alignment of clock signal 343.

[0073] PHY layer circuit 322 receives data signal 304 and generates data signal 323 from data signal 304 and clock signals 349 and 343. In one example, PHY layer circuit 322 receives data signal 304 using clock signal 343 and generates data signal 353 using clock signal 349. Link layer circuit 324 detects the framing pattern associated with data signal 323, identifies the start of data signal 323 based on this framing pattern, and generates data signal 325 based on clock signal 343. In one example, a received framing signal is used to determine the valid data within data signal 323.

[0074] The data signal 325 has a frequency corresponding to the operating frequency of the application circuit 312. For example, the frequency of the data signal 325 is the same as the frequency of the clock signal 315. In addition, the bit data signal of the data signal 325 is greater than the bit size of the data signal 304. The bit size of the data signal 325 is two or more times the bit size of the data signal 304, where the frequency of the data signal 304 is two or more times the frequency of the data signal 325. In one example, the PHY layer circuit 322 divides the frequency of the data signal 304 by two or a larger number and multiplies the bit size of the data signal 304 by two or a larger number to generate the data signal 323. In one example, the PHY layer circuit 322 has a multiplication ratio of twenty to one. In another example, the PHY layer circuit 322 has other multiplication ratios.

[0075] In one or more examples, the link layer circuit 324 includes a buffer 321. The buffer 321 can be a FIFO buffer. Although a single buffer 321 is illustrated Figure 3 here, in other examples, the link layer circuit 324 may include multiple buffers 365. The buffer 321 receives a write clock signal and a read clock signal. The write clock signal and the read clock signal are in different clock domains (e.g., have different frequencies). The buffer 321 may include an array of memory elements addressed via a write pointer or a read pointer. During a write operation, data is written to the address of the write pointer. During a read operation, data is read from the address of the read pointer. In one example, the read pointer is offset from the write pointer to ensure that the data read based on the read pointer does not change when read.

[0076] The data signal 325 is received by the application circuit 312 based on the clock signal 315. In one example, the flip - flop 317 captures the data signal 325 based on the clock signal 315.

[0077] The receiver circuit 337 receives the sideband clock signal 308 from the driver circuit 341 and outputs a clock signal 338. The clock signal 338 is output to the clock circuit 346. The clock circuit 346 shifts the phase of the clock signal 338 by 90 degrees to generate a clock signal 339. The phase of the clock signal 339 is 90 degrees different from the phase of the clock signal 338. In addition, the clock circuit 346 generates a clock signal 347 from the clock signal 338. For example, the clock circuit 346 reduces the frequency of the clock signal 338 to one - half or less of the original (e.g., divides by two or a larger number). In one example, the clock circuit 346 reduces the frequency of the clock signal 338 to one - eighth of the original (e.g., divides by eight). The clock signal 347 is received by the PHY - layer circuit 332 and the link - layer circuit 334. The PHY - layer circuit 332 uses the clock signal 339 to receive the control signal 306 and uses the clock signal 347 to generate a control signal 333.

[0078] The application circuit 314 generates a clock signal 323, which is used by the link - layer circuit 334 to generate a control signal 335 and is used by the application circuit 314 to capture the value of the control signal 335. The flip - flop 319 captures the value of the control signal 335 based on the clock signal 323. The link - layer circuit 334 receives the control signal 333 based on the clock signal 347 and generates the control signal 335 based on the clock signal 315 and the corresponding framing pattern. The link - layer circuit 334 identifies the start of the control signal 335 based on the framing pattern. In one example, the received framing signal is used to identify the valid data within the control signal 335.

[0079] The control signal 335 has a reduced frequency compared to the control signal 333 and is within the operating frequency parameters of the application circuit 314. In one example, the frequency of the control signal 335 is less than the frequency of the control signal 333; however, the bit size of the control signal 335 is greater than the bit size of the control signal 333.

[0080] In connection with Figure 3In the above-described example, the IC chip 310 receives the data signal 304 generated from the data signal 351 using the clock signal 305, which is generated from the data signal 351. Thus, any error in the data signal 353 and / or within the IC chip 350 that causes the clock signal 305 to stop will stop (e.g., abort) the functionality of the C2C interface circuit 320 and the application circuit 312. Additionally, since the IC chip 310 receives the control signal 306 using the sideband clock signal 307 that is independent of the clock signal 305, any error in the data signal 351 and / or within the IC chip 350 will not affect the operation of the C2C interface circuit 320 and the application circuit 312. Thus, when an error occurs in the data signal 351 and / or within the IC chip 350, the C2C interface circuit 320 and the application circuit 312 are able to continue receiving and processing protocol words.

[0081] In one example, the data paths associated with the application circuit 352, the C2C interface circuit 360, the C2C interface circuit 320, and the application circuit 312 may be referred to as synchronous data paths because the data paths send and receive data synchronously with the frequency of the data signal to be transmitted. The sideband paths associated with the application circuit 354, the C2C interface circuit 370, the C2C interface circuit 330, and the application circuit 314 may be referred to as asynchronous sideband paths because the sideband paths send and receive control data (e.g., protocol words) asynchronously with the frequency of the data signal. In the asynchronous sideband path, the application circuit that receives the control data (e.g., the application circuit 314) uses a locally generated clock signal to capture the data. The locally generated clock signal is generated locally within the IC chip 310 independent of any data signal. Additionally, the clock signal used by the C2C interface circuit 330 of the IC chip 310 is generated by the IC chip 350 independent of any data signal.

[0082] In Figure 4 the example, the data signal 425 is transferred from the application circuit 312 of the IC chip 310 to the application circuit 352 of the IC chip 350 for transmission. In such examples, the application circuit 352 is a transmitter circuit (e.g., the transmitter circuit of a SERDES transceiver, etc.) configured to transmit a data signal (e.g., the data signal 416). Compared with Figure 3 the example, in Figure 4In this case, the clock signal 483 is output from the clock generation circuit 382. The clock signal 483 is processed by the frequency divider circuit 384 to generate a divided clock signal 485a, similar to that described above with respect to the clock signal 383 and the divided clock signal 385a. In addition, the frequency divider circuit 384 receives the clock signal 489a from the frequency divider circuit 388 and generates a divided clock signal 485b, as described above with respect to the clock signal 389a and the divided clock signal 385b. The MDLL circuit 386 generates a clock signal 487 from the divided clock signals 485a and 485b, similar to that described above with respect to the divided clock signals 385a and 385b and the clock signal 387.

[0083] The clock signal 487 is output by the driver circuit 355 as the clock signal 408 and is received by the receiver circuit 348 as the clock signal 449. The clock signal 408 is transmitted as a differential signal via a pair of wires of the interface 302. The frequency divider circuit 342 outputs the clock signal 449 via a through circuit such that the clock signal 449 is not changed by the frequency divider circuit 342. The clock signal 408 has a frequency of 3.625 GHz.

[0084] The clock signal 407 is transmitted from the IC chip 310 to the IC chip 350 via the interface 302. For example, the driver circuit 448 of the IC chip 310 outputs the clock signal 489 as the clock signal 407 to the receiver circuit 455 of the IC chip 350. The clock signal 407 is transmitted as a differential signal via a pair of wires of the interface 302. In one example, the clock signal has a frequency of 3.625 GHz. The receiver circuit 455 receives the clock signal 407 and outputs the clock signal 407 to the frequency divider circuit 388. The frequency divider circuit 388 generates clock signals 489a, 489b, and 489c from the clock signal 407. For example, the frequency divider circuit 388 divides the frequency of the clock signal 407 by “Y” to generate the clock signal 489a, divides it by “Z” to generate the clock signal 489b, and shifts the phase of the clock signal 407 by ninety degrees to generate the clock signal 489c. In one or more examples, “Y” and “Z” are numbers of one or greater. In one example, “Y” is less than “Z”. In a specific example, “Y” is 2.5 and “Z” is 5. In such an example, and when the clock signal 407 has a frequency of 3.625 GHz, the frequency of the clock signal 489a is 1.45 GHz, and the frequency of the clock signal 489b is 725 MHz.

[0085] The frequency divider circuit 342 generates a clock signal 443 from the clock signal 489 by dividing the frequency of the clock signal 449 by two or a larger number. In one example, the frequency divider circuit 342 divides the frequency of the clock signal 449 by ten to generate the clock signal 443. In an example where the clock signal 449 has a frequency of 3.625 GHz, dividing the frequency of the clock signal 449 by ten generates a clock signal 443 having a frequency of 362.5 MHz. The clock signal 443 is output to the PHY layer circuit 322, the link layer circuit 324, and the MDLL circuit 344.

[0086] The MDLL circuit 344 additionally receives a feedback signal (e.g., the clock signal 415) from the application circuit 312. The application circuit 312 includes a buffer 313 that receives the clock signal 445 from the MDLL circuit 344 and outputs the clock signal 415 based on the clock signal 445. The MDLL circuit 344 deskews the clock signal 443, thereby adjusting the phase alignment mismatch between the clock signal 443 and the clock signal 415, thereby generating the clock signal 445.

[0087] The application circuit 312 uses the clock signal 415 to output a data signal 425. For example, the flip-flop 317 captures the values of the data signal 416 based on the clock signal 415 and outputs these values.

[0088] The link layer circuit 324 uses the clock signal 443 to receive the data signal 425 and outputs the data signal 425 to the PHY layer circuit 322 in a framed mode. The link layer circuit 324 generates a framed mode from the data signal 425. The PHY layer circuit 322 uses the clock signal 443 to receive the data signal 425 and the framed mode, and uses the clock signal 449 to output the data signal 425 and the framed mode as a data signal 404. In one example, the data signal 404 is transmitted at 7.25 GHz and has 16 bits. In addition, a double data rate process is used to transmit the data signal 404. In one example, a framing signal is received and used to determine the valid data within the data signal 425.

[0089] The PHY layer circuit 322 increases the frequency of the data signal 425 and reduces the number of bits in the data signal 425 to generate the data signal 404. In one example, the degree of frequency increase is the same as the degree of bit number reduction. For example, the frequency of the data signal 425 is increased to twenty times or more of the original, and the number of bits of the data signal 425 is reduced to one-twentieth or less of the original. In a specific example, the data signal 425 has 320 bits and a frequency of 362.5 MHz. In this example, the PHY layer circuit 322 increases the frequency of the data signal 425 to the frequency of the interface 302, which is 7.25 GHz. The frequency of the data signal 425 is increased to twenty times the original. Therefore, by dividing the number of bits by twenty, the number of bits of the data signal 425 is reduced from 320 bits to 16 bits.

[0090] The PHY layer circuit 362 receives the data signal 404 and the framing pattern using the clock signal 489c. The PHY layer circuit 362 outputs the data signal 463 and the framing pattern using the clock signal 489b. The link layer circuit 364 uses the clock signal 489b to detect the framing pattern and identify the start of the data signal 463. In one example, the received framing signal is used to determine the valid data within the data signal 463.

[0091] The link layer circuit 364 outputs a data signal 467 having a frequency based on the clock signal 489b. Since the frequency of the clock signal 489b is less than the frequency of the data signal 404, the link layer circuit 364 increases the number of bits in the data signal 467 based on the difference between the frequency of the data signal 404 and the frequency of the clock signal 489b.

[0092] The data signal 467 is received by the reducer circuit 368, which adjusts the frequency and bit size of the data signal 467 to generate the data signal 469. The reducer circuit 368 also receives the clock signal 489a. The reducer circuit 368 adjusts the frequency of the data signal 467 based on the frequency of the clock signal 489a. Since the frequency of the clock signal 489a is greater than the frequency of the data signal 467, the reducer circuit 368 increases the frequency of the data signal 467 to generate the data signal 469. The frequency of the data signal 469 is the frequency of the clock signal 489a. The number of bits of the data signal 469 is reduced by the degree to which the frequency of the data signal 469 increases. In an example where the frequency of the data signal 467 is 725 MHz, the number of bits of the data signal 467 is 160 bits, and the frequency of the clock signal 489b is 1.45 GHz, the data signal 469 has a frequency of 1.45 GHz and 80 bits.

[0093] The application circuit 352 receives the data signal 469 and transmits the data signal 469 out of the IC chip 350. For example, the application circuit 352 includes a transceiver circuit that transmits the data signal 469 to another IC chip or device. In one example, the application circuit 352 transmits the data signal 469 to a system external to the multi-IC chip device 300.

[0094] The protocol word 406 is transmitted from the IC chip 310 to the IC chip 550 via the sideband path. The sideband path uses a clock signal different from the clock signal used by the data path for transmitting the data signal 404 as described above to transmit the protocol word 406. The protocol word 406 is transmitted at a frequency of 8 GHz and a bit size of 16 bits. In one example, a 4 GHz double data rate process is used to transmit the protocol word 406.

[0095] In Figure 4 the example, the application circuit 314 includes a clock generation circuit 418 that generates the clock signal 417. In other examples, the clock generation circuit 418 can be external to the application circuit 314 and output the clock signal 417 to the application circuit 314. The clock signal 417 is the clock signal of the application circuit 314. For example, the flip-flop 319 of the application circuit 314 outputs the protocol word 421 from the data signal 419 based on the clock signal 417. The protocol word 421 is output to the link layer circuit 334, bypassing the protocol layer circuit 336. The link layer circuit 334 also receives the clock signal 447. The clock signal 447 is generated by the clock circuit 346 from the clock signal 445, and the clock signal 445 is generated by the clock generation circuit 444. In one example, the clock circuit 346 reduces the frequency of the clock signal 445 by dividing the frequency by two or a larger number. The clock signal 447 is output to the link layer circuit 334 and the PHY layer circuit 332.

[0096] The link layer circuit 334 uses the clock signal 417 to receive the protocol word 421 from the application circuit 314 and outputs the protocol word (or control signal) 435 from the protocol word 421 based on the clock signal 447. In addition, the link layer circuit 334 generates a framing pattern that is output together with the protocol word 435 and identifies the start of the control signal 435. The frequency of the protocol word 435 corresponds to the frequency of the clock signal 447. In one example, the control signal 435 is transmitted together with a framing signal. The framing signal defines the valid data region within the control signal 435. In one example, the framing signal is used to mask the invalid data within the control signal 435.

[0097] The clock circuit 346 also outputs a clock signal 445 to the PHY layer circuit 332 and the driver circuit 437. The PHY layer circuit 332 uses the clock signal 447 to receive the protocol word 435 and the corresponding framing pattern, and generates a protocol word 406 from the protocol word 435 based on the clock signal 445 and outputs the protocol word. In one example, the PHY layer circuit increases the frequency of the protocol word 435 and reduces the bit size of the protocol word 435 based on the frequency of the clock signal 445. Thus, the bit size of the protocol word 406 is smaller than the bit size of the protocol word 435, and the frequency of the protocol word 406 is greater than the frequency of the protocol word 435. In one or more examples, the PHY layer circuit 332 increases the frequency of the protocol word 435 to two times or more the original frequency, and reduces the bit size of the protocol word 435 to one-half or less of the original.

[0098] The clock signal 445 is transmitted by the driver circuit 437 as a clock signal 409, and is received at the IC chip 350 by the receiver circuit 438. The clock signal 409 is transmitted as a differential signal via two or more wires of the interface 302. The receiver circuit 438 outputs a clock signal 408 as a clock signal 439. The clock signal 439 is received by the clock circuit 390. The clock circuit 390 generates a clock signal 492 from the clock signal 439, and outputs the clock signal 492 to the PHY layer circuit 372. The clock circuit 390 shifts the frequency of the clock signal 439 to generate the clock signal 492. In addition, the clock circuit 390 generates a clock signal 491 from the clock signal 439. In one example, the clock circuit 390 generates the clock signal 491 by dividing the frequency of the clock signal 439 by two or a larger number. In one example, the clock circuit 390 generates the clock signal 491 by dividing the frequency of the clock signal 439 by eight. The clock signal 491 is output to the link layer circuit 374 and the PHY layer circuit 372.

[0099] The clock generation circuit 394 generates a clock signal 495, and outputs the clock signal 495 to the application circuit 354 and the link layer circuit 374. The frequency of the clock signal 395 is less than the frequency of the clock signal 491. In one example, the frequency of the clock signal 495 is 200 MHz.

[0100] The PHY layer circuit 372 uses the clock signal 492 to receive the framing pattern and the protocol word 406, and uses the clock signal 491 to output the protocol word 473. Thus, the frequency of the protocol word 473 is the same as the frequency of the clock signal 491, and is less than the frequency of the protocol word 406. In addition, the number of bits in the protocol word 473 is greater than the number of bits in the protocol word 406. The factor by which the number of bits in the protocol word 473 increases relative to the protocol word 406 is the same as the factor by which the frequency of the protocol word 473 decreases relative to the protocol word 406.

[0101] The link layer circuit 374 receives the protocol word 473 using the clock signal 491. The link layer circuit 374 identifies the framing pattern associated with the protocol word 473 and identifies the start of the protocol word 473. The link layer circuit 374 outputs the protocol word 475 using the clock signal 495. The link layer circuit 374 generates the control signal 375 from the protocol word 473 and the clock signal 495 by reducing the clock signal of the protocol word 473 to the frequency of the clock signal 495. Additionally, the link layer circuit 374 increases the number of bits within the protocol word 475 relative to the protocol word 473 based on the factor by which the frequency of the protocol word 475 is reduced relative to the protocol word 473.

[0102] The application circuit 354 receives the protocol word 475 using the clock signal 495 and transmits the control signal 477 from the IC chip 350 via the transmitter circuit of the application circuit 354. The application circuit 354 can transmit the control signal 477 to another IC chip of the multi-IC chip device 300 or to a system external to the multi-IC chip device 300.

[0103] As described above with respect to Figure 4 The sideband path including the application circuit 314, the C2C interface circuit 330, the C2C interface circuit 370, and the application circuit 354 uses a clock signal independent of the frequency of the data signal 471 transmitted by the application circuit 352. Thus, the sideband path including the application circuit 314, the C2C interface circuit 330, and the C2C interface circuit 370 is asynchronous with the data signal 471. In one or more examples, the data path including the application circuit 312, the C2C interface circuit 320, the C2C interface circuit 360, and the application circuit 352 uses a clock signal based on the frequency of the data signal 471. Thus, the data path including the application circuit 312, the C2C interface circuit 320, the C2C interface circuit 360, and the application circuit 352 uses a clock signal based on the frequency of the data signal 471 and is synchronous with the data signal 471. In one example, even when an error occurs within the data path and when the data path terminates transmitting the data signal, the sideband path continues to transmit protocol words (e.g., control data).

[0104] Figure 5 is a block diagram of the multi-IC chip device 500. The multi-IC chip device 500 includes the IC chip 510 and the IC chip 550. The IC chip 510 is connected to the IC chip 550 via the interface 502. The IC chip 510 is configured in a similar manner to the Figure 1 IC chip 110 and Figure 3 the IC chip 310, the IC chip 550 is configured in a similar manner to the Figure 1 IC chip 120 and the IC chip 350, and the interface 502 is configured in a similar manner to the Figure 1interface 130 and Figure 2 configured in a manner similar to interface 302. In Figure 5 example, IC chip 510 is the main IC chip, and IC chip 550 is the auxiliary IC chip or die.

[0105] As described above with respect to Figure 3 multi-IC chip device 300, multi-IC chip device 500 is configured in such a way that a data path and sideband connections are used between IC chip 510 and IC chip 550 to transfer data and control data (or other sideband information). However, compared with Figure 3 multi-IC chip device 300, multi-IC chip device 500 includes sideband circuits 522, 524, 552, 562 and 564 that communicate with each other via sideband and control signal 506.

[0106] IC chip 550 includes application circuit 352 and C2C interface circuit 560. C2C interface circuit 560 includes PHY layer circuit 362, link layer circuit 364, protocol layer circuit 366 and reducer circuit 368. In addition, IC chip 550 includes sideband circuits 552, 562 and 564. Sideband circuits 562 and 564 are included within C2C interface circuit 560. In addition, sideband circuit 562 may be included inside or outside PHY layer circuit 362. Sideband circuit 564 may be included inside or outside link layer circuit 364.

[0107] In addition, IC chip 350 includes clock circuit 380. Clock circuit 380 generates a data path clock signal (e.g., clock signal 505). The sideband clock signal is generated and transmitted via sideband circuits 552, 562 and 564. In one example, the sideband clock signal is transmitted as control signal 506. The sideband clock signal is generated independently of clock signal 505. The sideband clock signal may be referred to as a logic clock signal.

[0108] In one example, IC chip 550 is configured as the receiver circuit in a transceiver circuit. IC chip 550 receives data signal 551.

[0109] Clock circuit 380 includes clock generation circuit 382, multiplication delay locked loop (MDLL) circuit 386 and divider circuit 388. In one or more examples, clock circuit 380 includes optional divider circuit 38.

[0110] The IC chip 510 includes an application circuit 512 and a C2C interface circuit 320. The C2C interface circuit 320 includes a PHY layer circuit 322, a link layer circuit 324, and a protocol layer circuit 326. The C2C interface circuit 320 also includes sideband circuits 522 and 524. The sideband circuit 522 is included inside or outside the PHY layer circuit 322. The sideband circuit 524 is included inside or outside the link layer circuit 324.

[0111] In addition, the IC chip 510 includes a clock circuit 340. The clock circuit 340 receives a clock signal 505 (e.g., a data path or interface clock signal) from the IC chip 550. The clock signal 505 is transmitted as a differential signal. The sideband circuit 522 and the sideband circuit 524 receive a control signal 506 from the IC chip 350. The control signal 506 can be a sideband clock signal.

[0112] The clock circuit 340 includes a frequency divider circuit 342 and an MDLL circuit 344. The clock circuit 346 is a frequency divider circuit.

[0113] In one example, the IC chip 350 transmits a data signal 504, a clock signal 505, and a control signal 506 via an interface 302. The IC chip 550 generates the data signal 504 and the clock signal 505 based on the data signal 351. For example, the clock circuit 380 generates the clock signal 505 based on the data signal 551. The clock generation circuit 382 generates clock signals 583 and 584 from the data signal 351. The clock signals 583 and 584 can be the same or different in frequency. In one or more examples, the clock generation circuit 382 generates the clock signals 583 and 584 based on the received data signal 351. In addition, the frequency of the clock signal 583 and / or 584 corresponds to the frequency of the data signal 553 generated by the application circuit 352 from the data signal 351. In one example, the frequency of the clock signal 583 and / or 584 is 1.45 GHz, and the frequency of the data signal 553 is 1.45 GHz. The clock signal 583 is received by the application circuit 352, and the clock signal 584 is received by the MDLL circuit 386. In one example, the clock signal 584 is received by the frequency divider circuit 384. The clock signal 583 serves as the clock signal for the application circuit 352. In an example including a frequency divider circuit, the frequency divider circuit 384 divides the frequency of the clock signal 584 by two or a larger number to determine a divided clock signal 585. The divided clock signal 585 is received by the MDLL circuit 386. In an example where the frequency divider circuit 384 is omitted, the MDLL circuit 386 receives the clock signal 584.

[0114] The MDLL circuit 386 reduces the delay of the clock signal 584 or 585. In addition, the MDLL circuit 386 generates the clock signal 587 from the clock signal 584 or 585. For example, the MDLL circuit 386 multiplies the frequency of the clock signal 585 (or 584) by two or a larger number to generate the clock signal 587. In one or more examples, the clock signal 587 has a frequency of 2.9 GHz. The clock signal 587 is output by the driver circuit 356 via the interface 502 as the clock signal 505. In one example, the clock signal 505 is transmitted as a differential signal via two wires of the interface 502.

[0115] The clock signal 587 is also received by the frequency divider circuit 388. The frequency divider circuit 388 outputs the clock signals 589a, 589b, and 589c. The frequency divider circuit 388 generates the clock signal 589a by reversing the process applied by the frequency divider circuit 384 and the MDLL circuit 386. For example, the frequency divider circuit 588 divides the frequency of the clock signal 587 by two or a larger number, and multiplies the frequency of the clock signal by two or a larger number. In addition, the frequency divider circuit 388 generates the clock signal 589b by dividing the frequency of the clock signal 587 by two or a larger number. In addition, the clock signal 589c is passed through the frequency divider circuit 388 without being processed or changed. The frequency of the clock signal 589c is the same as the frequency of the clock signal 587.

[0116] The clock signal 589a is received by the reducer circuit 368 that uses the clock signal 589a to process the data signal 553. The reducer circuit 368 reduces the frequency of the data signal 553 to one-half or less of the original, and increases the number of bits of the data signal to two times or more of the original to generate the data signal 563. In one example, the data signal 553 has 80 bits and a frequency of 1.45 GHz. In such an example, when the frequency is reduced to one-half of the original and the number of bits is increased to two times the original, the data signal 563 has a frequency of 725 MHz. Reducing the frequency of the data signal 553 to generate the data signal 563 places the data signal 563 within the operating range of the link layer circuit 364 and the PHY layer circuit 362.

[0117] The protocol layer circuit 366 is bypassed because the data signal 563 is compatible with the link layer circuit 364 and the PHY layer circuit 362. The link layer circuit 364 receives the clock signal 589b and generates a framing pattern indicating the start of the data signal 563. The framing pattern, together with the data signal 563, is transmitted to the PHY layer circuit 362. In one example, the data signal 563 is transmitted together with a framing signal. The framing signal defines the valid data region within the data signal 563. In one example, the framing signal is used to mask the invalid data within the data signal 563. The PHY layer circuit 362 receives the clock signals 589b and 589c and generates the data signal 504 from the data signal 563. The PHY layer circuit 362 increases the frequency of the data signal 563 to two times or more of the original, and reduces the bit size to one-half or less of the original to generate the data signal 504. In one or more examples, the PHY layer circuit 362 increases the frequency of the data signal 563 to 5 times, 10 times, 15 times, 20 times or more of the original, and reduces the bit size to 1 / 5, 1 / 10, 1 / 15 or 1 / 20 or less of the original. In an example, the PHY layer circuit 362 increases the frequency of the data signal 563 to two times or more of the original, and reduces the bit size to one-half or less of the original. In an example where the data signal 563 has a bit size of 160 bits and a frequency of 725 MHz, the data signal 504 has a bit size of 16 bits and a frequency of 7.25 GHz. In one example, the PHY layer circuit 362 has a multiplication ratio of sixteen to one. In one or more examples, the PHY layer circuit 362 has other multiplication ratios. In one example, the data signal 504 has a frequency of 7.25 GHz and 16 bits. In another example, the data signal 504 has a frequency greater than or less than 7.25 GHz.

[0118] The control signal 506 is transmitted from the IC chip 550 to the IC chip 510 via the interface 502. The control signal 506 is generated based on the control signal generated by the application circuit 352. The control signal 506 can be a sideband clock signal or include an indication of the frequency of the sideband clock signal. The control signal 506 is received by the sideband circuit 522 and then by the sideband circuit 524. The output of the sideband circuit 524 is provided to the flip-flop 517. In one example, the clock signal of the control signal 506 is generated based on the clock signal generated by the IC chip 550 independently of the data signal 551.

[0119] The IC chip 510 receives a data signal 504, a clock signal 505, and a control signal 506. The receiver circuit 348 receives the clock signal 505. The receiver circuit 348 outputs the received clock signal 505 as a clock signal 549 to the frequency divider circuit 342. The frequency divider circuit 342 reduces the frequency of the clock signal 549 by two times or more. In a specific example, the frequency divider circuit 342 reduces the frequency of the clock signal 549 by ten times. The frequency divider circuit 342 also outputs the clock signal 549 to be used as a through circuit so that the clock signal 549 is not changed by the frequency divider circuit 342. The clock signal 549 is output to the PHY layer circuit 322.

[0120] The clock signal 543 is output to the PHY layer circuit 332 and the link layer circuit 334. In addition, the clock signal 543 is output to the MDLL circuit 344. The MDLL circuit 344 generates a clock signal 545 based on the clock signal 543 and a feedback signal (e.g., the clock signal 515) received from the application circuit 512. The clock signal 543 is output to the application circuit 512. In one example, the buffer 313 of the application circuit 512 receives the clock signal 545 and generates the clock signal 515. In one example, the clock signal 515 is a capture clock signal for the flip-flop 517 of the application circuit 512. Thus, the clock signal 515 is generated based on the data signal 553, which is a clock signal for the application circuit 512.

[0121] In one or more examples, the feedback signal (e.g., the clock signal 515) is used by the MDLL circuit 344 to deskew the clock signal 543 and for phase alignment of the clock signal 543.

[0122] The PHY layer circuit 322 receives the data signal 504 and generates a data signal 523 from the data signal 504 and the clock signals 549 and 543. In one example, the PHY layer circuit 322 receives the data signal 504 using the clock signal 543 and generates the data signal 553 using the clock signal 549. The link layer circuit 324 detects a framing pattern associated with the data signal 523, identifies the start of the data signal 523 based on the framing pattern, and generates a data signal 525 based on the clock signal 543. In one example, the framing signal is used to detect valid data within the data signal 525.

[0123] The data signal 525 has a frequency corresponding to the operating frequency of the application circuit 512. For example, the frequency of the data signal 525 is the same as the frequency of the clock signal 505. In addition, the bit data signal of the data signal 525 is greater than the bit size of the data signal 504. The bit size of the data signal 525 is two or more times the bit size of the data signal 504, where the frequency of the data signal 504 is two or more times the frequency of the data signal 525. In one example, the PHY layer circuit 322 divides the frequency of the data signal 504 by two or a larger number and multiplies the bit size of the data signal 504 by two or a larger number to generate the data signal 523. In one example, the PHY layer circuit 322 has a multiplication ratio of twenty to one. In another example, the PHY layer circuit 322 has other multiplication ratios.

[0124] The data signal 525 is received by the application circuit 512 based on the clock signal 515. In one example, the flip-flop 317 captures the data signal 525 based on the clock signal 315.

[0125] In the above example described with respect to Figure 5 the IC chip 510 receives the data signal 504 generated from the data signal 351 using the clock signal 505, which is generated from the data signal 351. Thus, any error in the data signal 553 and / or within the IC chip 550 that causes the clock signal 505 to stop will stop (e.g., abort) the functionality of the C2C interface circuit 320 and the application circuit 512. In addition, since the IC chip 310 receives the control signal 506 using a sideband clock signal independent of the clock signal 505, any error in the data signal 351 and / or within the IC chip 50 will not affect the operation of the C2C interface circuit 520 and the application circuit 512. Thus, when an error occurs in the data signal 351 and / or within the IC chip 550, the C2C interface circuit 520 and the application circuit 512 are able to continue to receive and process protocol words.

[0126] In one example, the data paths associated with the application circuit 352, the C2C interface circuit 560, the C2C interface circuit 520, and the application circuit 512 may be referred to as synchronous data paths because the data paths send and receive data synchronously with the frequency of the data signal to be transmitted. The sideband paths associated with the sideband circuits 552, 564, 562, and the sideband circuits 522 and 524 may be referred to as asynchronous sideband paths because the sideband paths send and receive control data (e.g., protocol words) asynchronously with the frequency of the data signal.

[0127] In Figure 6In the example, the data signal 625 is transmitted from the application circuit 312 of the IC chip 510 to the application circuit 352 of the IC chip 550 for transmission. In such examples, the application circuit 352 is a transmitter circuit (e.g., the transmitter circuit of a SERDES transceiver, etc.) configured to transmit a data signal (e.g., data signal 616). Compared with Figure 5 the example, in Figure 6 , the clock signals 681 and 683 are output from the clock generation circuit 382. The clock signal 683 is received by the application circuit 352.

[0128] The clock signal 681 is processed by the frequency divider circuit 384 to generate a divided clock signal 685, similar to that described above with respect to the clock signal 683 and the divided clock signal 685. In one or more examples, the frequency divider circuit 384 is omitted, and the clock signal 681 is received by the MDLL circuit 386. The MDLL circuit 386 generates a clock signal 687 from the divided clock signal 685 or the clock signal 681, similar to that described above.

[0129] The clock signal 687 is output by the driver circuit 355 as the clock signal 608 and is received by the receiver circuit 348 as the clock signal 649. The clock signal 608 is transmitted as a differential signal via a pair of wires of the interface 502. The frequency divider circuit 342 outputs the clock signal 649 via a through circuit such that the clock signal 649 is not changed by the frequency divider circuit 342.

[0130] The clock signal 607 is transmitted from the IC chip 510 to the IC chip 550 via the interface 502. For example, the driver circuit 448 of the IC chip 310 outputs the clock signal 649 as the clock signal 607 to the receiver circuit 455 of the IC chip 550. The clock signal 607 is transmitted as a differential signal via a pair of wires of the interface 502. The receiver circuit 455 receives the clock signal 607 and outputs the clock signal 607 to the frequency divider circuit 388. The frequency divider circuit 388 generates clock signals 689a, 689b, and 689c from the clock signal 607. For example, the frequency divider circuit 388 divides the frequency of the clock signal 607 by "Y" to generate the clock signal 689a, divides it by "Z" to generate the clock signal 689b, and shifts the phase of the clock signal 607 by ninety degrees to generate the clock signal 689c. In one or more examples, "Y" and "Z" are numbers of one or greater. In one example, "Y" is less than "Z". In a specific example, "Y" is 2.5 and "Z" is 5.

[0131] The frequency divider circuit 342 generates a clock signal 643 from a clock signal 689 by dividing the frequency of the clock signal 649 by two or a larger number. In one example, the frequency divider circuit 342 divides the frequency of the clock signal 649 by ten to generate the clock signal 643. The clock signal 643 is output to the PHY layer circuit 322, the link layer circuit 324, and the MDLL circuit 344.

[0132] The MDLL circuit 344 additionally receives a feedback signal (e.g., the clock signal 615) from the application circuit 312. The application circuit 312 includes a buffer 313 that receives the clock signal 645 from the MDLL circuit 344 and outputs the clock signal 615 based on the clock signal 645. The MDLL circuit 344 performs anti-skew on the clock signal 643, thereby adjusting the phase alignment mismatch between the clock signal 643 and the clock signal 615, so as to generate the clock signal 645.

[0133] The application circuit 312 uses the clock signal 615 to output a data signal 625. For example, the flip-flop 317 captures the values of the data signal 616 based on the clock signal 615 and outputs these values.

[0134] The link layer circuit 324 uses the clock signal 643 to receive the data signal 625 and outputs the data signal 627 to the PHY layer circuit 322 in a framed mode. The link layer circuit 324 generates a framed mode from the data signal 627. The PHY layer circuit 322 uses the clock signal 643 to receive the data signal 627 and the framed mode, and uses the clock signal 649 to output the data signal 627 and the framed mode as a data signal 604. In one example, the data signal 627 is sent together with a framing signal. The framing signal defines the valid data region within the data signal 627. In one example, the framing signal is used to mask the invalid data within the data signal 627.

[0135] The PHY layer circuit 322 increases the frequency of the data signal 627 and reduces the number of bits within the data signal 627 to generate a data signal 604. In one example, the degree of frequency increase is the same as the degree of bit reduction. For example, the frequency of the data signal 627 is increased to twenty times or more of the original, and the number of bits of the data signal 627 is reduced to one-twentieth or less of the original.

[0136] The PHY layer circuit 362 receives the data signal 604 and the framing pattern using the clock signal 689c. The PHY layer circuit 362 outputs the data signal 663 and the framing pattern using the clock signal 689b. The link layer circuit 364 uses the clock signal 689b to detect the framing pattern and identify the start of the data signal 663. Additionally, the framing signal is used to define the valid bits within the data signal 604. The link layer circuit 364 outputs the data signal 667 having a frequency based on the clock signal 689b. Since the frequency of the clock signal 689b is less than the frequency of the data signal 604, the link layer circuit 364 increases the number of bits within the data signal 667 based on the difference between the frequency of the data signal 604 and the frequency of the clock signal 689b.

[0137] The data signal 667 is received by the reducer circuit 368, which adjusts the frequency and bit size of the data signal 667 to generate the data signal 669. The reducer circuit 368 also receives the clock signal 689a. The reducer circuit 368 adjusts the frequency of the data signal 667 based on the frequency of the clock signal 689a. Since the frequency of the clock signal 689a is greater than the frequency of the data signal 667, the reducer circuit 368 increases the frequency of the data signal 667 to generate the data signal 669. The frequency of the data signal 669 is the frequency of the clock signal 689a.

[0138] The application circuit 352 receives the data signal 669 and sends the data signal 669 out of the IC chip 350.

[0139] The control word 609 is sent from the IC chip 510 to the IC chip 550 via the interface 502. The control signal 609 can be a sideband clock signal and / or an indication including the frequency of the sideband clock signal. In one example, the sideband circuits 522 and 524 generate the sideband clock signal and / or data indicating the frequency of the sideband clock signal, and send the control signal 609 including the sideband clock signal or information corresponding to the sideband clock signal. The sideband clock signal is independent of the clock signals 608 and 607 and is generated independently of the data signal 616. In one or more examples, the frequency of the sideband clock signal is different from the frequency of the clock signal 607 or 608. In one or more examples, the frequency of the sideband clock signal is less than the frequency of the clock signal 607 or 608.

[0140] The sideband clock signal transmitted as the control signal 609 is asynchronous with the data signal 671. In contrast, the data path including the application circuit 312, the C2C interface circuit 320, the C2C interface circuit 360, and the application circuit 352 uses a clock signal based on the frequency of the data signal 671 and is synchronous with the data signal 671. In one example, even when an error occurs within the data path and when the data path terminates transmitting the data signal, the control signal path continues to transmit control data and the sideband clock signal.

[0141] In Figure 5 and Figure 6 In an example, the interfaces 502 and 502 transmit control data via the sideband path. The sideband paths of the interfaces 502 and 502 include one or more data lines. In one example, the sideband path includes one data line, a single port of the IC chip 510, and a single port of the IC chip 550. In another example, the sideband path includes more than one data line, more than one port of the IC chip 510, and more than one port of the IC chip 550. Additionally, the interfaces 502 and 502 use two or more data lines to transmit the data signal 504, the clock signal 505, the data signal 604, and the clock signals 608 and 607, respectively. In one example, the interfaces 502 and 502 include 40 or more data lines.

[0142] In one or more examples, when data is sent from a first IC chip (e.g., IC chip 110) to a second IC chip (e.g., IC chip 120), the data is synchronized and sent as a continuous data stream. During the data transmission, the data is serialized and deserialized. However, during the transmission, the clock signal source can be constant. Therefore, errors may occur in the transmission of this data. In one example, to ensure the existence of a constant clock signal source, synchronization with the high-speed clock signal generated within the IC chip (e.g., IC chip 110 or 120) is used.

[0143] Figure 7 Illustrates the waveforms of various clock signals, control signals, and data signals. As Figure 7 illustrated, the clock signal 710 is the clock signal of an application circuit (e.g., Figure 7 the application circuit 210). The clock signal 712 is the clock signal for the PHY layer circuit (e.g., Figure 2 the PHY layer circuit 216), and the clock signal 714 is the clock signal for the link layer circuit (e.g., Figure 2 the link layer circuit 214). The signal 716 is the mux selection signal, and the data signal 718 is the channel data signal. Additionally, the signal 720 is for a receiver (e.g., Figure 2The link layer circuit clock signal of the link layer circuit 224), and the signal 722 is a data output signal. The clock signal 714 is synchronized with the clock signal 712. In addition, at the rising edge of the clock signal 714, the data within the data signal 718 is transmitted. When the transmission of the data within the data signal is completed, a series of 0s is transmitted within the data signal 718 until the next rising edge is detected. At the next rising edge, a framing pattern (e.g., a series of 1s) and a new data signal are transmitted.

[0144] As Figure 7 Illustrated by the timing diagram of, the synchronization of four cycles is reduced to 0.5 cycles. In one example, within 14.5 cycles of the clock signal 712, there are 0.5 cycles available for setting the transmitter circuit, 12 cycles of delay, 1 cycle of jitter, 1 cycle of mismatch, and 0 cycles for receiver circuit setting. In one example, Figure 8 One or more of the MDLL circuits 840, 842, 881, and 886 (or Figures 3 to 6 One or more of the MDLL circuits 386, 390, 344, 346) of are configured in a primary-secondary configuration. The primary MDLL circuit is locked to the corresponding C2C interface clock signal. The primary MDLL circuit sets the control voltage for the C2C interface circuit. In addition, the primary MDLL circuit provides a continuous clock signal for regenerating the corresponding architecture (e.g., application circuit) clock signal. The secondary MDLL circuit generates a burst clock signal. This burst clock signal can be used by the PHY layer circuit (e.g., Figures 3 to 6 And Figures 8 to 9 The PHY layer circuits 322, 332, 822, 836, 892, 922, and / or 982) of. This burst clock signal starts at the rising edge of the clock signal for the application circuit.

[0145] In one example, the clock synchronization technique is applied to Figure 8 The multi-IC chip device of. Figure 8 Illustrates the multi-IC chip device 800. The multi-IC chip device 800 includes the IC chip 810 and the IC chip 850. The IC chips 810 and 850 are main IC chips configured similarly to the Figure 1 IC chips 110 and 120 of. The IC chip 810 includes the application circuit 812, the application circuit 814, the C2C interface circuit 820, and the C2C interface circuit 830. In addition, the IC chip 810 includes the clock circuit 840, the clock circuit 842, the driver circuit 844, the driver circuit 846, and the receiver circuit 848.

[0146] The C2C interface circuit 820 includes a PHY layer circuit 822, a link layer circuit 824, and a protocol layer circuit 826. The C2C interface circuit 820 is configured to be similar to the C2C interface circuit 112. The PHY layer circuit 822 is configured in a manner similar to the Figure 2 PHY layer circuit 216, the link layer circuit 824 is configured in a manner similar to the Figure 2 link layer circuit 214, and the protocol layer circuit 826 is configured in a manner similar to the Figure 2 protocol layer circuit 212.

[0147] The C2C interface circuit 830 includes a PHY layer circuit 832, a link layer circuit 834, and a protocol layer circuit 836. The C2C interface circuit 830 is configured to be similar to the C2C interface circuit 112. The PHY layer circuit 832 is configured in a manner similar to the Figure 2 PHY layer circuit 216, the link layer circuit 834 is configured in a manner similar to the Figure 2 link layer circuit 214, and the protocol layer circuit 836 is configured in a manner similar to the Figure 2 protocol layer circuit 212.

[0148] The IC chip 850 includes an application circuit 852, an application circuit 854, a C2C interface circuit 860, and a C2C interface circuit 870. In addition, the IC chip 850 includes a clock circuit 880, a clock circuit 881, a receiver circuit 883, a receiver circuit 889, and a driver circuit 852.

[0149] The C2C interface circuit 860 includes a PHY layer circuit 882, a link layer circuit 884, and a protocol layer circuit 866. The C2C interface circuit 860 is configured to be similar to the C2C interface circuit 112. The PHY layer circuit 882 is configured in a manner similar to the Figure 2 PHY layer circuit 216, the link layer circuit 884 is configured in a manner similar to the Figure 2 link layer circuit 214, and the protocol layer circuit 866 is configured in a manner similar to the Figure 2 protocol layer circuit 212.

[0150] The C2C interface circuit 870 includes a PHY layer circuit 872, a link layer circuit 894, and a protocol layer circuit 896. The C2C interface circuit 870 is configured to be similar to the C2C interface circuit 112. The PHY layer circuit 872 is configured in a manner similar to the Figure 2 PHY layer circuit 216, the link layer circuit 874 is configured in a manner similar to the Figure 2 link layer circuit 214, and the protocol layer circuit 876 is configured in a manner similar to the Figure 2 protocol layer circuit 212.

[0151] The application circuit 812 outputs a data signal 813 based on a clock signal 815. The clock signal 815 is the clock signal of the application circuit 812. The clock signal 815 is output to the clock circuit 840. The clock circuit 840 also receives a clock signal 817. The clock signal 817 is generated and output from a clock generation circuit (not shown) inside or outside the IC chip 810. The clock circuit 840 divides the frequency of the clock signal 817 and synchronizes the clock signal 817 with the clock signal 815 to generate a clock signal 841. The clock circuit 840 divides the frequency of the clock signal 817 by two or a larger number. In one example, the clock circuit 840 divides the frequency of the clock signal 817 by eight. In addition, the clock circuit 840 outputs a clock signal 843. In one example, the clock signal 843 is the clock signal 817. In this example, the clock circuit 840 serves as a through circuit, outputting the clock signal 843 such that the clock signal 817 is the same as the clock signal 843. In one example, the clock signal has a frequency of 4 GHz. In one or more examples, the clock signal has a frequency greater than or less than 4 GHz.

[0152] The link layer circuit 824 receives the clock signal 841 and the data signal 813. The link layer circuit 824 generates a framing pattern from the data signal 813. In addition, the link layer circuit 824 generates a data signal 825 based on the clock signal 841. In one example, the data signal 813 is transmitted together with a framing signal. The framing signal defines a valid data region within the data signal 813. In one example, the framing signal is used to mask invalid data within the data signal 813.

[0153] The frequency of the data signal 825 is greater than the frequency of the data signal 813, and the number of bits within the data signal 825 is less than the number of bits of the data signal 813. In one example, the factor by which the number of bits within the data signal 825 is reduced relative to the number of bits of the data signal 813 is the same as the factor by which the frequency of the data signal 825 is increased relative to the frequency of the data signal 813. The frequency of the data signal 825 is based on the frequency of the clock signal 841. In one example, the frequency of the data signal 825 is the same as the frequency of the data signal 841.

[0154] The PHY layer circuit 822 receives the clock signal 841, the clock signal 843, and the data signal 825 (as well as the corresponding framing pattern). The PHY layer circuit 822 uses the clock signal 841 to receive the data signal 825. The PHY layer circuit 822 uses the clock signal 841 to generate and output the data signal 827 and the corresponding framing pattern. In addition, the framing signal can be received and used to detect the valid bits within the data signal 827. The frequency of the data signal 827 is greater than the frequency of the data signal, and the number of bits within the data signal 827 is less than the number of bits of the data signal 825. In one example, the factor by which the number of bits within the data signal 827 is reduced relative to the number of bits of the data signal 825 is the same as the factor by which the frequency of the data signal 827 is increased relative to the frequency of the data signal 825. The frequency of the data signal 827 is based on the frequency of the clock signal 843. In one example, the frequency of the data signal 827 is the same as the frequency of the clock signal 843. In one example, the data signal 827 is transmitted at 4 GHz. In addition, a double data rate process is used to transmit the data signal 827.

[0155] The driver circuit 844 receives the clock signal 843 and outputs the clock signal 843 to the receiver circuit 883 of the IC chip 850. In addition, the driver circuit 846 outputs the clock signal 845 to the receiver circuit 884 of the IC chip 850. In one example, the clock signal 845 is generated and transmitted via the sideband circuit as described above with respect to Figure 5 and Figure 6 In one example, the clock signal 843 is generated at the transition (e.g., rising edge or falling edge) of the clock signal 845.

[0156] The clock circuit 880 receives the clock signal 843 from the receiver circuit 883 and generates and outputs the clock signals 891 and 892. The clock circuit 880 shifts the phase of the clock signal 843 by ninety degrees to generate the clock signal 891. In addition, the clock circuit 880 divides the frequency of the clock signal 843 by two or a larger number to generate the clock signal 892. In one example, the clock circuit 880 divides the frequency of the clock signal 843 by eight to generate the clock signal 892.

[0157] The PHY layer circuit 882 receives the clock signal 891, the clock signal 892, the data signal 827, and the corresponding framing pattern. The PHY layer circuit 882 uses the clock signal 891 to receive the data signal 827 and the corresponding framing pattern, and uses the clock signal 892 to output the data signal 863 to the link layer circuit 884. The framing signal is received and used to identify the valid data within the data signal 827. For example, the PHY layer circuit 882 reduces the frequency of the data signal 827 by a common factor and increases the bit size of the data signal 827 to generate the data signal 863. The frequency of the data signal 863 is the frequency of the clock signal 892.

[0158] The data signal 863, the corresponding framing pattern, and the clock signal 892 are received by the link layer circuit 884. The link layer circuit 884 uses the clock signal 892 to receive the data signal 863 and the corresponding framing pattern. Since the data in the data signal 863 is in serial format, the link layer circuit 884 uses the framing pattern to identify the start of the data signal 863. The framing signal is received and used to identify the valid data within the data signal 863.

[0159] The link layer circuit 884 generates the data signal 865 from the data signal 863. The frequency of the data signal 865 is less than the frequency of the data signal 863, while the number of bits of the data signal 865 is greater than the number of bits of the data signal 863. In one example, the link layer circuit 884 increases the number of bits of the data signal 865 and reduces the frequency of the data signal 865 by the same factor to generate the data signal 863. In one example, the data signal 865 has a frequency of 200 MHz and a bit size of 892 bits.

[0160] The data signal 865 is received by the application circuit 852. The application circuit 852 receives the data signal 865 using the clock signal 894. In one example, the clock circuit 881 is an MDLL that receives the clock signal 815 from the receiver circuit 884. The clock circuit 881 also receives a feedback signal (e.g., the clock signal 894). The clock circuit 881 reduces the phase alignment error based on the feedback signal and performs anti-skew on the clock signal 815, thereby generating and outputting the clock signal 893. The clock signal 893 is received by the application circuit 852. In one example, the application circuit 852 includes a buffer 853 and a flip-flop 855. The buffer 853 outputs the clock signal 894 from the clock signal 893. The clock signal 894 is received by the flip-flop 855 and used to receive the data signal 865.

[0161] The application circuit 854 also receives the clock signal 894 from the application circuit 852. The application circuit 854 includes a flip-flop 855 that outputs the data signal 857 using the clock signal 894.

[0162] The clock signal 894 is also received by the clock circuit 886. The clock circuit 886 further receives a clock signal 895 from a clock generation circuit (not shown) external or internal to the IC chip 850. The clock circuit 886 uses the clock signal 894 to synchronize the clock signal 895, thereby generating clock signals 887 and 897. The clock signal 887 is the same as the clock signal 895. In one example, the clock signal 895 is the same as the clock signal 817. The clock signal 895 may have a frequency of 4 GHz. In one example, the clock signal 895 has a frequency greater than or less than about 4 GHz.

[0163] The clock circuit 886 reduces the frequency of the clock signal 895 to generate the clock signal 897. For example, the clock circuit 886 divides the frequency of the clock signal 895 by two or a larger number to generate the clock signal 897. In one example, the clock circuit 886 divides the frequency of the clock signal 895 by eight to generate the clock signal 897.

[0164] The link layer circuit 874 receives the clock signal 897 from the clock circuit 886. The link layer circuit 874 uses the clock signal 897 to receive the data signal 857 from the application circuit 854. The link layer circuit 874 uses the clock signal 897 to generate a framing pattern and a data signal 875 from the data signal 857. The frequency of the data signal 875 is greater than the frequency of the data signal 857, and the bit size of the data signal is smaller than the bit size of the data signal 857. In one example, the data signal 875 is transmitted together with a framing signal. The framing signal defines the valid data region within the data signal 875. In one example, the framing signal is used to mask invalid data within the data signal 875.

[0165] The PHY layer circuit 872 receives the clock signals 896 and 897. The PHY layer circuit 872 uses the clock signal 897 to receive the data signal 875 and the corresponding framing pattern, and uses the clock signal 896 to generate a data signal 873 from the data signal. In one example, the framing signal is received and used to identify the valid data within the data signal 873.

[0166] The PHY layer circuit 872 increases the frequency of the data signal 875 and decreases the bit size of the data signal 875 by the same factor to generate the data signal 873. In one or more examples, the PHY layer circuit 872 increases the frequency of the data signal 875 to two or more times the original frequency and decreases the bit size of the data signal 875 to one-half or less of the original bit size to generate the data signal 873. In one or more examples, the PHY layer circuit 872 increases the frequency of the data signal 875 to two or more times the original frequency and decreases the bit size of the data signal 875 to one-sixteenth of the original bit size to generate the data signal 873. The data signal 873 has a bit size of 42 bits and a frequency of 4 GHz. In addition, the data signal 873 is transmitted via a double data rate process.

[0167] The driver circuit 885 receives the clock signal 896 and outputs the clock signal 896 as the clock signal 887 to the receiver circuit 848 of the IC chip 810. The clock circuit 842 receives the clock signal 887 and outputs the clock signals 897 and 898. The clock circuit 842 shifts the phase of the clock signal 887 by ninety degrees to generate the clock signal 897. The clock circuit 842 divides the frequency of the clock signal 887 by two or a larger number to generate the clock signal 898. In one example, the clock circuit 842 divides the frequency of the clock signal 887 by eight to generate the clock signal 898.

[0168] The PHY layer circuit 832 receives the clock signal 897 and the clock signal 898. The PHY layer circuit 832 uses the clock signal 897 to receive the data signal 873 and the corresponding framing pattern. In one example, the PHY layer circuit 832 decreases the frequency of the data signal 873 to one-half or less of the original frequency and increases the bit size of the data signal 873 to two or more times the original bit size to generate the data signal 837. In a specific example, the PHY layer circuit 832 decreases the frequency of the data signal 873 to 1 / 16 of the original frequency and increases the bit size of the data signal 873 to 16 times the original bit size to generate the data signal 837. The PHY layer circuit 832 also uses the clock signal 898 to generate and output the data signal 837 and the corresponding framing pattern.

[0169] The link layer circuit 834 receives the clock signal 898. In addition, the link layer circuit 834 uses the clock signal 898 to receive the data signal 837 and the corresponding framing pattern. The link layer circuit 834 uses the framing pattern to identify the start of the data signal 837 and generates the data signal 835. In one example, a framing signal is received and used to determine the valid bits within the data signal 837.

[0170] In addition, the link layer circuit 834 reduces the frequency of the data signal 837 and increases the number of bits of the data signal to the same extent to generate the data signal 835. In one example, the link layer circuit 834 reduces the frequency of the data signal 837 to one-half or less of the original, and increases the number of bits of the data signal to twice or more than twice the original to generate the data signal 835. In one example, the link layer circuit 834 reduces the frequency of the data signal 837 such that the data signal 837 has the frequency of the clock signal 898. In one example, the data signal 835 has a bit size of 892 bits and a frequency of 200 MHz.

[0171] The application circuit 814 receives the clock signal 815 and uses the clock signal 815 to receive the data signal 835. In one example, the application circuit 814 includes a flip-flop 819. The flip-flop 819 receives the data signal 835 using the clock signal 815.

[0172] In Figure 8 an example, the clock signal (e.g., the clock signal 815) used by the application circuit 812 that sends the data signal is transmitted and shared within the IC chips 810 and 850 such that the application circuits 812, 814, 852, and 854 are driven by the same clock signal (e.g., the clock signal 815). In addition, the C2C interface circuits 820 and 860 of the IC chips 810 and 850 operate respectively based on the same clock signal (e.g., the clock signal 843). The clock signal is sent between the IC chips 810 and 850 such that the C2C interface circuits 820 and 860 operate based on the same clock signal. The C2C interface circuits 830 and 890 of the IC chips 810 and 850 operate respectively based on the same clock signal (e.g., the clock signal 887). The clock signal 887 is sent between the IC chips 810 and 850 such that the C2C interface circuits 860 and 890 operate based on the same clock signal.

[0173] In one or more examples, the scheme described as Figure 8 in the example can be referred to as an oversampling process or scheme. As described above, the frequency of the clock signal 843 is a multiple (e.g., N times) of the frequency of the clock signal 845. N is a number equal to or greater than two. In one example, N is four. N can be set such that the frequency of the clock signal 843 is based on the minimum frequency required for the accurate reproduction of the signal 827. In addition, in one or more examples, the C2C interface circuits 820, 830, 860, and 870 operate at a frequency higher than the frequency of the incoming data signal.

[0174] Figure 9Illustrated is a multi-IC chip device 900 according to one or more examples. The multi-IC chip device 900 includes an IC chip 910 and an IC chip 950. The IC chip 910 includes an application circuit 912 and a C2C interface circuit 920. In addition, the IC chip 810 includes a driver circuit 918. The C2C interface circuit 920 includes a PHY layer circuit 922, a link layer circuit 924, and a protocol layer circuit 926. The C2C interface circuit 920 is configured in a manner similar to that of the C2C interface circuit 112 of Figure 1 The PHY layer circuit 922 is configured in a manner similar to that of the PHY layer circuit 216 of Figure 2 The link layer circuit 924 is configured in a manner similar to that of the link layer circuit 214 of Figure 2 and the protocol layer circuit 926 is configured in a manner similar to that of the protocol layer circuit 212 of Figure 2 .

[0175] The IC chip 950 includes an application circuit 952 and a C2C interface circuit 960. In addition, the IC chip 950 includes a receiver circuit 958. The C2C interface circuit 960 includes a PHY layer circuit 962, a link layer circuit 964, and a protocol layer circuit 966. The C2C interface circuit 960 is configured in a manner similar to that of the C2C interface circuit 112 of Figure 1 The PHY layer circuit 962 is configured in a manner similar to that of the PHY layer circuit 216 of Figure 2 The link layer circuit 964 is configured in a manner similar to that of the link layer circuit 214 of Figure 2 and the protocol layer circuit 966 is configured in a manner similar to that of the protocol layer circuit 212 of Figure 2 .

[0176] As Figure 9The illustrated example is used as part of a test interface to test the functionality of IC chips 910 and 950. In this example, protocol layer circuits 926, link layer circuits 924, link layer circuit 964, and protocol layer circuit 966 are bypassed. Thus, data signal 990 output from application circuit 912 is transmitted to PHY layer circuit 922 bypassing the protocol layer circuits and link layer circuits. Application circuit 912 outputs data signal based on clock signal 992. In one example, application circuit 912 includes buffer 916 and flip-flop 914. Buffer 916 outputs clock signal 992. Clock signal 992 is generated by a clock generation circuit (not shown) connected to the input of buffer 916. Flip-flop 914 receives clock signal 992 and outputs data signal 990 based on clock signal 992. Further, clock signal 992 is received by driver circuit 918, which outputs clock signal 992 to receiver circuit 958. Clock signal 992 is output from receiver circuit 958 and received by the application circuit. For example, clock signal 992 is received and output by buffer 956 and then received by flip-flop 954.

[0177] PHY layer circuit 922 outputs data signal 990 via interface 902. PHY layer circuit 962 receives data signal 990 via interface 902 and outputs data signal 990 to application circuit 952.

[0178] Application circuit 952 receives data signal 990 using clock signal 992. For example, application circuit 952 includes flip-flop 954 that receives clock signal 992 from buffer 956, and flip-flop 954 receives data signal 990 using clock signal 992.

[0179] As Figure 9 illustrated, clock signal 992 is used by IC chips 910 and 950 to transmit and receive data signal 990.

[0180] In one or more examples, clock signal 992 is transmitted via the sideband circuits of C2C interface circuit 920 and C2C interface circuit 960, as described above with respect to Figure 5 and Figure 6 described.

[0181] Figure 10 Illustrated is an example clock generation circuit 1000 according to one or more examples. Clock generation circuit 1000 can be used to deskew clock signals within an IC chip (e.g., Figure 1 IC chips 110 and / or 120). The clock generation circuit includes MDLL circuit 1010, phase interpolator circuit 1020, phase reference circuit 1030, and phase detector circuit 1040. In one example, clock generation circuit 1000 can be used asFigure 3 a part of the clock circuit 344 and / or Figure 8 the clock circuit 881.

[0182] The clock generation circuit 1000 generates clock signals 1062, 1064, and 1066, and drives and outputs the clock signals 1062, 1064, and 1066 to the clock tree circuit 1050. The clock tree circuit 1050 includes a PHY layer clock tree circuit 1052, a link and protocol clock tree circuit 1054, and an application clock tree circuit 1056. The PHY layer clock tree circuit 1052 corresponds to Figure 2 the PHY layer circuit 216, the link and protocol clock tree circuit 1054 corresponds to Figure 2 the link layer circuit 214 and the protocol layer circuit 212, and the application clock tree circuit 1056 corresponds to Figure 2 the application circuit 210.

[0183] The MDLL circuit 1010 receives the clock signal 1008 and generates clock signals 1012, 1014, and 1016 from the clock signal 1008 and the feedback signal. The frequency of the clock signal 1012 is greater than the frequency of the clock signal 1014, and the frequency of the clock signal 1014 is greater than the frequency of the clock signal 1016. The clock signals 1012, 1014, and 1016 are received by the phase interpolator circuit 1020.

[0184] The phase interpolator circuit 1020 also receives phase signals 841, 1043, and 1045 from the phase detector circuit 1040. The phase detector circuit 1040 receives clock signals 1053, 1055, and 1057 from the clock tree circuit 1050. The phase detector circuit 1040 includes a phase detector section circuit 1042, a phase detector section circuit 1044, and a phase detector section circuit 1046. The phase detector section circuit 1042 determines the phase difference between the clock signals 1053 and 1055, the phase detector section circuit 1044 determines the phase difference between the clock signals 1055 and 1057, and the phase detector section circuit 1046 determines the phase difference between the clock signals 1053 and the clock signal 1062.

[0185] The phase detector section circuit 1042 generates and outputs the phase signal 1043 based on the phase difference between the clock signals 1053 and 1055, the phase detector section circuit 1044 generates and outputs the phase signal 1045 based on the phase difference between the clock signals 1053 and 1057, and the phase detector section circuit 1046 generates and outputs the phase signal 1047 based on the phase difference between the clock signals 1053 and 1062.

[0186] The phase interpolator circuit 1020 includes a phase interpolator circuit 1022, a phase interpolator circuit 1024, and a phase interpolator circuit 1026. The phase interpolator circuit 1022 receives a clock signal 1012, a reference clock signal 1031, and a phase signal 1043, and generates a clock signal 1062. The phase interpolator circuit 1022 adjusts the phase of the clock signal 1012 based on the phase signal 1043 and the reference clock signal 1031 to generate the clock signal 1062. The phase interpolator circuit 1024 receives a clock signal 1014, a reference clock signal 1031, and a phase signal 1045, and generates a clock signal 1064. The phase interpolator circuit 1024 adjusts the phase of the clock signal 1014 based on the phase signal 1045 and the reference clock signal 1031 to generate the clock signal 1064. The phase interpolator circuit 1026 receives a clock signal 1016, a reference clock signal 1031, and a phase signal 1047, and generates a clock signal 1066. The phase interpolator circuit 1026 adjusts the phase of the clock signal 1016 based on the phase signal 1047 and the reference clock signal 1031 to generate the clock signal 1066.

[0187] In one or more examples, an IC device includes a first IC chip, a second IC chip, and a chip-to-chip interface connected between the first IC chip and the second IC chip. The chip-to-chip interface is configured to transfer an interface clock signal and a logic clock signal between the first IC chip and the second IC chip. The interface clock signal is synchronized with a data signal received by one of the first IC chip and the second IC chip, and the logic clock signal is asynchronous with the data signal.

[0188] In one or more examples, a logical clock signal is generated independently of an interface clock signal. In one or more examples, a first IC chip is configured as a receiver and outputs the interface clock signal and the logical clock signal, and a second IC chip is configured as a transmitter and receives the interface clock signal and the logical clock signal from the first IC chip. In one or more examples, the first IC chip is configured as a receiver and outputs the logical clock signal and receives the interface clock signal, and the second IC chip is configured as a transmitter and outputs the interface clock signal and receives the logical clock signal. In one or more examples, the first IC chip is further configured to output the interface clock signal to the second IC chip based on the interface clock signal received from the second IC chip, and the second IC chip uses the interface clock signal to receive a second data signal. In one or more examples, one of the first IC chip and the second IC chip is configured to receive the interface clock signal, and one of the first IC chip and the second IC chip includes: a divider circuit configured to receive the interface clock signal and generate a first clock signal having a frequency less than the frequency of the interface clock signal; and a clock circuit configured to receive the first clock signal and phase-align the first clock signal. In one or more examples, the chip-to-chip interface is further configured to transmit a second data signal between the first IC chip and the second IC chip, and the frequency of the data signal is greater than the frequency of the interface clock signal. In one or more examples, the chip-to-chip interface is further configured to transmit a control signal between the first IC chip and the second IC chip, and the frequency of the control signal is greater than the frequency of the second data signal. In one or more examples, the interface clock signal and the control signal are differential signals. In one or more examples, the interface clock signal and the logical clock signal are transmitted during at least partially overlapping periods.

[0189] In one or more examples, a chip-to-chip interface is configured to transfer an interface clock signal between an IC chip and a second IC chip. The first IC chip and the second IC chip are connected to each other via the chip-to-chip interface. The interface clock signal is synchronized with the data signal. The data signal is received by one of the first IC chip and the second IC chip. The chip-to-chip interface is further configured to transfer a logic clock signal between the first IC chip and the second IC chip. The logic clock signal is asynchronous with the data signal. In one or more examples, the logic clock signal is generated independently of the interface clock signal. In one or more examples, the first IC chip is configured as a receiver and outputs the interface clock signal and the logic clock signal, and the second IC chip is configured as a transmitter and receives the interface clock signal and the logic clock signal from the first IC chip. In one or more examples, the first IC chip is configured as a receiver, and outputs the logic clock signal and receives the interface clock signal, and the second IC chip is configured as a transmitter, and outputs the interface clock signal and receives the logic clock signal. In one or more examples, the first IC chip is further configured to output the interface clock signal to the second IC chip based on the interface clock signal received from the second IC chip, and the second IC chip uses the interface clock signal to receive a second data signal. In one or more examples, the chip-to-chip interface is further configured to transfer a second data signal between the first IC chip and the second IC chip, and the frequency of the data signal is greater than the frequency of the interface clock signal. In one or more examples, the chip-to-chip interface is further configured to transfer a control signal between the first IC chip and the second IC chip, and the frequency of the control signal is greater than the frequency of the second data signal.

[0190] In one or more examples, an IC chip includes a chip-to-chip interface connected to a second IC chip, the chip-to-chip interface being configured to transfer an interface clock signal to the second IC chip, the interface clock signal being synchronized with a data signal received by the IC chip, and to transfer a logic clock signal to the second IC chip, the logic clock signal being asynchronous with the data signal. In one or more examples, the logic clock signal is generated independently of the interface clock signal. In one or more examples, the chip-to-chip interface is further configured to transfer a second data signal to the second IC chip, and the frequency of the data signal is greater than the frequency of the interface clock signal.

[0191] In one or more examples, an IC device includes a first IC chip, a second IC chip, and a chip-to-chip interface connected between the first IC chip and the second IC chip. The chip-to-chip interface is configured to transfer an interface clock signal and a logic clock signal between the first IC chip and the second IC chip. The frequency of the interface clock signal is a multiple of the frequency of the logic clock signal.

[0192] In one or more examples, the frequency of the interface clock signal is at least twice the frequency of the logic clock signal. In one or more examples, the chip-to-chip interface is further configured to transmit a data signal between the first IC chip and the second IC chip, and the data signal is synchronized with the interface clock signal. In one or more examples, the chip-to-chip interface is further configured to transmit a data signal between the first IC chip and the second IC chip, and the chip-to-chip interface is configured to transmit a framing pattern with the data signal. In one or more examples, the chip-to-chip interface is configured to transmit a data signal using a framing signal that defines a valid data region within the data signal. In one or more examples, the interface clock signal is generated by one of the first IC chip and the second IC chip. In one or more examples, the interface clock signal is generated based on the rising edge of the logic clock signal. In one or more examples, the first IC chip includes a first application circuit and a second application circuit, and the second IC chip includes a third application circuit and a fourth application circuit, and the first application circuit, the second application circuit, the third application circuit, and the fourth application circuit are configured to operate based on the logic clock signal. In one or more examples, the first IC chip includes a first interface circuit and a second interface circuit, and the second IC chip includes a third interface circuit and a fourth interface circuit, and the first interface circuit, the second interface circuit, the third interface circuit, and the fourth interface circuit are configured to operate based on the interface clock signal.

[0193] In one or more examples, the chip-to-chip interface is configured to transmit an interface clock signal between the first IC chip and the second IC chip, and to transmit a logic clock signal between the first IC chip and the second IC chip, wherein the frequency of the interface clock signal is a multiple of the frequency of the logic clock signal.

[0194] In one or more examples, the frequency of the interface clock signal is at least twice the frequency of the logic clock signal. In one or more examples, the chip-to-chip interface is further configured to transfer a data signal between a first IC chip and a second IC chip, and the data signal is synchronized with the interface clock signal. In one or more examples, the chip-to-chip interface is further configured to transfer a data signal between a first IC chip and a second IC chip, and transfer a framing pattern with the data signal. In one or more examples, the chip-to-chip interface is further configured to transfer a data signal between a first IC chip and a second IC chip using a framing signal that defines a valid data region within the data signal. In one or more examples, the interface clock signal is generated by one of the first IC chip and the second IC chip. In one or more examples, the interface clock signal is generated based on the rising edge of the logic clock signal. In one or more examples, the first IC chip includes a first application circuit and a second application circuit, and the second IC chip includes a third application circuit and a fourth application circuit, and the first application circuit, the second application circuit, the third application circuit, and the fourth application circuit are configured to operate based on the logic clock signal.

[0195] In one or more examples, an IC chip includes a chip-to-chip interface that is configured to transfer an interface clock signal to a second IC chip and transfer a logic clock signal to the second IC chip. The frequency of the interface clock signal is a multiple of the frequency of the logic clock signal. In one or more examples, the chip-to-chip interface is further configured to transfer a data signal to the second IC chip, and the data signal is synchronized with the interface clock signal. In one or more examples, the chip-to-chip interface is further configured to perform at least one of the following operations: transfer a framing pattern with the data signal and transfer the data signal using a framing signal that defines a valid data region within the data signal.

[0196] While the foregoing is directed to particular examples, other and additional examples can be devised without departing from the basic scope of the invention, and the scope of the invention is determined by the appended claims.

Claims

1. An integrated circuit (IC) device, the integrated circuit (IC) device comprising: A first IC chip; A second IC chip; And A chip-to-chip interface connected between the first IC chip and the second IC chip, the chip-to-chip interface being configured to transmit an interface clock signal and a logic clock signal between the first IC chip and the second IC chip.

2. The IC device according to claim 1, wherein the interface clock signal is synchronized with a data signal received by one of the first IC chip and the second IC chip, and the logic clock signal is asynchronous with the data signal.

3. The IC device according to claim 2, wherein the logic clock signal is generated independently of the interface clock signal.

4. The IC device according to claim 2, wherein: The first IC chip is configured as a receiver and outputs the interface clock signal and the logic clock signal; and The second IC chip is configured as a transmitter and receives the interface clock signal and the logic clock signal from the first IC chip.

5. The IC device according to claim 2, wherein: The first IC chip is configured as a receiver and outputs the logic clock signal and receives the interface clock signal; and The second IC chip is configured as a transmitter and outputs the interface clock signal and receives the logic clock signal, wherein the first IC chip is further configured to output the interface clock signal to the second IC chip based on receiving the interface clock signal from the second IC chip, and wherein the second IC chip uses the interface clock signal to receive a second data signal.

6. The IC device according to claim 2, wherein one of the first IC chip and the second IC chip is configured to receive the interface clock signal, and one of the first IC chip and the second IC chip comprises: A frequency divider circuit configured to receive the interface clock signal and generate a first clock signal having a frequency less than the frequency of the interface clock signal; And A clock circuit configured to receive the first clock signal and phase-align the first clock signal.

7. The IC device according to claim 2, wherein the chip-to-chip interface is further configured to: Transmit a second data signal between the first IC chip and the second IC chip, and wherein the frequency of the data signal is greater than the frequency of the interface clock signal; and Transmit a control signal between the first IC chip and the second IC chip, and wherein the frequency of the control signal is greater than the frequency of the second data signal, and wherein the interface clock signal and the control signal are differential signals.

8. The IC device according to claim 1, wherein the frequency of the interface clock signal is a multiple of the frequency of the logic clock signal.

9. The IC device according to claim 8, wherein the frequency of the interface clock signal is at least twice the frequency of the logic clock signal.

10. The IC device according to claim 8, wherein the chip-to-chip interface is further configured to transfer data signals between the first IC chip and the second IC chip, and wherein the data signals are synchronized with the interface clock signal.

11. The IC device according to claim 8, wherein the chip-to-chip interface is further configured to transfer data signals between the first IC chip and the second IC chip, and the chip-to-chip interface is configured to transfer a framing pattern together with the data signals.

12. The IC device according to claim 8, wherein the chip-to-chip interface is configured to transfer data signals using a framing signal that defines a valid data region within the data signals.

13. The IC device according to claim 8, wherein at least one of the following cases exists: the interface clock signal is generated by one of the first IC chip and the second IC chip; or the interface clock signal is generated based on a rising edge of the logic clock signal.

14. The IC device according to claim 8, wherein the first IC chip includes a first application circuit and a second application circuit, and the second IC chip includes a third application circuit and a fourth application circuit, and wherein the first application circuit, the second application circuit, the third application circuit, and the fourth application circuit are configured to operate based on the logic clock signal.

15. The IC device according to claim 14, wherein the first IC chip includes a first interface circuit and a second interface circuit, and the second IC chip includes a third interface circuit and a fourth interface circuit, and wherein the first interface circuit, the second interface circuit, the third interface circuit, and the fourth interface circuit are configured to operate based on the interface clock signal.

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