Method and apparatus for GIDL erasure in memory system

Abstract

The invention relates to a method and apparatus for memory erase. In one example, a method for operating a memory device includes increasing a voltage of a source line (SL) coupled to a string from an initial voltage at the beginning of a time period, where the voltage of the SL increases to an erase voltage at the end of the time period. The memory device may apply a first voltage to a first word line (WL) before an end of a time period. The memory device may apply a second voltage to a second WL adjacent to the first WL before an end of the time period. The memory device may also apply a third voltage to the second WL no later than the end of the time period, where the third voltage is higher than the second voltage.

Description

Technical Field

[0001] The present disclosure generally relates to memory devices and memory systems, and more particularly, to memory cell erase operations. Background Art

[0002] Semiconductor memory devices can be classified into volatile memory devices and non-volatile memory devices. Volatile memory devices lose data when the power is turned off. Non-volatile memory devices can retain stored data when the power is not connected. Flash memory is a low-cost and high-density non-volatile memory device, which includes NOR flash memory and NAND flash memory. Flash memory can perform various operations, such as reading, programming (writing), and erasing. Summary of the Invention

[0003] The present disclosure relates to methods and apparatuses for memory erasure. In one example, a method of operating a memory device includes: increasing a voltage of a source line (SL) coupled to a memory string from an initial voltage at the start of a time period, wherein the voltage of the SL increases to an erase voltage at the end of the time period. The memory device may apply a first voltage to a first word line (WL) before the end of the time period. The memory device may apply a second voltage to a second WL adjacent to the first WL before the end of the time period. The memory device may further apply a third voltage to the second WL not later than the end of the time period, wherein the third voltage is higher than the second voltage.

[0004] Although generally described as computer-implemented software embodied on a tangible medium that processes and transforms the corresponding data, some or all aspects may be computer-implemented methods, or may be further included in corresponding systems or other apparatuses for performing the described functionality. Details of these and other aspects and embodiments of the present disclosure are set forth in the accompanying drawings and the following description. Other features, objects, and advantages of the present disclosure will become apparent from the specification, drawings, and claims. Brief Description of the Drawings

[0005] Figure 1 An example of a schematic diagram of a memory device including peripheral circuits according to some aspects of the present disclosure is shown.

[0006] Figure 2 An example of a side view of a cross-section of a memory cell array including NAND memory strings according to some aspects of the present disclosure is shown.

[0007] Figure 3 An example of a schematic diagram of some peripheral circuits according to some aspects of the present disclosure is shown.

[0008] Figure 4Shows an example of gate-induced drain leakage (GIDL) current generation in a memory string according to some aspects of the present disclosure.

[0009] Figure 5 Shows an exemplary circuit for performing a GIDL erase operation according to some aspects of the present disclosure.

[0010] Figure 6 Shows an exemplary timing diagram of a GIDL erase operation according to some aspects of the present disclosure.

[0011] Figure 7 Shows an exemplary timing diagram of another GIDL erase operation according to some aspects of the present disclosure.

[0012] Figure 8 Shows an exemplary flowchart of a method for performing a GIDL erase operation according to some aspects of the present disclosure.

[0013] Figure 9 Shows a block diagram of an exemplary system having a memory device according to some aspects of the present disclosure.

[0014] Figure 10A Shows an illustration of a memory card having a memory device according to some aspects of the present disclosure.

[0015] Figure 10B Shows an illustration of a solid-state drive (SSD) having a memory device according to some aspects of the present disclosure.

[0016] Like reference numerals and names in the various figures indicate like elements. Detailed Description

[0017] The gate-induced drain leakage (GIDL) effect can be used for the erase operation of flash memory cells (e.g., NAND memory cells). GIDL occurs when a high voltage is applied to the drain of a metal-oxide-semiconductor field-effect transistor (MOSFET) and a low voltage is applied to the gate of the transistor. In this case, a depletion region is formed in the overlapping region between the drain and the gate. Due to band-to-band tunneling, electron-hole pairs can be generated in the depletion region. As a result, holes can flow from the drain to the substrate of the transistor, which generates a GIDL current. When the voltage difference between the drain and the gate is increased, the GIDL current increases. In the GIDL erase operation of a flash memory device, the transistors of a memory string (e.g., a bottom select gate (BSG)) can act as GIDL generators. Specifically, a low voltage can be applied to the gate of the BSG, and a high voltage can be applied to the source line (SL) coupled to the BSG. Then, a GIDL current can be generated from the BSG, and holes can be injected into the channel of the memory string to raise the voltage of the channel to the erase voltage. Thus, when an appropriate voltage is applied to the gate of the memory cell, the memory cells in the memory string will be erased. When the GIDL current is large, the voltage of the channel will reach the erase voltage more quickly. In other words, the execution of the GIDL erase operation may depend on the efficiency of the GIDL effect. Therefore, techniques for improving the efficiency of the GIDL effect in a memory device are needed.

[0018] Figure 1 An example of a schematic circuit diagram of a memory device 100 including a peripheral circuit according to some aspects of the present disclosure is shown. The memory device 100 may include a memory cell array 101 and a peripheral circuit 102 coupled to the memory cell array 101. The memory cell array 101 may be a NAND flash memory cell array, where the memory cells 106 are provided in the form of an array of memory strings 108 (e.g., NAND memory strings), and each memory string extends vertically above a substrate (not shown). In some embodiments, each NAND memory string 108 includes a plurality of memory cells 106 coupled in series and stacked vertically. Each memory cell 106 may hold a continuous analog value, such as a voltage or a charge, depending on the number of electrons trapped within the region of the memory cell 106. Each memory cell 106 may be a floating-gate type memory cell including a floating-gate transistor or a charge-trapping type memory cell including a charge-trapping transistor.

[0019] In some embodiments, each memory cell 106 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some embodiments, each memory cell 106 is a multi-level cell (MLC) capable of storing more than one bit of data in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also referred to as a triple-level cell (TLC)), or four bits per cell (also referred to as a quad-level cell (QLC)). Each MLC may be programmed to achieve a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC may be programmed to achieve one of three possible programmed levels from an erased state by writing one of three possible nominal storage values into the cell. A fourth nominal storage value may be used for the erased state.

[0020] As Figure 1 shown, each NAND memory string 108 may include a source select gate (SSG) 110 at its source extreme and a drain select gate (DSG) 112 at its drain extreme. The SSG 110 may be referred to as a bottom select gate (BSG), and the DSG 112 may be referred to as a top select gate (TSG). The BSG 110 and the TSG 112 may be configured to activate a selected NAND memory string 108 (a column of the array) during a read operation and a program operation. In some embodiments, the sources of the NAND memory strings 108 located in the same block 104 are coupled by the same source line (SL) 114 (e.g., a common SL). In other words, according to some embodiments, the NAND memory strings 108 located in the same block 104 have an array common source (ACS). According to some embodiments, the TSG 112 of each NAND memory string 108 is coupled to a corresponding bit line 116, and data may be read from or written to the bit line 116 via an output bus (not shown). In some embodiments, each NAND memory string 108 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of the transistor having the TSG 112) or a deselected voltage (e.g., 0V) to the corresponding TSG 112 via one or more TSG lines 113 and / or by applying a select voltage (e.g., higher than the threshold voltage of the transistor having the BSG 110) or a deselected voltage (e.g., 0V) to the corresponding BSG 110 via one or more BSG lines 115. In some embodiments, the NAND memory string 108 includes a bottom memory cell adjacent to the BSG 110 and a top memory cell adjacent to the TSG 112, wherein the bottom memory cell is coupled to a bottom word line, e.g.,Figure 1 WL5 as shown, and the top memory cells are coupled to the top word lines, e.g., Figure 1 WL0 as shown.

[0021] As Figure 1 shown, the NAND memory strings 108 can be organized into multiple blocks 104, and each of the multiple blocks 104 can have a common source line 114 (e.g., coupled to the ACS). In some embodiments, each block 104 is a basic data unit for an erase operation, i.e., all the memory cells 106 located on the same block 104 are erased simultaneously. To erase the memory cells 106 in a selected block 104, the source line 114 coupled to the selected block 104 and the unselected blocks 104 in the same plane as the selected block 104 can be biased with an erase voltage (Verase) (e.g., a high positive voltage (e.g., 20V or higher)). In some examples, the erase operation can be performed at a half-block level, a quarter-block level, or at a level with any appropriate number of blocks or any appropriate fraction of a block. The memory cells 106 of adjacent NAND memory strings 108 can be coupled through word lines 118, and the word lines 118 select which row of the memory cells 106 is affected by a read operation and a program operation. Figure 1 Exemplary word lines as shown include the top word lines WL0, WL1, WL2, WL3, WL4, and the bottom word line WL5 located between one or more TSG lines 113 and one or more BSG lines 115.

[0022] Figure 2 An example of a side view of a cross-section of a memory cell array 101 including NAND memory strings 108 in accordance with some aspects of the present disclosure is shown. As Figure 2 shown, the NAND memory strings 108 can extend vertically above the substrate 202 through the memory stack 204. The substrate 202 can include silicon (e.g., single-crystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0023] The memory stack 204 may include interleaved gate conductive layers 206 and gate-to-gate dielectric layers 208. The number of pairs of gate conductive layers 206 and gate-to-gate dielectric layers 208 in the memory stack 204 may determine the number of memory cells 106 in the memory cell array 101. The gate conductive layer 206 may include a conductive material, including but not limited to: tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 206 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 206 includes a doped polysilicon layer. Each gate conductive layer 206 may include a control gate surrounding the memory cell 106, a TSG 112, or a BSG 110, and may extend laterally at the top of the memory stack 204 as a TSG line 113, extend laterally at the bottom of the memory stack 204 as a BSG line 115, or extend laterally between the TSG line 113 and the BSG line 115 as a word line 118.

[0024] As Figure 2 shown, the NAND memory string 108 includes a channel 210 that extends vertically through the memory stack 204. In some embodiments, the channel 210 includes multiple layers, each layer formed of a different material (e.g., a semiconductor material or a dielectric material).

[0025] Figure 3 Some exemplary peripheral circuits are shown in accordance with some aspects of the present disclosure. The exemplary peripheral circuits include a page buffer / sense amplifier 304, a column decoder / bit line driver 306, a row decoder / word line driver 308, a voltage generator 310, a control logic unit 312, a register 314, an interface 316, and a data bus. In some examples, additional peripheral circuits not shown in Figure 3 may also be included. The peripheral circuit 102 may be coupled to the memory cell array 101 through the Figure 1 bit lines 116, word lines 118, source lines 114, BSG lines 115, and TSG lines 113 therein. The peripheral circuit 102 may include any suitable analog, digital, and mixed-signal circuits for facilitating the operation of the memory cell array 101 by applying voltage signals and / or current signals to each target memory cell 106 and sensing voltage signals and / or current signals from each target memory cell 106 through the bit lines 116, word lines 118, source lines 114, BSG lines 115, and TSG lines 113. The peripheral circuit 102 may include various types of peripheral circuits formed using metal oxide semiconductor (MOS) technology.

[0026] The page buffer / sense amplifier 304 can be configured to read data from the memory cell array 101 and program (write) data to the memory cell array 101 according to control signals from the control logic unit 312. In one example, the page buffer / sense amplifier 304 can store a page of programming data (write data) to be programmed into a page in the memory cell array 101. In another example, the page buffer / sense amplifier 304 can perform a program verification operation to ensure that data has been properly programmed into the memory cells 106 coupled to the selected word line 118. In yet another example, the page buffer / sense amplifier 304 can also sense a low-power signal from the bit line 116 representing the data bits stored in the memory cells 106 and amplify a small voltage swing to an identifiable logic level during a read operation. The column decoder / bit line driver 306 can be configured to be controlled by the control logic unit 312 and select one or more NAND memory strings 108 by applying a bit line voltage generated from the voltage generator 310.

[0027] The row decoder / word line driver 308 can be configured to be controlled by the control logic unit 312 and select / deselect the blocks 104 of the memory cell array 101 and select / deselect the word lines 118 of the blocks 104. The row decoder / word line driver 308 can also be configured to drive the word lines 118 with the word line voltage generated from the voltage generator 310. In some embodiments, the row decoder / word line driver 308 can also select / deselect and drive the BSG line 115 and the TSG line 113. As described in detail below, the row decoder / word line driver 308 is configured to apply a read voltage to the selected word line 118 during a read operation of the memory cells 106 coupled to the selected word line 118.

[0028] The voltage generator 310 can be configured to be controlled by the control logic unit 312 and generate word line voltages (e.g., read voltage, program voltage, pass voltage, local voltage, verify voltage, etc.), bit line voltages, and source line voltages to supply to the memory cell array 101.

[0029] The control logic unit 312 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. The register 314 can be coupled to the control logic unit 312 and includes a status register, a command register, and an address register for storing status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit. As described in detail below, the status register of the register 314 can include one or more registers configured to store open block information indicating the (multiple) open blocks in all the blocks 104 in the memory cell array 101. In some embodiments, the open block information also indicates the last programmed page of each open block.

[0030] The interface 316 can be coupled to the control logic unit 312 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic unit 312, and buffer status information received from the control logic unit 312 and relay it to the host. The interface 316 can also be coupled to the column decoder / bit line driver 306 via a data bus and act as a data input / output (I / O) interface and data buffer to buffer and relay data to and from the memory cell array 101.

[0031] Figure 4 An example of GIDL current generation in a memory string 400 according to some aspects of the present disclosure is shown. The memory string 400 can be Figure 1 an example of the NAND memory string 108 in Figure 4 A cross-section of the memory string 400 is shown. As Figure 4 shown, the memory string 400 includes a channel 402, a storage film 404, and word lines 406. The channel 402 has two ends 408 and 410. The end 408 is connected to a bit line ( Figure 4 not shown in Figure 1 ), and the end 410 is connected to a source 412. The source 412 is connected to a source line (e.g., Figure 1 the source line 114 in Figure 1 ). The memory string 400 includes transistors and memory cells 414 - 428 formed by the channel 402, the storage film 404, and the word lines 406. The transistors and memory cells 414 - 428 are coupled in series and stacked vertically. The transistor 414 is a TSG (e.g.,

[0032] The GIDL erase operation may require at least one transistor from the memory string 400 to generate a GIDL current. This transistor may be referred to as a GIDL generator or a GIDL transistor. In one embodiment, the TSG 414 or the BSG 428 may be the GIDL transistor. For example, a low voltage may be applied to the gate of the BSG 428, and a high voltage may be applied to the source 412. A GIDL current may be generated from the BSG 428, and holes may be injected into the channel 402. The voltage of the channel 402 will be raised to the erase voltage. Thus, when an appropriate voltage (e.g., 0V) is applied to the gates of the memory cells 418 - 424, the memory cells 418 - 424 will be erased. Similarly, when a high voltage is applied to the bit line coupled to the end 408 and a low voltage is applied to the gate of the TSG 414, the TSG 414 may act as a GIDL transistor to generate a GIDL current flowing into the channel 402 from the top side. In another embodiment, both the TSG 414 and the BSG 428 may be GIDL transistors, which is referred to as bilateral GIDL injection. In some other embodiments, the dummy cells (e.g., dummy cells 416 or 426) of the memory string 400 may also be GIDL transistors during the GIDL erase operation.

[0033] Figure 5 An exemplary circuit 500 for performing a GIDL erase operation in accordance with some aspects of the present disclosure is shown. Figure 5 The circuit 500 in Figure 1 may be part of the memory device 100 in Figure 1 . The circuit 500 includes a row decoder / word line driver 308 and is coupled to at least one memory string 108 (e.g., a NAND memory string). The circuit 500 may be part of the peripheral circuit of the memory device (e.g., Figure 3 the peripheral circuit 102 in Figure 3 or the peripheral circuit shown in Figure 5 ). In some embodiments, the circuit 500 further includes a voltage generator (e.g., Figure 3The voltage generator 310). The driver 505 can be referred to as a TSG driver, and the TSG driver is configured to provide a control voltage to the TSG 112. The driver 515 can be referred to as a BSG driver, and the BSG driver is configured to provide a control voltage to the BSG 110. The drivers 507-513 are word line drivers, and the word line drivers are configured to provide a control voltage to WL1-WL30. In some embodiments, the word line drivers 507-513 are coupled between a voltage generator (e.g., Figure 3 the voltage generator 310) in and WL1-WL30, and are configured to provide the voltage from the voltage generator to WL1-WL30. The string driver 502 includes driving transistors 504-514, and the driving transistors 504-514 are coupled in parallel through their gates. Controlled by the voltage from the decoder 503, each of the driving transistors 504-514 is configured to transfer the voltage from one of the drivers 505-515 to the corresponding transistor in the memory string 108.

[0034] The circuit 500 can be configured to perform a GIDL erase operation by using the TSG 112 (applying a high voltage to the bit line 116) or the BSG 110 (applying a high voltage to the source line 114) as a GIDL transistor. Optionally, as Figure 5 shown, the bit line 116 and the source line 114 can be connected through a switch 540. When the switch 540 is closed (turned on), a high voltage can be applied to both the bit line 116 and the source line 114. In this case, the memory string 108 can have two GIDL transistors (TSG 414 and BSG 428), and GIDL current can be injected into the channel of the memory string 108 from both ends simultaneously. This is Figure 4 the bilateral GIDL injection discussed in.

[0035] Figure 6 FIG. 600 shows a timing diagram of an exemplary GIDL erase operation according to some aspects of the present disclosure. Figure 6 The GIDL erase operation shown can be performed by the one disclosed herein including Figure 5Any suitable device of the circuit 500 in. In this example, the BSG 110 can act as a GIDL transistor. To generate a GIDL current, the voltage difference (which can be referred to as the incremental voltage) between the gate of the BSG 110 (i.e., WL0) and the source line 114 must be high enough (e.g., greater than 6V). Thus, the operation of erasing the memory cell 516 can start at time 601 by increasing the voltage at the source line 114. It should be understood that this exemplary erase operation is not intended to be construed in a limiting sense. In some embodiments, the erase operation can be performed at the block level, half-block level, quarter-block level, or any suitable fractional level of the memory block by applying a voltage to a selected set of word lines. When the voltage at the source line 114 starts to increase, the voltage at the gate of the BSG 110 is maintained at a lower level, e.g., at the source supply voltage (Vss). In some embodiments, Vss can be 0V. The voltage at the gate of the BSG 110 is provided by the BSG driver 515 through the drive transistor 514 of the string driver 502. At time 601, a low voltage (e.g., Vss) provided by the word line driver 507 through the drive transistor 506 of the string driver 502 can be applied to WL30 (i.e., the gate of the memory cell 516). Thus, the voltage at WL30 (the first word line) can change from the common collector voltage Vcc to Vss. In some embodiments, Vss can also be applied to WL30 before time 601. At time 601, the string driver gate voltage applied to the gate of the drive transistor changes from an initial value (e.g., Vss) to the pass voltage Vpass. The pass voltage Vpass turns on the drive transistor of the string driver 502, allowing the voltages from the word line driver 507 and the BSG driver 515 to be transferred to WL30 and WL0. The string driver gate voltage can be provided by the decoder 503. In some embodiments, Vpass can be around 10V.

[0036] Since the voltage at the gate of BSG 110 is held at Vss, the incremental voltage increases as the voltage at the source line 114 increases. A greater incremental voltage can improve GIDL efficiency. However, over time, continuously holding the voltage at the source of BSG 110 higher than the voltage at the gate of BSG 110 may cause weak erasure (i.e., threshold voltage shift) of BSG 110. To prevent the erasure operation of the memory cell from affecting the functionality of BSG 110, once the incremental voltage is high enough to trigger the GIDL effect, the voltage at the gate of BSG 110 can be increased to a higher level. In this example, when the voltage at the source line 114 reaches the release voltage (Vrls) at time 602, the voltage from the BSG driver 515 can be increased from Vss to the pass voltage Vpass. As a result, the voltages at both the drain and the gate of the drive transistor 514 are at the same level (Vpass), which causes the drive transistor 514 to become a diode, thus preventing current from flowing from the BSG driver 515 to BSG 110. This change will increase the voltage at the gate of BSG 110 from Vss to the offset voltage Voffset (e.g., 3V - 5V) at time 603 and float BSG 110. Voffset is determined by Vpass and the threshold voltage of the drive transistor 514. For example, Voffset can be equal to Vpass minus the threshold voltage of the drive transistor 514. In some embodiments, the difference between Vrls and Voffset (Vrls - Voffset) is between 6V and 8V. When the voltage at the source line 114 reaches Vrls at time 602, due to the GIDL effect, the voltage at the channel of the memory string 108 begins to increase. After BSG 110 is floated at 603, since BSG 110 is now coupled to the channel, the voltage at the gate of BSG 110 increases as the voltage at the channel increases.

[0037] At time 604, the voltage at the source line 114 reaches the high erase voltage Verase (e.g., 20V), and the voltage at the channel is determined by the erase voltage Verase and a smaller bias voltage caused by the coupling capacitor between the channel and the source line 114. By maintaining the voltage difference between the channel and WL30 for a period of time (e.g., between 604 and 605), the memory cell 516 will be erased.

[0038] The source line 114 can be coupled to the sources of other memory strings in the same memory block, and WL1 - WL30 can be coupled to the corresponding memory cells of other memory strings. In the block erase mode, the word line drivers 509 - 513 also supply Vss to WL1 - WL29, such that the memory cells in the entire memory block (including the memory cells 518 - 522) are erased during this erase operation. In this case, the incremental voltage of the GIDL effect is determined by the voltage at the source line 114 at time 603 (when the BSG 110 is floating) minus the voltage (Voffset) at the gate of the BSG 110 at time 603. Voffset can be reduced by reducing the pass voltage Vpass. In the block erase mode, the GIDL erase operation can use a lower Vpass, which can increase the incremental voltage and thus improve the efficiency of the erase operation.

[0039] In the partial erase mode, there can be more restrictions on the lower limit of the pass voltage Vpass. The erase operation can be performed at the half - block level, quarter - block level, or any appropriate fraction level of the memory block by applying Vss only to a subset of the word lines selected from WL1 - WL30 of the memory string 108. For example, in the odd / even erase mode, the memory cells coupled to the word lines with even indices (e.g., Figure 5 the memory cells 516 and 520 in Figure 5The memory cells 518 and 524) are not erased in the same erase operation. In this case, when Vss is applied to WL30 to erase the memory cell 516, a higher voltage can be applied to WL29 to prevent the memory cell 518 from being erased. WL30 and WL29 can be associated with two consecutive index numbers (e.g., consecutive natural numbers). Thus, one of WL30 and WL29 has an even index number and the other of them has an odd index number. The floating memory cell 518 can raise the voltage at WL29 to a high level. However, if the floating voltage at WL29 is too high, since WL29 can be coupled to WL30, it may reduce the erase efficiency of the memory cell 516. Therefore, a better way to prevent the memory cell 518 from being erased is to suppress the voltage at WL29 at a controllable level (e.g., Vrestrain), and the controllable level can be provided by the word line driver 509. For example, Vrestrain can be 7V - 8V. To provide the suppression voltage Vrestrain from the word line driver 509 to WL29, the pass voltage Vpass needs to be high enough to turn on the drive transistor 508. Specifically, Vpass is higher than the sum of the suppression voltage Vrestrain and the threshold voltage of the drive transistor 508. In other words, in the partial erase mode, the lower limit of the pass voltage Vpass is limited by the suppression voltage Vrestrain. Therefore, a higher suppression voltage may reduce the incremental voltage and thus may reduce the efficiency of the GIDL erase operation.

[0040] The present disclosure provides techniques for a memory device that boosts the string driver gate voltage and the suppression voltage in two steps during a GIDL erase operation, which can improve the efficiency of the GIDL erase operation in the partial erase mode. The above and some other aspects of the present disclosure will be discussed in more detail below.

[0041] Figure 7 A timing diagram 700 of another GIDL erase operation according to some aspects of the present disclosure is shown. Figure 7 The illustrated GIDL erase operation can be performed by the one disclosed herein including Figure 5Any suitable device of the circuit 500 in [the context] to perform. In this example, the BSG 110 acts as a GIDL transistor, and the GIDL erase operation is in a partial erase mode, where the memory cell 516 will be erased and the memory cell 518 will not be erased. The GIDL erase operation starts at time 701 by increasing the voltage at the source line 114. When the voltage at the source line 114 starts to increase, the voltage at the gate of the BSG 110 is maintained at a lower level (e.g., Vss). The BSG driver 515 can be configured to supply a voltage to the gate of the BSG 110 through the drive transistor 514 of the string driver 502. At time 701, the word line driver 507 can be configured to supply a low voltage (e.g., Vss) to WL30 (i.e., the gate of the memory cell 516) through the drive transistor 506 of the string driver 502. At time 701, the word line driver 509 can be configured to supply a first restraining voltage Vrestrain1 (e.g., 3V) to WL29 (i.e., the gate of the memory cell 518) through the drive transistor 508 of the string driver 502. In some embodiments, the voltage Vss (the first voltage) and Vrestrain1 (the second voltage) can be applied to WL30 (the first word line) and WL29 (the second word line) respectively before time 701.

[0042] At time 701, the string driver gate voltage applied to the gate of the drive transistor of the string driver 502 can increase from an initial value (e.g., Vss) to a first pass voltage Vpass1 (e.g., 5.6V) to turn on the drive transistor. As a result, the voltages from the BSG driver 515, the word line driver 507, and the word line driver 509 are transferred to the corresponding word lines.

[0043] At time 702, the voltage at the source line 114 reaches a first release voltage Vrls1 (e.g., 4V - 10V). In response to detecting that the voltage at the source line 114 reaches Vrls, the voltage from the BSG driver 515 can increase from Vss to the first pass voltage Vpass1. This change will cause the voltage at the gate of the BSG 110 to increase from Vss to a first offset voltage Voffset1 at time 703 and float the BSG 110. Voffset1 is determined by Vpass1 and the threshold voltage of the drive transistor 514. For example, Voffset1 can be equal to Vpass1 minus the threshold voltage of the drive transistor 514. When the voltage at the source line 114 reaches Vrls at time 702, due to the GIDL effect, the voltage at the channel of the storage string 108 starts to increase. Starting from time 703, the BSG 110 is floated and coupled to the channel, and thus the voltage at the gate of the BSG 110 increases as the voltage at the channel increases.

[0044] At time 704, the voltage at the source line 114 reaches the high erase voltage Verase (e.g., 20V), and the voltage at the channel is determined by this erase voltage Verase and a smaller bias voltage generated by a coupling capacitor located between the channel and the source line 114. In response to detecting that the voltage at the source line 114 reaches Verase, the string driver gate voltage can increase from the first pass voltage Vpass1 to the pass voltage Vpass, and the voltage applied to WL29 can increase from the first restrain voltage Vrestrain1 to the restrain voltage Vrestrain (the third voltage). By maintaining the voltage difference between the channel and WL30 for a period of time (e.g., between 704 and 705), the memory cell 516 will be erased. On the other hand, since the voltage at WL29 remains at a higher level (i.e., Vrestrain) during this period, the memory cell 518 will not be erased.

[0045] In some embodiments, the string driver gate voltage can increase from the first pass voltage Vpass1 to the pass voltage Vpass before time 704. As long as Vpass is equal to or less than the sum of the floating voltage of the BSG 110 and the threshold voltage of the driving transistor 514, the BSG 110 will remain in the floating state between time 703 and time 704. In this way, the increase in the voltage at the source line 114 between time 703 and time 704 will not be interrupted by the change in the string driver gate voltage.

[0046] As Figure 7 shown, during the voltage boost of the source line 114, a two-step increase is applied to the string driver gate voltage and the voltage at WL29, rather than directly increasing them to the target voltage (as Figure 6 shown). Therefore, when the BSG 110 is floating at time 703, the first offset voltage at the gate of the BSG 110 can be lower (since Vpass1 < Vpass, so Voffset1 < Voffset). Therefore, Figure 7 the incremental voltage for the GIDL erase operation shown is higher, which improves the efficiency of the erase operation.

[0047] In some embodiments, only the string driver gate voltage increases in two steps, while the voltage at WL29 can be directly increased to the restrain voltage. For example, at time 701, the string driver gate voltage increases from Vss to Vpass1. At 704, the string driver gate voltage increases from Vpass1 to Vpass. On the other hand, the voltage at WL29 can directly increase from Vcc to Vrestrain at time 701 and be maintained at this level during the erase operation ( Figure 7 not shown in).

[0048] Although in some examples provided in the present disclosure, the BSG of a storage string is used as a GIDL transistor, these examples are not intended to be construed in a limiting sense. Any suitable GIDL transistor known in the art (e.g., BSG, TSG, dummy memory cell, or any combination of the foregoing) can act as one or more GIDL transistors in the GIDL erase operation described in the present disclosure.

[0049] Figure 8 A flowchart of an exemplary method 800 for performing a GIDL erase operation in accordance with some aspects of the present disclosure is shown. Method 800 may be performed by any suitable apparatus including the Figure 5 circuit 500 disclosed herein. As Figure 8 shown, operation 802 includes: increasing the voltage of a source line coupled to a storage string from an initial voltage at the start of a time period. The voltage of the SL may be increased to an erase voltage at the end of the time period.

[0050] Operation 804 includes: applying a first voltage to a first word line before the end of the time period.

[0051] Operation 806 includes: applying a second voltage to a second WL adjacent to the first WL before the end of the time period.

[0052] Operation 808 includes: applying a third voltage to the second WL no later than the end of the time period, where the third voltage is higher than the second voltage.

[0053] In some embodiments, method 800 further includes: in response to detecting that the voltage of the SL increases to a release voltage during the time period, increasing the voltage of the gate of a first transistor included in the storage string to an offset voltage.

[0054] In some embodiments, the first transistor may be the BSG of the storage string. The BSG is coupled to a first terminal of a first drive transistor of a string driver. The first WL is coupled to a first terminal of a second drive transistor of the string driver. The second WL is coupled to a first terminal of a third drive transistor of the string driver.

[0055] In some embodiments, method 800 further includes: applying a string driver gate voltage to the gates of the first drive transistor, the second drive transistor, and the third drive transistor. The string driver gate voltage may be increased from a supply voltage to a first string driver voltage before the end of the time period. The string driver gate voltage may also be increased from the first string driver voltage to a second string driver voltage no later than the end of the time period.

[0056] In some embodiments, the storage string further includes a TSG coupled to the bit line. The BL can be coupled to the SL through a switch, and the TSG can be coupled to the first terminal of the fourth driving transistor of the string driver. In these embodiments, method 800 can further include: providing a voltage to the second terminal of the fourth driving transistor; and increasing the voltage of the second terminal of the fourth driving transistor in response to detecting that the voltage of the BL increases to a second release voltage.

[0057] Figure 9 An example of a block diagram of a system 900 having a memory device in accordance with some aspects of the present disclosure is shown. System 900 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, an in-vehicle computer, a game controller, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. As Figure 9 shown, system 900 can include a host 908 and a memory system 902 having one or more memory devices 904 and a memory controller 906. The host 908 can be a processor (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 908 can be configured to send data to or receive data from the memory device 904. In some embodiments, the memory device in one or more memory devices 904 can include Figure 5 circuit 500 for performing a memory erase operation therein.

[0058] Memory device 904 can be any memory device disclosed in this disclosure. According to some embodiments, memory controller 906 is coupled to memory device 904 and host 908, and is configured to control memory device 904. Memory controller 906 can manage data stored in memory device 904 and communicate with host 908. In some embodiments, memory controller 906 is designed to operate in a low-duty-cycle environment, such as a Secure Digital (SD) card, Compact Flash (CF) card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, memory controller 906 is designed to operate in a high-duty-cycle environment, such as a Solid State Drive (SSD) or Embedded Multimedia Card (eMMC), which is used as a data storage device for mobile devices such as smart phones, tablets, laptop computers, etc. and enterprise storage arrays. Memory controller 906 can be configured to control the operations of memory device 904 (e.g., read operations, erase operations, and program operations). Memory controller 906 can also be configured to manage various functions regarding data stored in or to be stored in memory device 904, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, memory controller 906 is also configured to process error correction codes (ECCs) regarding data read from or written to memory device 904. Memory controller 906 can also perform any other appropriate functions, such as formatting memory device 904.

[0059] Memory controller 906 can communicate with an external device (e.g., host 908) according to a specific communication protocol. For example, memory controller 906 can communicate with an external device through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, High-Speed PCI (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, FireWire protocol, etc.

[0060] Memory controller 906 and one or more memory devices 904 can be integrated into various types of storage devices, such as being included in the same package (e.g., Universal Flash Storage device (UFS) package or eMMC package). That is to say, memory system 902 can be implemented and packaged into different types of terminal electronic products. In Figure 10AIn one example shown, the memory controller 906 and a single memory device 904 may be integrated into a memory card 1002. The memory card 1002 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 1002 may also include a memory card connector 1004 that couples the memory card 1002 to a host (e.g., Figure 9 the host 908 in Figure 10B ). In another example shown, the memory controller 906 and multiple memory devices 904 may be integrated into an SSD 1006. The SSD 1006 may also include an SSD connector 1008 that couples the SSD 1006 to a host (e.g., Figure 9 the host 908 in

[0061] ). In some embodiments, the storage capacity and / or operating speed of the SSD 1006 is greater than that of the memory card 1002.

[0061] Although this specification contains many specific implementation details, these should not be construed as limitations on the scope of what is claimed, but rather as descriptions of features that may be specific to particular embodiments. In the context of separate embodiments, certain features described in this specification may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented separately or in any sub-combination in multiple embodiments. Additionally, although the foregoing features may be described as acting in certain combinations and even initially claimed as such, one or more features from the claimed combination may in some cases be deleted from the combination, and the claimed combination may be directed to a sub-combination or a variant of a sub-combination.

[0062] As used in this disclosure, unless the context clearly indicates otherwise, the terms "a" or "the" are used to include one or more than one. Unless otherwise indicated, the term "or" is used to mean a non-exclusive "or". The statement "at least one of A and B" has the same meaning as "A, B, or A and B". Additionally, the wording or terms employed in this disclosure that are not otherwise defined are for descriptive purposes only and not for purposes of limitation. Any use of section headings is intended to aid in reading the document and should not be construed as limiting; information related to a section heading may appear within or outside of that particular section.

[0063] As used in this disclosure, the terms "about" or "approximately" may allow for a certain degree of variability in a value or range, e.g., within 10%, within 5%, or within 1% of the stated value or the stated range limits.

[0064] As used in this disclosure, the term "substantially" means majority or most, such as at least about 50%, 60%, 70%, 80%, 90%, 95%, 96%, 97%, 98%, 99%, 99.5%, 99.9%, 99.99% or at least about 99.999% or more.

[0065] Values expressed in a range format should be interpreted in a flexible manner to include not only the values explicitly recited as the limits of the range, but also the individual values or sub-ranges subsumed within that range, as if each value and sub-range were explicitly recited. For example, a range of "0.1% to about 5%" or "0.1% to 5%" should be interpreted to include from about 0.1% to about 5%, as well as the individual values (e.g., 1%, 2%, 3% and 4%) and sub-ranges (e.g., 0.1% to 0.5%, 1.1% to 2.2%, 3.3% to 4.4%) within the indicated range. Unless otherwise specified, the statement "X to Y" has the same meaning as "about X to about Y". Similarly, unless otherwise specified, the statement "X, Y or Z" has the same meaning as "about X, about Y or about Z".

[0066] Specific embodiments of the subject matter have been described. As will be apparent to those skilled in the art, other embodiments, alternatives and permutations of the described embodiments are within the scope of the following claims. Although the operations are described in a particular order in the figures and claims, to achieve the desired results, it is not required to perform the operations in the specific order shown or in a sequential order, or to perform all the operations shown (some operations may be considered optional). In certain cases, multitasking or parallel processing (or a combination of multitasking and parallel processing) may be advantageous and is performed when considered appropriate.

[0067] Furthermore, the separation or integration of the various system modules and components in the previously described embodiments is not required in all embodiments, and the described components and systems can generally be integrated together or packaged into multiple products.

[0068] Accordingly, the previously described exemplary embodiments do not define or constrain this disclosure. Other changes, substitutions and alterations are possible without departing from the spirit and scope of this disclosure.

[0069] According to one aspect of the present disclosure, a method for operating a memory device is provided. The method includes: increasing the voltage of the SL coupled to the memory string from an initial voltage at the start of a time period. The voltage of the SL is increased to an erase voltage at the end of the time period. The method further includes: applying a first voltage to a first WL before the end of the time period. The method further includes: applying a second voltage to a second WL adjacent to the first WL before the end of the time period. The method further includes: applying a third voltage to the second WL no later than the end of the time period. The third voltage is higher than the second voltage.

[0070] In some embodiments, the method further includes: in response to detecting that the voltage of the SL increases to a release voltage during the time period, increasing the voltage of the gate of the first transistor included in the memory string to an offset voltage.

[0071] In some embodiments, the first transistor is the BSG of the memory string, the BSG is coupled to the first terminal of the first driving transistor of the string driver, the first WL is coupled to the first terminal of the second driving transistor of the string driver, and the second WL is coupled to the first terminal of the third driving transistor of the string driver. The method further includes: applying a string driver gate voltage to the gates of the first driving transistor, the second driving transistor, and the third driving transistor. The method further includes: increasing the string driver gate voltage from a supply voltage to a first string driver voltage before the end of the time period. The method further includes: increasing the string driver gate voltage from the first string driver voltage to a second string driver voltage no later than the end of the time period.

[0072] In some embodiments, the offset voltage is determined based on subtracting the threshold voltage of the first transistor from the first string driver voltage.

[0073] In some embodiments, providing the first voltage to the first WL includes: providing the first voltage to the second terminal of the second driving transistor, and providing the second voltage to the second WL includes: providing the second voltage to the second terminal of the third driving transistor.

[0074] In some embodiments, the second string driver voltage is less than the sum of the threshold voltage of the BSG driver and the floating voltage of the BSG.

[0075] In some embodiments, after floating the first transistor, the floating voltage of the BSG increases as the voltage of the SL increases.

[0076] In some embodiments, the storage string further includes a TSG coupled to the BL, the BL is coupled to the SL through a switch, and the TSG is coupled to the first terminal of the fourth driving transistor of the string driver. The method further includes: providing a voltage to the second terminal of the fourth driving transistor; and increasing the voltage of the second terminal of the fourth driving transistor in response to detecting that the voltage of the BL increases to a second release voltage.

[0077] In some embodiments, the memory cell coupled to the first WL will be erased during a selective erase operation after a time period, and the first WL and the second WL are associated with two consecutive index numbers. The two consecutive index numbers are natural numbers.

[0078] In some embodiments, the memory cell driven by the first WL will be erased during an erase operation, and the second WL is a dummy WL adjacent to the first WL.

[0079] According to another aspect provided herein, a memory device is provided. The memory device includes: a storage block including a BSG, an SL, a first WL, a second WL, and a storage string including a channel coupled to the SL. The memory device further includes: a peripheral circuit including a voltage generator, a string driver coupled to the BSG, the first WL, and the second WL. The peripheral circuit is configured to: increase the voltage of the SL from an initial voltage at the start of a time period, wherein the voltage of the SL increases to an erase voltage at the end of the time period; apply a first voltage to the first WL through the string driver before the end of the time period; apply a second voltage to the second WL through the string driver before the end of the time period; and apply a third voltage to the second WL through the string driver not later than the end of the time period, wherein the third voltage is higher than the second voltage.

[0080] In some embodiments, the peripheral circuit is further configured to: increase the voltage of the gate of the BSG to an offset voltage in response to detecting that the voltage of the SL increases to a release voltage during the time period to float the BSG.

[0081] In some embodiments, the first driving transistor of the string driver is coupled to the BSG, the second driving transistor of the string driver is coupled to the first WL, the third driving transistor of the string driver is coupled to the second WL, and the gates of the first driving transistor, the second driving transistor, and the third driving transistor are coupled together. The voltage generator is further configured to: apply a string driver gate voltage to the gate of the first driving transistor; increase the string driver gate voltage from a supply voltage to a first string driver voltage after the start of the time period; and increase the string driver gate voltage from the first string driver voltage to a second string driver voltage not later than the end of the time period.

[0082] In some embodiments, a first voltage is provided to a second terminal of a second driving transistor, and a second voltage is provided to a second terminal of a third driving transistor.

[0083] In some embodiments, the second string driver voltage is less than the sum of the threshold voltage of the first driving transistor and the floating voltage of the BSG.

[0084] In some embodiments, after floating the first transistor, the floating voltage of the BSG increases as the voltage of the SL increases.

[0085] In some embodiments, the memory block further includes a BL and a TSG. The BL is coupled to the SL through a switch, and the TSG is coupled to a first terminal of a fourth driving transistor of the string driver. The voltage generator is further configured to: provide a voltage to a second terminal of the fourth driving transistor; and increase the voltage of the second terminal of the fourth driving transistor in response to detecting that the voltage of the BL increases to a second release voltage.

[0086] In some embodiments, a first WL and a second WL are associated with two consecutive index numbers, the two consecutive index numbers being natural numbers, and the memory cells driven by the first WL will be erased during a selective erase operation after a time period.

[0087] In some embodiments, the memory cells driven by the first WL will be erased during an erase operation, and the second WL is a dummy WL adjacent to the first WL.

[0088] According to another aspect of the present disclosure, a memory system is provided. The memory system includes a memory device and a memory controller. The memory controller is configured to control the memory device. The memory device includes: a memory block including a BSG, an SL, a first WL and a second WL, and a memory string including a channel coupled to the SL. The memory device further includes: a peripheral circuit including a voltage generator, a string driver coupled to the BSG, the first WL, and the second WL. The peripheral circuit is configured to: increase the voltage of the SL from an initial voltage at the start of a time period, wherein the voltage of the SL increases to an erase voltage at the end of the time period; apply a first voltage to the first WL through the string driver before the end of the time period; apply a second voltage to the second WL through the string driver before the end of the time period; and apply a third voltage to the second WL through the string driver no later than the end of the time period, wherein the third voltage is higher than the second voltage.

[0089] The foregoing description of specific embodiments can be readily modified and / or adapted for various applications. Accordingly, such adaptations and modifications are intended to be within the meaning and scope of the equivalent embodiments disclosed herein, based on the teachings and guidance provided herein.

[0090] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents. Accordingly, other embodiments are also within the scope of the claims.

Claims

1. A method for operating a memory device, the method comprising: increasing a voltage of a source line (SL) coupled to a memory string from an initial voltage at the start of a time period, wherein the voltage of the SL is increased to an erase voltage at the end of the time period; applying a first voltage to a first word line (WL) before the end of the time period; applying a second voltage to a second WL adjacent to the first WL before the end of the time period; and applying a third voltage to the second WL no later than the end of the time period, wherein the third voltage is higher than the second voltage.

2. The method according to claim 1, further comprising: increasing a voltage of a gate of a first transistor included in the memory string to an offset voltage in response to detecting that the voltage of the SL increases to a release voltage during the time period.

3. The method according to claim 2, wherein, The first transistor is a bottom select gate (BSG) of the memory string, the BSG is coupled to a first terminal of a first drive transistor of a string driver, the first WL is coupled to a first terminal of a second drive transistor of the string driver, and the second WL is coupled to a first terminal of a third drive transistor of the string driver, and wherein the method further comprises: applying a string driver gate voltage to the gate of the first drive transistor, the gate of the second drive transistor, and the gate of the third drive transistor; increasing the string driver gate voltage from a supply voltage to a first string driver voltage before the end of the time period; and increasing the string driver gate voltage from the first string driver voltage to a second string driver voltage no later than the end of the time period.

4. The method according to claim 2, wherein The offset voltage is determined based on subtracting a threshold voltage of the first transistor from the first string driver voltage.

5. The method according to claim 3, wherein: providing the first voltage to the first WL includes: providing the first voltage to a second terminal of the second drive transistor, and providing the second voltage to the second WL includes: providing the second voltage to a second terminal of the third drive transistor.

6. The method according to claim 3, wherein The second string driver voltage is less than a sum of a threshold voltage of the BSG driver and a floating voltage of the BSG.

7. The method according to claim 6, wherein After floating the first transistor, the floating voltage of the BSG increases as the voltage of the SL increases.

8. The method according to claim 7, wherein, The memory string further includes a top select gate (TSG) coupled to a bit line (BL), the BL is coupled to the SL through a switch, and the TSG is coupled to a first terminal of a fourth drive transistor of the string driver, and wherein the method further comprises: providing a voltage to a second terminal of the fourth drive transistor; and increasing the voltage of the second terminal of the fourth drive transistor in response to detecting that the voltage of the BL increases to a second release voltage.

9. The method according to any one of claims 1 - 8, wherein Memory cells coupled to the first WL will be erased during a selective erase operation after the time period, and the first WL and the second WL are associated with two consecutive index numbers, wherein the two consecutive index numbers are natural numbers.

10. The method according to any one of claims 1-9, wherein, The first WL drives the memory cell to be erased during an erase operation, and the second WL is a dummy WL adjacent to the first WL.

11. A memory device, comprising: A memory block, the memory block includes a bottom select gate (BSG), a source line (SL), a first word line (WL), a second WL, and a memory string including a channel coupled to the SL; and A peripheral circuit, the peripheral circuit includes a voltage generator, a string driver coupled to the BSG, the first WL, and the second WL, wherein the peripheral circuit is configured to: Increase the voltage of the SL from an initial voltage at the start of a time period, wherein the voltage of the SL increases to an erase voltage at the end of the time period; Apply a first voltage to the first WL through the string driver before the end of the time period; Apply a second voltage to the second WL through the string driver before the end of the time period; and Apply a third voltage to the second WL through the string driver no later than the end of the time period, wherein the third voltage is higher than the second voltage.

12. The memory device according to claim 11, wherein, The peripheral circuit is further configured to: In response to detecting that the voltage of the SL increases to a release voltage during the time period, increase the voltage of the gate of the BSG to an offset voltage to float the BSG.

13. The memory device according to claim 12, wherein, A first driving transistor of the string driver is coupled to the BSG, a second driving transistor of the string driver is coupled to the first WL, a third driving transistor of the string driver is coupled to the second WL, the gates of the first driving transistor, the second driving transistor, and the third driving transistor are coupled together, and wherein the voltage generator is further configured to: Apply a string driver gate voltage to the gate of the first driving transistor; Increase the string driver gate voltage from a supply voltage to a first string driver voltage after the start of the time period; and Increase the string driver gate voltage from the first string driver voltage to a second string driver voltage no later than the end of the time period.

14. The memory device according to claim 13, wherein, The first voltage is provided to a second terminal of the second driving transistor, and the second voltage is provided to a second terminal of the third driving transistor.

15. The memory device according to claim 14, wherein, The second string driver voltage is less than the sum of the threshold voltage of the first driving transistor and the floating voltage of the BSG.

16. The memory device according to claim 13, wherein, After floating the first transistor, the floating voltage of the BSG increases as the voltage of the SL increases.

17. The memory device according to claim 16, wherein, The memory block further includes a bit line (BL) and a top select gate (TSG), the BL is coupled to the SL through a switch, and the TSG is coupled to a first terminal of a fourth driving transistor of the string driver, and wherein the voltage generator is further configured to: Provide a voltage to a second terminal of the fourth driving transistor; and In response to detecting that the voltage of the BL increases to a second release voltage, increase the voltage of the second terminal of the fourth driving transistor.

18. The memory device according to any one of claims 11-17, wherein, The first WL and the second WL are associated with two consecutive index numbers, where the two consecutive index numbers are natural numbers, and the memory cells driven by the first WL will be erased during a selective erase operation after the time period.

19. The memory device according to any one of claims 11-18, wherein, The memory cells driven by the first WL will be erased during the erase operation, and the second WL is a dummy WL adjacent to the first WL.

20. A memory system, comprising: A memory device and a memory controller, wherein: The memory controller is configured to control the memory device; and The memory device includes: A memory block including a bottom select gate (BSG), a source line (SL), a first word line (WL), a second WL, and a memory string including a channel coupled to the SL; and A peripheral circuit including a voltage generator, a string driver coupled to the BSG, the first WL, and the second WL, wherein the peripheral circuit is configured to: Increase the voltage of the SL from an initial voltage at the start of the time period, where the voltage of the SL increases to an erase voltage at the end of the time period; Apply a first voltage to the first WL through the string driver before the end of the time period; Apply a second voltage to the second WL through the string driver before the end of the time period; and Apply a third voltage to the second WL through the string driver no later than the end of the time period, where The third voltage is higher than the second voltage.

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