Power conversion device

Abstract

This power conversion device is provided with: a semiconductor element (1); a voltage detector (13) that detects a voltage between the two terminals of the semiconductor element (1); a current detector (14) that detects a current flowing between the two terminals of the semiconductor element (1); and a control device (200) that determines degradation of the power conversion device on the basis of the amount of change in the voltage detected by the voltage detector (13) at a plurality of timings when the currents detected by the current detector (14) are substantially the same. The control device (200) sets the detection frequency of the voltage in a first period after the amount of change in the voltage detected by the voltage detector (13) exceeds a threshold value to be higher than the detection frequency of the voltage in a period before the first period.

Description

Technical Field

[0001] The present disclosure relates to a power conversion device. Background Art

[0002] In the power module that constitutes the power conversion device, an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), which are power semiconductor elements, is installed inside. Metal wires are bonded to the metal electrodes on the surfaces of these power semiconductor elements. Therefore, during the operation of the power conversion device, heat generation and cooling occur repeatedly in the power semiconductor elements. As a result, cutting and peeling of the metal wires occur at the joint between the metal electrodes and the metal wires due to the difference in the linear expansion coefficients of the two.

[0003] For example, in the power conversion device described in Patent Document 1, points representing a set of collector-emitter voltage detection values and collector current detection values are projected onto the V-I plane to derive a distribution, and thereby the output characteristics of the IGBT generally recorded in a data sheet are obtained. This power conversion device estimates the degree of deterioration of the power conversion device by comparing the state based on this distribution with the initial state.

[0004] Patent Document 1: WO2022 / 044257 Summary of the Invention

[0005] Problems to be Solved by the Invention

[0006] In order to detect the collector-emitter voltage and determine the deterioration state of the power conversion device, it is necessary to measure the collector-emitter voltage for a plurality of current values and evaluate it. If the collector-emitter voltage is always measured and evaluated at a constant frequency (time interval), the efficiency of measurement and evaluation is poor, and the accuracy of evaluation is low. A high frequency of measurement and evaluation during a period when deterioration has not progressed results in a lot of waste. If the frequency of measurement and evaluation is low during a period when deterioration is progressing, the accuracy of deterioration determination deteriorates.

[0007] Therefore, an object of the present disclosure is to provide a power conversion device capable of efficiently and accurately determining the deterioration of a power conversion device.

[0008] Solutions to the Problems

[0009] The power conversion device of the present disclosure includes: a semiconductor element; a voltage detector that detects the voltage between two terminals of the semiconductor element; a current detector that detects the current flowing between the two terminals of the semiconductor element; and a control device that determines the deterioration of the power conversion device based on the change amount of the voltage detected by the voltage detector at a plurality of timings when the currents detected by the current detector are substantially the same. The control device sets the detection frequency of the voltage in the first period after the change amount of the voltage detected by the voltage detector exceeds a threshold value to be higher than the detection frequency of the voltage in the period before the first period.

[0010] Effects of the Invention

[0011] According to the power conversion device of the present disclosure, the detection frequency of the voltage in the first period after the change amount of the voltage detected by the voltage detector exceeds a threshold value is set to be higher than the detection frequency of the voltage in the period before the first period. Therefore, it is possible to determine the deterioration of the power conversion device efficiently and with high accuracy. Description of the Drawings

[0012] Figure 1 It is a diagram showing the structure of the power semiconductor element 1 inside the power module constituting the power conversion device and the peripheral part of the power semiconductor element 1.

[0013] Figure 2 It is a diagram showing the deterioration of the bonding wire 12 in the peripheral part of the power semiconductor element 1 inside the power module constituting the power conversion device.

[0014] Figure 3 It is a diagram showing an installation example of the voltage detector 13 and the current detector 14 in the power conversion device in Embodiment 1.

[0015] Figure 4 It is a diagram showing the voltage detector 13, the current detector 14, the control device 200, and the storage device 18 included in the power conversion device in Embodiment 1.

[0016] Figure 5 It is a diagram showing a general failure rate curve.

[0017] Figure 6 It is a diagram showing the change over time of the cumulative detection times of the collector-emitter voltage Vce used to estimate the deterioration state of the power conversion device in Embodiment 1.

[0018] Figure 7 It is a diagram showing the relationship between the detection voltage and the warning output of the power conversion device in Embodiment 1.

[0019] Figure 8This is a diagram showing an installation example of the voltage detector 13b and the current detector 14 in the power conversion device in Embodiment 2.

[0020] Figure 9 This is a diagram showing the insertion position of the current detector 14a in the power conversion device in Embodiment 3.

[0021] Figure 10 This is a diagram showing the detection timing in the power conversion device in Embodiment 3.

[0022] Figure 11 This is a diagram showing the insertion position of the current detector 14b in the power conversion device in Embodiment 4.

[0023] Figure 12 This is a diagram showing the detection timing in the power conversion device in Embodiment 4.

[0024] Figure 13 This is a diagram showing an explanation of the correction of the detected voltage in the power conversion device in Embodiment 5.

[0025] Figure 14 This is a diagram showing an explanation of the correction of the detected voltage in the power conversion device in Embodiment 6.

[0026] Figure 15 This is a diagram showing an explanation of the correction of the detected voltage in the power conversion device in Embodiment 7.

[0027] Figure 16 This is a diagram showing an explanation of the correction of the detected voltage in the power conversion device in a modified example of Embodiment 7. Detailed Embodiments

[0028] Embodiment 1.

[0029] The power conversion device in this embodiment performs power conversion between three-phase alternating current and direct current. The power conversion device has three-phase upper arms and lower arms and includes an inverter that is PWM-controlled. Each arm has a power semiconductor element 1. The power semiconductor element 1 is, for example, an IGBT or a MOSFET. Hereinafter, the IGBT is taken as an example for the power semiconductor element 1 for explanation.

[0030] Figure 1 This is a diagram showing the structure of the power semiconductor element 1 and the peripheral part of the power semiconductor element 1 inside the power module constituting the power conversion device.

[0031] Bonding wires 9, 10, 12a, 12b, and 12c are bonded to the metal electrode 2 on the surface of the power semiconductor element 1. The bonding wire 9 connects the metal electrode 2 to the gate terminal 3. The bonding wire 10 connects the metal electrode 2 to the reference emitter terminal 4. The bonding wires 12a, 12b, and 12c connect the metal electrode 2 to the emitter terminal 5. Sometimes, the bonding wires 12a, 12b, and 12c are collectively referred to as the bonding wire 12.

[0032] In the power conversion device, since the power semiconductor element 1 repeatedly switches between the on state and the off state, the power semiconductor element 1 is repeatedly heated and cooled.

[0033] When the power semiconductor element 1 is in the on state, the current flows as follows: collector terminal 6 → bonding wire 11 → collector substrate 7 → soldering portion 8 → metal electrode 2 → bonding wires 12a, 12b, and 12c → emitter terminal 5. Therefore, if the switching operation of the power semiconductor element 1 is repeated, cracks or the like are generated in the bonding wires 12a, 12b, and 12c at the joint between the metal electrode 2 and the bonding wires 12a, 12b, and 12c due to the difference in the linear expansion coefficients of the two, resulting in deterioration of the bonding wires 12a, 12b, and 12c. Eventually, the bonding wires 12a, 12b, and 12c are cut or peeled off.

[0034] Figure 2 It is a diagram showing the deterioration of the bonding wire 12 in the peripheral portion of the power semiconductor element 1 inside the power module constituting the power conversion device.

[0035] Bonding wires 12a, 12b, and 12c are connected between the metal electrode 2 and the emitter terminal 5. Suppose a crack has occurred in one bonding wire 12a due to deterioration. If a crack occurs in the bonding wire 12a among the parallel-connected bonding wires 12a, 12b, and 12c, the overall resistance of the bonding wires 12a, 12b, and 12c increases. If this crack gradually develops due to subsequent switching operations of the power semiconductor element 1, the overall resistance value of the bonding wires 12a, 12b, and 12c also gradually rises. If the bonding wire 12a is peeled off as the crack gradually develops, the overall resistance of the bonding wires 12a, 12b, and 12c rises sharply. Therefore, if the voltage between the collector and the emitter including the bonding wires 12a, 12b, and 12c is measured when a specified current flows through the power semiconductor element 1, the overall resistance value of the bonding wires 12a, 12b, and 12c becomes larger compared to the initial state, and accordingly, a larger voltage between the collector and the emitter is measured. From this, it can be known that the bonding wires 12a, 12b, and 12c are deteriorated as a whole.

[0036] Figure 3 It is a diagram showing an installation example of the voltage detector 13 and the current detector 14 in the power conversion device according to Embodiment 1. Figure 4FIG. is a diagram showing a voltage detector 13, a current detector 14, a control device 200, and a storage device 18 included in the power conversion device in Embodiment 1. The control device 200 may also be a processor that executes a program. A program executed by the processor may also be stored in the storage device 18.

[0037] The current detector 14 detects the current I0 flowing through the power semiconductor element 1. For example, the current detector 14 detects the collector current Ic flowing from the collector terminal 6 to the emitter terminal 5 of the power semiconductor element 1 as the current I0 flowing through the power semiconductor element 1. Examples of the current detector 14 include a CT (Current Transducer) or a shunt resistor. The current detector 14 detects the collector current Ic at a constant sampling interval and sends it to the control device 200.

[0038] The voltage detector 13 detects the voltage between the two main terminals of the power semiconductor element 1. Specifically, the voltage detector 13 detects the collector-emitter voltage Vce of the power semiconductor element 1. The path between the collector terminal 6 and the emitter terminal 5 includes a bonding wire 12. The voltage detector 13 may also detect the collector-emitter voltage Vce at the same timing as the current detector 14 and send it to the control device 200. The control device 200 stores only the required collector-emitter voltage Vce among the received collector-emitter voltages Vce in the storage device 18. Alternatively, the voltage detector 13 may detect the collector-emitter voltage Vce at a timing specified by the control device 200 and send it to the control device 200.

[0039] The storage device 18 can store the voltage Vce detected by the voltage detector 13 and the current I0 detected by the current detector 14.

[0040] When the currents detected by the current detector 14 are substantially the same, the control device 200 determines the deterioration of the power conversion device based on the change amount of the voltages detected by the voltage detector 13 at multiple timings. Here, substantially the same means substantially the same. The substantially the same range is a range in which the accuracy of the deterioration determination and the transition determination of the period remains unchanged compared to when they are the same. The substantially the same range also includes the same. The reason for setting it to substantially the same is that since the current changes continuously, there is a time difference when detecting the voltage after detecting that it is a specified current value, so the current value at the time of detecting the voltage may be different from the specified value.

[0041] In order to estimate the state in which the bonding wire 12 of the power semiconductor module gradually deteriorates over time due to the operation of the power conversion device, it is necessary to detect the current I0 flowing through the power semiconductor element 1 and the collector-emitter voltage Vce during the operation of the power conversion device and evaluate them. At this time, if the current I0 flowing through the power semiconductor element 1 and the collector-emitter voltage Vce are always detected and evaluated at a constant frequency, there is a lot of waste and the accuracy is poor.

[0042] Figure 5 It is a graph showing a general failure rate curve.

[0043] The failure rate curve shows the change in the failure rate of the device over time. Regarding the period of occurrence of failure, it can be divided into three periods: the early failure period, the random failure period, and the wear-out failure period according to the passage of time. In terms of estimating the remaining life of the power conversion device, in order to perform the evaluation, it is only necessary to detect the deterioration state of the bonding wire 12 in the wear-out failure period, but it is also necessary to assume the early failure and the random failure.

[0044] The control device 200 sets the detection frequency of the voltage Vce in the first period (wear-out failure period) after the change amount of the voltage Vce detected by the voltage detector 13 exceeds the threshold to be higher than the detection frequency of the voltage Vce in the period before the first period. And, the control device 200 sets the detection frequency of the voltage Vce in a predetermined second period (early failure period) after the power conversion device is set and starts operating in the period before the first period to be higher than the detection frequency of the voltage Vce in the third period (random failure period) after the second period. The detection frequency in the first period > the detection frequency in the second period > the detection frequency in the third period.

[0045] Figure 6 It is a graph showing the change over time of the cumulative detection times of the collector-emitter voltage Vce for estimating the deterioration state of the power conversion device in Embodiment 1.

[0046] In a predetermined period at the start of operation of the power conversion device corresponding to the early failure period, the voltage detector 13 detects Vce at a high frequency. In the period corresponding to the subsequent random failure period, the voltage detector 13 detects Vce at a low frequency. After that, the voltage value detected by the voltage detector 13 starts to show an upward trend. This indicates a sign of deterioration of the bonding wire 12 and shows that the life corresponding to the wear-out failure period is approaching. Therefore, the voltage detector 13 detects Vce at the highest frequency. Thereby, data can be obtained efficiently and with high accuracy.

[0047] Figure 7It is a diagram showing the relationship between the detection voltage and the warning output of the power conversion device in Embodiment 1. After the bonding wire 12 starts to show signs of deterioration, as the crack in the bonding wire 12 develops, the collector-emitter voltage Vce rises sharply. When the change amount of the collector-emitter voltage Vce is greater than the threshold value during the first period (wear failure period), the control device 200 outputs a warning to the outside.

[0048] During the first period (wear failure period), the control device 200 may also set the detection frequency to K times per period for every L1 periods of the current (output current) output from the power conversion device. During the second period (initial failure period), the control device 200 may also set the detection frequency to K times per period for every L2 periods of the current (output current) output from the power conversion device. During the third period (accidental failure period), the control device 200 may also set the detection frequency to K times per period for every L3 periods of the current (output current) output from the power conversion device. Here, K, L1, L2, and L3 are natural numbers, and L1 > L2 > L3.

[0049] Modification Example 1 of Embodiment 1.

[0050] Consider detecting the current I0 flowing through the power semiconductor element 1 and the collector-emitter voltage Vce during T cycles in such a way that it is detected K times in one cycle of the output current from the power conversion device. The T cycles are each L1 cycles of the output current in the first period (wear failure period), each L2 cycles of the output current in the second period (initial failure period), and each L3 cycles of the output current in the third period (random failure period). If the detection data for one time is stored as a data pair (i, v) with the current value set as i and the voltage value set as v, then (T×K) data pairs are stored. Alternatively, the value obtained by dividing the voltage value by the current value can be set as r for storing data. However, in either case, if stored randomly, it will become complicated data. Therefore, the storage device 18 sets the data for the p-th cycle as a K-dimensional vector V(p, K) and stores all the data as a matrix M(T, K). When the voltage detector 13 measures K times in one cycle of the output current, since the output current is a sine wave, according to its symmetry, when K is even, the collector-emitter voltage Vce is detected for K1 = (K / 2) current values, and when K is odd, the collector-emitter voltage Vce is detected for K1 = ((K + 1) / 2) current values. Therefore, the storage device 18 sets the data for the p-th cycle as a K1-dimensional vector V1(p, K1) and stores all the data as a matrix M1(T, K1), whereby comparison of the detected voltage values at substantially the same current values becomes easy. For example, when the vector V1(p, K1) is set as a row vector, the matrix M1(T1, K1) is a matrix with T1 rows and K1 columns, so it is only necessary to compare the detected voltage values of each column. Alternatively, when V1(p, K1) is set as a column vector, it is only necessary to compare the detected voltage values of each row.

[0051] Modification Example 2 of Embodiment 1.

[0052] When storing the pair of (i, v), the elements of V(p, K), M(T, K), V1(p, K1), and M1(T, K1) are the pair of (i, v), but it is not limited thereto. It is also possible to separately provide the vectors and matrices for i and the vectors and matrices for v.

[0053] Modification Example 3 of Embodiment 1.

[0054] Suppose the value of the current I0 at the j-th timing in the i-th (i≥1) cycle of each L3 cycles of the current output from the power conversion device in the third period (random failure period) is a preset I3(j) (j = 1 to K), and the value of the voltage Vce at the j-th timing in the i-th cycle is V3(i,

[0055] (j = 1 to K). The value of the current I0 at the j-th timing is the same for all i. These data are obtained, for example, as follows: The current detector 14 detects the current I0 at a constant sampling interval, the voltage detector 13 detects the voltage Vce at a constant sampling interval, and the control device 200 sets the Vce detected at the timing when the value of the current I0 becomes I3(j) as V3(i, j). Thus, the comparison between V3(m, j) and V3(n, j) can be made at substantially the same current I0 for each j.

[0056] The storage device 18 stores at least V3(i, j).

[0057] During the third period (accidental failure period), the control device 200 controls the transition from the third period (accidental failure period) to the first period (wear failure period) based on the comparison between V3(p, j) of the p-th (p ≥ 1) cycle and V3(p + 1, j) of the (p + 1)-th cycle. For example, the control device 200 may transfer from the third period (accidental failure period) to the first period (wear failure period) and change the detection frequency to the detection frequency of the first period when the value obtained by subtracting V3(p, j) from V3(p + 1, j) exceeds the threshold THV3(j) at at least one j. Or, the control device 200 may transfer from the third period (accidental failure period) to the first period (wear failure period) and change the detection frequency to the detection frequency of the first period when the value obtained by subtracting V3(p, j) from V3(p + 1, j) exceeds the threshold THV3(j) at all j. Or, the control device 200 may transfer from the third period (accidental failure period) to the first period (wear failure period) and change the detection frequency to the detection frequency of the first period when the average value of the value obtained by subtracting V3(p, j) from V3(p + 1, j) exceeds the threshold THV3A.

[0058] Modification Example 4 of Embodiment 1.

[0059] The value of the resistance obtained by dividing the value of the voltage Vce at the i-th (i ≥ 1) cycle and the j-th timing of each L3 cycle of the current output from the power conversion device during the third period (accidental failure period) by the value of the current I0 at the j-th timing of the i-th cycle is set as R3(i,

[0060] j) (j = 1 to K). In this modification example, different from Modification Example 3, the value of the current I0 at the j-th timing does not need to be the same for all i.

[0061] The storage device 18 stores at least R3(i, j).

[0062] During the third period (accidental failure period), the control device 200 controls the transition from the third period (accidental failure period) to the first period (wear failure period) based on the comparison between R3(p, 1) to R3(p, K) in the p-th (p≥1) cycle and R3(p + 1, 1) to R3(p + 1, K) in the (p + 1)-th cycle.

[0063] For example, the control device 200 may also transfer from the third period (accidental failure period) to the first period (wear failure period) and change the detection frequency to the detection frequency of the first period when the value obtained by subtracting the average value of R3(p, 1) to R3(p, K) from the average value of R3(p + 1, 1) to R3(p + 1, K) exceeds the threshold THR3.

[0064] Variant Example 5 of Embodiment 1.

[0065] Considering that measurement errors (deviations) always occur in the detection data, statistical data such as the average value μ and the standard deviation σ of the detection data are obtained by performing measurements at a high frequency in the initial stage of the operation of the power conversion device, thereby correcting the deviation of the data. Thus, it is possible to improve the accuracy of the detection data in a state where the power conversion device is not deteriorated.

[0066] The control device 200 calculates the average value μ and the standard deviation σ for the detection data values and the matrix M(T, K) stored in the storage device 18. Regarding the deviation and its degree of the detection data, approximately 95.5% of the detection data is included within μ±2σ, and approximately 99.7% of the detection data is included within μ±3σ. That is, it can be seen that when the deterioration of the bonding wire (emitter) 12 hardly progresses, almost all of the voltages detected by the voltage detector 13 converge within the range of μ±3σ. When peeling occurs as the deterioration of the bonding wire (emitter) 12 progresses, the resistance rises sharply at that timing, that is, the detected voltage value rises sharply, and thus it deviates from the range of μ±3σ.

[0067] When the output current of the power conversion device is detected K times in one cycle, the data detected until the p-th cycle is stored as the matrix M(p, K).

[0068] The control device 200 calculates the average value μ and the standard deviation σ for each column of the matrix M. Thus, the matrix M(p, K) can be represented as a K-dimensional vector V1(μ, K) with the average value μ as an element and a K-dimensional vector V2(σ, K) with the standard deviation σ as an element. Therefore, after performing the statistical processing, it is also possible to store only the vectors V1(μ, K) and V2(σ, K) and delete the data used in the statistical processing. In this way, the K-dimensional vector V1(μ, K) obtained by the statistical processing can be represented as V1(K)_μ, and the K-dimensional vector V2(σ, K) can be represented as V2(K)_σ.

[0069] When each element of V(p + 1, K) detected in the (p + 1)-th cycle is greater than each element of V1(K)_μ + 3×V2(K)_σ calculated based on the values detected up to the p-th cycle, the control device 200 can determine that it is approaching the remaining life as the bonding wire 12 deteriorates.

[0070] Modification Example 6 of Embodiment 1.

[0071] Let the value of the current at the j-th timing in the i-th (i ≥ 1) cycle of each L1 cycle of the current output from the power conversion device in the first period (wear failure period) be a predetermined I1(j) (j = 1 to K), and the value of the voltage at the j-th timing in the i-th cycle be V1(i,

[0072] j) (j = 1 to K). Let the average value of V1(s, j) (s = 1 to p) up to the p-th cycle be μ(j), and the standard deviation be σ(j).

[0073] The storage device 18 stores at least μ(j) and σ(j).

[0074] Based on the comparison between V1(p + 1, j) in the (p + 1)-th cycle and μ(j) + 3σ(j) in the first period, the control device 200 determines whether the power conversion device has deteriorated. For example, when V1(p + 1, j) exceeds {μ(j) + 3σ(j)} at at least one j, the control device 200 may transfer from the third period (random failure period) to the first period (wear failure period) and change the detection frequency to the detection frequency of the first period.

[0075] Alternatively, when V1(p + 1, j) exceeds {μ(j) + 3σ(j)} at all j, the control device 200 may transfer from the third period (random failure period) to the first period (wear failure period) and change the detection frequency to the detection frequency of the first period.

[0076] Modification Example 7 of Embodiment 1.

[0077] The power conversion device of the embodiment performs PWM operation. In this power conversion device, a triangular wave in the kHz order is generally used to generate a PWM signal. Therefore, the control device 200 can also set K detection points in one cycle at an arbitrary timing of the center timing of a plurality of pulses of the PWM signal. According to the pulse width of the PWM signal, the IGBT becomes in the on state, and thus a collector current flows. The center timing of the pulse becomes the center timing of the on period. At the rising or falling edge of the pulse, the collector current may change due to the deviation of the detection timing, while a stable current can be detected at the center timing of the pulse. Since the frequency of the PWM signal is constant, the period from the on state of a certain pulse to the on state of the next pulse is equal, but due to different pulse widths, the centers of the pulse widths are not equally spaced. In order to make the approximate centers of the on-pulse signals of the PWM signal in which the IGBT is in the on state equally spaced and become detection points, the control device 200 can also set the timings of a plurality of peaks of the triangular wave called the carrier as K detection points in one cycle.

[0078] For the power semiconductor element 1 of the upper arm, the control device 200 can also set K detection points in one cycle at an arbitrary timing of the timings of a plurality of triangular waves at the center of the pulses of the PWM signal during the period when the output current (the current flowing through the load) is positive. For the power semiconductor element 1 of the lower arm, the control device 200 can also set K detection points in one cycle at an arbitrary timing of the timings of a plurality of triangular waves at the center of the pulses of the PWM signal during the period when the output current (the current flowing through the load) is negative.

[0079] Modification Example 8 of Embodiment 1.

[0080] When x bonding wires 12 (x≥2) are connected to one power semiconductor element 1, the maximum allowable number of times of detecting a sharp rise in the voltage Vce as the bonding wire 12 peels off is (x - 1). The control device 200 can also output a warning when the number of times the change amount of the detected voltage Vce exceeds the threshold reaches the (x - 1)th time. Alternatively, the control device 200 can also output a warning every time the change amount of the detected voltage Vce exceeds the threshold. Further, the control device 200 can also output different warnings according to the number of times of the sharp rise in the detected voltage Vce, that is, the number of times the change amount of the detected voltage Vce exceeds the threshold (the number of warnings).

[0081] Modification Example 9 of Embodiment 1.

[0082] The control device 200 can also compare the collector-emitter voltage Vce in the initial state (before starting operation after the power conversion device is set) when substantially the same current flows through the power semiconductor element 1 with the collector-emitter voltage Vce at each time point.

[0083] The control device 200 may also compare the resistance, which is the value obtained by dividing the collector-emitter voltage Vce by the current I0 flowing through the power semiconductor element 1 when substantially the same current flows through the power semiconductor element 1, and which is in the initial state (before operation starts after the power conversion device is set), with the resistance, which is the value obtained by dividing the collector-emitter voltage Vce by the current I0 flowing through the power semiconductor element 1 at each time point.

[0084] Modification Example 10 of Embodiment 1.

[0085] In the embodiment, the control device 200 sets the detection frequency of the voltage Vce in the first period (wear failure period) after the change amount of the voltage Vce detected by the voltage detector 13 exceeds the threshold to be higher than the detection frequency of the voltage Vce in the period before the first period, but it is not limited thereto. The control device 200 may also set the detection frequency of the voltage Vce in the first period (wear failure period) after the value of the voltage Vce detected by the voltage detector 13 exceeds the threshold to be higher than the detection frequency of the voltage Vce in the period before the first period.

[0086] In the embodiment, the control device 200 outputs a warning to the outside when the change amount of the collector-emitter voltage Vce is greater than the threshold in the first period (wear failure period), but it is not limited thereto. The control device 200 may also output a warning to the outside when the value of the collector-emitter voltage Vce is greater than the threshold in the first period (wear failure period).

[0087] Embodiment 2.

[0088] Figure 8 FIG. is a diagram showing an installation example of the voltage detector 13b and the current detector 14 in the power conversion device according to Embodiment 2.

[0089] The voltage detector 13b detects the voltage between the reference terminal and the reference reference terminal of the power semiconductor element 1. Specifically, the voltage detector 13b detects the voltage Vee between the reference emitter terminal and the emitter terminal of the power semiconductor element 1. Even when measuring the voltage between the reference emitter terminal 4 and the emitter terminal 5, the path between the reference emitter terminal 4 and the emitter terminal 5 includes the bonding wire 12. Therefore, by detecting the current I0 flowing through the power semiconductor element 1 and the voltage Vee between the reference emitter terminal and the emitter terminal, it is also possible to detect the deterioration of the bonding wire 12.

[0090] The current detector 14 is the same as described in Embodiment 1. The operation of the control device 200 is the same as the operation described in Embodiment 1 and its modification examples.

[0091] When detecting the collector-emitter voltage Vce, the detected value includes the characteristics of the power semiconductor element 1. However, when detecting the voltage Vee between the reference emitter terminal and the emitter terminal, the path between the reference emitter terminal and the emitter terminal does not include the power semiconductor element 1. Therefore, it is possible to more directly detect the increase in the voltage value or the increase in the resistance value caused by the deterioration of the bonding wire 12.

[0092] Embodiment 3.

[0093] Figure 9 FIG. is a diagram showing the insertion position of the current detector 14a in the power conversion device according to Embodiment 3. Figure 9 An example is shown in the case where the power semiconductor element 1 to be measured is the power semiconductor element 1 of the upper arm of the U phase. The current detector 14a for detecting the current I0 flowing through the power semiconductor element 1 of the upper arm of the U phase is arranged on the emitter side of the power semiconductor element 1 of the upper arm of the U phase. The current detector 14a detects the collector current of the power semiconductor element 1 of the upper arm of the U phase.

[0094] Figure 10 FIG. is a diagram showing the detection timing in the power conversion device according to Embodiment 3. In the region where the output current of the U phase is positive, the power semiconductor element of the upper arm of the U phase and the diode of the lower arm of the U phase are turned on. Therefore, the control device 200 causes the current detector 14a to detect the collector current of the power semiconductor element 1 of the upper arm of the U phase and causes the voltage detector 13 to detect the collector-emitter voltage Vce of the power semiconductor element 1 of the upper arm of the U phase at the timing indicated by the upward arrow in the region where the output current of the U phase is positive. Regarding this timing, it can be determined based on the triangular wave as described in Embodiment 1.

[0095] In addition, in Figure 9 , the current detector 14a is provided at the position for detecting the current flowing through the power semiconductor element 1 of the upper arm of the U phase, but it is not limited to the U phase, and is not limited to the upper arm either. That is, it can be the V phase or the W phase, and can also be installed on all of the upper and lower arms of the three-phase arms of U, V, and W.

[0096] The control device 200 causes the current detector 14a to detect the collector current of the power semiconductor element 1 of the lower arm of the U phase and causes the voltage detector 13 to detect the collector-emitter voltage Vce of the power semiconductor element 1 of the lower arm of the U phase at the timing in the negative region of the output current of the U phase.

[0097] The control device 200 causes the current detector 14a to detect the collector current of the power semiconductor element 1 of the upper arm of the V-phase at the timing in the positive region of the output current of the V-phase, and causes the voltage detector 13 to detect the voltage Vce between the collector-emitter terminals of the power semiconductor element 1 of the upper arm of the V-phase.

[0098] The control device 200 causes the current detector 14a to detect the collector current of the power semiconductor element 1 of the lower arm of the V-phase at the timing in the negative region of the output current of the V-phase, and causes the voltage detector 13 to detect the voltage Vce between the collector-emitter terminals of the power semiconductor element 1 of the lower arm of the V-phase.

[0099] The control device 200 causes the current detector 14a to detect the collector current of the power semiconductor element 1 of the upper arm of the W-phase at the timing in the positive region of the output current of the W-phase, and causes the voltage detector 13 to detect the voltage Vce between the collector-emitter terminals of the power semiconductor element 1 of the upper arm of the W-phase.

[0100] The control device 200 causes the current detector 14a to detect the collector current of the power semiconductor element 1 of the lower arm of the W-phase at the timing in the negative region of the output current of the W-phase, and causes the voltage detector 13 to detect the voltage Vce between the collector-emitter terminals of the power semiconductor element 1 of the lower arm of the W-phase.

[0101] Embodiment 4.

[0102] Figure 11 FIG. is a diagram showing the insertion position of the current detector 14b in the power conversion device in Embodiment 4. Figure 11 This shows an example in the case where the power semiconductor element 1 to be measured is the power semiconductor element 1 of the upper arm or the lower arm of the U-phase. The current detector 14b for detecting the current I0 flowing through the power semiconductor element 1 of the upper arm or the lower arm of the U-phase is provided between the load M and the node NU between the upper arm of the U-phase and the lower arm of the U-phase. The current detector 14b detects the output current of the U-phase.

[0103] When the power semiconductor element 1 to be measured is the upper arm of the U-phase, the control device 200 may set the detection timing to the period when the current flowing through the U-phase is positive, similarly to Embodiment 3. When the power semiconductor element 1 to be measured is the lower arm of the U-phase, the control device 200 may set the detection timing to the period when the current flowing through the U-phase is negative, similarly to Embodiment 3. Alternatively, the control device 200 may set the detection timing as follows.

[0104] Figure 12 FIG. is a diagram showing the detection timing in the power conversion device in Embodiment 4. As Figure 12As shown, there is a period during which only the output current of the U-phase is positive while the output currents of the V-phase and W-phase are both negative (the period at the timing indicated by the upward arrow). This is because the phases of each phase are offset by 120°. During this period, the magnitude of the current flowing through the U-phase becomes high, so the current I0 flowing through the power semiconductor element 1 of the upper arm of the U-phase can be detected with high precision. Therefore, for the power semiconductor element 1 of the upper arm of the U-phase, the control device 200 can also set the period during which only the output current of the U-phase is positive while the output currents of the V-phase and W-phase are both negative as the detection timing period of the current detector 14b and the voltage detector 13. Regarding this period, it can be determined based on the triangular wave generated when performing PWM control.

[0105] There is also a timing during which only the output current of the U-phase is negative while the output currents of the V-phase and W-phase are positive. For the power semiconductor element 1 of the lower arm of the U-phase, the control device 200 can also set the period during which only the output current of the U-phase is negative while the output currents of the V-phase and W-phase are both positive as the detection timing period of the current detector 14b and the voltage detector 13.

[0106] Similarly, when the power semiconductor element 1 to be measured is the power semiconductor element 1 of the V-phase, the current detector 14b for detecting the current I0 flowing through the power semiconductor element 1 is provided between the load and the node NV between the upper arm of the V-phase and the lower arm of the V-phase. The current detector 14b detects the output current of the V-phase. For the power semiconductor element 1 of the upper arm of the V-phase, the control device 200 can also set the period during which only the output current of the V-phase is positive while the output currents of the U-phase and W-phase are both negative as the detection timing period of the current detector 14b and the voltage detector 13. For the power semiconductor element 1 of the lower arm of the V-phase, the control device 200 can also set the period during which only the output current of the V-phase is negative while the output currents of the U-phase and W-phase are both positive as the detection timing period of the current detector 14b and the voltage detector 13.

[0107] Similarly, when the power semiconductor element 1 to be measured is the power semiconductor element 1 of the W-phase, the current detector 14b for detecting the current I0 flowing through the power semiconductor element 1 is provided between the load and the node NW between the upper arm of the W-phase and the lower arm of the W-phase. For the power semiconductor element 1 of the upper arm of the W-phase, the control device 200 can also set the period during which only the output current of the W-phase is positive while the output currents of the U-phase and V-phase are both negative as the detection timing period of the current detector 14b and the voltage detector 13. For the power semiconductor element 1 of the lower arm of the W-phase, the control device 200 can also set the period during which only the output current of the W-phase is negative while the output currents of the U-phase and V-phase are both positive as the detection timing period of the current detector 14b and the voltage detector 13.

[0108] Embodiment 5.

[0109] Figure 13 This is a diagram showing the voltages of each part detected by the voltage detector 13 in the power conversion device of Embodiment 5. There is a parasitic inductance Lsc between the collector electrode of the power semiconductor element 1 and the collector terminal 6, and a parasitic inductance Lse between the emitter electrode of the power semiconductor element 1 and the emitter terminal 5. Therefore, when the current flowing through the power semiconductor element 1 during the operation of the power conversion device is set to I and the change amount per unit time thereof is set to dI / dt, the voltage detected by the voltage detector 13 includes an induced voltage of Vs1 = {(Lsc + Lse) × dI / dt}, and the voltage detected by the voltage detector 13b includes an induced voltage of Vs2 = (Lse × dI / dt). By subtracting the amount of such induced voltage from the detected voltage, a voltage value with higher accuracy can be detected.

[0110] The control device 200 of the present embodiment subtracts the induced voltage Vs1 from the voltage value detected by the voltage detector 13. Alternatively, the control device 200 subtracts the induced voltage Vs2 from the voltage value detected by the voltage detector 13b.

[0111] The control device 200 uses the voltage after the subtraction operation instead of the voltage detected by the voltage detector 13 or 13b, and performs the operations and controls described in the foregoing embodiments.

[0112] Modification example of Embodiment 5.

[0113] As described in Modification example 10 of Embodiment 1, when the control device 200 sets the detection frequency of the voltage Vce in the first period (wear failure period) after the value of the voltage Vce detected by the voltage detector 13 exceeds the threshold to be higher than the detection frequency of the voltage Vce in the period before the first period, the control device 200 may also increase the threshold by the amount of the induced voltage Vs1 or Vs2.

[0114] As described in Modification example 10 of Embodiment 1, when the control device 200 outputs a warning to the outside when the value of the collector - emitter voltage Vce is greater than the threshold in the first period (wear failure period), the control device 200 may also increase the threshold by the amount of the induced voltage Vs1 or Vs2.

[0115] Embodiment 6.

[0116] Figure 14 This is a diagram for explaining the correction of the detected voltage in the power conversion device of Embodiment 6. It is possible to obtain dI / dt based on the current value between two points detected by the current detector 14 and the detection timing difference. Figure 14An example showing two detection points (t1, v2) and (t2, v2) in a certain period of the power conversion device is shown. Regarding the parasitic inductances Lsc and Lse, they can be calculated and stored in advance through electromagnetic field analysis.

[0117] In the present embodiment, the control device 200 calculates dI / dt using two detection points (t1, v2) and (t2, v2) in a certain period of the power conversion device. The control device 200 can calculate the induced voltage Vs1 using dI / dt and the stored parasitic inductances Lsc and Lse. Alternatively, the control device 200 can calculate the induced voltage Vs2 using dI / dt and the stored parasitic inductance Lse.

[0118] Embodiment 7.

[0119] Figure 15 It is a diagram for explaining the correction of the detected voltage in the power conversion device in Embodiment 7. The relationship between the collector-emitter voltage Vce and the collector current Ic flowing through the power semiconductor element 1 is non-linear. The control device 200 uses three or more points of (Vce, Ic) to obtain a regression curve for obtaining Vce from Ic. As the regression curve, a quadratic equation (y = ax 2 + bx + c), a linear equation (y = ax + b), an exponential function, a trigonometric function, or a hyperbolic function, etc. can be used. In the regression curve, the value of the collector-emitter voltage Vce when the collector current Ic is 0 (that is, the offset x (intercept) with respect to the origin of the regression curve) is the induced voltage Vs1 included in the detected voltage of the voltage detector 13. The control device 200 obtains the offset x with respect to the origin of the regression curve as the induced voltage Vs1.

[0120] Modification of Embodiment 7.

[0121] Figure 16 It is a diagram for explaining the correction of the detected voltage in the power conversion device in the modification of Embodiment 7. The relationship between the reference emitter-terminal to emitter-terminal voltage Vee and the current I0 flowing through the power semiconductor element 1 is approximately linear. The control device 200 uses two or more points of (Vee, Ic) to obtain a regression line for obtaining Vee from Ic. In the regression line, the reference emitter-terminal to emitter-terminal voltage Vee when the collector current Ic is 0 (that is, the offset x (intercept) with respect to the origin of the regression line) is the induced voltage Vs2 included in the detected voltage of the voltage detector 13b. The control device 200 obtains the offset x with respect to the origin of the regression line as the induced voltage Vs2.

[0122] It should be considered that the embodiments disclosed herein are illustrative rather than restrictive in all respects. The scope of the present invention is represented not by the above description but by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0123] (Description of reference numerals)

[0124] 1: Power semiconductor element; 2: Metal electrode; 3: Gate terminal; 4: Reference emitter terminal; 5: Emitter terminal; 6: Collector terminal; 7: Collector substrate; 8: Welding portion; 9, 10, 11, 12, 12a, 12b, 12c, l2b: Bonding wire; 13, 13b: Voltage detector; 14, 14a, 14b: Current detector; 18: Storage device; 200: Control device; M: Load; NU, NV, NW: Node.

Claims

1. A power conversion device includes: A semiconductor element; A voltage detector that detects the voltage between two terminals of the semiconductor element; A current detector that detects the current flowing between the two terminals of the semiconductor element; And A control device that determines the deterioration of the power conversion device based on the change amount of the voltage detected by the voltage detector at multiple timings when the currents detected by the current detector are substantially the same. The control device sets the detection frequency of the voltage in a first period after the change amount of the voltage detected by the voltage detector exceeds a threshold to be higher than the detection frequency of the voltage in a period before the first period.

2. The power conversion device according to claim 1, wherein The control device sets the detection frequency of the voltage in a predetermined second period after the power conversion device starts operating after being set to be higher than the detection frequency of the voltage in a third period after the second period in a period before the first period.

3. The power conversion device according to claim 2, wherein The control device sets the detection frequency to K times per period for every L1 periods of the current output from the power conversion device in the first period, sets the detection frequency to K times per period for every L2 periods of the current output from the power conversion device in the second period, and sets the detection frequency to K times per period for every L3 periods of the current output from the power conversion device in the third period, where K, L1, L2, and L3 are natural numbers and L1 > L2 > L3.

4. The power conversion device according to claim 3, wherein In the third period, the value of the current at the j-th timing of the i-th (i≥1) period for every L3 periods of the current output from the power conversion device is a predetermined I3(j) (j = 1 to K), and the value of the voltage at the j-th timing of the i-th period is V3(i, j) (j = 1 to K). The power conversion device includes at least a storage device that stores V3(i, j). The control device controls the transition from the third period to the first period based on the comparison between V3(p, j) of the p-th (p≥1) period and V3(p + 1, j) of the (p + 1)-th period in the third period.

5. The power conversion device according to claim 3, wherein In the third period, the resistance value obtained by dividing the value of the voltage at the j-th timing of the i-th (i≥1) period for every L3 periods of the current output from the power conversion device by the value of the current at the j-th timing of the i-th period is R3(i, j) (j = 1 to K). The power conversion device includes at least a storage device that stores R3(i, j). The control device controls the transition from the third period to the first period based on the comparison between R3(p, 1) to R3(p, K) of the p-th (p≥1) period and R3(p + 1, 1) to R3(p + 1, K) of the (p + 1)-th period in the third period.

6. The power conversion device according to claim 3, wherein, in the first period, the value of the current at the j-th timing of the i-th (i≥1) cycle of each L1 cycle of the current output from the power conversion device is a predetermined I1(j) (j = 1 to K), the value of the voltage at the j-th timing of the i-th cycle is V1(i, j) (j = 1 to K), the average value of V1(s, j) (s = 1 to p) until the p-th (p≥1) cycle is μ(j), and the standard deviation is σ(j), the power conversion device includes a storage device that stores at least μ(j) and σ(j), the control device determines whether the power conversion device deteriorates based on the comparison between V1(p + 1, j) of the (p + 1)-th cycle and μ(j)+3σ(j) in the first period.

7. The power conversion device according to claim 6, wherein, the control device outputs a warning when it determines that the power conversion device deteriorates.

8. The power conversion device according to claim 7, wherein, the control device outputs different warnings according to the number of warnings.

9. The power conversion device according to claim 1, wherein, the control device causes the voltage detector to detect the voltage during the period when the output current of each phase is positive for the semiconductor element of the upper arm of each phase, and causes the voltage detector to detect the voltage during the period when the output current of each phase is negative for the semiconductor element of the lower arm of each phase.

10. The power conversion device according to claim 1, wherein, the control device causes the voltage detector to detect the voltage during the period when the output current of each phase is positive and the output currents of the other two phases are negative for the semiconductor element of the upper arm of each phase, and causes the voltage detector to detect the voltage during the period when the output current of each phase is negative and the output currents of the other two phases are positive for the semiconductor element of the lower arm of each phase.

11. The power conversion device according to any one of claims 1 to 10, wherein, the control device performs a subtraction operation of subtracting the induced voltage generated by the parasitic inductance between the two terminals of the semiconductor element from the voltage detected by the voltage detector, and uses the voltage after the subtraction operation to perform the determination of the deterioration of the power conversion device and the setting of the detection frequency of the voltage.

12. The power conversion device according to claim 11, wherein, the control device calculates the product of the parasitic inductance between the two terminals of the semiconductor element and the time derivative of the current detected by the current detector as the induced voltage.

13. The power conversion device according to claim 11, wherein, the control device uses a plurality of sampling data of the voltage detected by the voltage detector and the current detected by the current detector detected at substantially the same timing, calculates a regression line or a regression curve for obtaining the current from the voltage, and calculates the value of the current when the voltage is 0 in the regression line or the regression curve as the induced voltage.

14. The power conversion device according to any one of claims 1 to 13, wherein the two terminals of the semiconductor element are two main terminals of the semiconductor element.

15. The power conversion device according to any one of claims 1 to 13, wherein the two terminals of the semiconductor element are a reference terminal and a reference reference terminal of the semiconductor element.

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