Three-dimensional memory device with laterally spaced source select electrodes and method of forming same

Abstract

The three-dimensional memory device includes a main source side select gate electrode between a word line and a bottom source side select gate electrode. The main source side select gate electrode is laterally spaced in each memory block, while the word line and the bottom source side select gate electrode are not laterally spaced in each memory block.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of the entire contents of U.S. Non - Provisional Application No. 18 / 362,805, filed on July 31, 2023, entitled "THREE - DIMENSIONAL MEMORY DEVICE WITH LATERALLY SEPARATED SOURCE SELECT ELECTRODES AND METHODS OF FORMING THE SAME", which claims the priority of U.S. Provisional Application No. 63 / 508,386, filed on June 15, 2023. Field of the Invention

[0003] The present disclosure generally relates to the field of semiconductor devices, and more particularly to three - dimensional semiconductor devices including laterally separated source select electrodes in the same memory block and methods of manufacturing the same. Background Art

[0004] A three - dimensional vertical NAND string with one bit per cell is disclosed in the article "Novel Ultra High - Density Memory With A Stacked - Surrounding Gate Transistor (S - SGT)" by T. Endoh et al. (Proceedings of the IEDM Conference, 2001, pages 33 - 36). Summary of the Invention

[0005] According to one aspect of the present disclosure, a semiconductor structure includes: a memory block including an alternating stack of insulating layers and conductive layers arranged in a vertical direction and laterally extending in a first horizontal direction; a memory opening extending vertically through the alternating stack; and a memory opening fill structure located in the memory opening, wherein each memory opening fill structure in the memory opening fill structure includes a respective memory film and a respective vertical semiconductor channel. The conductive layer includes a word line, at least one bottom source side select gate electrode, and at least one main source side select gate electrode, and the at least one main source side select gate electrode is located between the word line and the at least one bottom source side select gate electrode in the vertical direction. The word line and the at least one bottom source side select gate electrode continuously laterally extend through the entirety of the memory block in a second horizontal direction perpendicular to the first horizontal direction; and

[0006] The at least one main source-side select gate electrode is laterally spaced along the second horizontal direction.

[0007] According to another aspect of the present disclosure, a method of forming a semiconductor structure is provided. The method includes: forming a first alternating stack of a first insulating layer and a first sacrificial material layer over a substrate, wherein the first sacrificial material layer includes at least one bottom source select level sacrificial material layer and at least one main source select level sacrificial material layer from bottom to top; forming a source-side dielectric isolation structure that laterally extends in a first horizontal direction through the at least one main source select level sacrificial material layer but does not pass through any part of the at least one bottom source select level sacrificial material layer; forming a second alternating stack of a second insulating layer and a second sacrificial material layer over the first alternating stack and the source-side dielectric isolation structure; forming a memory opening through the second alternating stack and the first alternating stack; forming a memory opening fill structure in the memory opening, wherein each memory opening fill structure in the memory opening fill structure includes a corresponding memory film and a corresponding vertical semiconductor channel; and replacing the second sacrificial material layer and the first sacrificial material layer with a conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic vertical cross-sectional view of an exemplary structure after forming a first alternating stack of a first insulating layer and a first sacrificial material layer over a carrier substrate according to an embodiment of the present disclosure.

[0009] Figure 2A is a schematic vertical cross-sectional view of an exemplary structure after forming a source-side dielectric isolation structure through at least one main source select level sacrificial material layer according to an embodiment of the present disclosure.

[0010] Figure 2B is Figure 2A a top-down view of an exemplary structure of. The vertical plane A-A' is Figure 2A the cutting plane of the vertical cross-sectional view of.

[0011] Figure 2C is along Figure 2B a vertical cross-sectional view of a region of an exemplary structure along the vertical plane C-C' of.

[0012] Figure 3A is a schematic vertical cross-sectional view of an exemplary structure after forming a second alternating stack of a second insulating layer and a second sacrificial material layer according to an embodiment of the present disclosure.

[0013] Figure 3B is Figure 3A a top-down view of an exemplary structure of. The vertical plane A-A' is Figure 3A the cutting plane of the vertical cross-sectional view of.

[0014] Figure 4 is a schematic vertical cross - sectional view of an exemplary structure after forming a stepped surface and a stepped dielectric material portion according to an embodiment of the present disclosure.

[0015] Figure 5A is a schematic vertical cross - sectional view of an exemplary structure after forming a support opening according to an embodiment of the present disclosure.

[0016] Figure 5B is Figure 5A a top - down view of an exemplary structure. The vertical plane A - A' is Figure 5A the cutting plane of the vertical cross - sectional view.

[0017] Figure 6 is a vertical cross - sectional view of an exemplary structure after forming a support pillar structure according to an embodiment of the present disclosure.

[0018] Figure 7A is a schematic vertical cross - sectional view of an exemplary structure after forming a memory opening according to an embodiment of the present disclosure.

[0019] Figure 7B is Figure 7A a top - down view of an exemplary structure. The vertical plane A - A' is Figure 7A the cutting plane of the vertical cross - sectional view.

[0020] Figure 7C is along Figure 7B a vertical cross - sectional view of a region of an exemplary structure along the vertical plane C - C'.

[0021] Figure 7D is along Figure 7C a horizontal cross - sectional view of a region of an exemplary structure along the horizontal plane D - D'.

[0022] Figures 8A to 8F is a sequential vertical cross - sectional view of a memory opening during the formation of a memory opening filling structure according to an embodiment of the present disclosure.

[0023] Figure 9A is a schematic vertical cross - sectional view of an exemplary structure after forming a memory opening filling structure according to an embodiment of the present disclosure.

[0024] Figure 9B is Figure 9A a top - down view of an exemplary structure. The vertical plane A - A' is Figure 9A the cutting plane of the vertical cross - sectional view.

[0025] Figure 9C is along Figure 9B a vertical cross - sectional view of a region of an exemplary structure along the vertical plane C - C'.

[0026] Figure 9D is a horizontal cross-sectional view of a region of an exemplary structure along the Figure 9C horizontal plane D-D'.

[0027] Figure 10A is a schematic vertical cross-sectional view of an exemplary structure after forming a drain-side dielectric isolation structure according to an embodiment of the present disclosure.

[0028] Figure 10B is Figure 10A a top-down view of an exemplary structure. The vertical plane A-A' is the Figure 10A cutting plane of the vertical cross-sectional view.

[0029] Figure 10C is a vertical cross-sectional view of a region of an exemplary structure along the Figure 10B vertical plane C-C'.

[0030] Figure 10D is a horizontal cross-sectional view of a region of an exemplary structure along the Figure 10C horizontal plane D-D'.

[0031] Figure 11A is a vertical cross-sectional view of an exemplary structure after forming a lateral isolation trench according to an embodiment of the present disclosure.

[0032] Figure 11B is Figure 11A a top-down view of an exemplary structure. The vertical plane A-A' is the Figure 11A cutting plane of the vertical cross-sectional view.

[0033] Figure 12 is a vertical cross-sectional view of an exemplary structure after forming a laterally extending cavity according to an embodiment of the present disclosure.

[0034] Figure 13A is a schematic vertical cross-sectional view of an exemplary structure after forming a conductive layer according to an embodiment of the present disclosure.

[0035] Figure 13B is Figure 13A a top-down view of an exemplary structure. The vertical plane A-A' is the Figure 13A cutting plane of the vertical cross-sectional view.

[0036] Figure 13C is a vertical cross-sectional view of a region of an exemplary structure along the Figure 13B vertical plane C-C'.

[0037] Figure 13D is a horizontal cross-sectional view of a region of an exemplary structure along the Figure 13C horizontal plane D-D'.

[0038] Figure 14A is a vertical cross - sectional view of an exemplary structure after forming a lateral isolation trench fill structure, a layer contact via structure, and a drain contact via structure, according to an embodiment of the present disclosure.

[0039] Figure 14B is Figure 14A a top - down view of an exemplary structure. The vertical plane A - A' is Figure 14A the cutting plane of the vertical cross - sectional view of

[0040] Figure 15 is a vertical cross - sectional view of an exemplary structure after forming a memory die, according to an embodiment of the present disclosure.

[0041] Figure 16 is a vertical cross - sectional view of a logic die, according to an embodiment of the present disclosure.

[0042] Figure 17 is a vertical cross - sectional view of an exemplary structure after attaching the logic die to the memory die, according to an embodiment of the present disclosure.

[0043] Figure 18A is a vertical cross - sectional view of an exemplary structure after removing the carrier substrate, according to an embodiment of the present disclosure.

[0044] Figure 18B is Figure 18A an enlarged view of region B of

[0045] Figure 19 is a vertical cross - sectional view of a region of an exemplary structure after vertically recessing a memory film, a channel, and a dielectric core, according to an embodiment of the present disclosure.

[0046] Figure 20A is a vertical cross - sectional view of an exemplary structure after forming a metal source structure, according to an embodiment of the present disclosure.

[0047] Figure 20B is Figure 20A an enlarged view of region B of DETAILED DESCRIPTION

[0048] As discussed above, the present disclosure relates to a three - dimensional semiconductor device and a method of manufacturing the same, the three - dimensional semiconductor device including a laterally divided main source select - level electrode and a source - side isolation structure, the source - side isolation structure being hierarchically offset from a source - side end of a vertical semiconductor channel through an undivided bottom source select - level electrode. Various aspects of the three - dimensional semiconductor device and the method of manufacturing the same will be described below. Embodiments of the present disclosure can be used to form various structures including semiconductor devices, such as a three - dimensional memory array device including multiple memory strings.

[0049] The accompanying drawings are not drawn to scale. In the case of illustrating a single instance of an element, multiple instances of the element may be repeated unless otherwise explicitly described or clearly indicated that the element is not repeated. Ordinal numbers such as "first", "second", and "third" are only used to identify similar elements, and different ordinal numbers may be used in the description and claims of the present disclosure. The term "at least one" element refers to all possibilities, including the possibility of a single element and the possibility of multiple elements.

[0050] Like reference numerals denote like or similar elements. Unless otherwise indicated, elements with the same reference numeral are considered to have the same composition and the same function. Unless otherwise indicated, "contact" between elements refers to direct contact between elements that provides an edge or surface shared by the elements. If two or more elements do not directly contact each other or one another, the two elements are "separated" from each other or one another. As used herein, an element located "on" a second element may be located on the outer side of the surface of the second element or on the inner side of the second element. As used herein, an element "directly lies on" a second element if there is physical contact between the surface of the element and the surface of the second element. As used herein, an element is "electrically connected to" a second element if there is an electrical conduction path composed of at least one conductive material between the element and the second element. As used herein, a "prototype" structure or "in-process" structure refers to an instantaneous structure in which the shape or composition of at least one component is subsequently changed.

[0051] As used herein, a "layer" refers to a portion of material that includes a region having a thickness. The layer may extend over the entirety of an underlying or overlying layer structure, or may have a scope that is less than the scope of the underlying or overlying layer structure. Additionally, a layer may be a region of a uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces. The layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers on, above, and / or below it.

[0052] Generally speaking, a semiconductor die or a semiconductor package may include memory chips. Each semiconductor package contains one or more dies (e.g., one, two, or four). A die is the smallest unit capable of independently executing commands or reporting status. Each die contains one or more planes (usually one or two). The same concurrent operations may occur on each plane, but there will be some limitations. Each plane contains multiple blocks, which are the smallest units that can be erased in a single erase operation. Each block contains multiple pages, which are the smallest units that are programmable, i.e., the smallest units on which a read operation can be performed.

[0053] As used herein, "semiconductor material" refers to a material having a conductivity in the range of 1.0×10 -5 S / m to 1.0×10 5 S / m. As used herein, "semiconductor material" refers to a material having a conductivity in the range of 1.0×10 -5 S / m to 1.0 S / m in the absence of electrical dopants, and which, when appropriately doped with electrical dopants, is capable of producing a doped material having a conductivity in the range of 1.0 S / m to 1.0×10 7 S / m. As used herein, "electrical dopant" refers to a p-type dopant that adds holes to the valence band within the band structure or an n-type dopant that adds electrons to the conduction band within the band structure. As used herein, "conductive material" refers to a material having a conductivity greater than 1.0×10 5 S / m. As used herein, "insulating material" or "dielectric material" refers to a material having a conductivity less than 1.0×10 -5 S / m. As used herein, "heavily doped semiconductor material" refers to a semiconductor material doped with electrical dopants at a high enough atomic concentration to become a conductive material (formed as a crystalline material or in the case of being transformed into a crystalline material by an annealing process (e.g., from an initial amorphous state)), i.e., thus providing a conductivity greater than 1.0×10 5 S / m. A "doped semiconductor material" can be a heavily doped semiconductor material or can be a semiconductor material including electrical dopants (i.e., p-type dopants and / or n-type dopants), the concentration of which provides a conductivity in the range of 1.0×10 - 5 S / m to 1.0×10 7 S / m. An "intrinsic semiconductor material" refers to a semiconductor material that is not doped with electrical dopants. Thus, a semiconductor material can be semi-conductive or conductive and can be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material can be semi-conductive or conductive, depending on the atomic concentration of the electrical dopants therein. As used herein, "metal material" refers to a conductive material that includes at least one metal element. All conductivity measurements are made under standard conditions.

[0054] Reference Figure 1 illustrates an exemplary structure according to an embodiment of the present disclosure. The exemplary structure includes a carrier substrate 9, which can be a semiconductor substrate or a conductive substrate. For example, the carrier substrate 9 can include a commercially available silicon wafer. Alternatively, the carrier substrate 9 can include any material that can be selectively removed from the materials of the subsequently formed insulating layer 32 and dielectric material portion.

[0055] A first alternating stack {32, (42B, 42P)} of a first insulating layer 32 and a first sacrificial material layer (42B, 42P) may be formed over a carrier substrate 9. The first insulating layer 32 includes an insulating material such as undoped silicon glass (i.e., silicon oxide) or doped silicon glass, and the first sacrificial material layer (42B, 42P) includes a sacrificial material such as silicon nitride or silicon germanium. In one embodiment, the first insulating layer 32 may include a silicon oxide layer, and the first sacrificial material layer (42B, 42P) may include a silicon nitride layer. The first sacrificial material layer (42B, 42P) includes at least one bottom source select level sacrificial material layer 42B and at least one main source select level sacrificial material layer 42P from bottom to top. Although the illustrated embodiment of the first alternating stack {32, (42B, 42P)} includes two bottom source select level sacrificial material layers 42B and two main source select level sacrificial material layers 42P, alternative embodiments are expressly contemplated herein in which the total number of at least one bottom source select level sacrificial material layer 42B is a positive integer other than 2 (such as 1, 3, 4, 5, 6, etc.), and / or the total number of at least one main source select level sacrificial material layer 42P is another positive integer other than 2 (such as 1, 3, 4, 5, 6, etc.).

[0056] Each bottom source select level sacrificial material layer 42B is a sacrificial material layer that is subsequently replaced with a bottom source select level conductive layer (i.e., a bottom source side select gate electrode). Each bottom source select level conductive layer may be used to erase a block of a NAND string. Each main source select level sacrificial material layer 42P is a sacrificial material layer that is subsequently replaced with a main source select level conductive layer (i.e., a main source side select gate electrode). Each main source select level conductive layer may be used to erase a sub-block of a NAND string, which is a part of the NAND string block that is less than the whole of the NAND string block. Thus, during erasing of a sub-block of a NAND string, each bottom source select level conductive layer and each main source select level conductive layer controlling the sub-block are turned on (i.e., an erase voltage is applied to these select gate electrodes).

[0057] An exemplary structure may include a memory array region 100 in which NAND strings will subsequently be formed, and a contact region 300 in which contact via structures for word lines and various select gate electrodes will subsequently be formed. The bottommost insulating layer in the insulating layer 32 is hereinafter referred to as the bottommost insulating layer 32.

[0058] Reference Figures 2A to 2C, a photoresist layer (not shown) may be applied over the first alternating stack {32, (42B, 42P)}, and may be lithographically patterned to form slit-shaped openings extending laterally along a first horizontal direction (e.g., the word line direction) hd1. The center-to-center spacing between each pair of adjacent slit-shaped openings along a second horizontal direction (e.g., the bit line direction) hd2 perpendicular to the first horizontal direction hd1 may be the same as the width of a sub-block of a NAND string to be formed subsequently along the second horizontal direction hd2. An anisotropic etching process may be performed to transfer the pattern of the slit-shaped openings in the photoresist layer through each of the at least one main source select level sacrificial material layer 42P. The trenches formed through the at least one main source select level sacrificial material layer 42P are referred to herein as source select level isolation trenches. The source select level isolation trenches extend vertically through each of the at least one main source select level sacrificial material layer 42P, but do not extend vertically into any of the bottom source select level sacrificial material layers 42B.

[0059] Reference Figure 2C , each of the source select level isolation trenches may extend vertically from a first horizontal plane HP1 to a second horizontal plane HP2, the first horizontal plane including the topmost layer of the first alternating stack {32, (42B, 42P)}, the second horizontal plane including the bottom surface of the source select level isolation trench within the insulating layer 32, the insulating layer contacting the top surface of the topmost layer of at least one of the bottom source select level sacrificial material layers 42B. The width of each source select level isolation trench in the first horizontal plane HP1 along the second horizontal direction hd2 is referred to herein as a first width w1, and the width of each source select level isolation trench in the second horizontal plane HP2 along the second horizontal direction hd2 is referred to herein as a second width w2.

[0060] According to an optional aspect of the present disclosure, the first width w1 may be less than the maximum lateral dimension of each memory opening to be formed subsequently. For example, the first width w1 may be in the range of 10 nm to 200 nm (such as 20 nm to 100 nm), but smaller and larger dimensions may also be employed. According to an optional aspect of the present disclosure, each of the source select level isolation trenches may have tapered sidewalls extending along the first horizontal direction such that the first width w1 is greater than the second width w2.

[0061] A dielectric filling material (such as silicon oxide) can be deposited in the source select level isolation trench, for example, by a chemical vapor deposition process. The excess portion of the dielectric filling material deposited above the first horizontal plane HP1 can be removed by a planarization process, which can include a recess etching process or a chemical mechanical polishing process. Each remaining portion of the dielectric filling material in the corresponding source select level isolation trench retained in the source select level isolation trench constitutes a dielectric isolation structure, which is referred to herein as the source side dielectric isolation structure 120.

[0062] In one embodiment, the top surface of each source side dielectric isolation structure 120 can be located within the first horizontal plane HP1, which includes the top surface of the topmost insulating layer 32 of the first alternating stack {32, (42B, 42P)}. The bottom surface of each source side dielectric isolation structure 120 can be located within a second horizontal plane HP2 below the top surface of another insulating layer in the insulating layer 32, and this another insulating layer is interposed between at least one main source select level sacrificial material layer 42P and at least one bottom source select level sacrificial material layer 42B. In one embodiment, the top surface of each source side dielectric isolation structure 120 has a first width w1 along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. In one embodiment, the bottom surface of the source side dielectric isolation structure 120 has a second width w2 along the second horizontal direction hd2 that is less than the first width w1. Thus, in one embodiment, the source select level isolation structure 120 can have a tapered sidewall extending along the first horizontal direction such that the first width w1 is greater than the second width w2.

[0063] Generally speaking, each source select level isolation trench does not extend into any of the bottom source select level sacrificial material layers 42B. Thus, the source side dielectric isolation structure 120 is formed through each main source select level sacrificial material layer 42P in the main source select level sacrificial material layer 42P without removing any portion of the bottom source select level sacrificial material layer 42B. In one embodiment, the source side dielectric isolation structure 120 divides each main source select level sacrificial material layer 42P in the main source select level sacrificial material layer 42P into a plurality of portions that are laterally spaced apart from each other along the second horizontal direction hd2. For example, each source side dielectric isolation structure 120 divides each main source select level sacrificial material layer 42P into a corresponding pair of sacrificial material strips, which are referred to herein as the first sacrificial material strip 42S1 and the second sacrificial material strip 42S1, as Figure 2C shown. The first sacrificial material strip 42S1 is located in the first memory sub-block 104A of the memory block 102, and the second sacrificial material strip 42S1 is located in the second memory sub-block 104B of the same memory block 102.

[0064] The source select level isolation trench may have a relatively high aspect ratio. In other words, the ratio of the vertical distance between the first horizontal plane HP1 and the second horizontal plane HP2 to the first width w1 may be a relatively large number, such as a number in the range of 3 to 10. Due to the high aspect ratio, the dielectric fill material deposited in the source select level isolation trench may have a laterally extending void (i.e., air gap) extending along the first horizontal direction hd1. The laterally extending void is referred to herein as the via 13. The portion of the dielectric fill material surrounding the via 13 extends laterally along the first horizontal direction hd1 with a uniform vertical cross-sectional profile and is referred to herein as the dielectric material rail 12R. Thus, each source-side dielectric isolation structure 120 may include a combination of the dielectric material rail 12R and the via 13, which is a cavity completely surrounded by the dielectric material rail 12R. The via 13 also extends laterally in the first horizontal direction hd1 between two memory sub-blocks (104A, 104B) of the same memory block 102. Alternatively, the via 13 may be omitted in some or all of the source-side dielectric isolation structures 120.

[0065] Reference Figure 3A and Figure 3B , a second alternating stack {32, (42W, 42D)} of the second insulating layer 32 and the second sacrificial material layer (42B, 42D) may be formed over the first alternating stack {32, (42B, 42P)} and the source-side dielectric isolation structure 120. The second insulating layer 32 includes an insulating material such as undoped silicon glass or doped silicon glass, and the second sacrificial material layer (42W, 42D) includes a sacrificial material such as silicon nitride or silicon germanium alloy. In one embodiment, the second insulating layer 32 may include a silicon oxide layer, and the second sacrificial material layer (42W, 42D) may include a silicon nitride layer. In one embodiment, the second insulating layer 32 may include the same material as the first insulating layer 32, and the second sacrificial material layer (42W, 42D) may include the same material as the first sacrificial material layer (42B, 42P). The second sacrificial material layer (42W, 42D) includes a word line level sacrificial material layer 42W and at least one drain select level sacrificial material layer 42D from bottom to top.

[0066] The total number of word - line - level sacrificial material layers 42W within the second alternating stack {32, (42W, 42D)} can be (for example) in the range of 8 to 1,024 (such as 32 to 256), but fewer or greater numbers of repetitions can be employed. The top - most layer of the insulating layer 32 is hereinafter referred to as the top - most insulating layer 32T. Although an embodiment is illustrated in which there is only a single drain - select - level sacrificial material layer 42D, alternative embodiments employing multiple drain - select - level sacrificial material layers 42D are expressly contemplated herein. At least one bottom - source - select - level sacrificial material layer 42B, at least one main - source - select - level sacrificial material layer 42P, word - line - level sacrificial material layers 42W, and at least one drain - select - level sacrificial material layer 42D are collectively referred to as sacrificial material layers 42. The combination of the first alternating stack {32, (42B, 42P)} and the second alternating stack {32, (42W, 42D)} is hereinafter referred to as the alternating stack (32, 42) of the insulating layer 32 and the sacrificial material layer 42.

[0067] Reference Figure 4 , an optional stepped surface is formed in the contact region 300. As used herein, a "stepped surface" refers to a set of surfaces that includes at least two horizontal surfaces and at least two vertical surfaces such that each horizontal surface is adjacent to a first vertical surface extending upward from a first edge of the horizontal surface and is adjacent to a second vertical surface extending downward from a second edge of the horizontal surface. A stepped cavity is formed in the space from which a portion of the alternating stack (32, 42) is removed by forming the stepped surface. A "stepped cavity" refers to a cavity having a stepped surface.

[0068] The stepped cavity can have different stepped surfaces such that the horizontal cross - sectional shape of the stepped cavity varies step - wise with the vertical distance from the top surface of the carrier substrate 9. In one embodiment, the stepped cavity can be formed by repeatedly performing a set of processing steps. The set of processing steps can include, for example, a first type of etching process that vertically increases the depth of the cavity by one or more levels and a second type of etching process that laterally expands the region that will be vertically etched in subsequent etching processes of the first type. As used herein, a "layer level" of a structure including alternating multiple layers is defined as the relative position of a pair of a first material layer and a second material layer within the structure.

[0069] Each sacrificial material layer 42 within the alternating stack (32, 42) other than the top - most sacrificial material layer 42 extends further laterally than any overlying sacrificial material layer 42 within the alternating stack (32, 42) in the platform region. The stepped surface of the alternating stack (32, 42) extends continuously from the bottom - most layer (such as the bottom - most insulating layer 32B) within the alternating stack (32, 42) to the top - most layer (such as the top - most insulating layer 32T) within the alternating stack (32, 42).

[0070] The stepped dielectric material portion 65 (i.e., the insulating fill material portion) can be formed in the stepped cavity by depositing a dielectric material in the stepped cavity. For example, a dielectric material such as silicon oxide can be deposited in the stepped cavity. The excess portion of the deposited dielectric material can be removed from above the top surface of the topmost insulating layer 32T, for example, by chemical mechanical planarization (CMP). The remaining portion of the deposited dielectric material that fills the stepped cavity constitutes the stepped dielectric material portion 65. As used herein, a "stepped" element refers to an element having a stepped surface and a horizontal cross-sectional area that gradually increases or decreases with the vertical distance from the top surface of the substrate on which the element is located. If silicon oxide is used for the stepped dielectric material portion 65, the silicon oxide of the stepped dielectric material portion 65 can optionally be doped with dopants (such as B, P, and / or F).

[0071] Reference Figure 5A and Figure 5B optionally, a first etch mask layer (such as a photoresist layer) can be formed over the alternating stack (32, 42) and can be lithographically patterned to form an opening in the contact region 300. An optional anisotropic etch process can be performed to transfer the pattern of the opening in the first etch mask layer through the stepped dielectric material portion 65 and the alternating stack (32, 42). Support openings 19 can be formed through the stepped dielectric material portion 65 and the alternating stack (32, 42) in the contact region 300. Each of the support openings 19 can extend vertically into the carrier substrate 9. In one embodiment, the bottom surface of the support opening 19 can be formed at or below the top surface of the carrier substrate 9. The support openings 19 can have a diameter in the range of 20 nm to 400 nm (such as 50 nm to 300 nm), but smaller and larger thicknesses can be employed.

[0072] Reference Figure 6 optionally, a dielectric fill material (such as silicon oxide) can be deposited in the support openings 19 by a conformal deposition process. The excess dielectric fill material can be removed from above the top surface of the topmost insulating layer 32T, for example, by a recess etching process. Each portion of the dielectric fill material that fills the corresponding support opening 19 constitutes a support pillar structure 20, which can be used to provide structural support to the insulating layer 32 and the stepped dielectric material portion 65 during the replacement of the sacrificial material layer 42 with a conductive layer.

[0073] Reference Figures 7A to 7D, a second etch mask layer (such as a photoresist layer) may be formed over the alternating stack (32, 42) and may be lithographically patterned to form openings in the memory array region 100. An anisotropic etch process may be performed to transfer the pattern of the openings in the second etch mask layer through the alternating stack (32, 42). Memory openings 49 may be formed through the alternating stack (32, 42) in the memory array region 100. Each of the memory openings 49 in the memory openings 49 may extend vertically into the carrier substrate 9. In one embodiment, the bottom surface of the memory openings 49 may be formed at or below the top surface of the carrier substrate 9. Each cluster of the memory openings 49 in the corresponding memory sub-blocks (104A, 104B) may include multiple rows of memory openings 49. Each row of the memory openings 49 may include a plurality of memory openings 49 arranged at a uniform pitch along a first horizontal direction hd1. The rows of the memory openings 49 may be laterally spaced from each other along a second horizontal direction hd2, which may be perpendicular to the first horizontal direction hd2. In one embodiment, each cluster of the memory openings 49 may be formed as a two-dimensional periodic array of the memory openings 49. The memory openings 49 may have a diameter in the range of 60 nm to 400 nm (such as 120 nm to 300 nm), but smaller and larger thicknesses may be employed.

[0074] According to one aspect of the present disclosure, each cluster of the memory openings 49 includes multiple rows of first memory openings 49F, multiple rows of second memory openings 49S, and one row of third memory openings 49T. The first memory openings 49F are located in the first memory sub-block 104A, vertically extend through at least one first sacrificial material strip 42S1 of at least one main source select level conductive layer 42P, and are laterally spaced from each second sacrificial material strip 42S2 of at least one main source select level conductive layer 42P located in the second memory sub-block 104B. The second memory openings 49S are located in the second memory sub-block 104B, vertically extend through at least one second sacrificial material strip 42S2 of at least one main source select level conductive layer 42P, and are laterally spaced from each first sacrificial material strip 42S1 of at least one main source select level conductive layer 42P located in the first memory sub-block 104A. The row of third memory openings 49T is arranged along the first horizontal direction hd1 and divides the source-side dielectric isolation structure 120 into a plurality of dielectric material blocks 12. In other words, the third memory openings 49T extend through the source-side dielectric isolation structure 120 between two memory sub-blocks (104A, 104B) of the same memory block 102.

[0075] Thus, each dielectric material track 12R can be divided into a corresponding row of dielectric material blocks 12 by a corresponding row of third memory openings 49T. In one embodiment, a plurality of dielectric material blocks 12 surround corresponding vias 13 that extend laterally along a first horizontal direction hd1. Each via 13 in the vias 13 can be connected to at least one memory opening 49. At least one third memory opening 49T in the third memory openings 49T within each row of third memory openings 49T can be laterally defined by a pair of dielectric material blocks 12 and / or can be connected to a pair of vias 13. The dielectric material blocks 12 within each row can be laterally spaced apart from each other along the first horizontal direction hd1 and can be staggered with a row of third memory openings 49T along the first horizontal direction hd1. A row of third memory openings 49T can be interconnected by a row of staggered vias 13 (if present).

[0076] Figures 8A to 8F is a sequential vertical cross - sectional view of the memory openings 49 during the formation of the memory opening filling structure 58 according to an embodiment of the present disclosure.

[0077] Reference Figure 8A , a sacrificial base structure 11 can be formed at the bottom of each of the memory openings 49. In an embodiment where the carrier substrate 9 includes a semiconductor material (such as single - crystal silicon), the sacrificial base structure 11 can include a semiconductor material (such as single - crystal silicon or poly - silicon) and can be formed by selectively growing a semiconductor material from a physically exposed surface of the carrier substrate 9. A selective semiconductor deposition process (such as selective epitaxial process) can be employed to form the sacrificial base structure 11.

[0078] Reference Figure 8B , a layer stack including a memory material layer 54 can be conformally deposited. In an illustrative example, the layer stack can include an optional barrier dielectric layer 52, a memory material layer 54, an optional dielectric liner 56, and an optional sacrificial capping layer (not illustrated). The memory material layer 54 includes a memory material, i.e., a material in which data bits can be stored. The memory material layer 54 can include a charge storage material (such as silicon nitride), a ferroelectric material, a phase - change memory material, or any other memory material that can store data bits by inducing a change in resistivity, ferroelectric polarization, or any other measurable physical property. In the case where the memory material layer 54 includes a charge storage material, the optional dielectric liner 56 can include a tunneling dielectric layer. The sacrificial capping layer (if present) includes a material that can protect the dielectric liner 56 or the memory material layer 54 during subsequent anisotropic etching processes. The sacrificial capping layer includes a sacrificial capping material, such as amorphous silicon, poly - silicon, or a carbon - based material (such as amorphous carbon or diamond - like carbon).

[0079] According to one aspect of the present disclosure, a portion of the layer stack (52, 54, 56) may be deposited in the lateral through-hole 13 that is connected to the third memory opening 49T (i.e., a subset of the memory openings 49 that is in direct contact with the dielectric material block 12 of the source-side dielectric isolation structure 120). The lateral through-hole 13 (if present) may optionally be at least partially filled with a portion of the layer stack (52, 54, 56).

[0080] Reference Figure 8C , a semiconductor channel material layer 60L may be deposited over each memory film 50 by performing a conformal deposition process. If the semiconductor channel material layer 60L is doped, the semiconductor channel material layer 60L may have a doping of a first conductivity type, which may be p-type or n-type.

[0081] Reference Figure 8D , a dielectric core layer 62L including a dielectric filling material may be deposited in the reserved space of the memory opening 49. The dielectric core layer 62L may include any insulating material, such as silicon oxide.

[0082] Reference Figure 8E , the dielectric core layer 62L may be vertically recessed such that each remaining portion of the dielectric core layer has a top surface that is at or near the horizontal plane of the bottom surface of the topmost insulating layer 32. Each remaining portion of the dielectric core layer 62L constitutes the dielectric core 62.

[0083] Reference Figure 8F , a semiconductor material doped with a doping of a second conductivity type may be deposited in each recessed region above the dielectric core 62. The second conductivity type is opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The dopant concentration in the deposited semiconductor material may be in the range of 5.0×10 18 / cm 3 to 2.0×10 21 / cm 3 , but smaller or larger dopant concentrations may also be employed. The doped semiconductor material may be, for example, doped polysilicon.

[0084] The excess portion of the deposited semiconductor material doped with the second conductivity type and the horizontal portion of the semiconductor channel layer 60L may be removed from above the horizontal plane of the top surface of the topmost insulating layer 32T, for example, by chemical mechanical planarization (CMP) or a trench etching process. Each remaining portion of the semiconductor material doped with the second conductivity type constitutes the drain region 63. Each remaining portion of the semiconductor channel layer 60L (which has a doping of the first conductivity type) constitutes the vertical semiconductor channel 60.

[0085] Each portion of the layer stack including the memory material layer 54 constitutes a memory film 50, and the memory material layer is retained in the corresponding memory opening 49. In one embodiment, the memory film 50 may include an optional barrier dielectric layer 52, a memory material layer 54, and an optional dielectric liner 56. Each adjacent combination of the memory film 50 and the vertical semiconductor channel 60 constitutes a memory stack structure 55. Each combination of the sacrificial pedestal structure 11 (if present) within the memory opening 49, the memory stack structure 55, the dielectric core 62, and the drain region 63 constitutes a memory opening fill structure 58. Each memory opening fill structure 58 includes a corresponding vertical stack of memory elements, and the corresponding vertical stack may include a portion of the memory material layer 54 located at the level of the sacrificial material layer 42 (or generally, at the level of the spacer material layer, which may be formed as a conductive layer or may be subsequently at least partially replaced with a conductive layer).

[0086] Reference Figures 9A to 9D , illustrates an exemplary structure after forming the memory opening fill structure 58 within the memory opening 49. The memory opening fill structure 58 is located in the memory opening 49. Each memory opening fill structure within the memory opening fill structure 58 includes a corresponding memory film 50 and a corresponding vertical semiconductor channel 60.

[0087] According to one aspect of the present disclosure, each cluster of the memory opening fill structures 58 includes multiple rows of first memory opening fill structures 58F, multiple rows of second memory opening fill structures 58S, and one row of third memory opening fill structures 58T. The first memory opening fill structures 58F are located in the first memory sub-block 104A, vertically extend through at least one first sacrificial material strip 42S1 of at least one main source selection level conductive layer 42P, and are laterally spaced apart from each second sacrificial material strip 42S2 of at least one main source selection level conductive layer 42P located on the second memory sub-block 104B. The second memory opening fill structures 58S are located in the second memory sub-block 104B, vertically extend through at least one second sacrificial material strip 42S2 of at least one main source selection level conductive layer 42P, and are laterally spaced apart from each first sacrificial material strip 42S1 of at least one main source selection level conductive layer 42P located in the first memory sub-block 104A. The row of third memory opening fill structures 58T is arranged along the first horizontal direction hd1 and divides the source-side dielectric isolation structure 120 into multiple dielectric material blocks 12. In other words, the row of third memory opening fill structures 58T is located between two memory sub-blocks (104A, 104B) of the same memory block 102.

[0088] In one embodiment, the third memory opening filling structure 58T may include a virtual memory opening filling structure in which the memory film 50 is not used for storing data (e.g., not used for storing electrons). In this case, the drain region 63 and the vertical semiconductor channel 60 of the third memory opening filling structure 58T will not be electrically connected to any of the subsequently formed bit lines. Instead, the drain regions 63 and the vertical semiconductor channels 60 of the first and second memory opening filling structures (58F, 58S) will be electrically connected to a respective one of the subsequently formed bit lines.

[0089] In one embodiment, each source-side dielectric isolation structure 120 includes a plurality of dielectric material blocks 12 that are laterally spaced apart from each other along a first horizontal direction hd1 and are staggered with a row of memory opening filling structures 58 along the first horizontal direction hd1. Each dielectric material block 12 within each source select level isolation structure 120 may surround a respective optional lateral through hole 13 that extends laterally along the first horizontal direction hd1. In one embodiment, each lateral through hole 13 may be filled with a respective dielectric hole filling structure 14 that includes at least one dielectric material having the same material composition as a constituent layer within the memory film 50 during the formation of the memory film 50.

[0090] In the illustrated example, each dielectric hole filling structure 14 includes an optional first dielectric material portion, a second dielectric material portion, and an optional third dielectric material portion. The optional first dielectric material portion has the same material composition as the optional barrier dielectric layer 52, the second dielectric material portion has the same material composition as the memory material layer 54, and the optional third dielectric material portion has the same material composition as the optional dielectric liner 56 (such as a tunneling dielectric layer). In one embodiment, each memory film in the memory film 50 includes a respective barrier dielectric layer 52 and a respective vertical stack of memory elements laterally surrounded by the respective barrier dielectric layer 52, and each dielectric hole filling structure 14 of each dielectric material block 12 includes a dielectric filling material layer that is an extension of one of the barrier dielectric layers 52 into the respective lateral through hole 13 in the lateral through hole 13.

[0091] Reference Figures 10A to 10C, a photoresist layer (not shown) may be applied over the topmost insulating layer 32T and may be lithographically patterned to form slit-shaped openings extending laterally along a first horizontal direction hd1. The pattern of the openings through the photoresist layer may be the same as the pattern of the source select level isolation structure 120. An anisotropic etching process may be performed to transfer the pattern of the slit-shaped openings in the photoresist layer through each of the drain select level sacrificial material layers in the at least one drain select level sacrificial material layer 42D. The trenches formed through the at least one drain select level sacrificial material layer 42D are referred to herein as drain select level isolation trenches. The drain select level isolation trenches extend vertically through each of the drain select level sacrificial material layers in the at least one drain select level sacrificial material layer, but do not extend vertically into any of the word line level sacrificial material layers in the word line level sacrificial material layer 42W.

[0092] A dielectric filling material such as silicon oxide may be deposited in the drain select level isolation trenches, for example, by a chemical vapor deposition process. The excess dielectric filling material deposited above the horizontal plane including the top surface of the topmost insulating layer 32T may be removed by a planarization process, which may include a recess etching process or a chemical mechanical polishing process. Each remaining portion of the dielectric filling material retained in the corresponding drain select level isolation trench constitutes a dielectric isolation structure, which is referred to herein as a drain side dielectric isolation structure 72.

[0093] In one embodiment, the top surface of each drain side dielectric isolation structure 72 may be located within a horizontal plane HP1 that includes the top surface of the topmost insulating layer 32T. In one embodiment, the drain side dielectric isolation structures 72 divide each of the drain select level sacrificial material layers in the at least one drain select level sacrificial material layer 42D into a plurality of portions that are laterally spaced apart from each other along a second horizontal direction hd2. For example, each drain side dielectric isolation structure 72 divides each drain select level sacrificial material layer 42D into a corresponding pair of sacrificial material strips (42DS1, 42DS2), which are referred to herein as a third sacrificial material strip and a fourth sacrificial material strip, and the third sacrificial material strip and the fourth sacrificial material strip are located in the corresponding first memory sub-block and second memory sub-block (104A, 104B) of the same memory block 102.

[0094] The drain select level isolation trenches may have a relatively high aspect ratio. In other words, the ratio of the depth of the drain select level isolation trenches to the width of each drain select level isolation trench may be a relatively large number, such as a number in the range of 3 to 10. Due to the high aspect ratio, the dielectric fill material deposited in the drain select level isolation trenches may optionally have laterally extending voids extending along the first horizontal direction hd1. The laterally extending voids are referred to herein as drain select level vias 73. Alternatively, the drain select level vias 73 may be omitted.

[0095] In one embodiment, each drain side dielectric isolation structure 72 may be cut to a corresponding row of third memory opening fill structures 58T and may contact a corresponding row of dielectric cores 62 within the corresponding row of third memory opening fill structures 58T. In this embodiment, the third memory opening fill structures include virtual memory opening fill structures.

[0096] Reference Figure 11A and Figure 11B , a dielectric material (such as undoped silicon glass or doped silicon glass) may be deposited over the alternating stack (32, 42) to form a contact level dielectric layer 80. The thickness of the contact level dielectric layer 80 may be in the range of 100 nm to 600 nm (such as 200 nm to 400 nm), but smaller and larger thicknesses may also be employed.

[0097] A photoresist layer (not shown) may be applied over the contact level dielectric layer 80 and may be lithographically patterned to form elongated openings that extend laterally in the first horizontal direction hd1 between adjacent clusters of memory opening fill structures 58. An anisotropic etching process may be performed to transfer the pattern of the openings in the photoresist layer through the contact level dielectric layer 80, the alternating stack (32, 42), and the stepped dielectric material portion 65 and at least reach the top surface of the carrier substrate 9. Lateral isolation trenches 79 that extend laterally in the first horizontal direction hd1 may be formed through the alternating stack (32, 42), the stepped dielectric material portion 65, and the contact level dielectric layer 80. Each of the lateral isolation trenches 79 in the lateral isolation trenches 79 may include a corresponding pair of longitudinal sidewalls that are parallel to the first horizontal direction hd1 and extend perpendicularly from the carrier substrate 9 to the top surface of the contact level dielectric layer 80. The surface of the carrier substrate 9 may be physically exposed under each of the lateral isolation trenches 79. Subsequently, the photoresist layer may be removed, for example, by ashing.

[0098] Generally speaking, a pair of lateral isolation trenches 79 extend through each layer within an alternating stack (32, 42) (i.e., a combination of the second alternating stack {32, (42W, 42D)} and the first alternating stack {32, (42B, 42P)}) around each cluster of the memory opening filling structure 58. Each of the pair of lateral isolation trenches 79 extends laterally along a first horizontal direction hd1. The source-side dielectric isolation structure 120 and the drain-side dielectric isolation structure 72 are located between the pair of lateral isolation trenches 79. The pair of lateral isolation trenches 79 includes lateral boundaries along the first horizontal direction hd1 of the corresponding memory block 102.

[0099] Reference Figure 12 , for example, an isotropic etching process can be used to introduce an etchant into the access trench 79, and the etchant selectively etches the material of the sacrificial material layer 42 with respect to the material of the insulating layer 32. A lateral groove 43 is formed in the space where the sacrificial material layer 42 is removed. The sacrificial material layer 42 is selectively removed with respect to the material of the insulating layer 32, the stepped dielectric material portion 65, the semiconductor material of the substrate 9, and the outermost layer material of the memory film 50. In one embodiment, the sacrificial material layer 42 may include silicon nitride, and the materials of the insulating layer 32 and the stepped dielectric material portion 65 may be selected silicon oxides.

[0100] The etching process for selectively removing the second material with respect to the first material and the outermost layer of the memory film 50 can be a wet etching process using a wet etching solution, or can be a gas-phase (dry) etching process in which the etchant is introduced into the access trench 79 in a gas phase. For example, if the sacrificial material layer 42 includes silicon nitride, the etching process can be a wet etching process in which an exemplary structure is immersed in a wet etching bath including phosphoric acid, and this wet etching process selectively etches silicon nitride with respect to silicon oxide, silicon, and various other materials used in the present technology. The support pillar structure 20, the stepped dielectric material portion 65, and the memory opening filling structure 58 provide structural support while the lateral groove 43 exists in the space previously occupied by the sacrificial material layer 42.

[0101] Each lateral groove 43 can be a laterally extending cavity, and the lateral dimension of the laterally extending cavity is greater than the vertical extent of the cavity. In other words, the lateral dimension of each lateral groove 43 can be greater than the height of the lateral groove 43. In the space where the second material of the sacrificial material layer 42 is removed, a plurality of lateral grooves 43 can be formed. Compared with the lateral grooves 43, the memory opening 49 forming the memory stack structure 55 is referred to herein as a front-side opening or a front-side cavity. Each of the plurality of lateral grooves 43 can extend substantially parallel to the top surface of the substrate 9. The lateral grooves 43 can be vertically defined by the top surface of the underlying insulating layer 32 and the bottom surface of the overlying insulating layer 32. In one embodiment, each lateral groove 43 can always have a consistent height.

[0102] Reference Figures 13A to 13D Optionally, an outer barrier dielectric layer 44 may be formed. The outer barrier dielectric layer 44 (if present) includes a dielectric material that serves as a control gate dielectric for a control gate to be subsequently formed in the lateral groove 43. The outer barrier dielectric layer 44 is optional when the barrier dielectric layer 52 is present in each memory opening. When the barrier dielectric layer 52 is omitted, the outer barrier dielectric layer 44 is present.

[0103] At least one conductive material may be deposited in the lateral groove 43 by providing at least one reactive gas into the lateral groove 43 through the access trench 79. A metal barrier layer may be deposited in the lateral groove 43. The metal barrier layer includes a conductive metal material that can serve as a diffusion barrier layer and / or an adhesion promoting layer for a metal fill material to be subsequently deposited. The metal barrier layer may include a conductive metal nitride material (such as TiN, TaN, WN, or a stack thereof), or may include a conductive metal carbide material (such as TiC, TaC, WC, or a stack thereof). In one embodiment, the metal barrier layer may be deposited by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the metal barrier layer may be in the range of 2 nm to 8 nm (such as 3 nm to 6 nm), but smaller and larger thicknesses may also be employed. In one embodiment, the metal barrier layer may consist essentially of a conductive metal nitride (such as TiN).

[0104] A metal fill material is deposited in the plurality of lateral grooves 43, on the sidewalls of at least one access trench 79, and above the top surface of the contact-level dielectric layer 80 to form a metal fill material layer. The metal fill material may be deposited by a conformal deposition method, which may be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. In one embodiment, the metal fill material layer may consist essentially of at least one elemental metal. The at least one elemental metal of the metal fill material layer may be selected from, for example, tungsten, cobalt, ruthenium, titanium, and tantalum. In one embodiment, the metal fill material layer may consist essentially of a single elemental metal. In one embodiment, a fluorine-containing precursor gas (such as WF6) may be employed to deposit the metal fill material layer. In one embodiment, the metal fill material layer may be a tungsten layer that includes fluorine atoms at a residual level as an impurity. The metal fill material layer is spaced apart from the insulating layer 32 and the memory stack structure 55 by the metal barrier layer that blocks the diffusion of fluorine atoms therethrough.

[0105] A plurality of conductive layers 46 may be formed in the plurality of lateral grooves 43, and a continuous metal material layer may be formed on the sidewalls of each access trench 79 and above the contact-level dielectric layer 80. Each conductive layer 46 includes a portion of a metal barrier layer and a portion of a metal fill material layer, and the portion of the metal barrier layer and the portion of the metal fill material layer are located between a pair of vertically adjacent dielectric material layers (such as a pair of insulating layers 32). The continuous metal material layer includes a continuous portion of the metal barrier layer and a continuous portion of the metal fill material layer, and the continuous portion of the metal barrier layer and the continuous portion of the metal fill material layer are located in the access trench 79 or above the contact-level dielectric layer 80.

[0106] By performing an isotropic etching process, the deposited metal material of the continuous conductive material layer is etched back from the sidewalls of each access trench 79 and from above the contact-level dielectric layer 80, and the isotropic etching process etches the at least one conductive material of the continuous conductive material layer. Each remaining portion of the deposited metal material in the lateral groove 43 constitutes a conductive layer 46. Each conductive layer 46 may be a wire structure. Thus, the sacrificial material layer 42 is replaced by the conductive layer 46. Generally, the conductive layer 46 may be formed by supplying a metal precursor gas into the lateral isolation trench 79 and the lateral groove 43.

[0107] Generally, the remaining portions of the sacrificial material layer 42 may be replaced by the conductive layer 46. A layer stack (32, 46, 80) is formed, and the layer stack extends laterally in a first horizontal direction hd1 and is laterally spaced from each other through the access trench 79 in a second horizontal direction hd2. Each layer stack in the layer stack (32, 42, 80) includes a corresponding alternating stack (32, 46) of a corresponding insulating layer 32 and a corresponding conductive layer 46, and also includes a corresponding contact-level dielectric layer 80 covering the corresponding alternating stack (32, 46). In one embodiment, each alternating stack in the alternating stack (32, 46) includes a corresponding pair of longitudinal sidewalls, and in the corresponding pair of longitudinal sidewalls, a plurality of vertically straight surface segments and laterally recessed surface segments are adjacent to each other in the first horizontal direction hd1.

[0108] The conductive layer 46 includes a bottom source selection stage conductive layer (i.e., the bottom source side select gate electrode 46B that replaces the bottom source selection stage sacrificial material layer 42B), a main source selection stage conductive layer (i.e., the main source side select gate electrode) 46P that replaces the main source selection stage sacrificial material layer 42P, a word line 46W (also referred to as the word line stage conductive layer 46W) that replaces the word line stage sacrificial material layer 42W, and a drain selection stage conductive layer (i.e., the drain side select gate electrode) 46D that replaces the drain selection stage sacrificial material layer 42D. The main source selection stage conductive layer (i.e., the main source side select gate electrode) 46P is located between the word line 46W and the bottom source selection stage conductive layer (i.e., the bottom source side select gate electrode 46B) in a vertical direction perpendicular to the top surface of the substrate 9.

[0109] Each alternating stack of the insulating layer 32 and the conductive layer 46 formed between a pair of adjacent lateral isolation trenches 79 includes at least one main source selection stage conductive layer 46P, and the at least one main source selection stage conductive layer may include a single main source selection stage conductive layer 46P or multiple main source selection stage conductive layers 46P, and the multiple main source selection stage conductive layers are formed at multiple source selection stages and are vertically spaced apart from each other. In one embodiment, each main source selection stage conductive layer 46P includes a first conductive strip and a second conductive strip 46S2 located in the second memory sub-block 104B, and the first conductive strip replaces the first sacrificial material strip 46S1 located in the first memory sub-block 104A. Each main source selection stage conductive layer 46P includes a combination of a corresponding first conductive strip 46S1 and a corresponding second conductive strip 46S2, and the first conductive strip and the second conductive strip are laterally spaced apart from each other in a second horizontal direction hd2 by a source side dielectric isolation structure 120.

[0110] Reference Figure 14A and Figure 14B , a dielectric filling material (such as silicon oxide) can be deposited in the lateral isolation trenches 79. The excess portion of the dielectric filling material can be removed above the contact stage dielectric layer 80. Each remaining portion of the dielectric filling material constitutes a lateral isolation trench filling structure 76, and the dielectric filling material fills the corresponding lateral isolation trench in the lateral isolation trenches 79, and the lateral isolation trench filling structure can be a dielectric wall structure. In an alternative embodiment, an insulating spacer having a tubular configuration can be formed in the peripheral portion of each lateral isolation trench in the lateral isolation trenches 79, and a through-stack conductive via structure can be formed within the corresponding insulating spacer among the insulating spacers. In this case, each lateral isolation trench filling structure 76 can include a combination of the through-stack conductive via structure and the insulating spacer, and the insulating spacer laterally surrounds the through-stack conductive via structure. A pair of adjacent lateral isolation trench filling structures 76 are on the sidewalls of the corresponding memory block 102. Each lateral isolation trench filling structure 76 laterally separates adjacent memory blocks 102.

[0111] Contact vias structures (88, 86) can be formed through the contact-level dielectric layer 80 and optionally through the stepped dielectric material portion 65. For example, a drain contact via structure 88 can be formed through the contact-level dielectric layer 80 over each drain region 63. A layer contact via structure 86 can be formed through the contact-level dielectric layer 80 and through the stepped dielectric material portion 65 over the conductive layer 46.

[0112] According to one aspect of the present disclosure, an alternating stack (32, 42) of insulating layers 32 and conductive layers 46 arranged in a vertical direction can be formed between a pair of adjacent laterally isolated trench fill structures 76 extending laterally along a first horizontal direction hd1. The conductive layer 46 includes, from bottom to top, at least one bottom source select level conductive layer 46B, at least one main source select level conductive layer 46P, a word line 46W, and at least one drain select level conductive layer 46D. Each bottom source select level conductive layer 46P can include a corresponding first single continuous structure that extends along a second horizontal direction hd2 through the entire memory block 102 and contacts each of the pair of adjacent laterally isolated trench fill structures 76. Each main source select level conductive layer in the at least one main source select level conductive layer 46P can include a corresponding pair of first conductive bars 46S1 (only located in the first memory sub-block 104A) and second conductive bars 46S2 (only located in the second memory sub-block 104B), the first conductive bar and the second conductive bar being laterally spaced apart from each other and contacting one of the pair of adjacent laterally isolated trench fill structures 76 but not the other. The word line 42W can include a corresponding second single continuous structure that extends laterally along the second horizontal direction hd2 through the entire memory block 102 and contacts each of the pair of adjacent laterally isolated trench fill structures 76.

[0113] In one embodiment, the first conductive bars 46S1 and the second conductive bars 46S2 within each main source select level conductive layer in the at least one main source select level conductive layer 46P are laterally spaced apart from the source-side dielectric isolation structure 120 by corresponding outer barrier dielectric layers 44. In one embodiment, the at least one bottom source select level conductive layer 46B and the word line 46W are spaced apart from each memory opening fill structure in the memory opening fill structure 58 by additional outer barrier dielectric layers 44 having the same material composition and the same thickness as the corresponding outer barrier dielectric layers 44.

[0114] In one embodiment, a top surface of the source - side dielectric isolation structure 120 has a first width w1 along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1, and a bottom surface of the source - side dielectric isolation structure 120 has a second width w2 along the second horizontal direction hd2 that is less than the first width w1. In one embodiment, the top surface of the source - side dielectric isolation structure 120 lies within a first horizontal plane HP1 that includes a top surface of one of the insulating layers 32 that is interposed between the word line 46W and at least one main source - select - level conductive layer 46P; and the bottom surface of the source - side dielectric isolation structure 120 lies within a second horizontal plane HP2 that is below a top surface of another one of the insulating layers 32 that is interposed between at least one main source - select - level conductive layer 46P and at least one bottom source - select - level conductive layer 46B.

[0115] In one embodiment, the conductive layer 46 further includes at least one drain - select - level conductive layer 46D located above the word line 46W. Each drain - select - level conductive layer in the at least one drain - select - level conductive layer 46D includes a respective pair of third conductive bars 46D1 (located in the first memory sub - block 104A) and fourth conductive bars 46D2 (located in the second memory sub - block 104B), and the third conductive bar and the fourth conductive bar are laterally spaced apart from each other along the second horizontal direction hd2 by a drain - side dielectric isolation structure 72. For each drain - select - level conductive layer in the at least one drain - select - level conductive layer 46D, the drain - side dielectric isolation structure 72 can be located between the respective pair of third conductive bars 46D1 and fourth conductive bars 46D2.

[0116] Reference Figure 15 , an additional dielectric material layer and an additional metal interconnect structure can be formed above the contact - level dielectric layer 80. The additional dielectric material layer can include at least one via - level dielectric layer, at least one additional line - level dielectric layer, and / or at least one additional line - and - via - level dielectric layer. The additional metal interconnect structure can include a metal via structure, a metal line structure, and / or an integrated metal line - and - via structure. The additional dielectric material layer formed above the contact - level dielectric layer 80 is referred to herein as the memory - side dielectric material layer 960. The additional metal interconnect structure is collectively referred to as the memory - side metal interconnect structure 980. The memory - side dielectric material layer 960 includes a bit - line - level dielectric material layer that embeds bit lines, which are a subset of the memory - side metal interconnect structure 980.

[0117] A metal bonding pad (which is referred to herein as the upper bonding pad 988) can be formed at the topmost layer of the memory - side dielectric material layer 960. The upper bonding pad 988 can be electrically connected to the memory - side metal interconnect structure 980 and to respective nodes of the three - dimensional memory array that includes an alternating stack of the insulating layers 32 and the conductive layer 46 and the memory - opening fill structure 58.

[0118] Thus, a memory die 900 is formed that includes a memory-side dielectric material layer 960 formed over an alternating stack (32, 46), a memory-side metal interconnect structure 980 embedded within the memory-side dielectric material layer 960, and a memory-side bonding pad 988 embedded within the topmost layer of the memory-side dielectric material layer 960. The memory-side bonding pad 988 can be electrically connected to the memory-side metal interconnect structure 980.

[0119] Reference Figure 16 , a logic die 700 can be provided. The logic die 700 includes a logic-side substrate 709, a peripheral circuit 720, a logic-side metal interconnect structure 780, and a logic-side bonding pad 778. The peripheral circuit is located on the logic-side substrate 709 and includes logic-side semiconductor devices (such as field effect transistors). The logic-side metal interconnect structure is embedded within a logic-side dielectric material layer 760. The peripheral circuit 720 can be configured to control the operation of a memory array within the memory die 900. Specifically, the peripheral circuit 720 can be configured to drive various electrical components within the memory array, including but not limited to the conductive layer 46, the drain region 63, and a source structure to be formed subsequently. The peripheral circuit 720 can be configured to control the operation of the vertical stacking of memory elements within the memory array within the memory die 900.

[0120] Reference Figure 17 , the logic die 700 can be attached to the memory die 900, for example, by bonding the logic-side bonding pad 788 to the memory-side bonding pad 988 at a bonding interface 800. A wafer-to-wafer bonding process can be employed to perform the bonding between the memory die 900 and the logic die 700, in which a two-dimensional array of memory dies 900 is bonded to a two-dimensional array of logic dies 700 through a die-to-bond process or through a die-to-die bonding process. The logic-side bonding pad 788 within each logic die 700 can be bonded to the memory-side bonding pad 988 within a corresponding memory die 900.

[0121] Reference Figure 18A and Figure 18B, the carrier substrate 9 and the sacrificial pedestal structure 11 can be removed, for example, by grinding, polishing, cutting, isotropic etching processes, and / or anisotropic etching processes. If a polishing process such as chemical mechanical polishing is used to remove the carrier substrate 9, the bottommost insulating layer 32B can be used as the polish stop material layer. If an etching process such as a wet etching process is used to remove the carrier substrate 9 and the sacrificial pedestal structure 11, the bottommost insulating layer 32B can be used as the etch stop material layer. In one embodiment, at least one final step of at least one removal process for removing the carrier substrate 9 and the sacrificial pedestal structure 11 can include a selective wet etching process that selectively etches semiconductor material relative to the dielectric materials of the memory film 50 and the dielectric core 62. In an illustrative example, the final step of at least one removal process can include a wet etching process using hot trimethyl-2-hydroxyethyl ammonium hydroxide (“hot TMY”) or tetramethyl ammonium hydroxide (TMAH). The entirety of the carrier substrate 9 and each sacrificial pedestal structure in the sacrificial pedestal structure 11 can be removed by the selective wet etching process. When removing the carrier substrate 9, the dorsal end surface of the sacrificial pillar structure 20 can be physically exposed.

[0122] Reference Figure 19 , at least one etching process can be performed to vertically recess the memory film 50, the vertical semiconductor channel 60, and the dielectric core 62, and the at least one etching process etches the bottom portions of the memory film 50, the vertical semiconductor channel 60, and the dielectric core 62. The vertically extending surface segments of the vertical semiconductor channel 60 can be physically exposed in the recess 223 from which the materials of the memory film 50, the vertical semiconductor channel 60, and the dielectric core 62 are removed. In one embodiment, the physically exposed surface segment of each vertical semiconductor channel 60 can include the end of the inner cylindrical surface of the corresponding vertical semiconductor channel 60. Optionally, one or more insulating spacers (not shown) can be formed on the bottom end of the dielectric core 62 exposed to the recess 223 to seal any exposed seams that may be present in the dielectric core 62.

[0123] According to one aspect of the present disclosure, the source-side dielectric isolation structure 120 is vertically spaced apart from portions of the dielectric core 62, the vertical semiconductor channel 60, and the memory film 50 that are removed during the various processing steps described in reference Figure 19 Therefore, the source-side dielectric isolation structure 120 is not exposed to any of the etchants used to remove the bottom portions of the vertical semiconductor channel 60, the memory film 50, and / or the dielectric core 62. Accordingly, the source-side dielectric isolation structure 120 is not exposed to the recess 223 and is protected from reference Figure 19The effects of the various etching processes employed during the described processing steps. Accordingly, structural damage to the source-side dielectric isolation structure 120 due to the lateral via 13 expanding during etching or a degradation in the electrical isolation performance provided by the source-side dielectric isolation structure 120 can be eliminated.

[0124] Reference Figure 20A and Figure 20B , a metal barrier material can be conformally deposited in the groove 223 and over the bottommost insulating layer 32B, the groove being formed by removing the ends of the memory film 50, the vertical semiconductor channel 60, and the dielectric core 62. The metal barrier material can include a metal nitride material (such as titanium nitride, tantalum nitride, tungsten nitride, or molybdenum nitride) and / or can include a metal carbide material (such as titanium carbide, tantalum carbide, or tungsten carbide). The metal barrier material can be deposited by a conformal deposition process (such as a chemical vapor deposition process). A metal barrier liner 224B can be formed on the physically exposed end surfaces of the dielectric core 62, the vertical semiconductor channel 60, and the memory film 50 in the groove 223 and over the bottommost insulating layer 32B.

[0125] A metal fill material can then be deposited over the metal barrier liner 224B. The metal fill material can include tungsten, tantalum, titanium, molybdenum, cobalt, ruthenium, copper, etc. A metal layer 224M can be formed over the metal barrier liner 224B. Subsequently, the metal layer 224M and the metal barrier liner 224B can be patterned by, for example, applying and patterning a photoresist layer over the metal layer 224M; and removing the portions of the metal layer 224M and the metal barrier liner 224B that are not masked by the patterned portion of the photoresist layer. Thereby, a conductive source electrode 224 is formed.

[0126] A memory block 102 of NAND strings can be provided between each pair of adjacent laterally isolated trench fill structures 76, the memory block including a plurality of memory sub-blocks (104A, 104B) of NAND strings. By applying an erase voltage, each memory sub-block (104A or 104B) of the NAND strings can be erased by gate-induced leakage (e.g., by injecting holes from the source side into the vertical semiconductor channel 60). To erase the NAND strings in the first memory sub-block 104A (e.g., the first memory opening fill structure 58F), a hole transfer erase voltage is applied to the bottom source select level conductive layer 46B and the first conductive strip 46S1 of the main source select level conductive layer 46P located in the first memory sub-block 104A to inject holes into the vertical semiconductor channel 60 of the NAND strings in the first memory sub-block 104A. However, a hole cut-off voltage is applied to the second conductive strip 46S2 of the main source select level conductive layer 46P located in the second memory sub-block 104B to prevent holes from being injected into the vertical semiconductor channel 60 of the NAND strings in the second memory sub-block 104B. Thus, the NAND strings in the second memory sub-block 104B (e.g., the second memory opening fill structure 58S) are not erased during the erasure of the NAND strings in the first memory sub-block 104A of the same memory block 102.

[0127] Reference Figures 1 to 20B According to various embodiments of the present disclosure, a semiconductor structure is provided that includes: a memory block 102 including an alternating stack (32, 46) of insulating layers 32 and conductive layers 46 arranged in a vertical direction and laterally extending in a first horizontal direction hd1; a memory opening 49 extending vertically through the alternating stack (32, 46); and a memory opening fill structure 58 located in the memory opening 49, where each memory opening fill structure in the memory opening fill structure 58 includes a corresponding memory film 50 and a corresponding vertical semiconductor channel 60. The conductive layer 46 includes a word line 46W, at least one bottom source side select gate electrode 46B, and at least one main source side select gate electrode 46P, the at least one main source side select gate electrode being located in the vertical direction between the word line 46W and the at least one bottom source side select gate electrode 46B. The word line 46W and the at least one bottom source side select gate electrode 46B continuously laterally extend through the entirety of the memory block 102 in a second horizontal direction hd2 perpendicular to the first horizontal direction hd1, and the at least one main source side select gate electrode 46P is laterally spaced in the second horizontal direction hd2.

[0128] In one embodiment, the semiconductor structure further includes a pair of adjacent laterally isolated trench fill structures 76 that extend laterally along a first horizontal direction hd1 and extend vertically at least from the bottommost layer to the topmost layer of the alternating stack (32, 46). The alternating stack (32, 46) is located between the pair of adjacent laterally isolated trench fill structures 76; and the pair of adjacent laterally isolated trench fill structures includes corresponding sidewalls of the memory block 102.

[0129] At least one bottom source side select gate electrode 46B includes a bottom source select level conductive layer 46B, and each bottom source select level conductive layer includes a corresponding first single continuous structure that contacts each of the laterally isolated trench fill structures 76 in the pair of adjacent laterally isolated trench fill structures. At least one main source side select gate electrode 46P includes a main source select level conductive layer, and each main source select level conductive layer includes a corresponding pair of first conductive strips 46S1 and second conductive strips 46S2 that are laterally spaced apart from each other along the second horizontal direction hd2. Each word line 46W includes a corresponding second single continuous structure that contacts each of the laterally isolated trench fill structures 76 in the pair of adjacent laterally isolated trench fill structures.

[0130] In one embodiment, the semiconductor structure further includes a source side dielectric isolation structure 120 that is located between the corresponding pair of first conductive strips 46S1 and second conductive strips 46S2 of each main source select level conductive layer in the main source select level conductive layers 46P.

[0131] In one embodiment, the source side dielectric isolation structure 120 includes a plurality of dielectric material blocks 12 that are laterally spaced apart from each other along the first horizontal direction hd1 and are staggered with a row of virtual memory opening fill structures 58T along the first horizontal direction hd1. In one embodiment, the plurality of dielectric material blocks 12 surround a corresponding lateral through hole 13 that extends laterally along the first horizontal direction hd1. In one embodiment, the corresponding lateral through hole 13 is filled with a corresponding dielectric hole fill structure 14, and the corresponding dielectric hole fill structure includes at least one dielectric material having the same material composition as the constituent layers in the memory film 50. In one embodiment, each memory film in the memory film 50 includes a corresponding barrier dielectric layer 52 and a corresponding vertical stack of memory elements that are laterally surrounded by the corresponding barrier dielectric layer 52; and each dielectric hole fill structure 14 includes a dielectric fill material layer that is an extension of the barrier dielectric layer 52 into the corresponding lateral through hole in the lateral through hole 13.

[0132] In one embodiment, a top surface of the source-side dielectric isolation structure 120 has a first width w1 along a second horizontal direction hd2; and a bottom surface of the source-side dielectric isolation structure 120 has a second width w2 along the second horizontal direction hd2 that is less than the first width w1. In one embodiment, the top surface of the source-side dielectric isolation structure 120 is located within a first horizontal plane HP1 that includes a top surface of one of the insulating layers 32 that is interposed between the word line 46W and the main source select level conductive layer 46P; and the bottom surface of the source-side dielectric isolation structure 120 is located within a second horizontal plane HP2 that is below a top surface of another one of the insulating layers 32 that is interposed between the main source select level conductive layer 46P and the bottom source select level conductive layer 46B.

[0133] In one embodiment, the conductive layer 46 includes at least one drain select level conductive layer 46D located above the word line 46W, wherein each drain select level conductive layer of the at least one drain select level conductive layer 46D includes a respective pair of third conductive bars 46DS1 and fourth conductive bars 46DS2 that are laterally spaced apart from each other along the second horizontal direction hd2. In one embodiment, the semiconductor structure further includes a drain-side dielectric isolation structure 72 that is located between the respective pair of third conductive bars and fourth conductive bars.

[0134] In one embodiment, the semiconductor structure further includes a source electrode 224 that is located above a first (e.g., bottom) side of the alternating stack (32, 46) and contacts a bottom end of the vertical semiconductor channel 60. The alternating stack is located within the memory die 900, and the semiconductor structure further includes a logic die 700 that is bonded to the memory die 900 above a second (e.g., top) side of the alternating stack that is opposite the first side.

[0135] Various embodiments of the present disclosure can be employed to form the source-side dielectric isolation structure 120 that is vertically offset from the source electrode 224 that is formed on a bottom end of the vertical semiconductor channel 60. The source-side dielectric isolation structure 120 can be vertically spaced apart from the metal source electrode 224 by at least one insulating layer 32 and at least one bottom source select level conductive layer 46B. By vertically offsetting the position of the source-side dielectric isolation structure 120 by at least one conductive layer 46 (such as at least one bottom source select level conductive layer 46B), damage to the source-side dielectric isolation structure 120 can be avoided.

[0136] Although the foregoing relates to specific preferred embodiments, it should be understood that the present disclosure is not limited thereto. Those of ordinary skill in the art will recognize that various modifications can be made to the disclosed embodiments, and such modifications are intended to be within the scope of the present disclosure. Compatibility is assumed between all embodiments that are not alternatives to each other. The word "comprising" contemplates all embodiments in which the words "consisting essentially of" or "consisting of" replace the word "comprising", unless expressly stated otherwise. Whenever two or more elements are listed as alternatives in the same or different paragraphs, a Markush group comprising the list of those two or more elements is also implicitly disclosed. Whenever the auxiliary verb "can" is used in the present disclosure to describe the formation of an element or the performance of a processing step, embodiments in which such element or such processing step is not performed are also expressly contemplated, provided that the resulting device or apparatus can provide an equivalent result. Thus, when the auxiliary verb "can" is applied to the formation of an element or the performance of a processing step, the term should be understood to mean "may" or "may, or may not" in cases where the omission of the formation of the element or the performance of the processing step still provides the same or an equivalent result (such equivalent result including a slightly better or slightly worse result). In cases where embodiments employing a specific structure and / or configuration are illustrated in the present disclosure, it should be understood that the present disclosure can be practiced using any other compatible structure and / or configuration that is functionally equivalent, provided that such substitution is not expressly prohibited or is not known to those of ordinary skill in the art to be infeasible. If publications, patent applications, and / or patents are cited herein, each such document is hereby incorporated by reference in its entirety.

Claims

1. A semiconductor structure, the semiconductor structure comprising: a memory block, the memory block comprising an alternating stack of insulating layers and conductive layers arranged in a vertical direction and laterally extending in a first horizontal direction; a memory opening, the memory opening extending vertically through the alternating stack; and a memory opening fill structure, the memory opening fill structure being located in the memory opening, wherein each memory opening fill structure in the memory opening fill structure comprises a respective memory film and a respective vertical semiconductor channel, wherein: the conductive layer comprises a word line, at least one bottom source side select gate electrode, and at least one main source side select gate electrode, the at least one main source side select gate electrode being located in the vertical direction between the word line and the at least one bottom source side select gate electrode; the word line and the at least one bottom source side select gate electrode continuously extend laterally through the entirety of the memory block in a second horizontal direction perpendicular to the first horizontal direction; and the at least one main source side select gate electrode is laterally spaced apart in the second horizontal direction.

2. The semiconductor structure according to claim 1, the semiconductor structure further comprising a pair of adjacent lateral isolation trench fill structures, the lateral isolation trench fill structures extending laterally in the first horizontal direction and vertically extending at least from the bottommost layer of the alternating stack to the topmost layer of the alternating stack.

3. The semiconductor structure according to claim 2, wherein: the alternating stack is located between the pair of adjacent lateral isolation trench fill structures; and the pair of adjacent lateral isolation trench fill structures comprises respective sidewalls of the memory block.

4. The semiconductor structure according to claim 2, wherein: the at least one bottom source side select gate electrode comprises a bottom source select level conductive layer, each bottom source select level conductive layer comprising a respective first single continuous structure that contacts each of the lateral isolation trench fill structures in the pair of adjacent lateral isolation trench fill structures; the at least one main source side select gate electrode comprises a main source select level conductive layer, each main source select level conductive layer comprising a respective pair of first conductive strips and second conductive strips that are laterally spaced apart from each other in the second horizontal direction; and the word lines each comprise a respective second single continuous structure that contacts each of the lateral isolation trench fill structures in the pair of adjacent lateral isolation trench fill structures.

5. The semiconductor structure according to claim 4, the semiconductor structure further comprising a source side dielectric isolation structure, the source side dielectric isolation structure being located between the respective pair of first conductive strips and second conductive strips of each main source select level conductive layer in the main source select level conductive layers.

6. The semiconductor structure according to claim 5, wherein the source side dielectric isolation structure comprises a plurality of dielectric material blocks, the plurality of dielectric material blocks being laterally spaced apart from each other in the first horizontal direction and being staggered with a row of virtual memory opening fill structures in the first horizontal direction.

7. The semiconductor structure according to claim 6, wherein the plurality of dielectric material blocks surround respective lateral through-holes extending laterally along the first horizontal direction.

8. The semiconductor structure according to claim 7, wherein: the respective lateral through-holes are filled with respective dielectric hole filling structures; each memory film in the memory film stack includes a respective barrier dielectric layer and a respective vertical stack of memory elements laterally surrounded by the respective barrier dielectric layer; and each dielectric hole filling structure includes a dielectric filling material layer, which is an extension of the barrier dielectric layer into the respective lateral through-hole in the lateral through-holes.

9. The semiconductor structure according to claim 5, wherein: the top surface of the source-side dielectric isolation structure has a first width along the second horizontal direction; and the bottom surface of the source-side dielectric isolation structure has a second width along the second horizontal direction that is less than the first width.

10. The semiconductor structure according to claim 9, wherein: the top surface of the source-side dielectric isolation structure is located in a first horizontal plane, the first horizontal plane including the top surface of one of the insulating layers, the one insulating layer being interposed between the word line and the main source select level conductive layer; and the bottom surface of the source-side dielectric isolation structure is located in a second horizontal plane, the second horizontal plane being below the top surface of the other insulating layer, the other insulating layer being interposed between the main source select level conductive layer and the bottom source select level conductive layer.

11. The semiconductor structure according to claim 5, wherein the conductive layer further includes a drain select level conductive layer above the word line, and each drain select level conductive layer in the drain select level conductive layer includes a respective pair of third conductive strips and fourth conductive strips that are laterally spaced apart from each other along the second horizontal direction.

12. The semiconductor structure according to claim 11, the semiconductor structure further including a drain-side dielectric isolation structure located between the respective pair of third conductive strips and fourth conductive strips.

13. The semiconductor structure according to claim 1, the semiconductor structure further including a source electrode located above the first side of the alternating stack and contacting the bottom end of the vertical semiconductor channel.

14. The semiconductor structure according to claim 13, wherein the alternating stack is located in a memory die, and the semiconductor structure further includes a logic die, the logic die being bonded to the memory die above the second side of the alternating stack that is opposite to the first side.

15. A method of forming a semiconductor structure, the method comprising: forming a first alternating stack of a first insulating layer and a first sacrificial material layer above a substrate, wherein the first sacrificial material layer includes at least one bottom source select level sacrificial material layer and at least one main source select level sacrificial material layer from bottom to top; Form a source-side dielectric isolation structure that extends laterally in a first horizontal direction through the at least one main source select level sacrificial material layer but does not pass through any part of the at least one bottom source select level sacrificial material layer; Form a second alternating stack of a second insulating layer and a second sacrificial material layer over the first alternating stack and the source-side dielectric isolation structure; Form a memory opening through the second alternating stack and the first alternating stack; Form a memory opening fill structure in the memory opening, where each memory opening fill structure in the memory opening fill structure includes a corresponding memory film and a corresponding vertical semiconductor channel; And Replace the second sacrificial material layer and the first sacrificial material layer with a conductive layer.

16. The method according to claim 15, wherein the source-side dielectric isolation structure divides each main source select level sacrificial material layer in the at least one main source select level sacrificial material layer into a corresponding pair of first sacrificial material strips and second sacrificial material strips.

17. The method according to claim 16, wherein: The conductive layer includes at least one first conductive strip and at least one second conductive strip, the at least one first conductive strip replaces each first sacrificial material strip, and the at least one second conductive strip replaces each second sacrificial material strip; And The main source select level conductive layer includes a combination of the first conductive strip and the second conductive strip that are laterally spaced apart from each other by the source-side dielectric isolation structure.

18. The method according to claim 16, wherein the memory opening includes: A first memory opening that extends vertically through each first sacrificial material strip and is laterally spaced apart from each second sacrificial material strip; A second memory opening that extends vertically through each second sacrificial material strip and is laterally spaced apart from each first sacrificial material strip; And A row of third memory openings that are arranged in the first horizontal direction and divide the source-side dielectric isolation structure into a plurality of dielectric material blocks.

19. The method according to claim 18, wherein: The plurality of dielectric material blocks surround a corresponding lateral through hole that extends laterally in the first horizontal direction; and The corresponding lateral through hole is filled with a corresponding dielectric hole fill structure, and the corresponding dielectric hole fill structure includes at least one dielectric material having the same material composition as the constituent layers in the memory film.

20. The method according to claim 15, the method further includes: Form a pair of lateral isolation trenches through each layer in the second alternating stack and the first alternating stack, where each lateral isolation trench in the pair of lateral isolation trenches extends laterally in the first horizontal direction, and the source-side dielectric isolation structure is located between the pair of lateral isolation trenches; Remove the second sacrificial material layer and the first sacrificial material layer by providing an isotropic etchant to the pair of lateral isolation trenches to form a lateral groove; Form the conductive layer in the lateral groove; And A pair of lateral isolation trench fill structures are formed in the pair of lateral isolation trenches, wherein the conductive layer further includes at least one bottom source select level conductive layer that replaces the at least one bottom source select level sacrificial material layer, and wherein each bottom source select level conductive layer in the at least one bottom source select level conductive layer includes a corresponding first single continuous structure that contacts each lateral isolation trench fill structure in the pair of lateral isolation trench fill structures.

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