Non-volatile memory with reject state operation

Abstract

A non-volatile memory is configured to transition a memory cell from a program data state having a higher threshold voltage range to a program data state having a lower threshold voltage range without transitioning the memory cell to an erase data state.

Description

[0001] Claim for Priority

[0002] This application claims priority to U.S. Non - Provisional Application No. 18 / 361,841, filed on July 29, 2023, entitled "NON - VOLATILE MEMORY WITH DECLINE STATE OPERATION", which claims priority to U.S. Provisional Application No. 63 / 505,306, filed on May 31, 2023, and the entire content of the U.S. Non - Provisional Application is hereby incorporated by reference for all purposes. Background Art

[0003] This disclosure relates to non - volatile memory.

[0004] Semiconductor memories are widely used in various electronic devices (such as cellular phones, digital cameras, personal digital assistants, medical electronic devices, mobile computing devices, servers, solid - state drives, non - mobile computing devices, and other devices). Semiconductor memories can include non - volatile memories or volatile memories. Non - volatile memories allow storage and retention of information even when not connected to a power source (e.g., a battery). An example of a non - volatile memory is flash memory (e.g., NAND - type and NOR - type flash memories).

[0005] Users of non - volatile memories can program (e.g., write) data into the non - volatile memories and then read the data back. For example, a digital camera can take a photo and store the photo in a non - volatile memory. Later, the user of the digital camera can view the photo by having the digital camera read the photo from the non - volatile memory. Since users of non - volatile memories do not want to wait for the non - volatile memory to complete memory operations, it is desirable for non - volatile memories to have high performance. Brief Description of the Drawings

[0006] Elements with the same reference numerals represent common components in different drawings.

[0007] Figure 1 is a block diagram depicting one embodiment of a storage system.

[0008] Figure 2A is a block diagram of one embodiment of a memory die.

[0009] Figure 2B is a block diagram of one embodiment of an integrated memory component.

[0010] Figure 3A and Figure 3B depict different embodiments of the integrated memory component.

[0011] Figure 4 A perspective view of a portion of an embodiment of a monolithic three-dimensional memory structure.

[0012] Figure 4A A block diagram of an embodiment of a memory structure having two planes.

[0013] Figure 4B A top view of a portion of an embodiment of a memory cell block.

[0014] Figure 4C A cross-sectional view of a portion of an embodiment of a memory cell block.

[0015] Figure 4D A cross-sectional view of a portion of an embodiment of a memory cell block.

[0016] Figure 4E A cross-sectional view of an embodiment of a vertical column of memory cells.

[0017] Figure 4F A schematic diagram of multiple NAND strings in multiple regions of the same block.

[0018] Figure 5A Depicts a threshold voltage distribution.

[0019] Figure 5B Depicts a threshold voltage distribution.

[0020] Figure 5C Depicts a threshold voltage distribution.

[0021] Figure 5D Depicts a threshold voltage distribution.

[0022] Figure 6 A flowchart of an embodiment describing a process for programming a non-volatile memory.

[0023] Figure 7 A flowchart of an embodiment describing a process for transitioning a memory cell from a programmed data state having a higher threshold voltage range to a programmed data state having a lower threshold voltage range without transitioning the memory cell to an erased data state.

[0024] Figure 8 A flowchart of an embodiment describing a process for transitioning a memory cell from a programmed data state having a higher threshold voltage range to a programmed data state having a lower threshold voltage range without transitioning the memory cell to an erased data state.

[0025] Figure 9It is a timing diagram depicting the process used during the transition of a memory cell from a programmed data state with a higher threshold voltage range to a programmed data state with a lower threshold voltage range without transitioning the memory cell to an erased data state.

[0026] Figure 10 It is a flowchart of an embodiment depicting the process for adjusting the speed of transitioning a memory cell from a programmed data state with a higher threshold voltage range to a programmed data state with a lower threshold voltage range without transitioning the memory cell to an erased data state.

[0027] Figure 11 It is a timing diagram depicting the process used during the transition of a memory cell from a programmed data state with a higher threshold voltage range to a programmed data state with a lower threshold voltage range without transitioning the memory cell to an erased data state.

[0028] Figure 12A and Figure 12B depicts a command sequence for transitioning a memory cell from a programmed data state with a higher threshold voltage range to a programmed data state with a lower threshold voltage range without transitioning the memory cell to an erased data state. Detailed Description

[0029] In prior art systems, when existing data currently stored in a set of non - volatile memory cells is to be overwritten with new data, the non - volatile memory cells are first erased to an erased state and then programmed with the new data. It is proposed to accelerate the programming process by forgoing the time spent erasing the non - volatile memory cells to an erased state and instead adjusting the non - volatile memory cells directly from storing the existing data to storing the new data without entering the erased state. Thus, the non - volatile memory is configured to transition a memory cell from a programmed data state with a higher threshold voltage range to a programmed data state with a lower threshold voltage range without transitioning the memory cell to an erased data state.

[0030] One embodiment includes transitioning a first memory cell among a plurality of non - volatile memory cells from a first programmed data state in a set of data states to a second programmed data state in the set of data states without transitioning the first memory cell to an erased data state, where the second data state corresponds to a lower threshold voltage range than the first data state.

[0031] Figure 1FIG. 0 is a block diagram of an implementation of a storage system 100 that implements the proposed technology described herein. In one implementation, the storage system 100 is a solid state drive (“SSD”). The storage system 100 can also be a memory card, a USB drive, or other types of storage systems. The proposed technology is not limited to any one type of memory system. The storage system 100 is connected to a host 102, which can be a computer, a server, an electronic device (e.g., a smart phone, a tablet computer, or other mobile device), an appliance, or another device that uses memory and has data processing capabilities. In some implementations, the host 102 is separate from but connected to the storage system 100. In other implementations, the storage system 100 is embedded within the host 102.

[0032] Figure 1 The components of the storage system 100 depicted in FIG. 4 are circuitry. The storage system 100 includes a memory controller 120 connected to a non-volatile memory 130 and a local high-speed volatile memory 140 (e.g., DRAM). The memory controller 120 uses the local high-speed volatile memory 140 to perform certain functions. For example, the local high-speed volatile memory 140 stores a logical address to physical address translation table (“L2P table”).

[0033] The memory controller 120 includes a host interface 152 that is connected to and communicates with the host 102. In one embodiment, the host interface 152 implements Non-Volatile Memory Express (NVMe) over Peripheral Component Interconnect Express (PCIe). Other interfaces such as Small Computer System Interface (SCSI), Serial Advanced Technology Attachment (SATA), etc. may also be used. The host interface 152 is also connected to a Network-on-Chip (NOC) 154. The NOC is a communication subsystem on an integrated circuit. The NOC may span synchronous and asynchronous clock domains, or use non-clock asynchronous logic. NOC technology applies network theory and methods to on-chip communication and brings significant improvements over conventional buses and crossbar interconnections. Compared with other designs, the NOC improves the scalability of the System-on-Chip (SoC) and the power efficiency of complex SoCs. The lines and links of the NOC are shared by many signals. Since all links in the NOC can operate on different data packets simultaneously, a high level of parallelism is achieved. Therefore, as the complexity of integrated subsystems continues to grow, the NOC provides enhanced performance (such as throughput) and scalability compared to previous communication architectures (e.g., dedicated point-to-point signal lines, shared buses, or segmented buses with bridges). In other embodiments, the NOC 154 may be replaced by a bus. Connected to and communicating with the NOC 154 are a processor 156, an ECC engine 158, a memory interface 160, and a DRAM controller 164. The DRAM controller 164 is used to operate and communicate with the local high-speed volatile memory 140 (e.g., DRAM). In other embodiments, the local high-speed volatile memory 140 may be Static Random Access Memory (SRAM) or another type of volatile memory.

[0034] The ECC engine 158 performs error correction services. For example, the ECC engine 158 performs data encoding and decoding according to the implemented ECC technology. In one embodiment, the ECC engine 158 is a circuit programmed by software. For example, the ECC engine 158 may be a programmable processor. In other embodiments, the ECC engine 158 is a custom and dedicated hardware circuit without any software. In another embodiment, the functions of the ECC engine 158 are implemented by the processor 156.

[0035] The processor 156 performs various controller memory operations, such as programming, erasing, reading, and memory management processes. In one embodiment, the processor 156 is programmed by firmware. In other embodiments, the processor 156 is custom and dedicated hardware circuitry without any software. The processor 156 also implements the translation module as a software / firmware process or dedicated hardware circuitry. In many systems, the non-volatile memory is internally addressed to the storage system using physical addresses associated with one or more memory dies. However, the host system will use logical addresses to address various memory locations. This enables the host to allocate data to contiguous logical addresses while the storage system is free to store the data at locations among one or more memory dies as it desires. To implement this system, the memory controller 120 (e.g., the translation module) performs the address translation between the logical addresses used by the host and the physical addresses used by the memory die. An example implementation is to maintain a table (i.e., the aforementioned L2P table) that identifies the current translations between logical addresses and physical addresses. Entries in the L2P table may include the identification of the logical address and the corresponding physical address. Although the logical address to physical address table (or L2P table) includes the word "table", they do not need to be in a strict table form. Instead, the logical address to physical address table (or L2P table) can be any type of data structure. In some examples, the memory space of the storage system is so large that the local memory 140 cannot hold all the L2P tables. In such cases, the entire set of L2P tables is stored in the memory die 130, and a subset of the L2P tables is cached (L2P cache) in the local high-speed volatile memory 140.

[0036] The memory interface 160 communicates with the non-volatile memory 130. In one embodiment, the memory interface provides a switching mode interface. Other interfaces may also be used. In some example implementations, the memory interface 160 (or another part of the controller 120) implements a scheduler and buffer for sending data to and receiving data from one or more memory dies.

[0037] In one embodiment, the non-volatile memory 130 includes one or more memory dies. Figure 2A is a functional block diagram of one embodiment of the memory die 200 that includes the non-volatile memory 130. Each of the one or more memory dies in the non-volatile memory 130 can be implemented as Figure 2A the memory die 200. Figure 2AThe components depicted in [description] are circuits. Memory die 200 includes a memory array 202, which may include non-volatile memory cells, as described in more detail below. The array terminal lines of memory array 202 include various layers of word lines organized as rows and various layers of bit lines organized as columns. However, other orientations may also be implemented. Memory die 200 includes row control circuitry 220, the output 208 of which is connected to the corresponding word lines of memory array 202. Row control circuitry 220 receives a set of M row address signals and one or more various control signals from system control logic circuitry 260, and generally may include circuitry for both read operations and write (programming) operations, such as row decoder 222, array terminal driver 224, and block selection circuitry 226. Row control circuitry 220 may also include read / write circuitry. Memory die 200 further includes column control circuitry 210, which includes sense amplifiers 230, the input / output 206 of which is connected to the corresponding bit lines of memory array 202. Although only a single block is shown for array 202, the memory die may include multiple arrays that can be accessed separately. Column control circuitry 210 receives a set of N column address signals and one or more various control signals from system control logic 260, and generally may include circuitry such as column decoder 212, array terminal receiver or driver circuitry 214, block selection circuitry 216, and read / write circuitry and I / O multiplexer.

[0038] System control logic 260 receives data and commands from memory controller 120 and provides output data and status to the host. In some embodiments, system control logic 260 (which includes one or more circuits) includes a state machine 262 that provides die-level control of memory operations. In one embodiment, state machine 262 may be programmed by software. In other embodiments, state machine 262 does not use software and is implemented entirely in hardware (e.g., circuitry). In another embodiment, state machine 262 is replaced by a microcontroller or microprocessor on or off the memory chip. System control logic 262 may also include a power control module 264 that controls the power and voltage supplied to the rows and columns of memory structure 202 during memory operations, and may include a charge pump and regulator circuitry for generating regulated voltages. System control logic 262 includes a storage device 366 (e.g., RAM, registers, latches, etc.), which may be used to store parameters for operating memory array 202.

[0039] Commands and data are transferred between the memory controller 120 and the memory die 200 via the memory controller interface 268 (also referred to as the "communication interface"). The memory controller interface 268 is an electrical interface for communicating with the memory controller 120. Examples of the memory controller interface 268 include a toggle mode interface and an Open NAND Flash Interface (ONFI). Other I / O interfaces may also be used.

[0040] In some embodiments, all elements of the memory die 200, including the system control logic 260, may be formed as part of a single die. In other embodiments, some or all of the system control logic 260 may be formed on different dies.

[0041] In one embodiment, the memory structure 202 includes a three-dimensional memory array of non-volatile memory cells, where multiple memory levels are formed on a single substrate (such as a wafer). The memory structure may include any type of non-volatile memory monolithically formed in one or more physical levels of memory cells having active areas disposed on a silicon (or other type of) substrate. In one example, the non-volatile memory cells include vertical NAND strings having a charge trapping layer.

[0042] In another embodiment, the memory structure 302 includes a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells utilizing a floating gate. Other types of memory cells (e.g., NOR-type flash memory) may also be used.

[0043] The exact type of memory array architecture or memory cells included in the memory structure 202 is not limited to the above examples. Many different types of memory array architectures or memory technologies may be used to form the memory structure 202. For the purposes of the embodiments claimed herein, no particular non-volatile memory technology is required. Other examples of suitable technologies for the memory cells of the memory structure 202 include ReRAM memory (resistive random access memory), magnetoresistive memory (e.g., MRAM, spin-transfer torque MRAM, spin-orbit torque MRAM), FeRAM, phase change memory (e.g., PCM), etc. Examples of suitable technologies for the memory cell architecture of the memory structure 202 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bit line arrays, etc.

[0044] An example of a ReRAM cross-point memory includes reversible resistive switching elements arranged in a cross-point array accessed by X and Y lines (e.g., word lines and bit lines). In another embodiment, the memory cell may include a conductive-bridging memory element. The conductive-bridging memory element may also be referred to as a programmable metallization cell. The conductive-bridging memory element can be used as a state-changing element based on the physical repositioning of ions within a solid electrolyte. In some cases, the conductive-bridging memory element may include two solid metal electrodes, one solid metal electrode being relatively inert (e.g., tungsten), and the other solid metal electrode being electrochemically active (e.g., silver or copper), with a solid electrolyte thin film between the two electrodes. As the temperature increases, the mobility of the ions also increases, resulting in a lower programming threshold for the conductive-bridging memory cell. Thus, the conductive-bridging memory element can have a wide range of programming thresholds that vary with temperature.

[0045] Another example is a magnetoresistive random access memory (MRAM) that stores data using magnetic storage elements. These elements are formed from two ferromagnetic layers, each of which can maintain magnetization, and the two ferromagnetic layers are separated by a thin insulating layer. One of the two layers is a permanent magnet set to a specific polarity; the magnetization of the other layer can be changed to match the magnetization of an external field, thereby storing memory. Memory devices are constructed from a grid of such memory cells. In one embodiment for programming, each memory cell is located between a pair of write lines that are arranged at right angles to each other and parallel to the cell, with one write line above the cell and one write line below the cell. When current passes through them, an induced magnetic field is generated. Memory implementations based on MRAM will be discussed in more detail below.

[0046] Phase change memory (PCM) utilizes the unique properties of chalcogenide glasses. One embodiment uses a GeTe-Sb2Te3 superlattice to achieve non-thermal phase change by simply changing the coordination state of germanium atoms using a laser pulse (or a light pulse from another source). Thus, the programming dose is the laser pulse. Memory cells can be prohibited from receiving light by blocking them. In other PCM embodiments, the memory cells are programmed by current pulses. Note that the use of "pulse" in this document does not require a square pulse, but includes (continuous or non-continuous) vibrations or bursts of sound, current, voltage, light, or other waves. These memory elements within individual selectable memory cells or bits may include another series element as a selector, such as a two-way threshold switch or a metal-insulator substrate.

[0047] One of ordinary skill in the art will recognize that the techniques described herein are not limited to a single specific memory structure, memory configuration, or material composition, but rather encompass many related memory structures within the spirit and scope of the techniques as described herein and as understood by one of ordinary skill in the art.

[0048] Figure 2A The components of can be grouped into two parts: (1) the memory structure 202 and (2) the peripheral circuit, which includes Figure 2A all of the other components depicted in. An important characteristic of the memory circuit is its capacity, which can be increased by increasing the area of the memory die of the storage system 100 dedicated to the memory structure 202; however, this reduces the area of the memory die available for the peripheral circuit. This can impose rather stringent limitations on these components of the peripheral circuit. For example, the need to fit a sense amplifier circuit within the available area can be a significant limitation on the sense amplifier design architecture. With respect to the system control logic 260, the reduced area availability can limit the available functionality that can be implemented on the chip. Thus, a fundamental tradeoff in the design of the memory die for the storage system 100 is the amount of area dedicated to the memory structure 202 and the amount of area dedicated to the peripheral circuit.

[0049] Another area where the memory structure 202 and the peripheral circuit often conflict is in the processing involved in forming these areas, as these areas typically involve different processing techniques and the tradeoffs of having different technologies on a single die. For example, when the memory structure 202 is a NAND flash memory, which is an NMOS structure, while the peripheral circuit is typically CMOS-based. For example, components such as sense amplifier circuits, charge pumps, logic elements in state machines, and other peripheral circuits in the system control logic 260 typically employ PMOS devices. The processing operations for fabricating a CMOS die will differ in many respects from those optimized for an NMOS flash NAND memory or other memory cell technologies.

[0050] To improve on these limitations, the embodiments described below can Figure 2AThe components are separated onto individually formed dies, which are then bonded together. More specifically, the memory structure 202 can be formed on one die (referred to as the memory die), and some or all of the peripheral circuit components (including one or more control circuits) can be formed on a separate die (referred to as the control die). For example, the memory die can be formed solely of memory elements (such as an array of memory cells of a flash NAND memory, an MRAM memory, a PCM memory, a ReRAM memory, or other memory types). Some or all of the peripheral circuits (even including components such as decoders and sense amplifiers) can then be moved to a separate control die. This allows each memory die in the memory die stack to be individually optimized according to its technology. For example, a NAND memory die can be optimized for an NMOS-based memory array structure without concern for CMOS components that have now been moved to a control die that can be optimized for CMOS processing. This allows for more space for the peripheral components, which can now incorporate additional capabilities that could not be easily incorporated in the case where they were limited to the edges of the same die that holds the memory cell array. The two dies can then be bonded together in a bonded multi-die memory circuit, where the array on one die is connected to the peripheral components on the other die. Although the following will focus on a bonded memory circuit of one memory die and one control die, other embodiments can use more dies, such as two memory dies and one control die.

[0051] Figure 2B illustrates Figure 2A an alternative arrangement of the arrangement shown, which can be implemented using wafer-to-wafer bonding to provide a pair of bonded dies. Figure 2B FIG. 8 depicts a functional block diagram of one embodiment of an integrated memory component 207. One or more integrated memory components 207 can be used to implement the non-volatile memory 130 of the storage system 100. The integrated memory component 207 includes two types of semiconductor dies (or more simply, "dies"). The memory die 201 includes a memory structure 202. The memory structure 202 includes non-volatile memory cells. The control die 211 includes control circuits 260, 210, and 220 (as described above). In some embodiments, the control die 211 is configured to be connected to the memory structure 202 in the memory die 201. In some embodiments, the memory die 201 and the control die 211 are bonded together.

[0052] Figure 2B illustrates an example of a peripheral circuit (including control circuits) formed in a peripheral circuit or a control die 211 coupled to the memory structure 202 formed in the memory die 201. As with Figure 2ACommon components are similarly labeled. System control logic 260, row control circuit 220, and column control circuit 210 are located in control die 211. In some embodiments, all or a portion of column control circuit 210 and all or a portion of row control circuit 220 are located on memory die 201. In some embodiments, some of the circuits in system control logic 260 are located on memory die 201.

[0053] System control logic 260, row control circuit 220, and column control circuit 210 may be formed by a common process (e.g., a CMOS process) such that additional elements and functionality (such as ECC) more commonly found on memory controller 120 may require few or no additional process steps (i.e., the same process steps used to fabricate controller 120 may also be used to fabricate system control logic 260, row control circuit 220, and column control circuit 210). Thus, while moving such circuits from a die (such as memory die 201) may reduce the number of steps required to fabricate such a die, adding such circuits to a die (such as control die 211) may not require many additional process steps. Since CMOS technology is used to implement some or all of control circuits 260, 210, 220, control die 211 may also be referred to as a CMOS die.

[0054] Figure 2B Column control circuit 210 including sense amplifiers 230 on control die 211 is shown, which is coupled to memory structure 202 on memory die 201 via circuit path 206. For example, circuit path 206 may provide an electrical connection between column decoder 212, driver circuit 214, and block select 216 and the bit lines of memory structure 202. The circuit path may extend from column control circuit 210 in control die 211 through pads on control die 211 that are bonded to corresponding pads on memory die 201, and these corresponding pads are connected to the bit lines of memory structure 202. Each bit line of memory structure 202 may have a corresponding circuit path in circuit path 206, including a pair of bonded pads connected to column control circuit 210. Similarly, row control circuit 220 including row decoder 222, array driver 224, and block select 226 is coupled to memory structure 202 via circuit path 208. Each of the circuit paths 208 may correspond to a word line, a dummy word line, or a select gate line. Additional circuit paths may also be provided between control die 211 and memory die 201.

[0055] For the purposes of this document, the phrase "control circuit" or "one or more control circuits" may include any one or any combination of a memory controller 120, a state machine 262, all or a portion of system control logic 260, all or a portion of row control circuit 220, all or a portion of column control circuit 210, a microcontroller, a microprocessor, and / or other similar functional circuits. The control circuit may include only hardware or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of a control circuit. The control circuit may include a processor, an FGA, an ASIC, an integrated circuit, or other types of circuits.

[0056] In some embodiments, there are more than one control die 211 and more than one memory die 201 in the integrated memory component 207. In some embodiments, the integrated memory component 207 includes a stack of multiple control dies 211 and multiple memory dies 201. Figure 3A A side view of an embodiment of an integrated memory component 207 (e.g., including a stack of control die 211 and memory die 201) stacked on a substrate 271 is depicted. The integrated memory component 207 has three control dies 211 and three memory dies 201. In some embodiments, there are more than three memory dies 201 and more than three control dies 211.

[0057] Each control die 211 is attached (e.g., bonded) to at least one of the memory dies 201. Some of the bond pads 282 / 284 are depicted. There may be more bond pads. The space between two dies 201, 211 bonded together is filled with a solid layer 280, which may be formed of an epoxy resin or other resin or polymer. The solid layer 280 protects the electrical connection between the dies 201, 211 and further holds the dies together. Various materials may be used as the solid layer 280, but in an embodiment, it may be a Hysol epoxy resin from Henkel Corp. with an office in California, USA.

[0058] The integrated memory component 207 may be stacked, for example, in a stepped offset such that the bond pads at each level are not covered and can be accessed from above. Wire bonds 270 connected to the bond pads connect the control die 211 to the substrate 271. Several such wire bonds may be formed across the width of each control die 211 (i.e., into the Figure 3A page).

[0059] Memory die through - silicon vias (TSVs) 276 can be used to route signals through memory die 201. Control die through - silicon vias (TSVs) 278 can be used to route signals through control die 211. The TSVs 276, 278 can be formed before, during, or after the formation of the integrated circuits in semiconductor dies 201, 211. The TSVs can be formed by etching holes through the wafer. These holes can then be lined with a barrier layer that prevents metal diffusion. The barrier layer can in turn be lined with a seed layer, and the seed layer can be plated with a conductor (such as copper), but other suitable materials such as aluminum, tin, nickel, gold, doped polysilicon, and their alloys or combinations can also be used.

[0060] Solder balls 272 can optionally be attached to contact pads 274 on the lower surface of substrate 271. The solder balls 272 can be used to electrically and mechanically couple the integrated memory component 207 to a host device (such as a printed circuit board). In the case where the integrated memory component 207 is to be used as an LGA package, the solder balls 272 can be omitted. The solder balls 272 can form part of the interface between the integrated memory component 207 and the memory controller 120.

[0061] Figure 3B A side view of another embodiment of the integrated memory component 207 stacked on substrate 271 is depicted. Figure 3B The integrated memory component 207 has three control dies 211 and three memory dies 201. In some embodiments, there are many more than three memory dies 201 and many more than three control dies 211. In this example, each control die 211 is bonded to at least one memory die 201. Optionally, the control die 211 can be bonded to two or more memory dies 201.

[0062] Some of the bonding pads 282, 284 are depicted. There can be more bonding pads. The space between two dies 201, 211 bonded together is filled with a solid layer 280, which can be formed of epoxy resin or other resin or polymer. Compared with Figure 3A the example in Figure 3B the integrated memory component 207 in

[0063] does not have a stepped offset. Memory die through - silicon vias (TSVs) 276 can be used to route signals through memory die 201. Control die through - silicon vias (TSVs) 278 can be used to route signals through control die 211. Solder balls 272 can optionally be attached to contact pads 274 on the lower surface of substrate 271. The solder balls 272 can be used to electrically and mechanically couple the integrated memory component 207 to a host device (such as a printed circuit board). In the case where the integrated memory component 207 is to be used as an LGA package, the solder balls 272 can be omitted.

[0064] As briefly discussed above, the control die 211 and the memory die 201 can be bonded together. The bonding pads on each of the dies 201, 211 can be used to bond the two dies together. In some embodiments, in a so-called Cu-Cu bonding process, the bonding pads are bonded directly to each other without solder or other additive materials. In the Cu-Cu bonding process, the bonding pads are controlled to be highly planar and are formed in a highly controlled environment substantially free of ambient particles that might otherwise deposit on the bonding pads and prevent tight bonding. Under such suitably controlled conditions, the bonding pads are aligned and pressed against each other to form an inter-bond based on surface tension. This bond can be formed at room temperature, but heat can also be applied. In embodiments using Cu-Cu bonding, the bonding pads can be squares with side lengths of about 5 μm and are spaced apart from each other by a pitch of 5 μm to 5 μm. Although this process is referred to herein as Cu-Cu bonding, this term can also be applied even in cases where the bonding pads are formed of materials other than Cu.

[0065] When the area of the bonding pads is small, it may be difficult to bond semiconductor dies together. By providing a film layer on the surface of the semiconductor die including the bonding pads, the size of the bonding pads and the pitch between the bonding pads can be further reduced. The film layer is provided around the bonding pads. When the dies are placed together, the bonding pads can be bonded to each other, and the film layers on the respective dies can be bonded to each other. This bonding technique can be referred to as hybrid bonding. In embodiments using hybrid bonding, the bonding pads can be squares with side lengths of about 5 μm and are spaced apart from each other by a pitch of 1 μm to 5 μm. Bonding techniques can be used to provide bonding pads with even smaller (or larger) sizes and pitches.

[0066] Some embodiments can include a film on the surfaces of the dies 201, 211. In cases where such a film is not initially provided, the space between the dies can be underfilled with an epoxy resin or other resin or polymer. The underfill material can be applied as a liquid, which then hardens into a solid layer. This underfill step protects the electrical connections between the dies 201, 211 and further secures the dies together. Various materials can be used as the underfill material, but in an embodiment, it can be Hysol epoxy resin from Henkel Corp. with an office in California, USA.

[0067] Figure 4 is a perspective view of a portion of an exemplary embodiment of a monolithic three-dimensional memory array / structure that can include a memory structure 202, the memory structure including a plurality of non-volatile memory cells arranged as vertical NAND strings. For example, Figure 4Shows a portion 400 of a block of memory. The depicted structure includes a set of bit lines BL positioned above a stack 401 of alternating dielectric and conductive layers. For purposes of illustration, one of the dielectric layers in the dielectric layer stack is labeled D, and one of the conductive layers (also referred to as the word line layer) is labeled W. The number of alternating dielectric and conductive layers can vary based on specific implementation requirements. As will be explained below, in one embodiment, the alternating dielectric and conductive layers are divided into four or five (or a different number) of regions by isolation regions IR. Figure 4 Shows an isolation region IR that separates two regions. Below the alternating dielectric and word line layers is a source line layer SL. Memory holes are formed in the stack of alternating dielectric and conductive layers. For example, one of the memory holes in the memory holes is labeled MH. Note that in Figure 4 the dielectric layer is depicted as transparent so that the reader can see the memory holes located in the stack of alternating dielectric and conductive layers. In one embodiment, NAND strings are formed by filling the memory holes with a material including a charge trapping material to create vertical columns of memory cells. Each memory cell can store one or more data bits. Thus, non-volatile memory cells are arranged in the memory holes. More details of a three-dimensional monolithic memory array including the memory structure 202 are provided below.

[0068] Figure 4A Is a block diagram explaining an example organization of the memory structure 202, which is divided into two planes 402 and 404. Each plane is then divided into M blocks. In one example, each plane has approximately 2000 blocks. However, different numbers of blocks and planes can also be used. In one embodiment, the memory cell block is an erase unit. That is, all the memory cells of the block are erased together. In other embodiments, the block can be divided into sub-blocks and these sub-blocks can be the erase units. Memory cells can also be grouped into blocks for other reasons, such as to organize the memory structure to enable signaling and selection circuits. In some embodiments, a block represents a group of connected memory cells because the memory cells of the block share a common set of word lines. For example, the word lines for a block are all connected to all the vertical NAND strings for that block. Although Figure 4A shows two planes 402 / 404, more or fewer than two planes can be implemented. In some embodiments, the memory structure 202 includes eight planes.

[0069] Figure 4B to Figure 4 G depicts an example three-dimensional (“3D”) NAND structure of the memory structure 202 corresponding to the Figure 4 structure and can be used to implement Figure 2A and Figure 2B of the memory structure 202. Figure 4Bis a block diagram showing a top view of portion 406 of block 2 depicting plane 402. As can be seen from Figure 4B it, Figure 4B the blocks depicted therein extend in the direction of 432. In one embodiment, the memory array has a number of layers; however, Figure 4B only the top layer is shown.

[0070] Figure 4B Depicted are a number of circles representing memory holes, also referred to as vertical columns. Each of the memory holes / vertical columns includes a number of select transistors (also referred to as select gates or selection gates) and a number of memory cells. In one embodiment, each memory hole / vertical column implements a NAND string. For example, Figure 4B a subset of memory holes / vertical columns / NAND strings 432, 436, 446, 456, 462, 466, 472, 474, and 476 are labeled.

[0071] Figure 4B Also depicted is a set of bit lines 415, including bit lines 411, 412, 413, 414, …, 419. Figure 4B Twenty-four bit lines are shown as only a portion of the block is depicted. It is envisioned that more than twenty-four bit lines are connected to the memory holes / vertical columns of the block. Each of the circles representing the memory holes / vertical columns has an “x” to indicate its connection to one of the bit lines. For example, bit line 411 is connected to memory holes / vertical columns 436, 446, 456, 466, and 476.

[0072] Figure 4B The block depicted in includes a set of isolation regions 482, 484, 486, and 488, which are formed of SiO2; however, other dielectric materials may also be used. The isolation regions 482, 484, 486, and 488 are used to divide the top layer of the block into five regions; for example, Figure 4BThe top layer depicted is divided into regions 430, 440, 450, 460, and 470. In one embodiment, the isolation regions only divide the layer for implementing the select gates such that different NAND strings in different regions can be selected independently. In an example implementation, the bit lines are connected to one memory hole / vertical column / NAND string in each of the regions 430, 440, 450, 460, and 470. In this implementation, each block has twenty-four rows of active columns, and each bit line is connected to five rows in each block. In one embodiment, all five memory holes / vertical columns / NAND strings connected to a common bit line are connected to the same set of word lines; thus, the system uses drain side select lines to select one (or another subset) of these five memory holes / vertical columns / NAND strings to undergo a memory operation (program, verify, read, and / or erase).

[0073] Figure 4B Line interconnections LI are also shown, which are metal connections from above the memory array to the source line SL. The line interconnections LI are positioned adjacent to regions 430 and 470.

[0074] Although Figure 4B it is shown that each of the regions 430, 440, 450, 460, and 470 has four rows of memory holes / vertical columns in a block, five regions, and twenty-four rows of memory holes / vertical columns, these exact numbers are example implementations. Other embodiments may include more or fewer regions per block, more or fewer rows of memory holes / vertical columns per region, and more or fewer rows of vertical columns per block. Figure 4B It is also shown that the memory holes / vertical columns are staggered. In other embodiments, different staggering patterns may be used. In some embodiments, the memory holes / vertical columns are not staggered.

[0075] Figure 4C A portion of one embodiment of a three-dimensional memory structure 202 is depicted, which shows a cross-sectional view along Figure 4B line AA. This cross-sectional view cuts through memory holes / vertical columns (NAND strings) 472 and 474 of region 470 (see Figure 4B ). Figure 4CThe structure includes two drain-side select layers SGD0 and SGD; two source-side select layers SGS0 and SGS1; two drain-side GIDL generation transistor layers SGDT0 and SGDT1; two source-side GIDL generation transistor layers SGSB0 and SGSB1; two drain-side dummy word line layers DD0 and DD1; two source-side dummy word line layers DS0 and DS1; dummy word line layers DU and DL; one hundred and sixty-two word line layers WL0 - WL161 for connecting to data memory cells, and a dielectric layer DL. Other embodiments may implement more or fewer than the quantities described above for Figure 4C as described. In one embodiment, SGD0 and SGD1 are connected together; and SGS0 and SGS1 are connected together. In other embodiments, more or fewer numbers of SGD (greater than or less than two SGD) are connected together, and more or fewer numbers of SGS (greater than or less than two SGS) are connected together.

[0076] In one embodiment, gate-induced drain leakage (GIDL) is used to perform erasing of memory cells, which includes generating charge carriers at GIDL generation transistors such that the carriers are injected into the charge trapping layer of the NAND string to change the threshold voltage of the memory cells. Figure 4C Two GIDL generation transistors are shown at each end of the NAND string; however, in other embodiments, there are more or fewer than three GIDL generation transistors. Embodiments using GIDL on both sides of the NAND string may have GIDL generation transistors on both sides. Embodiments using GIDL only on the drain side of the NAND string may have GIDL generation transistors only on the drain side. Embodiments using GIDL only on the source side of the NAND string may have GIDL generation transistors only on the source side.

[0077] Figure 4C Two GIDL generation transistors are shown at each end of the NAND string. It is likely that charge carriers are generated only by GIDL at one of the two GIDL generation transistors at each end of the NAND string. Due to process variations during manufacturing, it is likely that one of the two GIDL generation transistors at one end of the NAND string is most suitable for GIDL. For example, the GIDL generation transistor has a mutated pn junction to generate charge carriers for GIDL, and during manufacturing, phosphorus diffusion is performed at the polysilicon channel of the GIDL generation transistor. In some cases, the GIDL generation transistor with the shallowest phosphorus diffusion is the GIDL generation transistor that generates charge carriers during erasing. However, in some embodiments, charge carriers may be generated by GIDL at multiple GIDL generation transistors on a particular side of the NAND string.

[0078] Memory holes / vertical columns 472 and 474 are depicted as protruding through the drain-side select layer, source-side select layer, dummy word line layer, GIDL generation transistor layer, and word line layer. In one embodiment, each memory hole / vertical column includes a vertical NAND string. Below the memory hole / vertical column and the layers listed below are substrate 453, insulating film 454 on the substrate, and source line SL. The NAND string of memory hole / vertical column 472 has a source extreme at the bottom of the stack and a drain extreme at the top of the stack. Consistent with Figure 4B consistent, Figure 4C Vertical memory hole / column 472 connected to bit line 414 via connection member 417 is shown.

[0079] For ease of reference, the drain-side select layer; source-side select layer, dummy word line layer, GIDL generation transistor layer, and data word line layer are collectively referred to as conductive layers. In one embodiment, the conductive layer is made of a combination of TiN and tungsten. In other embodiments, other materials may be used to form the conductive layer, such as doped polysilicon, metals (such as tungsten), metal silicides (such as nickel silicide, tungsten silicide, aluminum silicide), or combinations thereof. In some embodiments, different conductive layers may be formed of different materials. Between the conductive layers is dielectric layer DL. In one embodiment, the dielectric layer is made of SiO2. In other embodiments, other dielectric materials may be used to form the dielectric layer.

[0080] Non-volatile memory cells are formed along the memory holes / vertical columns that extend through alternating conductive and dielectric layers in the stack. In one embodiment, the memory cells are arranged as NAND strings. Word line layers WL0-W161 are connected to the memory cells (also referred to as data memory cells). The dummy word line layer is connected to the dummy memory cells. The dummy memory cells do not store and are not eligible to store host data (data provided by the host, such as user data from the host), while the data memory cells are eligible to store host data. In some embodiments, the data memory cells and the dummy memory cells may have the same structure. Drain-side select layers SGD0 and SGD1 are used to electrically connect and disconnect the NAND string from the bit line. Source-side select layers SGS0 and SGS1 are used to electrically connect and disconnect the NAND string from source line SL.

[0081] Figure 4CIllustrated is a memory array implemented as a two - layer architecture, where the layers are separated by a joint region. In one embodiment, etching so many word - line layers mixed with dielectric layers is expensive and / or challenging. To alleviate this burden, one embodiment includes laying a first stack of word - line layers (e.g., WL0 - WL80) alternating with dielectric layers, laying the joint region, and laying a second stack of word - line layers (e.g., WL81 - WL161) alternating with dielectric layers. The joint region is located between the first stack and the second stack. In one embodiment, the joint region is made of the same material as the word - line layers. In other embodiments, there may be no joint region or there may be multiple joint regions.

[0082] Figure 4D Depicts a portion of an embodiment of a three - dimensional memory structure 202, which shows a cross - sectional view along Figure 4B line BB. This cross - sectional view cuts through memory holes / vertical columns (NAND strings) 432 and 434 of region 430 (see Figure 4B ). Figure 4D Illustrates the same alternating conductive and dielectric layers as Figure 4C . Figure 4D Also shown is an isolation region 482. Isolation regions 482, 484, 486, and 488 occupy space that would otherwise be used for a portion of the memory holes / vertical columns / NAND strings. For example, isolation region 482 occupies space that would otherwise be used for a portion of memory hole / vertical column 434. More specifically, a portion (e.g., half of the diameter) of vertical column 434 has been removed in layers SGDT0, SGDT1, SGD0, and SGD1 to accommodate isolation region 482. Thus, while most of vertical column 434 is cylindrical (with a circular cross - section), the portion of vertical column 434 in layers SGDT0, SGDT1, SGD0, and SGD1 has a semi - circular cross - section. In one embodiment, after forming the stack of alternating conductive and dielectric layers, the stack is etched to create space for the isolation regions, and then the space is filled with SiO2. This structure allows for individual control of SGDT0, SGDT1, SGD0, and SGD1 for regions 430, 440, 450, 460, and 470.

[0083] Figure 4E Depicts Figure 4CCross-sectional view of region 429, which includes a portion of memory hole / vertical column 472. In one embodiment, the memory hole / vertical column is circular; however, in other embodiments, other shapes may be used. In one embodiment, memory hole / vertical column 472 includes an inner core layer 490 made of a dielectric such as SiO2. Other materials may also be used. Surrounding inner core 490 is polysilicon channel 491. Materials other than polysilicon may also be used. Note that it is channel 491 that connects to the bit line and the source line. Surrounding channel 491 is tunneling dielectric 492. In one embodiment, tunneling dielectric 492 has an ONO structure. Surrounding tunneling dielectric 492 is charge trapping layer 493, such as (for example) silicon nitride. Other memory materials and structures may also be used. The techniques described herein are not limited to any particular material or structure.

[0084] Figure 4E Depicts dielectric layer DL and word line layers WL160, WL159, WL158, WL157, and WL156. Each word line layer in the word line layers includes a word line region 496 surrounded by an alumina layer 497, which is surrounded by a blocking oxide layer 498. In other embodiments, the blocking oxide layer may be a vertical layer parallel and adjacent to charge trapping layer 493. The physical interaction between the word line layer and the vertical column forms a memory cell. Thus, in one embodiment, a memory cell includes channel 491, tunneling dielectric 492, charge trapping layer 493, blocking oxide layer 498, alumina layer 497, and word line region 496. For example, word line layer WL160 and a portion of memory hole / vertical column 472 constitute memory cell MC1. Word line layer WL159 and a portion of memory hole / vertical column 472 constitute memory cell MC2. Word line layer WL158 and a portion of memory hole / vertical column 472 constitute memory cell MC3. Word line layer WL157 and a portion of memory hole / vertical column 472 constitute memory cell MC4. Word line layer WL156 and a portion of memory hole / vertical column 472 constitute memory cell MC5. In other architectures, the memory cell may have a different structure; however, the memory cell will still be the storage unit.

[0085] When a memory cell is programmed, electrons are stored in a portion of the charge trapping layer 493 associated with (e.g., within) the memory cell. In response to an appropriate voltage on the word line region 496, these electrons are attracted from the channel 491 into the charge trapping layer 493 through the tunneling dielectric 492. The threshold voltage (Vth) of the memory cell increases proportionally to the amount of charge stored. In one embodiment, programming is achieved by Fowler-Nordheim tunneling of electrons into the charge trapping layer. During an erase operation, the electrons return to the channel or holes are injected into the charge trapping layer to recombine with the electrons. In one embodiment, erase is achieved using hole injection into the charge trapping layer via a physical mechanism such as GIDL.

[0086] Figure 4F is Figure 4 to Figure 4E A schematic view of a portion of the three-dimensional memory array 202 depicted in. Figure 4F Shows physical data word lines WL0 - WL161 extending across the entire block. Figure 4F The structure corresponding to Figure 4A Portion 406 in block 2 of, including bit line 411. Within the block, in one embodiment, each bit line is connected to five NAND strings, one NAND string in each of regions 430, 440, 450, 460, 470. Thus, Figure 4F Shows bit line 411 connected to NAND string NS0 (which corresponds to memory hole / vertical column 436 in region 430), NAND string NS1 (which corresponds to memory hole / vertical column 446 in region 440), NAND string NS2 (which corresponds to vertical column 456 in region 450), NAND string NS3 (which corresponds to memory hole / vertical column 466 in region 460), and NAND string NS4 (which corresponds to memory hole / vertical column 476 in region 470).

[0087] The drain - side selection line / layer SGD0 is separated by isolation regions isolation regions 482, 484, 486, and 488 to form SGD0 - s0, SGD0 - s1, SGD0 - s2, SGD0 - s3, and SGD0 - s4 so as to be separately connected to and independently control regions 430, 440, 450, 460, 470. Similarly, the drain - side selection line / layer SGD1 is separated by isolation regions 482, 484, 486, and 488 to form SGD1 - s0, SGD1 - s1, SGD1 - s2, SGD1 - s3, and SGD1 - s4 so as to be separately connected to and independently control regions 430, 440, 450, 460, 470; the drain - side GIDL - generating transistor control line / layer SGDT0 is separated by isolation regions 482, 484, 486, and 488 to form SGDT0 - s0, SGDT0 - s1, SGDT0 - s2, SGDT0 - s3, and SGDT0 - s4 so as to be separately connected to and independently control regions 430, 440, 450, 460, 470; the drain - side GIDL - generating transistor control line / layer SGDT1 is separated by isolation regions 482, 484, 486, and 488 to form SGDT1 - s0, SGDT1 - s1, SGDT1 - s2, SGDT1 - s3, and SGDT1 - s4 so as to be separately connected to and independently control regions 430, 440, 450, 460, 470.

[0088] Figure 4F Only the NAND strings connected to bit line 411 are shown. However, a complete schematic of the block would show each bit line and the five vertical NAND strings (which are in separate regions) connected to each bit line.

[0089] Although Figure 4 to Figure 4F the example memory is a three - dimensional memory structure including vertical NAND strings having a charge - trapping material, other (2D and 3D) memory structures may also be used with the techniques described herein.

[0090] The memory system discussed above can be erased, programmed, and read. At the end of a successful programming process, the threshold voltage of the memory cells should be appropriately within one or more distributions of the threshold voltage of the programmed memory cells or within the distribution of the threshold voltage of the erased memory cells. Figure 5A is a graph of threshold voltage versus the number of memory cells and illustrates an example threshold voltage distribution of a memory array when each memory cell stores one data bit per memory cell. A memory cell that stores one data bit per memory cell is referred to as a single - level cell (“SLC”). The data stored in an SLC memory cell is referred to as SLC data; thus, SLC data includes one bit per memory cell. The data stored as one bit per memory cell is SLC data.Figure 5A Shows two threshold voltage distributions: E and P. The threshold voltage distribution E corresponds to the erased data state. The threshold voltage distribution P corresponds to the programmed data state. Memory cells having threshold voltages in the threshold voltage distribution E are thus in the erased data state (e.g., they are erased). Memory cells having threshold voltages in the threshold voltage distribution P are thus in the programmed data state (e.g., they are programmed). In one embodiment, the erased memory cells store data “1” and the programmed memory cells store data “0”. Figure 5A Depicts a read reference voltage Vr. By testing (e.g., performing one or more sense operations) whether the threshold voltage of a given memory cell is above or below Vr, the system can determine whether the memory cell is erased (state E) or programmed (state P). Figure 5A Also depicts a verify reference voltage Vv. In some embodiments, when programming memory cells to the data state P, the system will test whether those memory cells have a threshold voltage greater than or equal to Vv.

[0091] Figure 5B to Figure 5D Illustrates an example threshold voltage distribution of a memory array when each memory cell stores multiple bits of data per memory cell. Memory cells that store multiple bits of data per memory cell are referred to as multi-level cells (“MLC”). The data stored in an MLC memory cell is referred to as MLC data; thus, MLC data includes multiple bits per memory cell. Data stored as multiple data bits per memory cell is MLC data. In Figure 5B the example embodiment, each memory cell stores two data bits. Other embodiments may use other data capacities per memory cell (e.g., such as three, four, or five data bits per memory cell).

[0092] Figure 5B Shows a first threshold voltage distribution E of erased memory cells. Also depicts three threshold voltage distributions A, B, and C of programmed memory cells. In one embodiment, the threshold voltages in distribution E are negative and the threshold voltages in distributions A, B, and C are positive. Figure 5B Each different threshold voltage distribution corresponds to a predetermined value of a set of data bits. In one embodiment, each of the two data bits stored in a memory cell is in a different logical page (referred to as the lower page (LP) and the upper page (UP)). In other embodiments, all of the data bits stored in a memory cell are in a common logical page. The specific relationship between the data programmed into a memory cell and the threshold voltage level of the cell depends on the data encoding scheme employed for the cell. Table 1 provides an example encoding scheme.

[0093] Table 1

[0094] E A B C LP 1 0 0 1 UP 1 1 0 0

[0095] In one implementation, referred to as full sequence programming, the process of Figure 6 discussed below can be used to program memory cells directly from an erased data state E to any one of programmed data states A, B, or C. For example, a population of memory cells to be programmed can first be erased so that all memory cells in the population are in the erased data state E. Then, the memory cells are directly programmed to data states A, B, and / or C using a programming process. For example, while some memory cells are being programmed from data state E to data state A, other memory cells are being programmed from data state E to data state B and / or from data state E to data state C. Figure 5B The arrows of

[0096] Figure 5C depict an example threshold voltage distribution of memory cells, where each memory cell stores three data bits per memory cell (which is another example of MLC data). Figure 5C shows eight threshold voltage distributions corresponding to eight data states. The first threshold voltage distribution (data state) Er represents erased memory cells. The other seven threshold voltage distributions (data states) A through G represent programmed memory cells and are therefore also referred to as programmed states. Each threshold voltage distribution (data state) corresponds to a predetermined value of a set of data bits. The specific relationship between the data programmed into a memory cell and the threshold voltage level of the cell depends on the data encoding scheme employed for the cell. In one implementation, a Gray code assignment is used to assign data values to threshold voltage ranges such that if the threshold voltage of a memory erroneously shifts to its adjacent physical state, only one bit will be affected. Table 2 provides an example of an encoding scheme for an implementation in which each of the three data bits stored in a memory cell is in a different logical page (referred to as the lower page (LP), middle page (MP), and upper page (UP)).

[0097] Table 2

[0098] Er A B C D E F G UP 1 1 1 0 0 0 0 1 MP 1 1 0 0 1 1 0 0 LP 1 0 0 0 0 1 1 1

[0099] Figure 5CSeven read reference voltages VrA, VrB, VrC, VrD, VrE, VrF, and VrG for reading data from memory cells are shown. By testing (e.g., performing a sensing operation) whether the threshold voltage of a given memory cell is higher or lower than the seven read reference voltages, the system can determine what data state (i.e., A, B, C, D, …) the memory cell is in.

[0100] Figure 5C Seven verification reference voltages VvA, VvB, VvC, VvD, VvE, VvF, and VvG are also shown. In some embodiments, when programming a memory cell to data state A, the system will test whether those memory cells have a threshold voltage greater than or equal to VvA. When programming a memory cell to data state B, the system will test whether the memory cell has a threshold voltage greater than or equal to VvB. When programming a memory cell to data state C, the system will determine whether the memory cell has a threshold voltage greater than or equal to VvC. When programming a memory cell to data state D, the system will test whether those memory cells have a threshold voltage greater than or equal to VvD. When programming a memory cell to data state E, the system will test whether those memory cells have a threshold voltage greater than or equal to VvE. When programming a memory cell to data state F, the system will test whether those memory cells have a threshold voltage greater than or equal to VvF. When programming a memory cell to data state G, the system will test whether those memory cells have a threshold voltage greater than or equal to VvG. Figure 5C Vev is also shown, which is an erase verification reference voltage for testing whether a memory cell has been properly erased.

[0101] In embodiments that utilize full-sequence programming, the Figure 6 process (discussed below) can be used to program a memory cell directly from an erased data state Er to any one of programmed data states A through G. For example, first, a population of memory cells to be programmed can be erased so that all memory cells in the population are in the erased data state Er. Then, the memory cells are directly programmed to data states A, B, C, D, E, F, and / or G using a programming process. For example, when some memory cells are being programmed from data state Er to data state A, other memory cells are being programmed from data state Er to data state B and / or from data state Er to data state C, and so on. Figure 5C The arrows of the

[0102] Generally, during a verify operation and a read operation, a selected word line is connected to a voltage (an example of a reference signal), and for each read operation (e.g., see Figure 5C the read comparison voltages / levels VrA, VrB, VrC, VrD, VrE, VrF, and VrG) or verify operation (e.g., see Figure 5C the verify target voltages / levels VvA, VvB, VvC, VvD, VvE, VvF, and VvG), the level of this voltage is specified to determine whether the threshold voltage of the memory cell of interest has reached this level. After applying the word line voltage, the conduction current of the memory cell is measured to determine whether the memory cell turns on (conducts current) in response to the voltage applied to the word line. If the conduction current is measured to be greater than a specific value, it is assumed that the memory cell is on and the voltage applied to the word line is greater than the threshold voltage of the memory cell. If the conduction current is not measured to be greater than the specific value, it is assumed that the memory cell is not on and the voltage applied to the word line is not greater than the threshold voltage of the memory cell. During a read or verify process, unselected memory cells are provided with one or more read pass voltages (also referred to as bypass voltages) at their control gates such that these memory cells will operate as pass gates (e.g., conduct current regardless of whether they are programmed or erased).

[0103] There are many ways to measure the conduction current of a memory cell during a read or verify operation. In one example, the conduction current of the memory cell is measured by the rate at which the memory cell discharges or charges a dedicated capacitor in a sense amplifier. In another example, the conduction current of the selected memory cell allows (or does not allow) a NAND string including the memory cell to discharge a corresponding bit line. The voltage on the bit line is measured after a period of time to see if it has been discharged. Note that the techniques described herein can be used with different methods for verify / read known in the art. Other read and verify techniques known in the art can also be used.

[0104] Figure 5D Depicts the threshold voltage distribution when each memory cell stores four data bits (another example of MLC data). Figure 5DDepicts that there may be some overlap between the threshold voltage distributions (data states) S0 to S15. The overlap may occur due to factors such as a memory cell losing charge (and thus the threshold voltage decreasing). Programming interference may inadvertently increase the threshold voltage of a memory cell. Similarly, read interference may inadvertently increase the threshold voltage of a memory cell. Over time, the position of the threshold voltage distribution may change. Such a change may increase the bit error rate, thereby increasing the decoding time or even making decoding impossible. Changing the read reference voltage can help mitigate such effects. Using ECC during the read process can correct errors and ambiguities. Note that in some embodiments, the threshold voltage distributions of a population of memory cells storing four data bits per memory cell do not overlap and are separated from each other. Figure 5D The threshold voltage distribution will include a read reference voltage and a verify reference voltage, as discussed above.

[0105] When using four bits per memory cell, the memory can be programmed using the full-sequence programming discussed above or a multi-pass programming process known in the art. Figure 5D Each threshold voltage distribution (data state) corresponds to a predetermined value of a set of data bits. The specific relationship between the data programmed into a memory cell and the threshold voltage level of the cell depends on the data encoding scheme employed for the cell. Table 3 provides an example of an encoding scheme for an embodiment in which each of the four data bits stored in a memory cell is in a different logical page (referred to as the lower page (LP), middle page (MP), upper page (TP), and top page (TP)).

[0106] Table 3

[0107] S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 TP 1 1 1 1 1 0 0 0 0 0 1 1 0 0 0 1 UP 1 1 0 0 0 0 0 0 1 1 1 1 1 1 0 0 MP 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 LP 1 0 0 0 1 1 0 0 0 0 0 1 1 1 1 1

[0108] Figure 6 Is a flowchart depicting one embodiment of a process for programming a memory cell. For the purposes of this document, the terms program and programming are synonymous with write and writing. In one example embodiment, one or more of the control circuits discussed above (e.g., system control logic 260, column control circuit 210, row control circuit 220) are used to perform Figure 6 the process on the memory array 202. In one example embodiment, Figure 6The process is performed by the integrated memory component 207 using one or more control circuits (e.g., system control logic 260, column control circuit 210, row control circuit 220) of the control die 211 to program the memory cells on the memory die 201. The process includes multiple loops, and each loop in the multiple loops includes a programming phase and a verification phase. The execution Figure 6 of the process is to achieve full-sequence programming and other programming schemes including multi-stage programming. When implementing multi-stage programming, Figure 6 the process is used to implement any / each stage of the multi-stage programming process.

[0109] Generally, during a programming operation, the programming voltage applied to the control gate (via a selected data word line) is applied as a series of programming voltage pulses. Between the programming voltage pulses is a set of verification pulses (e.g., voltage pulses) for performing verification. In many embodiments, the amplitude of the programming voltage pulses increases by a predetermined step with each successive pulse. In Figure 6 step 602 of, the programming voltage signal (Vpgm) is initialized to a starting amplitude (e.g., about 12V to 16V or another suitable level), and the programming counter PC maintained by the state machine 262 is initialized to 1. In one embodiment, the group of memory cells selected for programming (referred to herein as the selected memory cells) are programmed concurrently and all connected to the same word line (the selected word line). There may be other memory cells not selected for programming (unselected memory cells), and these memory cells are also connected to the selected word line. That is, the selected word line will also be connected to memory cells for which programming should be prohibited. Additionally, when a memory cell reaches its intended target data state, further programming of these memory cells is prohibited. Those NAND strings (e.g., unselected NAND strings) including the memory cells connected to the selected word line for which programming should be prohibited have their channels boosted to prohibit programming. When the channel has a boosted voltage, the voltage difference between the channel and the word line is not large enough to cause programming. To assist in boosting, in step 604, the control die will pre-charge the channels of the NAND strings including the memory cells connected to the selected word line for which programming should be prohibited. In step 606, the channels of the NAND strings including the memory cells connected to the selected word line for which programming should be prohibited are boosted to prohibit programming. Such NAND strings are referred to herein as "unselected NAND strings". In one embodiment, the unselected word line receives one or more boosted voltages (e.g., about 7 volts to 11 volts) to perform a boosting scheme. A programming inhibit voltage is applied to the bit lines coupled to the unselected NAND strings.

[0110] In step 608, a programming voltage pulse of the programming voltage signal Vpgm is applied to the selected word line (the word line selected for programming). If the memory cells on the NAND string are to be programmed, the corresponding bit line is biased to a programming enable voltage. In step 608, the programming pulses are applied concurrently to all the memory cells connected to the selected word line such that all the memory cells connected to the selected word line are programmed concurrently (unless programming of them is prohibited). That is, they are programmed at the same time or during overlapping times (both of which are considered concurrent). In this way, all the memory cells connected to the selected word line will have their threshold voltages changed concurrently, unless programming of them is prohibited.

[0111] In step 610, a programming verification is performed, which includes testing whether the memory cells being programmed have successfully reached their target data states. The memory cells that have reached their target states are locked against further programming by the control die. Step 610 includes performing the verification of the programming by sensing at one or more verification reference levels. In one embodiment, the verification process is performed by testing whether the threshold voltages of the memory cells selected for programming have reached appropriate verification reference voltages. In step 610, the memory cells can be locked after they have been verified (by testing of Vt) to have reached their target states.

[0112] In one embodiment of step 610, intelligent verification techniques are used such that the system verifies only a subset of the data states during the programming loop (steps 604 to 628). For example, a first programming loop includes verifying data state A (see Figure 5C ), and depending on the result of the verification operation, a second programming loop can verify data states A and B, and depending on the result of the verification operation, a third programming loop can verify data states B and C, and so on.

[0113] In step 616, the number of memory cells that have not reached their corresponding target threshold voltage distributions is counted. That is, the number of memory cells that have so far failed to reach their target states is counted. This counting can be done by the state machine 262, the memory controller 120, or another circuit. In one embodiment, there is an overall count that reflects the total number of the currently programmed memory cells that failed the last verification step. In another embodiment, separate counts are maintained for each data state.

[0114] In step 617, the system determines whether the verification operation in the most recent execution of step 610 included verification of the last data state (e.g., Figure 5CData state G). If so, in step 618, it is determined whether the count from step 616 is less than or equal to a predetermined limit. In one embodiment, the predetermined limit is the number of bits that can be corrected by an error correction code (ECC) during the read process for a page of memory cells. If the number of failed cells is less than or equal to the predetermined limit, the programming process can stop and a "pass" status is reported in step 614. In this case, enough memory cells are programmed correctly such that the ECC can be used during the read process to correct the few remaining memory cells that have not been fully programmed. In some embodiments, the predetermined limit used in step 618 is lower than the number of bits that can be corrected by an error correction code (ECC) during the read process to allow for future / additional errors. When programming less than all memory cells for a page, the predetermined limit can be a portion (proportional or non-proportional) of the number of bits that can be corrected by the ECC during the read process for a page of memory cells. In some embodiments, the limit is not predetermined. Instead, the limit changes based on the number of errors that have been counted for the page, the number of program-erase cycles that have been performed, or other criteria.

[0115] If in step 617 it is determined that the verification operation in the most recent execution of step 610 does not include verifying the final data state, or in step 618 it is determined that the number of failed memory cells is not less than the predetermined limit, then in step 619, the data state to be verified in the next execution of step 610 (in the next programming loop) is adjusted according to the intelligent verification scheme discussed above. In step 620, the programming counter PC is checked against the programming limit value (PL). Examples of programming limit values include 6, 12, 16, 19, 20, and 30; however, other values can be used. If the programming counter PC is not less than the programming limit value PL, the programming process is considered to have failed, and a failed status is reported in step 624. If the programming counter PC is less than the programming limit value PL, the process continues at step 626, during which the programming counter PC is incremented by 1 and the programming voltage signal Vpgm is incremented stepwise to the next amplitude. For example, the next pulse will have an amplitude that is a larger step ΔVpgm (e.g., a step of 0.1 volts to 1.0 volts) than the previous pulse. After step 626, the process continues at step 604, and another programming pulse is applied to the selected word line (through the die) such that Figure 6 another programming loop (steps 604 to 626) of the programming process is performed.

[0116] In one embodiment, the memory cells are erased prior to programming. Erasing is the process of changing the threshold voltage of one or more memory cells from a programmed data state to an erased data state. For example, changing the threshold voltage of one or more memory cells from Figure 5A state P to state E, fromFigure 5B The state A / B / C of Figure 5C changes from state A to G to state Er or from Figure 5D The states S1 to S15 of change to state S0. In one embodiment, the control circuit is configured to program the memory cells in a direction from an erased data state towards the highest data state (e.g., from data state Er to data state G), and to erase the memory cells in a direction from the highest data state towards the erased data state (e.g., from data state G to data state Er).

[0117] One technique for erasing memory cells in some memory devices is to bias a p-well (or other type of) substrate to a high voltage to charge the NAND channel. An erase enable voltage (e.g., a low voltage) is applied to the control gate of the memory cell while the NAND channel is at a high voltage to erase the memory cell. In this document, this is referred to as p-well erase.

[0118] Another method for erasing memory cells is to generate a gate-induced drain leakage (“GIDL”) current to charge the NAND string channel. An erase enable voltage is applied to the control gate of the memory cell while maintaining the NAND string channel potential to erase the memory cell. In this document, this is referred to as GIDL erase. Both p-well erase and GIDL erase can be used to lower the threshold voltage (Vt) of the memory cells.

[0119] In one embodiment, a GIDL current is generated by causing a drain-gate voltage at a GIDL generation transistor (e.g., a transistor connected to SGDT0, SGDT1, SGSB0, and SGSB1). In some embodiments, a select gate (e.g., SGD or SGS) can be used as the GIDL generation transistor. The drain-gate voltage of the transistor that generates the GIDL current is referred to as the GIDL voltage in this document. When the drain voltage of the GIDL generation transistor is significantly higher than the control gate voltage of the GIDL generation transistor, a GIDL current can be generated. The GIDL current is the result of carrier generation, i.e., electron-hole pairs are generated due to band-to-band tunneling and / or trap-assisted generation. In one embodiment, the GIDL current may cause one type of carrier (also referred to as a charge carrier) (e.g., holes) to mainly move into the NAND channel, thereby raising or changing the potential of the channel. Another type of carrier (e.g., electrons) is extracted from the channel in the direction of the bit line or in the direction of the source line by an electric field. During erase, holes can tunnel from the channel to the charge storage region of the memory cell (e.g., tunnel to the charge trapping layer 493) and recombine with electrons there to lower the threshold voltage of the memory cell.

[0120] GIDL current can be generated at either (or both) ends of the NAND string. A first GIDL voltage can be generated between two terminals of a GIDL generation transistor (e.g., connected to SGDT0, SGDT1) connected to or near the bit line to generate a first GIDL current. A second GIDL voltage can be generated between two terminals of a GIDL generation transistor (e.g., SGSB0, SGSB1) connected to or near the source line to generate a second GIDL current. Erasure based on GIDL current at only one end of the NAND string is referred to as one-sided GIDL erasure. Erasure based on GIDL currents at both ends of the NAND string is referred to as two-sided GIDL erasure. The techniques described herein can be used with one-sided GIDL erasure and two-sided GIDL erasure.

[0121] In prior art systems, when existing data currently stored in a set of non-volatile memory cells is to be overwritten with new data, the non-volatile memory cells are first erased to an erased state and then programmed with the new data. For example, if a memory cell is storing existing data corresponding to a memory cell that is in programmed data state G (see Figure 5C ) and this existing data is to be overwritten with new data corresponding to a memory cell that is in programmed data state F, the memory cell is first erased to data state Er and then programmed to data state F. This process uses additional time to perform the erasure and full programming. It is proposed to accelerate the programming process by forgoing the time spent erasing the non-volatile memory cells to the erased state and instead adjusting the non-volatile memory cells from directly storing the existing data to storing the new data. In the above example, rather than erasing the memory cell from data state G to data state Er and then programming it to data state F, the threshold voltage of the memory cell is adjusted such that the memory cell transitions directly from data state G to data state F without first being erased to data state Er (and without being erased to any other data state with a threshold voltage lower than the target data state F). Thus, the non-volatile memory is configured to transition a memory cell from a programmed data state with a higher threshold voltage range to a programmed data state with a lower threshold voltage range without transitioning the memory cell to an erased data state, which accelerates the programming process and increases the endurance of the memory cells because these memory cells undergo fewer erasures and fewer programming operations.

[0122] Figure 7 is a flowchart depicting one embodiment of a process for transitioning a memory cell from a programmed data state with a higher threshold voltage range to a programmed data state with a lower threshold voltage range without transitioning the memory cell to an erased data state. In one embodiment, Figure 7The process may be performed by any one of the one or more control circuits discussed above. Figure 7 The process may be performed entirely by the control circuit on the memory die 200 (see Figure 2A ) or entirely by the control circuit on the integrated memory component 207 (see Figure 2B ), rather than by the memory controller 120. In one example, Figure 7 the process is performed by the state machine 262 or under its guidance using other components of the system control logic 260, column control circuit 210, and row control circuit 220. In another implementation, Figure 7 the process is performed by the memory controller 120 or under its guidance. Figure 7 The process may be performed on a memory implementing any one of the structures depicted in Figure 1 to Figure 4F or other memory structures.

[0123] In step 702, the control circuit receives new data to be programmed into a set of non-volatile memory cells that already store existing data in a set of data states. Each of these data states corresponds to a threshold voltage range. The set of data states includes an erased data state (e.g., Figure 5C Er) and programmed data states (e.g., Figure 5C A through G). The programmed data states include a first data state (e.g., Figure 5C data state A) that is adjacent to the erased data state in terms of threshold voltage and a highest data state (e.g., Figure 5C data state G) that is the farthest from the erased data state. The highest data state has the highest threshold voltage range of the set of data states.

[0124] In step 704, the control circuit compares the new data with the existing data to identify a subset of memory cells that are in a programmed data state with a higher threshold voltage range and need to transition to a programmed data state with a lower threshold voltage range. For example, if a particular memory cell is storing existing data 101 of UP / MP / LP corresponding to data state G (see Table 2) and is targeted to store new data 000 of UP / MP / LP corresponding to data state C (see Table 2), then that particular memory cell is identified as a memory cell that needs to transition from data state G to data state C. In an embodiment, step 704 is performed to identify all memory cells that need to transition from a first data state with a higher threshold voltage range to a second data state with a lower threshold voltage range. In another embodiment, step 704 is performed to identify all memory cells that need to transition from any one of the programmed data states to another of the programmed data states with a lower threshold voltage range. For example, the control circuit may identify some memory cells that need to transition from data state F to data state E, some memory cells that need to transition from data state F to data state C, some memory cells that need to transition from data state G to data state B, some memory cells that need to transition from data state D to data state A, some memory cells that need to transition from data state B to data state Er, etc.

[0125] In step 706, the control circuit transitions the identified memory cells from a programmed data state with a higher threshold voltage range to a programmed data state with a lower threshold voltage range without transitioning the identified memory cells to an erased data state. In one embodiment, step 706 includes transitioning multiple subsets of memory cells from multiple programmed data states with a higher threshold voltage range to a programmed data state with a lower threshold voltage range without transitioning the identified memory cells to an erased data state (e.g., transitioning some memory cells from data state F to data state E, some memory cells from data state F to data state C, some memory cells from data state G to data state B, some memory cells from data state D to data state A, some memory cells that need to transition from data state B to data state Er, etc.). In one embodiment, step 706 includes adjusting the threshold voltage of the memory cells during the transition from a programmed data state with a higher threshold voltage range to a programmed data state with a lower threshold voltage range, and stopping the adjustment of the threshold voltage after completion of the transition from a programmed data state with a higher threshold voltage range to a programmed data state with a lower threshold voltage range.

[0126] In step 708, the control circuit performs other memory operations after the transition. For example, other memory cells can be programmed, read, and erased. In step 710, the control circuit persistently maintains the identified memory cell in a programmed data state with a lower threshold voltage range during and after the other memory operations of step 708 (and after the transition). In one embodiment (as explained below), the control circuit is configured to verify that the first memory cell is in the second programmed data state during / after the transition. In Figure 7 the embodiment, as explained above, the control circuit is configured to transition the first memory cell from the first programmed data state to the second programmed data state in order to change the data stored in the first memory cell.

[0127] Figure 8 is a flowchart depicting one embodiment of a process for transitioning a memory cell from a programmed data state having a higher threshold voltage range to a programmed data state having a lower threshold voltage range without transitioning the memory cell to an erased data state. Figure 8 The process of Figure 7 is a specific implementation example of steps 702 to 706 of Figure 8 . In one embodiment, Figure 8 the process of Figure 2A can be performed entirely by the control circuit on the memory die 200 (see Figure 2B ) or entirely by the control circuit on the integrated memory component 207 (see Figure 8 ), rather than by the memory controller 120. In one example, Figure 8 the process of Figure 8 is performed by the state machine 262 or by other components of the system control logic 260, column control circuit 210, and row control circuit 220 under its guidance. In another embodiment, Figure 1 to Figure 4F the process of

[0128] In Figure 8In step 802, the control circuit receives new data to be programmed into a set of non-volatile memory cells that already store existing data in a set of data states. Step 802 is similar to step 702. In step 804, in response to receiving the new data in step 802, the control circuit reads the existing data in the non-volatile memory cells targeted to store the new data received in step 802. In one embodiment, step 804 includes performing a read process to read data from the memory structure 202. If step 802 is being executed by the memory controller 120, then step 804 includes the memory controller 804 issuing one or more read commands, and the state machine 262 executing these read commands. In step 806, the control circuit compares the new data received in step 802 with the existing data read in step 804. Steps 804 and 806 together are similar to step 704. In step 808, based on the comparison of step 806, the control circuit identifies a subset of memory cells in a programmed data state with a higher threshold voltage range that need to transition to a programmed data state with a lower threshold voltage range. In step 810, a de-state operation is performed. For the purposes of this document, the de-state operation includes reducing the data state of the memory cells from a programmed data state with a higher threshold voltage range to a programmed data state with a lower threshold voltage range (e.g., from programmed data state F to programmed data state C). In one embodiment, the de-state operation includes applying a de-state voltage pulse to the memory cells identified in step 808 for de-state transition while prohibiting de-state transition for those memory cells not identified in step 808 (more details will be explained regarding Figure 9 ).

[0129] In step 812, the control circuit performs a verification operation to verify that the identified memory cells have reached and are in a programmed data state with a lower threshold voltage range. The verification process of step 812 may include testing whether the threshold voltage of the memory cells transitioning to the target programmed data state with a lower threshold voltage range has a threshold voltage less than the highest threshold voltage of the target programmed data state with a lower threshold voltage range. For example, if the memory cells are transitioning from programmed data state G (see Figure 5C ) to programmed data state F, then step 812 may include determining whether the threshold voltage of the memory cells being transitioned is lower than Vfd (see Figure 5C)。In another embodiment, the verification process of step 812 may include testing whether the threshold voltage of a memory cell that is transitioning to a programmed data state with a lower threshold voltage range has a threshold voltage that is less than the highest threshold voltage of the target programmed data state with the lower threshold voltage range and greater than the lowest threshold voltage of the target programmed data state with the lower threshold voltage range. For example, if a memory cell is transitioning from the programmed data state G (see Figure 5C ) to the programmed data state F, then step 812 may include determining whether the threshold voltage of the memory cell being transitioned is below Vfd and above VvF. Other variations for verification may also be used (including other tests and other test voltages).

[0130] If all memory cells transitioning to a programmed data state with a lower threshold voltage range have successfully passed the verification process of step 812, then (step 816) Figure 8 the process has passed (been successfully completed). In some embodiments, if at least a minimum number of memory cells being transitioned successfully pass the verification process of step 812, then Figure 8 the process has passed (been successfully completed). If not all (or not enough) memory cells transitioning to a programmed data state with a lower threshold voltage range have successfully passed the verification process of step 812, then in step 818 it is determined whether the maximum number of erase state voltage pulses (e.g., 2 to 6 erase state voltage pulses) has been applied. If so, then Figure 8 the process has failed (820). If fewer than the maximum number of erase state voltage pulses have been applied, then in step 822, the control circuit increases the amplitude of the next erase state voltage pulse (e.g., by 0.1v to 1v), and the process loops back to step 810 to repeat steps 810 to 822, including applying another erase state voltage pulse. Figure 8 the process may be performed once for each type of transition (e.g., once for G to F, once for G to E, once for G to D, …, once for F to E, once for F to D, …), or Figure 8 the process may be performed concurrently for multiple or all types of transitions for each combination of programmed data states (e.g., concurrently for G to F, G to E, G to D, …, F to E, F to D, …).

[0131] Figure 9 is a signal timing diagram depicting an example implementation of step 810 for performing the erase state operation. Figure 9depicts the following signals: Sel BL, Unsel BL, Sel SGDT0 / 1, Unsel SGDT0 / 1, SGD0 / 1, DD0 / 1, WL0 to WLx-1, WLx, WLx+1 to WL161, DS0 / 1, SGS0 / 1, SGSB0 / 1, and SL. The signal Sel BL is the voltage applied to all bit lines connected to NAND strings having memory cells identified in step 808 as being programmed to transition from a programming data state with a higher threshold voltage range to a programming data state with a lower threshold voltage range. The signal Unsel BL is the voltage applied to all bit lines connected to NAND strings not having memory cells identified in step 808 as being programmed to transition from a programming data state with a higher threshold voltage range to a programming data state with a lower threshold voltage range. The signal Sel SGDT0 / 1 is the voltage applied to SGDT0 and SGDT1 for regions (e.g., 430, 440, 450, 460, 470) selected for performing Figure 8 the process. The signal Unsel SGDT0 / 1 is the voltage applied to SGDT0 and SGDT1 for regions not selected for performing Figure 8 the process. The signal SGD0 / 1 is the voltage applied to SGD0 and SGD1 for all regions of the selected block (e.g., 430, 440, 450, 460, 470). Thus, SGD0 / 1 is the voltage applied to SGD0-s0, SGD1-s0, SGD0-s1, SGD1-s1, SGD0-s2, SGD1-s2, SGD0-s3, SGD1-s3, SGD0-s4, and SGD1-s4. The signal DD0 / 1 is the voltage applied to DD0 and DD1. The signal WLx is the voltage applied to the selected word line (the word line connected to the memory cell programmed to transition from a programming data state with a higher threshold voltage range to a programming data state with a lower threshold voltage range). The signals WL0 to WLx+1 are the voltages applied to the unselected word lines on the source side of the selected word line. The signals WLx+1 to WL161 are the voltages applied to the unselected word lines on the drain side of the selected word line. The signal DS0 / 1 is the voltage applied to DS0 and DS1. The signal SGS0 / 1 is the voltage applied to SGS0 and SGS1 for all regions of the selected block (e.g., 430, 440, 450, 460, 470). The signal SGSB0 / 1 is the voltage applied to SGSB0 and SGSB1 for all regions of the selected block (e.g., 430, 440, 450, 460, 470). The signal SL is the voltage applied to the source line SL.

[0132] All signals start at Vss (ground or 0v). Sel BL is raised to Vdestate (e.g., 18 volts). Vdestate is an example of an erase voltage. Although Figure 9 the Vdestate applied to Sel BL is shown as a voltage pulse, other waveforms can also be used. Additionally, Unsel BL is raised to Vdestate - 7.6v, Sel SGDT0 / 1 is raised to Vdestate - 11.2v, Unsel SGDT0 / 1 is raised to Vdestate, SGD0 / 1 is raised to Vdestate - 7.6v, DD0 / 1 is raised to Vdestate - 10.4v, WL0 to WLx - 1 are raised to Vdestate - 7.6v, WLx + 1 to WL161 are raised to Vdestate - 7.6v, WLx is held at 0v (or near 0v), DS0 / 1 is raised to Vdestate - 10.4v, SGS0 / 1 is raised to Vdestate - 10.v, SGSB0 / 1 is raised to Vdestate - 10.4v, and SL is floating. All signals will return to Vss (ground or 0v).

[0133] These voltage conditions cause GIDL to occur at the drain side of the NAND strings (at SGDT0 and / or SGDT1) that have memory cells identified in step 808 as being programmed to transition from a programming data state with a higher threshold voltage range to a programming data state with a lower threshold voltage range, and inhibit GIDL from occurring in NAND strings that do not have memory cells identified in step 808 as being transitioned. GIDL causes holes to be generated in the channels of the corresponding NAND strings, and these holes will enter the corresponding charge trapping layer 493 to lower the threshold voltage of the memory cells that are to be transitioned from a programming data state with a higher threshold voltage range to a programming data state with a lower threshold voltage range without transitioning to the erase state. For example, a memory cell can be directly transitioned from data state G to data state F by lowering the threshold voltage of the memory cell from above Vvg to below Vfd without first entering data state Er (see Figure 5C ). In some embodiments, two conditions need to be met for GIDL to occur: (1) a high voltage (e.g., Vdestate) needs to be on the BL, and (2) SGDT0 / 1 needs to be low enough (e.g., Vdestate - 11.2V). To inhibit GIDL, Unsel SGDT0 / 1 is raised to Vdestate. Note that Figure 9 the voltages depicted in

[0134] Figure 10 is a flowchart depicting one embodiment of a process for adjusting the speed at which memory cells are transitioned from a programmed data state having a higher threshold voltage range to a programmed data state having a lower threshold voltage range without transitioning the memory cells to an erased data state. Some memory cells may change their threshold voltage faster than other memory cells. Additionally, over time, the rate of change of the threshold voltage may become slower or faster. Thus, in one embodiment, a process for tuning the erase state speed of memory cells (e.g., tuning the speed at which memory cells change their threshold voltage during step 810) is presented. That is, the control circuit is configured to adjust the speed of the transition based on the rate of change of the threshold voltage of the memory cells.

[0135] In one embodiment, Figure 10 the process may be performed by any one of the one or more control circuits discussed above. Figure 10 the process may be performed entirely by the control circuit on the memory die 200 (see Figure 2A ) or entirely by the control circuit on the integrated memory component 207 (see Figure 2B ) and not by the memory controller 120. In one example, Figure 8 the process is performed by the state machine 262 or by other components of the system control logic 260, column control circuit 210, and row control circuit 220 under its guidance. In another embodiment, Figure 10 the process is performed by the memory controller 120 or under its guidance. Figure 10 the process may be performed on a memory implementing any one of the structures depicted in Figure 1 to Figure 4F or other memory structures.

[0136] In Figure 10 step 1002 of Figure 8The process. In step 1004, the control circuit detects the erase state speed of the memory cells. For example, the control circuit can sense whether the threshold voltage of the memory cells is higher or lower than one or more test voltages. Those memory cells having a threshold voltage lower than the test voltage are considered faster speed memory cells and their GIDL can be slowed down. There can be multiple test voltages such that the amount of GIDL slowdown is determined by how much lower the threshold voltage of the memory cell is than the test voltage. In one embodiment, there can be three test voltages: a low test voltage, a middle test voltage, and a high test voltage, such that the memory cells having a threshold voltage lower than the low test voltage are slowed down the most, the memory cells having a threshold voltage lower than the middle test voltage and higher than the low test voltage are slowed down less, the memory cells having a threshold voltage lower than the high test voltage and higher than the middle test voltage are slowed down the least, and the memory cells having a threshold voltage higher than the high test voltage are not slowed down. In step 1006, the control circuit tunes the erase state speed of the memory cells (adjusts the speed of the transition) in response to the detection in step 1004. In one embodiment (see, for example, FIG. 12), the control circuit adjusts (e.g., reduces) the bit line voltage in order to adjust the speed of the transition (e.g., slow down the speed of the transition). In step 1008, the erase state process is completed; for example, Figure 8 the process is resumed and completed with the adjustment made in step 1006. Thus, the control circuit senses the threshold voltage of the memory cells midway through the Figure 8 transition and then adjusts the speed of the transition based on the sensed threshold voltage.

[0137] Figure 11 is a signal timing diagram depicting an example implementation of step 810 for performing the erase state operation (including adjusting the speed of the transition). Thus, Figure 11 describes when Figure 8 the process as Figure 10 an example implementation of step 810 when the process is performed as part of Figure 11 depicts the same signals as Figure 9 except that Figure 9 the Sel BL of Figure 11Two signals in, Sel BL_fast and Sel BL_slow, are substituted. The signal Sel BL_fast is the voltage applied to the bit lines connected to the NAND strings that have memory cells identified in step 808 as being programmed data states transitioning from a higher threshold voltage range to a lower threshold voltage range and identified in step 1004 as fast memory cells. The signal Sel BL_slow is the voltage applied to the bit lines connected to the NAND strings that have memory cells identified in step 808 as being programmed data states transitioning from a higher threshold voltage range to a lower threshold voltage range and not identified in step 1004 as fast memory cells. In other embodiments, there may be more than two bit line voltages.

[0138] The signals Unsel BL, Sel SGDT0 / 1, Unsel SGDT0 / 1, SGD0 / 1, DD0 / 1, WL0 to WLx - 1, WLx, WLx + 1 to WL161, DS0 / 1, SGS0 / 1, SGSB0 / 1, and SL Figure 11 in behave in the same manner as Figure 9 (as described above). In Figure 11 the timing diagram of, the signal Sel BL_slow receives Vdestate, the same as the Sel BL in Figure 9 . The signal Sel BL_fast receives Vdestate - delta, where delta can be any one of 0.1v, 0.2v, 0.5v, 0.75v, 1v, etc. The value of delta is used to reduce the voltage on the selected bit line to reduce the efficiency of GIDL, which reduces the number of holes generated and slows down the reduction of the threshold voltage. As described above, the value of delta is selected in step 1006 based on step 1004. The value of delta can be determined for each individual memory cell, globally for the entire memory, for all memory cells connected to a word line, for all memory cells in a region, for all memory cells in a block, etc. As explained above, different memory cells can have different deltas.

[0139] In one embodiment, Figure 7 to Figure 11 the process of is executed by the state machine 262 or by other components of the system control logic 260, column control circuit 210, and row control circuit 220 under its guidance. In another embodiment, Figure 7 to Figure 11 the process of is executed by the memory controller 120 or under its guidance. When Figure 7 to Figure 11When the process is performed by or under the direction of the memory controller 120, the memory controller 120 will issue a command to the memory die 200 or the integrated memory component 207 to perform the de-status operation in step 810. Figure 12A Illustrates an example command sequence, for an embodiment where the memory system stores three data bits per memory cell, the memory controller 120 may transfer this command sequence to the memory die 200 or the integrated memory component 207 to perform the de-status operation in step 810. This example is consistent with the ONFI specification, where CMD XXh is a user-defined command for performing the de-status operation. Figure 12B Illustrates an example command sequence, for an embodiment where the memory system stores four data bits per memory cell, the memory controller 120 may transfer this command sequence to the memory die 200 or the integrated memory component 207 to perform the de-status operation in step 810.

[0140] A non-volatile memory has been proposed that transitions a memory cell from a programmed data state with a higher threshold voltage range to a programmed data state with a lower threshold voltage range without transitioning the memory cell to an erased data state, in order to reduce the time required for programming and increase the endurance of the memory cell (e.g., due to fewer erasures and programs).

[0141] One embodiment includes a non-volatile storage device that includes a plurality of non-volatile memory cells and control circuitry coupled to the memory cells. Each of the memory cells is configured to store data in a set of data states. Each of the data states corresponds to a threshold voltage range. The set of data states includes an erased data state and a programmed data state. The control circuitry is configured to transition a first memory cell of the plurality of non-volatile memory cells from a first programmed data state of the set of data states to a second programmed data state of the set of data states without transitioning the first memory cell to the erased data state. The second programmed data state corresponds to a lower threshold voltage range than the first programmed data state.

[0142] In an example implementation, the control circuitry is configured to receive new data to be programmed into the first memory cell, the first memory cell already storing existing data in the first programmed data state; and compare the new data with the existing data to identify that the first memory cell is to be transitioned from the first programmed data state to the second programmed data state to store the new data, and perform the transition of the first memory cell from the first programmed data state to the second programmed data state in response to comparing the new data with the existing data.

[0143] In an example embodiment, the control circuit is configured to transition the first memory cell from the first programmed data state to the second programmed data state by using gate-induced drain leakage (GIDL) to reduce the threshold voltage of the first memory cell.

[0144] In an example embodiment, the programmed data states include a first data state adjacent to the erased data state in terms of threshold voltage and a highest data state farthest from the erased data state, the highest data state having the highest threshold voltage range of the set of data states, and the programmed data states corresponding to threshold voltages higher than the erased data state.

[0145] In an example embodiment, the control circuit is configured to program the memory cells in a direction from the erased data state towards the highest data state, and to erase the memory cells in a direction from the highest data state towards the erased data state.

[0146] In an example embodiment, the control circuit is configured to persistently maintain the first memory cell in the second programmed data state after the transition.

[0147] In an example embodiment, the control circuit is configured to perform other memory operations after the transition; and the control circuit is configured to persistently maintain the first memory cell in the second programmed data state during and after the other memory operations.

[0148] In an example embodiment, the control circuit is configured to verify that the first memory cell is in the second programmed data state after the transition.

[0149] In an example embodiment, the control circuit is configured to transition the first memory cell from the first programmed data state to the second programmed data state in order to change the data stored in the first memory cell.

[0150] In an example embodiment, the control circuit is configured to adjust the threshold voltage of the first memory cell during the transition from the first programmed data state to the second programmed data state; and the control circuit is configured to stop adjusting the threshold voltage of the first memory cell after completing the transition from the first programmed data state to the second programmed data state.

[0151] In an example embodiment, the control circuit is configured to adjust the speed of the transition.

[0152] In an example embodiment, the apparatus further includes a bit line connected to the first memory cell, and the control circuit is configured to: apply a bit line voltage to the bit line to cause the transition, and adjust the bit line voltage to adjust the speed of the transition.

[0153] In an example embodiment, the control circuit is configured to adjust the speed of the transition based on a rate of change of a threshold voltage of the first memory cell.

[0154] In an example embodiment, the control circuit is configured to adjust the speed of the transition during the transition.

[0155] In an example embodiment, the control circuit is configured to sense a threshold voltage of the first memory cell midway through the transition and then adjust the speed of the transition based on the sensed threshold voltage.

[0156] One embodiment includes a method that includes: receiving new data to be programmed into a set of non-volatile memory cells that already store existing data in a set of data states, each data state in the set corresponding to a threshold voltage range, the set of data states including an erased data state and a programmed data state; comparing the new data with the existing data to identify a subset of memory cells in a programmed data state having a higher threshold voltage range that need to transition to a programmed data state having a lower threshold voltage range to store the new data; and transitioning the identified memory cells from the programmed data state having the higher threshold voltage range to the programmed data state having the lower threshold voltage range without transitioning the identified memory cells to the erased data state.

[0157] An example embodiment further includes: performing other memory operations after the transition; and the control circuit is configured to persistently maintain the identified memory cells in the programmed data state having the lower threshold voltage range during and after the other memory operations.

[0158] In an example embodiment, the transition includes verifying that the identified memory cells are in the programmed data state having the lower threshold voltage range.

[0159] An example embodiment further includes: sensing a threshold voltage of the identified memory cells; and adjusting the speed of the transition based on the sensing.

[0160] One embodiment includes a non - volatile storage device that includes a plurality of non - volatile memory cells. Each of these memory cells is configured to store data individually in a set of data states. Each of these data states corresponds to a threshold voltage range. The set of data states includes an erased data state and programmed data states. The programmed data states include a first data state that is adjacent to the erased data state in terms of threshold voltage and a highest data state that is the farthest from the erased data state. The highest data state has the highest threshold voltage range of the set of data states. The non - volatile storage device further includes means for transitioning a memory cell from a programmed data state having a higher threshold voltage range to a programmed data state having a lower threshold voltage range without transitioning to the erased data state.

[0161] In one embodiment, the means for transitioning a memory cell from a programmed data state having a higher threshold voltage range to a programmed data state having a lower threshold voltage range without transitioning to the erased data state includes one or more of a memory controller 120, system control logic 260, state machine 262, FPGA, ASIC, a processor, and / or an integrated circuit that perform the Figure 7 , Figure 8 , Figure 9 , Figure 10 and / or Figure 11 processes.

[0162] For the purposes of this document, references in this specification to "an embodiment", "one embodiment", "some embodiments", or "another embodiment" may be used to describe different embodiments or the same embodiment.

[0163] For the purposes of this document, a connection can be a direct connection or an indirect connection (e.g., via one or more other components). In some cases, when an element is said to be connected or coupled to another element, the element can be directly connected to the other element or indirectly connected to the other element via one or more intermediate elements. When an element is said to be directly connected to another element, there are no intermediate elements between the element and the other element. Two devices are "in communication" if they are directly or indirectly connected such that the two devices can communicate electronic signals with each other.

[0164] For the purposes of this document, the term "based on" can be interpreted as "at least partially based on".

[0165] For the purposes of this document, in the absence of additional context, the use of numerical terms (such as "first" object, "second" object, and "third" object) may not imply an ordering of the objects, but may be used for identification purposes to identify different objects.

[0166] For the purposes of this document, a "collection" of objects may refer to a "collection" of one or more of the objects.

[0167] The foregoing specific embodiments have been presented for purposes of illustration and description. It is not intended to be exhaustive or limited to the precise forms disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the proposed technology and its practical application, thereby enabling others skilled in the art to best utilize the proposed technology in various embodiments and various modifications suited to the particular uses contemplated. The scope of the present disclosure is intended to be defined by the appended claims.

Claims

1. A non-volatile storage device, comprising: A plurality of non-volatile memory cells, each of the memory cells being configured to store data in a set of data states, each of the data states corresponding to a threshold voltage range, the set of data states including an erased data state and a programmed data state; And A control circuit connected to the memory cells, the control circuit being configured to transition a first memory cell of the plurality of non-volatile memory cells from a first programmed data state in the set of data states to a second programmed data state in the set of data states without transitioning the first memory cell to the erased data state, the second programmed data state corresponding to a threshold voltage range lower than the first programmed data state.

2. The non-volatile storage device according to claim 1, wherein the control circuit is configured to: Receive new data to be programmed into the first memory cell, the first memory cell having stored existing data in the first programmed data state; and Compare the new data with the existing data to identify that the first memory cell is to be transitioned from the first programmed data state to the second programmed data state to store the new data, and perform the transition of the first memory cell from the first programmed data state to the second programmed data state in response to comparing the new data with the existing data.

3. The non-volatile storage device according to claim 1, wherein: The control circuit is configured to transition the first memory cell from the first programmed data state to the second programmed data state by using gate-induced drain leakage (GIDL) to reduce the threshold voltage of the first memory cell.

4. The non-volatile storage device according to claim 1, wherein: The programmed data states include a first data state adjacent to the erased data state in terms of threshold voltage and a highest data state farthest from the erased data state, the highest data state having the highest threshold voltage range of the set of data states, and the programmed data states corresponding to threshold voltages higher than the erased data state.

5. The non-volatile storage device according to claim 4, wherein: The control circuit is configured to program the memory cells in a direction from the erased data state towards the highest data state, and erase the memory cells in a direction from the highest data state towards the erased data state.

6. The non-volatile storage device according to claim 1, wherein: The control circuit is configured to persistently maintain the first memory cell in the second programmed data state after the transition.

7. The non-volatile storage device according to claim 1, wherein: The control circuit is configured to perform other memory operations after the transition; and The control circuit is configured to persistently maintain the first memory cell in the second programmed data state during and after the other memory operations.

8. The non-volatile storage device according to claim 1, wherein: the control circuit is configured to verify that the first memory cell is in the second programmed data state after the transition.

9. The non-volatile storage device according to claim 1, wherein: the control circuit is configured to transition the first memory cell from the first programmed data state to the second programmed data state so as to change the data stored in the first memory cell.

10. The non-volatile storage device according to claim 1, wherein: the control circuit is configured to adjust a threshold voltage of the first memory cell during the transition from the first programmed data state to the second programmed data state; and the control circuit is configured to stop adjusting the threshold voltage of the first memory cell after completing the transition from the first programmed data state to the second programmed data state.

11. The non-volatile storage device according to claim 1, wherein: the control circuit is configured to adjust a speed of the transition.

12. The non-volatile storage device according to claim 1, further comprising: a bit line connected to the first memory cell, the control circuit being configured to: apply a bit line voltage to the bit line to cause the transition, and adjust the bit line voltage so as to adjust the speed of the transition.

13. The non-volatile storage device according to claim 1, wherein: the control circuit is configured to adjust the speed of the transition based on a rate of change of a threshold voltage of the first memory cell.

14. The non-volatile storage device according to claim 1, wherein: the control circuit is configured to adjust the speed of the transition during the transition.

15. The non-volatile storage device according to claim 1, wherein: the control circuit is configured to sense a threshold voltage of the first memory cell midway through the transition and subsequently adjust the speed of the transition based on the sensed threshold voltage.

16. A method, comprising: receiving new data to be programmed into a set of non-volatile memory cells that already store existing data in a set of data states, each data state in the set of data states corresponding to a threshold voltage range, the set of data states including an erased data state and a programmed data state; comparing the new data with the existing data to identify a subset of memory cells in a programmed data state having a higher threshold voltage range that need to be transitioned to a programmed data state having a lower threshold voltage range in order to store the new data; and without transitioning the identified memory cells to the erased data state, transitioning the identified memory cells from the programmed data state having the higher threshold voltage range to the programmed data state having the lower threshold voltage range.

17. The method according to claim 16, further comprising: performing other memory operations after the transition; and The control circuit is configured to persistently maintain the identified memory cells in the programmed data state having the lower threshold voltage range during and after the other memory operations.

18. The method according to claim 17, wherein: The transition includes verifying that the identified memory cells are in the programmed data state having the lower threshold voltage range.

19. The method according to claim 16, further comprising: Sensing a threshold voltage of the identified memory cells; And Adjusting a speed of the transition based on the sensing.

20. A non-volatile storage device, comprising: A plurality of non-volatile memory cells, each of the memory cells being configured to store data individually in a set of data states, each of the data states corresponding to a threshold voltage range, the set of data states including an erased data state and a programmed data state, the programmed data state including a first data state adjacent to the erased data state in terms of threshold voltage and a highest data state farthest from the erased data state, the highest data state having the highest threshold voltage range of the set of data states; And Means for transitioning a memory cell from a programmed data state having a higher threshold voltage range to a programmed data state having a lower threshold voltage range without transitioning to the erased data state.

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