Electronic component testing and classifying system and method thereof
By introducing a confirmation signal mechanism in the electronic component testing and classification system, the problem that the classification device cannot determine the signal accuracy of the test results is solved, and accurate electronic component classification is achieved.
Patent Information
- Application Number
- CN202411898949.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-01-10
- Filing Date
- 2024-12-23
- Publication Date
- 2025-07-11
AI Technical Summary
In the existing electronic component testing and classification systems, the classification device cannot determine whether the test result signal is correct, resulting in the possibility of incorrect classification of electronic components.
By introducing a confirmation signal mechanism between the classification device and the testing device, the test device generates a test result signal and a confirmation signal after receiving the start signal, and the classification device judges the correctness of the test result signal based on the confirmation signal, thereby performing accurate classification.
When ensuring that the test result signal is not affected by signal loss or interference, the classification device can perform correct actions to avoid incorrect classification.
Smart Images
Figure CN120286379A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of electronic component testing, and in particular to an electronic component testing and sorting system and method thereof. Background Art
[0002] Before leaving the factory, electronic components (such as integrated circuits) need to be functionally tested by a testing device to generate a plurality of test result signals, thereby representing the test results. Then, a sorting device sorts the electronic components into a good product area or a defective product area according to these test result signals of the testing device. In this way, the electronic components sorted into the good product area can be shipped out, and the electronic components sorted into the defective product area can be recycled to correct their faulty functions.
[0003] However, since the sorting device cannot determine whether these test result signals output by the testing device are correct, the sorting device may misclassify the electronic components. For example, assume that the testing device tests a good electronic component. At this time, the test results represented by these test result signals generated by the testing device should be good product results. However, when the testing device sends these test result signals to the sorting device, some factors (such as signal loss and signal interference) may cause the test result signals received by the sorting device to be incorrect (such as the level being changed). At this time, based on these incorrect test result signals, the sorting device will misclassify the electronic components. For example, a good electronic component is sorted into the defective product area, or a defective electronic component is sorted into the good product area. Summary of the Invention
[0004] In view of the above, the present invention provides an electronic component testing and sorting system and method thereof. The electronic component testing and sorting system includes a sorting device and a testing device. The testing device is connected to the sorting device. The sorting device outputs a first start signal. The testing device responds to the first start signal to test the device under test, generates a plurality of test result signals, and outputs a first end signal and these test result signals to the sorting device. When the sorting device receives the first end signal and one of these test result signals is asserted, the sorting device outputs a second start signal to the testing device. The testing device responds to the second start signal to generate a plurality of confirmation signals, and outputs a second end signal and these confirmation signals to the sorting device. The sorting device responds to the second end signal and determines whether at least one test result signal is correct according to these confirmation signals.
[0005] The method for testing and classifying electronic components includes: outputting a first start signal through a classification device; testing a device under test by a testing device in response to the first start signal to generate a plurality of test result signals, and outputting a first end signal and these test result signals to the classification device; when the classification device receives the first end signal and one of these test result signals is valid, outputting a second start signal to the testing device through the classification device; generating a plurality of confirmation signals by the testing device in response to the second start signal, and outputting a second end signal and these confirmation signals to the classification device; and judging whether at least one test result signal is correct according to these confirmation signals by the classification device in response to the second end signal.
[0006] In summary, according to some embodiments, the present invention can judge whether the test result signal is correct through the confirmation signal, and when the classification device judges that the test result signal is correct (for example, the test result signal has not changed due to factors such as signal loss and signal interference), it will perform corresponding actions according to the test result signal (for example, correctly classifying the device under test). In this way, it can avoid the classification device from performing incorrect actions (for example, incorrectly classifying the device under test) due to incorrect test result signals (for example, the test result signal has changed due to factors such as signal loss and signal interference).
[0007] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments, but it is not intended to limit the present invention. Description of the Drawings
[0008] Figure 1 It is a block diagram of an electronic component testing and classification system according to some embodiments of the present invention.
[0009] Figure 2 It is a flowchart of a method for testing and classifying electronic components according to some embodiments of the present invention.
[0010] Figure 3 It is a waveform diagram of signals on the signal channel between a classification device and a testing device according to some embodiments of the present invention.
[0011] Figure 4 It is a block diagram of an electronic component testing and classification system according to some embodiments of the present invention.
[0012] Figure 5 It is a waveform diagram of signals on the signal channel between a classification device and a testing device according to some embodiments of the present invention.
[0013] Figure 6 It is a waveform diagram of signals on the signal channel between a classification device and a testing device according to some embodiments of the present invention.
[0014] Wherein, reference numerals:
[0015] 10: Electronic component testing and classification system
[0016] 20: Classification device
[0017] 30: Testing device
[0018] 40: Device under test
[0019] SOT: First signal channel
[0020] SOT_1: First start signal
[0021] SOT_2: Second start signal
[0022] EOT: Second signal channel
[0023] EOT_1: First end signal
[0024] EOT_2: Second end signal
[0025] Bin1: Third signal channel
[0026] Bin1_1: First test result signal
[0027] Bin1_2: First confirmation signal
[0028] Bin2: Fourth signal channel
[0029] Bin2_1: Second test result signal
[0030] Bin2_2: Second confirmation signal
[0031] Bin3: Fifth signal channel
[0032] Bin3_1: Third test result signal
[0033] Bin3_2: Third confirmation signal
[0034] Bin4: Sixth signal channel
[0035] Bin4_1: Fourth test result signal
[0036] Bin4_2: Fourth confirmation signal
[0037] Bin5: Seventh signal channel
[0038] Bin5_1: Fifth test result signal
[0039] Bin5_2: Fifth confirmation signal
[0040] Bin6: Eighth signal channel
[0041] Bin6_1: Sixth test result signal
[0042] Bin6_2: Sixth confirmation signal
[0043] Bin7: Ninth signal channel
[0044] Bin7_1: Seventh test result signal
[0045] Bin7_2: Seventh confirmation signal
[0046] Bin8: Tenth signal channel
[0047] Bin8_1: Eighth test result signal
[0048] Bin8_2: Eighth confirmation signal
[0049] A: First block
[0050] B: Second block
[0051] C: Third block
[0052] S201~S209: Steps Detailed implementation manners
[0053] In some embodiments herein, the assertion of a single signal means that the signal is in the "1" state, that is to say, the assertion of the signal corresponds to the digital value "1"; the de-assertion of the signal means that the signal is in the "0" state, that is to say, the de-assertion of the signal corresponds to the digital value "0". For example, the assertion of the signal means that the signal is at a high level, while the de-assertion of the signal means that the signal is at a low level. However, the present invention is not limited thereto. In other embodiments, the assertion of a single signal means that the signal is in the "0" state, that is to say, the assertion of the signal corresponds to the digital value "0"; the de-assertion of the signal means that the signal is in the "1" state, that is to say, the de-assertion of the signal corresponds to the digital value "1". For example, the assertion of the signal means that the signal is at a low level, while the de-assertion of the signal means that the signal is at a high level. In some embodiments, the assertion of different types of signals can correspond to different states and different digital values, and the de-assertion of different types of signals can correspond to different states and different digital values. For example, assume that the assertion of a certain type of signal is in the "1" state (digital value "1"), and the de-assertion of the certain type of signal is in the "0" state (digital value "0"), then the assertion of another type of signal is in the "0" state (digital value "0"), and the de-assertion of the another type of signal is in the "1" state (digital value "1"). In some embodiments, a high-level or low-level signal can be used as a valid signal according to different systems; for example, the high-level signal is +5V (positive 5 volts), while the low-level signal is implemented with 0V.
[0054] In this text, if the first signal and the second signal are in opposite states, it means that the first signal is logically inverted with respect to the second signal. For example, when the first signal is at a low level and the second signal is at a high level; or when the first signal is at a high level and the second signal is at a low level, then the first signal is said to be logically inverted with respect to the second signal. In other words, when the first signal is active and the second signal is inactive; or when the first signal is inactive and the second signal is active, then the first signal is said to be logically inverted with respect to the second signal. If the first signal is the logical inversion of the second signal, it means that the first signal and the second signal are complementary.
[0055] Referring to Figure 1 , it is a block diagram of an electronic component testing and sorting system 10 according to some embodiments of the present invention. The electronic component testing and sorting system 10 includes a sorting device 20 and a testing device 30. The sorting device 20 is connected to the testing device 30 to communicate with the testing device 30. Specifically, signals are transmitted between the sorting device 20 and the testing device 30 via a plurality of signal channels (such as a first signal channel SOT, a second signal channel EOT, a third signal channel Bin1, a fourth signal channel Bin2, and a fifth signal channel Bin3). In some embodiments, communication between the sorting device 20 and the testing device 30 is, for example, carried out using a Transistor-Transistor Logic (TTL) signal transmission method.
[0056] Here, Figure 1 Only five signal channels (i.e., the first signal channel SOT, the second signal channel EOT, the third signal channel Bin1, the fourth signal channel Bin2, and the fifth signal channel Bin3) are shown, but the present invention is not limited thereto. The number of signal channels between the sorting device 20 and the testing device 30 can be less than five or more than five. The sorting device (Handler) 20 can classify the device under test 40 (such as an integrated circuit) into a corresponding area (such as a good product area, a first type of defective product area, a second type of defective product area, or a retest area, etc.) according to the test result signal (to be described in detail later) returned by the testing device 30.
[0057] In other embodiments, the sorting device 20 may also be other test peripheral devices, such as a control device, which can control the test device 30 to perform functional tests on the device under test 40, and according to the test result signal (to be described in detail later) returned by the test device 30, perform storing the test results (such as the digital value of the test result signal) or corresponding actions. The test device 30 can be an IC board-level test device, a wafer CP (Chip Probing) test device, a post-packaging finished product FT test device, a system-level SLT test device, a reliability test device (such as a Burn-in test). In other words, the device under test 40 can include (but is not limited to) wafers, bare chips, and semiconductor packaging components, etc., or other passive components such as LEDs, resistors, inductors, or capacitors can also be included.
[0058] Referring to Figures 1 to 3 。 Figure 2 is a flowchart of an electronic component testing and sorting method according to some embodiments of the present invention. Figure 3 is a waveform diagram of signals on the signal channel between the sorting device 20 and the test device 30 according to some embodiments of the present invention. The electronic component testing and sorting system 10 is adapted to perform the electronic component testing method of the present invention on a certain device under test 40. For the convenience of description, the present invention will Figure 3 The waveform diagram is divided into three blocks (i.e., the first block A, the second block B, and the third block C). The first block A, the second block B, and the third block C are the waveforms generated when the electronic component testing and sorting system 10 tests different devices under test 40, respectively. The waveform of the first block A (i.e., the waveform generated when the electronic component testing and sorting system 10 performs the electronic component testing and sorting method of the present invention on a certain device under test 40) will be described below.
[0059] In step S201, the sorting device 20 outputs a first start signal SOT_1 to the test device 30 via the first signal channel SOT. Specifically, the sorting device 20 outputs an effective first start signal SOT_1 to the test device 30 via the first signal channel SOT. The first start signal SOT_1 is a low-level signal of 0V, because it is a low-level compared to +5V. In other embodiments, the first start signal SOT_1 can also be an effective signal that is a high-level compared to 0V (low-level signal), for example, using +5V as the high-level signal.
[0060] In step S203, the test device 30 receives the first start signal SOT_1 via the first signal channel SOT, and tests the device under test 40 in response to receiving the first start signal SOT_1 to generate a plurality of test result signals (such as the first test result signal Bin1_1, the second test result signal Bin2_1, and the third test result signal Bin3_1). The test device 30 also stores the test results it generates for subsequent processing. Then, the test device 30 outputs these test result signals to the classification device 20 via other signal channels (such as the third signal channel Bin1, the fourth signal channel Bin2, and the fifth signal channel Bin3) other than the first signal channel SOT and the second signal channel EOT.
[0061] Specifically, the test device 30 outputs the first test result signal Bin1_1 via the third signal channel Bin1, outputs the second test result signal Bin2_1 via the fourth signal channel Bin2, and outputs the third test result signal Bin3_1 via the fifth signal channel Bin3. That is to say, the number of test result signals corresponds to the number of other signal channels other than the first signal channel SOT and the second signal channel EOT. After that, the test device 30 outputs the first end signal EOT_1 to the classification device 20 via the second signal channel EOT. Specifically, the test device 30 outputs the effective first end signal EOT_1 to the classification device 20 via the second signal channel EOT. The first end signal EOT_1 is an effective signal with a higher level compared to 0V (low-level signal), for example, using +5V as the high-level signal. In other embodiments, the first end signal EOT_1 can also be an effective signal with a lower level compared to +5V (high-level signal), for example, using 0V as the low-level signal. In some embodiments, the output start time of the first end signal EOT_1 is delayed from the output start time of these test result signals, and the output end time of these test result signals is delayed from the output start time of the first end signal EOT_1.
[0062] For example, the test device 30 stores a plurality of test rules, respectively corresponding to the tests of the operations of different functional modules of the device under test 40. In response to receiving the first start signal SOT_1, the test device 30 tests the operations of various functional modules of the device under test 40 according to the stored test rules, so as to generate a plurality of test result signals (such as the first test result signal Bin1_1, the second test result signal Bin2_1, and the third test result signal Bin3_1). Specifically, assuming that the device under test 40 passes the tests defined by all the test rules, it means that the device under test 40 is a good product. At this time, the test device 30 generates a first test result signal Bin1_1 that is in effect, and generates a second test result signal Bin2_1 and a third test result signal Bin3_1 that are in failure. In this embodiment, the test result signal that is in effect uses a valid signal with a higher level compared to 0V (low-level signal), for example, +5V is used as the high-level signal; the test result signal that is in failure uses a low-level signal, for example, 0V is used as the low-level signal. However, the present invention is not limited thereto. In some other embodiments, the test result signal that is in effect uses a low-level signal, for example, 0V is used as the low-level signal; the test result signal that is in failure uses a high-level signal, for example, +5V is used as the high-level signal.
[0063] Further explanation, assuming that the device under test 40 passes the tests defined by some of the test rules but fails the tests defined by other parts of the test rules, it means that the device under test 40 is a first type of defective product (i.e., a defective product with partial faults). At this time, the test device 30 generates a second test result signal Bin2_1 that is in effect, and generates a first test result signal Bin1_1 and a third test result signal Bin3_1 that are in failure. Assuming that the device under test 40 fails all the tests defined by the test rules, it means that the device under test 40 is a second type of defective product (i.e., a defective product with complete faults). At this time, the test device 30 generates a third test result signal Bin3_1 that is in effect, and generates a first test result signal Bin1_1 and a second test result signal Bin2_1 that are in failure. Then, the test device 30 outputs these test result signals to the classification device 20, and outputs a first end signal EOT_1 to the classification device 20 to notify the classification device 20 to perform subsequent steps.
[0064] In step S205, when the classification device 20 receives the first end signal EOT_1 via the second signal channel EOT and one of these test result signals (for example, one of the first test result signal Bin1_1, the second test result signal Bin2_1, and the third test result signal Bin3_1) is valid, the classification device 20 outputs a second start signal SOT_2 to the test device 30 via the first signal channel SOT. Specifically, when the classification device 20 receives the first end signal EOT_1 via the second signal channel EOT, one of these test result signals is valid, and the remaining ones of these test result signals are invalid, the classification device 20 outputs, via the first signal channel SOT, the valid second start signal SOT_2 to the test device 30, and the second start signal SOT_2 uses a low-level signal of 0V. Similarly, in other embodiments, the second start signal SOT_2 may also use a valid signal with a high level compared to 0V (low-level signal), such as a high-level signal of +5V. The classification device 20 also stores the digital values it receives for subsequent processing. For example, as shown by the waveform of the first block A of Figure 3 when the classification device 20 receives the first end signal EOT_1 via the second signal channel EOT, the first test result signal Bin1_1 is valid, the second test result signal Bin2_1 is invalid, and the third test result signal Bin3_1 is invalid, the classification device 20 outputs the second start signal SOT_2 to the test device 30 via the first signal channel SOT and stores the digital values corresponding to each test result signal it receives.
[0065] In step S207, the testing device 30 receives the second start signal SOT_2 via the first signal channel SOT, and generates a plurality of confirmation signals (such as the first confirmation signal Bin1_2, the second confirmation signal Bin2_2, and the third confirmation signal Bin3_2) in response to the received second start signal SOT_2. Then, the testing device 30 outputs these confirmation signals to the classification device 20 via other signal channels (such as the third signal channel Bin1, the fourth signal channel Bin2, and the fifth signal channel Bin3) other than the first signal channel SOT and the second signal channel EOT. Specifically, the testing device 30 outputs the first confirmation signal Bin1_2 via the third signal channel Bin1, outputs the second confirmation signal Bin2_2 via the fourth signal channel Bin2, and outputs the third confirmation signal Bin3_2 via the fifth signal channel Bin3. That is to say, the number of confirmation signals corresponds to the number of other signal channels other than the first signal channel SOT and the second signal channel EOT. After that, the testing device 30 outputs the second end signal EOT_2 in effect to the classification device 20 via the second signal channel EOT. The second end signal EOT_2 is an active signal with a higher level compared to 0V (low-level signal), for example, +5V is used as the high-level signal. Similarly, in other embodiments, the second end signal EOT_2 may also be an active signal with a lower level compared to +5V (high-level signal), for example, 0V is used as the low-level signal. In some embodiments, the output start time of the second end signal EOT_2 is delayed from the output start time of these confirmation signals, and the output end time of these confirmation signals is delayed from the output start time of the second end signal EOT_2.
[0066] In step S209, the classification device 20 receives the second end signal EOT_2 via the second signal channel EOT, and determines whether at least one test result signal (such as at least one of the first test result signal Bin1_1, the second test result signal Bin2_1, and the third test result signal Bin3_1) is correct according to these confirmation signals (such as the first confirmation signal Bin1_2, the second confirmation signal Bin2_2, and the third confirmation signal Bin3_2) in response to the received second end signal EOT_2. In this way, it is possible to prevent the classification device 20 from performing incorrect actions due to incorrect test result signals (such as the test result signals being changed due to factors such as signal loss and signal interference).
[0067] In some embodiments of step S207, the test device 30 generates the confirmation signals (such as the first confirmation signal Bin1_2, the second confirmation signal Bin2_2, and the third confirmation signal Bin3_2) based on the previous test result signals generated thereby (such as the first test result signal Bin1_1, the second test result signal Bin2_1, and the third test result signal Bin3_1). For example, the test device 30 generates the confirmation signals based on the digital values respectively corresponding to the stored test result signals. The following is illustrated with two exemplary cases.
[0068] In the first exemplary case of step S207, as Figure 3 shown by the waveforms of the first block A and the third block C in, the test device 30 performs a logical inversion operation on the digital values respectively corresponding to the stored test result signals (such as the first test result signal Bin1_1, the second test result signal Bin2_1, and the third test result signal Bin3_1) to generate the confirmation signals (such as the first confirmation signal Bin1_2, the second confirmation signal Bin2_2, and the third confirmation signal Bin3_2). Thus, the confirmation signals are the logical inversions of the previous test result signals generated by the test device 30, that is, the confirmation signals are complementary to the previous test result signals generated by the test device 30.
[0069] In other words, each test result signal generated by the test device 30 previously is complementary to the confirmation signal of the same signal channel. In step S209 of this first exemplary case, the classification device 20 determines whether at least one of the previously received test result signals is complementary to the confirmation signal of the same signal channel. For example, the classification device 20 performs an exclusive-OR (XOR) logical operation or an exclusive-NOR (XNOR) logical operation on at least one of the digital values respectively corresponding to the stored test result signals and the digital value of the confirmation signal of the same signal channel to determine whether the test result signal and the confirmation signal of the same signal channel are complementary. Specifically, as Figure 3 shown by the waveforms of the first block A and the third block C in, the classification device 20 determines whether the previously received first test result signal Bin1_1 is complementary to the first confirmation signal Bin1_2, determines whether the previously received second test result signal Bin2_1 is complementary to the second confirmation signal Bin2_2, and / or determines whether the previously received third test result signal Bin3_1 is complementary to the third confirmation signal Bin3_2.
[0070] If the test result signal of the same signal channel is complementary to the confirmation signal, it indicates that the test result signal is correct (for example, the test result signal has not changed due to factors such as signal loss and signal interference). At this time, the classification device 20 performs corresponding actions according to these test result signals (such as the first test result signal Bin1_1, the second test result signal Bin2_1, and the third test result signal Bin3_1).
[0071] Specifically, in the case where it is confirmed that the test result signal is correct (that is, the test result signal is correct): when the first test result signal Bin1_1 is valid, the second test result signal Bin2_1 is invalid, and the third test result signal Bin3_1 is invalid, it indicates that the device under test 40 is a good product. At this time, the classification device 20 classifies the currently tested device under test 40 into the good product area; when the first test result signal Bin1_1 is invalid, the second test result signal Bin2_1 is valid, and the third test result signal Bin3_1 is invalid, it indicates that the device under test 40 is a first type of defective product. At this time, the classification device 20 classifies the currently tested device under test 40 into the first type of defective product area; when the first test result signal Bin1_1 is invalid, the second test result signal Bin2_1 is invalid, and the third test result signal Bin3_1 is valid, it indicates that the device under test 40 is a second type of defective product. At this time, the classification device 20 classifies the currently tested device under test 40 into the second type of defective product area.
[0072] If the test result signal of the same signal channel is not complementary to the confirmation signal, it indicates that the test result signal is incorrect (for example, the test result signal has changed due to factors such as signal loss and signal interference). At this time, the classification device 20 performs a preset action. Specifically, in the case where the test result signal is incorrect, the classification device 20 cannot determine which type the currently tested device under test 40 belongs to (for example, it cannot determine whether the currently tested device under test 40 belongs to a good product, a first type of defective product, or a second type of defective product). Therefore, the classification device 20 performs its preset action to classify the currently tested device under test 40 into the retest area, so that the device under test 40 can be retested later. In this way, it is possible to prevent the classification device 20 from misclassifying the device under test 40.
[0073] Refer to Figure 4 and Figure 5 。 Figure 4 FIG. is a block diagram of an electronic component testing and classification system 10 according to some embodiments of the present invention. Figure 5This is a waveform diagram of signals on the signal channel between the classification device 20 and the test device 30 according to some embodiments of the present invention. In the second exemplary embodiment of step S207, the test device 30 combines the digital values corresponding to the stored test result signals (such as the first test result signal Bin1_1 to the eighth test result signal Bin8_1) according to the arrangement order of the signal channels (such as the third signal channel Bin1 to the tenth signal channel Bin8) between the test device 30 and the classification device 20 to obtain the first sequence combination value. Specifically, the first test result signal Bin1_1 to the eighth test result signal Bin8_1 are respectively transmitted via the third signal channel Bin1 to the tenth signal channel Bin8. The test device 30 uses the digital value represented by the first test result signal Bin1_1 corresponding to the third signal channel Bin1 as the least significant bit of the first sequence combination value, and uses the digital value represented by the second test result signal Bin2_1 corresponding to the fourth signal channel Bin2 as the second least significant bit of the first sequence combination value, and so on to combine the first sequence combination value.
[0074] The test device 30 stores a first comparison sequence value, which is implemented by a digital sequence code formed by the digital values "0" and "1". The test device 30 calculates the difference between the first comparison sequence value and the first sequence combination value as the first feedback value, and converts the first feedback value into these confirmation signals (such as the first confirmation signal Bin1_2 to the eighth confirmation signal Bin8_2). Specifically, the first feedback value is a digital sequence code formed by the digital values "0" and "1". The test device 30 converts the digital value of each bit in the first feedback value into a confirmation signal according to the arrangement order of the signal channels (such as the third signal channel Bin1 to the tenth signal channel Bin8) between the test device 30 and the classification device 20.
[0075] For example, the first confirmation signal Bin1_2 to the eighth confirmation signal Bin8_2 are respectively transmitted via the third signal channel Bin1 to the tenth signal channel Bin8. The test device 30 converts the digital value of the least significant bit in the first feedback value into the first confirmation signal Bin1_2, and converts the digital value of the second least significant bit in the first feedback value into the second confirmation signal Bin2_2, and so on. Specifically, as Figure 5As shown, assume that the first comparison sequence value is "00001010", and the first sequence combination value formed by the digital values corresponding to the first test result signal Bin1_1 to the eighth test result signal Bin8_1 is "00000001", then the first feedback value is "00001001". At this time, the test device 30 generates a valid first confirmation signal Bin1_2 and a fourth confirmation signal Bin4_2, and generates an invalid second confirmation signal Bin2_2, a third confirmation signal Bin3_2, and fifth confirmation signals Bin5_2 to eighth confirmation signals Bin8_2. In this embodiment, the valid confirmation signal uses a high-level valid signal compared with 0V (low-level reference signal), for example, +5V is used as the high-level reference signal; the invalid confirmation signal uses a low-level signal, for example, 0V is used as the low-level signal. However, the present invention is not limited thereto. In some other embodiments, the valid confirmation signal uses a low-level signal, for example, 0V is used as the low-level signal; the invalid confirmation signal uses a high-level signal, for example, +5V is used as the high-level signal.
[0076] In step S209 of this second exemplary embodiment, the classification device 20 combines the digital values corresponding to the stored test result signals (such as the first test result signal Bin1_1 to the eighth test result signal Bin8_1) according to the arrangement order of the signal channels (such as the third signal channel Bin1 to the tenth signal channel Bin8) between the test device 30 and the classification device 20 to obtain a second sequence combination value. Specifically, the first test result signal Bin1_1 to the eighth test result signal Bin8_1 are respectively transmitted via the third signal channel Bin1 to the tenth signal channel Bin8. The classification device 20 uses the digital value represented by the first test result signal Bin1_1 corresponding to the third signal channel Bin1 as the least significant bit of the second sequence combination value, and uses the digital value represented by the second test result signal Bin2_1 corresponding to the fourth signal channel Bin2 as the second least significant bit of the second sequence combination value, and so on to combine the second sequence combination value.
[0077] The classification device 20 also combines the digital values of the received confirmation signals (such as the first confirmation signal Bin1_2 to the eighth confirmation signal Bin8_2) according to the arrangement order of the signal channels (such as the third signal channel Bin1 to the tenth signal channel Bin8) between the test device 30 and the classification device 20 to obtain a second feedback value. Specifically, the first confirmation signal Bin1_2 to the eighth confirmation signal Bin8_2 are respectively transmitted via the third signal channel Bin1 to the tenth signal channel Bin8. The classification device 20 uses the digital value represented by the first confirmation signal Bin1_2 corresponding to the third signal channel Bin1 as the least significant bit of the second feedback value, and uses the digital value represented by the second confirmation signal Bin2_2 corresponding to the fourth signal channel Bin2 as the second least significant bit of the second feedback value, and so on to combine the second feedback value.
[0078] The classification device 20 stores a second comparison sequence value, which is implemented by a digital sequence code formed by the digital values "0" and "1", and the second comparison sequence value is the same as the first comparison sequence value. The classification device 20 calculates the sum value between the second feedback value and the second sequence combination value, and determines whether the sum value matches the second comparison sequence value. For example, as Figure 5 shown, assume that the second sequence combination value combined by the digital values corresponding to the first test result signal Bin1_1 to the eighth test result signal Bin8_1 is "00000001", and the second feedback value combined by the digital values corresponding to the first confirmation signal Bin1_2 to the eighth confirmation signal Bin8_2 is "00001001", then the sum value between the second feedback value and the second sequence combination value is "00001010". If the sum value between the second feedback value and the second sequence combination value matches the second comparison sequence value, it means that the test result signals are correct (for example, the test result signals have not changed due to factors such as signal loss and signal interference). At this time, the classification device 20 performs corresponding actions according to the test result signals (the first test result signal Bin1_1 to the eighth test result signal Bin8_1). If the sum value between the second feedback value and the second sequence combination value does not match the second comparison sequence value, it means that the test result signal is incorrect (for example, the test result signal has changed due to factors such as signal loss and signal interference). At this time, the classification device 20 performs a preset action.
[0079] Refer to Figure 4 and Figure 6 . Figure 6Schematic diagram of the waveforms of signals on the signal channels between the classification device 20 and the test device 30 according to some embodiments of the present invention. In some embodiments of step S207, the test device 30 generates the confirmation signals (such as the first confirmation signal Bin1_2 to the eighth confirmation signal Bin8_2) according to the first comparison sequence value. Specifically, the test device 30 converts the first comparison sequence value signal into the confirmation signals. For example, the test device 30 converts the digital value of each bit in the first comparison sequence value into a confirmation signal according to the arrangement order of the signal channels (such as the third signal channel Bin1 to the tenth signal channel Bin8) between the test device 30 and the classification device 20. Specifically, the first confirmation signal Bin1_2 to the eighth confirmation signal Bin8_2 are respectively transmitted via the third signal channel Bin1 to the tenth signal channel Bin8, and the test device 30 converts the digital value of the least significant bit in the first comparison sequence value into the first confirmation signal Bin1_2, and converts the digital value of the second least significant bit in the first comparison sequence value into the second confirmation signal Bin2_2, and so on. In a demonstration example, as Figure 6 shown, assuming that the first comparison sequence value is "01000011", which corresponds to the character "C" in ASCII encoding. At this time, the test device 30 generates the first confirmation signal Bin1_2, the second confirmation signal Bin2_2, and the seventh confirmation signal Bin7_2 that are in effect, and generates the third confirmation signal Bin3_2 to the sixth confirmation signal Bin6_2 and the eighth confirmation signal Bin8_2 that are ineffectual.
[0080] In step S209 of the present embodiment, the classification device 20 combines the digital values of the received confirmation signals (such as the first confirmation signal Bin1_2 to the eighth confirmation signal Bin8_2) according to the arrangement order of the signal channels (such as the third signal channel Bin1 to the tenth signal channel Bin8) between the test device 30 and the classification device 20 to obtain a second feedback value. Specifically, the first confirmation signal Bin1_2 to the eighth confirmation signal Bin8_2 are respectively transmitted via the third signal channel Bin1 to the tenth signal channel Bin8. The classification device 20 uses the digital value represented by the first confirmation signal Bin1_2 corresponding to the third signal channel Bin1 as the least significant bit of the second feedback value, and uses the digital value represented by the second confirmation signal Bin2_2 corresponding to the fourth signal channel Bin2 as the second least significant bit of the second feedback value, and so on to combine the second feedback value. Then, if the second feedback value matches the second comparison sequence value, it indicates that the test result signals are correct (for example, the test result signals have not changed due to factors such as signal loss and signal interference). At this time, the classification device 20 performs corresponding actions according to the test result signals (the first test result signal Bin1_1 to the eighth test result signal Bin8_1). If the second feedback value does not match the second comparison sequence value, it indicates that the test result signal is incorrect (for example, the test result signal has changed due to factors such as signal loss and signal interference). At this time, the classification device 20 performs a preset action.
[0081] In some embodiments, the types of the test result signals output by the test device 30 are classified into a good product type, a first defective product type (i.e., a partial failure type), and a second defective product type (i.e., a complete failure type). For example, as Figure 1 and Figure 3 shown, when only the first test result signal Bin1_1 is effective, its corresponding type is the good product type. When only the second test result signal Bin2_1 is effective, its corresponding type is the first defective product type. When only the third test result signal Bin3_1 is effective, its corresponding type is the second defective product type.
[0082] As Figure 3As shown in the first block A, in some embodiments of step S205, the classification device 20 outputs the second start signal SOT_2 to the test device 30 and performs the subsequent step S207 when receiving the first end signal EOT_1 and the first test result signal Bin1_1 belonging to the good product type is valid (where the second test result signal Bin2_1 and the third test result signal Bin3_1 are both invalid). That is to say, the classification device 20 outputs the second start signal SOT_2 to the test device 30 and performs the subsequent signal verification (such as steps S207 and S209) only when the device under test 40 being currently tested may be a good product. In this way, the consumption of computing resources can be saved, and it can be confirmed whether the device under test 40 being currently tested is indeed a good product after signal verification. In this embodiment, in step S209, the classification device 20 determines whether the test result signal belonging to the good product type is correct. However, the present invention is not limited to this. In addition to determining whether the test result signal belonging to the good product type is correct, the classification device 20 can also determine whether the test result signals belonging to other types (such as the first defective product type and the second defective product type) are correct.
[0083] As Figure 3 As shown in the third block C, in some embodiments of step S205, the classification device 20 can also output the second start signal SOT_2 to the test device 30 and perform the subsequent step S207 when receiving the first end signal EOT_1 and the second test result signal Bin2_1 belonging to the first defective product type is valid (where the first test result signal Bin1_1 and the third test result signal Bin3_1 are both invalid). That is to say, the classification device 20 can also output the second start signal SOT_2 to the test device 30 and perform the subsequent signal verification (such as steps S207 and S209) when the device under test 40 being currently tested may be a defective product with partial failures, so as to confirm whether the device under test 40 being currently tested is indeed the first type of defective product (i.e., the defective product with partial failures). In this embodiment, in step S209, the classification device 20 determines whether the test result signal belonging to the first defective product type is correct. However, the present invention is not limited to this. In addition to determining whether the test result signal belonging to the first defective product type is correct, the classification device 20 can also determine whether the test result signals belonging to other types (such as the good product type and the second defective product type) are correct.
[0084] As Figure 3As shown in the second block B, in some embodiments of step S205, the classification device 20 may also be such that when receiving the first end signal EOT_1 and the third test result signal Bin3_1 belonging to the second defective product type is valid (wherein the first test result signal Bin1_1 and the second test result signal Bin2_1 are both invalid), instead of performing the output of the second start signal SOT_2 and its subsequent steps in step S205, it determines that the device under test 40 currently being tested is a second type of defective product (i.e., a completely failed defective product), and classifies the device under test 40 currently being tested into the second defective product area. In this way, the device under test 40 that is determined to be a completely failed defective product can be directly recycled and scrapped, and the consumption of computing resources can be saved. However, the present invention is not limited thereto. The classification device 20 may also be such that when receiving the first end signal EOT_1 and the third test result signal Bin3_1 belonging to the second defective product type is valid (wherein the first test result signal Bin1_1 and the second test result signal Bin2_1 are both invalid), it outputs the second start signal SOT_2 to the test device 30 (step S205) and performs the subsequent step S207.
[0085] In summary, according to some embodiments, the present invention can determine whether the test result signal is correct through the confirmation signal, and when the classification device determines that the test result signal is correct (for example, the test result signal has not changed due to factors such as signal loss and signal interference), it then performs corresponding actions according to the test result signal (for example, correctly classifying the device under test). In this way, it is possible to prevent the classification device from performing incorrect actions (such as incorrectly classifying the device under test) due to an incorrect test result signal (for example, the test result signal has changed due to factors such as signal loss and signal interference).
[0086] Of course, the present invention may also have many other embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and modifications according to the present invention, but these corresponding changes and modifications should all fall within the protection scope of the claims of the present invention.
Claims
1. An electronic component testing and sorting system, characterized in that, Comprising: A classification device that outputs a first start signal; and A test device connected to the classification device; the test device tests a device under test in response to the first start signal to generate a plurality of test result signals, and outputs a first end signal and the plurality of test result signals to the classification device; Wherein, when the classification device receives the first end signal and one of the plurality of test result signals is valid, the classification device outputs a second start signal to the test device; the test device generates a plurality of confirmation signals in response to the second start signal, and outputs a second end signal and the plurality of confirmation signals to the classification device; the classification device determines whether at least one of the test result signals is correct according to the plurality of confirmation signals in response to the second end signal.
2. The electronic component testing and sorting system according to claim 1, wherein When the device under test passes all the test rules of the test device, the plurality of test result signals generated by the test device belong to a good product type.
3. The electronic component testing and classification system according to claim 2, wherein The classification device outputs the second start signal to the test device when it receives the first end signal and the plurality of test result signals belonging to the good product type.
4. The electronic component testing and classification system according to claim 1, wherein When the device under test passes some of the test rules of the test device, the plurality of test result signals generated by the test device belong to a first defective product type.
5. The electronic component testing and sorting system according to claim 4, wherein The classification device outputs the second start signal to the test device when it receives the first end signal and the plurality of test result signals belonging to the first defective product type.
6. The electronic component testing and classification system according to claim 1, wherein When the device under test fails any of the test rules of the test device, the plurality of test result signals generated by the test device belong to a second defective product type.
7. The electronic component testing and sorting system according to claim 6, wherein When the classification device receives the first end signal and the plurality of test result signals belonging to the second defective product type, it does not output the second start signal to the test device, and classifies the device under test into a second defective product area.
8. The electronic component testing and sorting system according to claim 1, wherein, Further comprising a plurality of signal channels located between the classification device and the test device to transmit the plurality of test result signals and the plurality of confirmation signals; wherein, the test device performs a logical inversion operation on the plurality of test result signals to generate the plurality of confirmation signals, and the classification device determines whether the test result signal and the confirmation signal received from the same signal channel are complementary. When the test result signal and the confirmation signal in the same signal channel are complementary, the classification device determines that each test result signal is correct. When the test result signal and the confirmation signal in the same signal channel are not complementary, the classification device determines that each test result signal is incorrect.
9. The electronic component testing and classification system according to claim 1, characterized in that, Further comprising a plurality of signal channels located between the classification device and the testing device for transmitting the plurality of test result signals and the plurality of confirmation signals; wherein, the testing device stores a first comparison sequence value and generates the plurality of confirmation signals by using the first comparison sequence value; wherein, the classification device converts the plurality of confirmation signals received by it into a return value according to the arrangement order of the plurality of signal channels; wherein, the classification device stores a second comparison sequence value identical to the first comparison sequence value, generates an operation value by using the return value, and determines whether the operation value conforms to the second comparison sequence value. When the operation value conforms to the second comparison sequence value, the classification device determines that each of the test result signals is correct. When the operation value does not conform to the second comparison sequence value, the classification device determines that each of the test result signals is incorrect.
10. The electronic component testing and sorting system according to claim 9, characterized in that, The testing device converts the plurality of test result signals generated by it into a first sequence combination value according to the arrangement order of the plurality of signal channels, and generates the plurality of confirmation signals by using the first comparison sequence value and the first sequence combination value; wherein, the classification device converts the plurality of test result signals received by it into a second sequence combination value according to the arrangement order of the plurality of signal channels, and generates the operation value by using the return value and the second sequence combination value.
11. An electronic component testing and classification method, characterized in that, Comprising: Output a first start signal through a classification device; Through a testing device, in response to the first start signal, test a device under test to generate a plurality of test result signals, and output a first end signal and the plurality of test result signals to the classification device; When the classification device receives the first end signal and one of the plurality of test result signals is valid, output a second start signal to the testing device through the classification device; Through the testing device, in response to the second start signal, generate a plurality of confirmation signals, and output a second end signal and the plurality of confirmation signals to the classification device; And Through the classification device, in response to the second end signal, determine whether at least one of the test result signals is correct according to the plurality of confirmation signals.
12. The method for testing and classifying electronic components according to claim 11, wherein, When the device under test passes all the test rules of the testing device, the plurality of test result signals generated by the testing device belong to a good product type.
13. The method for testing and classifying electronic components according to claim 12, wherein The classification device outputs the second start signal to the testing device when it receives the first end signal and the plurality of test result signals belonging to the good product type.
14. The method for testing and classifying electronic components according to claim 11, wherein When the device under test passes some of the test rules of the testing device, the plurality of test result signals generated by the testing device belong to a first defective product type.
15. The method for testing and classifying electronic components according to claim 14, wherein, The classification device outputs the second start signal to the testing device when it receives the first end signal and the plurality of test result signals belonging to the first defective product type.
16. The method for testing and classifying electronic components according to claim 11, wherein When the device under test fails any of the test rules of the testing device, the plurality of test result signals generated by the testing device belong to a second defective product type.
17. The method for testing and classifying electronic components according to claim 16, wherein, When receiving the first end signal and the multiple test result signals belonging to the second defective product type, the classification device does not output the second start signal to the test device and classifies the device under test into a second defective product area.
18. The method for testing and classifying electronic components according to claim 11, wherein, The classification device and the test device transmit the multiple test result signals and the multiple confirmation signals via multiple signal channels; wherein, the test device performs a logical inversion operation on the multiple test result signals to generate the multiple confirmation signals, and the classification device determines whether the test result signals and the confirmation signals received from the same signal channel are complementary. When the test result signals and the confirmation signals on the same signal channel are complementary, the classification device determines that each of the test result signals is correct. When the test result signals and the confirmation signals on the same signal channel are not complementary, the classification device determines that each of the test result signals is incorrect.
19. The method for testing and classifying electronic components according to claim 11, wherein, The classification device and the test device transmit the multiple test result signals and the multiple confirmation signals via multiple signal channels; wherein, the test device stores a first comparison sequence value and generates the multiple confirmation signals by using the first comparison sequence value; wherein, the classification device converts the multiple confirmation signals received by it into a feedback value according to the arrangement order of the multiple signal channels; wherein, the classification device stores a second comparison sequence value identical to the first comparison sequence value, generates an operation value by using the feedback value, and determines whether the operation value matches the second comparison sequence value. When the operation value matches the second comparison sequence value, the classification device determines that each of the test result signals is correct. When the operation value does not match the second comparison sequence value, the classification device determines that each of the test result signals is incorrect.
20. The method for testing and classifying electronic components according to claim 19, wherein The test device converts the multiple test result signals generated by it into a first sequence combination value according to the arrangement order of the multiple signal channels, and generates the multiple confirmation signals by using the first comparison sequence value and the first sequence combination value; wherein, the classification device converts the multiple test result signals received by it into a second sequence combination value according to the arrangement order of the multiple signal channels, and generates the operation value by using the feedback value and the second sequence combination value.