Development method and development platform of ATE-based power management chip test system

Abstract

The invention relates to a development method and a development platform of a power management chip test system based on ATE, and belongs to the technical field of chips. By adopting the development method and the development platform provided by the invention, the test specification is established; designing a test board card; debugging and optimizing a chip test program; and the consistency and the stability of the chip test system are verified. Therefore, the chip testing system developed by using the method and the platform can effectively complete batch testing of the chips, and the accuracy, the precision, the performance integrity and the reliability of the chips after the testing is completed are ensured. Therefore, the invention provides a comprehensive and systematic power management chip test development architecture, the ATE automatic test development requirement of the chip is met, standardization and simplification are realized by the development method and platform, related technicians can conveniently use the development method and platform to carry out test system development work, and the development method and platform can be applied to various batch automatic tests of the chip.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, particularly to the field of chip testing technology, and specifically refers to a development method and a development platform for a power management chip testing system based on ATE. Background Art

[0002] With the rapid development of the domestic chip industry, domestic substitution, the chip blockade by the United States, and the strong support from the national level for technological innovation, the research and investment in related fields of chip testing have increased significantly. The technological investment in batch automated testing of chips based on ATE has also received increasing attention. The testing requirements for chips in fields such as analog power chips, power devices, and consumer electronics are constantly increasing. At the same time, with the rise of domestic chip testing machine manufacturers, especially the continuous promotion and application of the STS8200 series of testing machines by Beijing Huafeng and the CTA8280 series of testing machines by Hangzhou Changchuan Technology, the technical requirements for batch testing of chips are also constantly increasing, directly driving the growth of the ATE testing demand for chips.

[0003] In the aspect of batch automated testing (ATE) of chips, how to complete the development of systematic batch testing of chips, and how to ensure that the developed testing system will not have problems during the subsequent application process of chip mass production testing, and ensure the accuracy, precision, fluency, integrity, and reliability of testing, are tests for test developers, internal driving forces for test development technology, and requirements for test technology standardization.

[0004] Currently, in the development technology of chip ATE testing, each chip company has a set of testing systems and requirements based on its own chips. However, overall, there is no general technical template and systematic technical requirements provided to the relevant staff engaged in chip testing. Summary of the Invention

[0005] The object of the present invention is to overcome the above-mentioned disadvantages in the prior art and provide a standardized design of chip-based test development technology, a development method and a development platform for a power management chip testing system based on ATE that systematically improves all aspects of chip test development. The chip testing system developed based on this method and platform can effectively complete batch testing of chips and ensure the accuracy, precision, performance integrity, and reliability of the chips after testing.

[0006] In order to achieve the above object, the development method of the power management chip testing system based on ATE of the present invention includes:

[0007] (A) Establish test specifications, where the test specifications include test parameter indicators and grading requirements, test circuit diagrams and packaging forms, version definitions, and chip descriptions;

[0008] (B) Design a test board according to the test specifications, including the schematic diagram and PCB layout of the test board, as well as the design of the socket and quantity of the test board;

[0009] (C) Debug and optimize the chip test program applied to the test board;

[0010] (D) Use test samples to verify the consistency and stability of the chip test system.

[0011] In the development method of the ATE-based power management chip test system, the step (A) specifically includes:

[0012] (A1) Establish test parameter indicators and grading requirements, including marking the compliance identifier; indicating the meaning of each parameter; determining the specific test method for each parameter and the referenced circuit structure diagram; determining the lower limit value, upper limit value, and typical value of the test value for each parameter; determining the hardware bin and software bin in the specific test program;

[0013] (A2) Establish test circuit diagrams and packaging forms. According to the specific test methods of the test parameters, determine the corresponding test circuit diagrams and device models. For tests related to timing, provide relevant timing signal diagrams, and determine the packaging form and pin definition of the chip;

[0014] (A3) Determine the version definition and chip description, and clarify the version number, production time, packaging information, test board schematic diagram, test machine model selection, test site configuration, and test time UPH of each test specification.

[0015] In the development method of the ATE-based power management chip test system, the determination of the chip packaging form includes the CP test specification and the FT test specification.

[0016] In the development method of the ATE-based power management chip test system, the step (B) specifically includes:

[0017] (B1) Design the schematic diagram and PCB layout of the test board according to the test specifications. Specifically, according to the test parameter indicators and corresponding test methods and conditions in the test specifications, combined with the socket structure of the test sorter and the interface channel structure of the test machine platform, formulate the schematic diagram and PCB layout of the test board;

[0018] (B2) Determine the socket of the test board for the development of the test program of the test board; test and verify the demo board and the test fixture board for the test and verification of parameter performance;

[0019] (B3) Determine the number of test boards according to multi-site tests to adapt to batch ATE tests for multi-sites.

[0020] In the development method of the ATE-based power management chip test system, the step (C) specifically includes:

[0021] (C1) Debug the chip test program, including implementing parameter configuration and testing on the test board, outputting test values to determine whether the test values are within the theoretical value range, and finally confirming whether the test results of the parameters are qualified. The test content includes hardware configuration information, test binning, hardware configuration information, program version information, test program compilation, and time efficiency optimization;

[0022] (C2) Optimize the chip test program, including chip Cont test to test the contact resistance between the pins of the chip and the socket; changes in the multi-site test program and the single-site test program of the chip; site resistance configuration to bind site information.

[0023] In the development method of the ATE-based power management chip test system, the step (D) specifically includes:

[0024] (D1) Determine multiple golden samples;

[0025] (D2) Use the golden samples to verify the test consistency of different boards for multiple sites of the same chip and the test consistency of different sites of the same board;

[0026] (D3) Verify the consistency between the test values in the laboratory and the test values of the test system developed by this development method.

[0027] In the development method of the ATE-based power management chip test system, the step (D1) is specifically: determine at least 20 golden samples based on the data stability of no less than 100 cycles.

[0028] The present invention also provides a development platform for an ATE-based power management chip test system, which includes:

[0029] A test specification establishment module for establishing test specifications, including test parameter indicators and grading requirements, test circuit diagrams and package forms, version definitions, and chip descriptions;

[0030] A test board design module for designing test boards according to the test specifications, including designing the schematic diagram and PCB diagram of the test board and designing the socket and quantity of the test board;

[0031] A test program debugging module for debugging and optimizing the chip test program applied to the test board

[0032] A verification module for verifying the consistency and stability of the chip test system using test samples

[0033] In the development platform of the ATE-based power management chip test system, the verification module specifically includes

[0034] Multiple golden samples

[0035] A consistency verification unit for verifying the test consistency of different boards at multiple sites of the same chip and the test consistency of different sites on the same board using the golden samples; and verifying the consistency between the laboratory test values and the test values of the test system developed by this development method

[0036] In the development platform of the ATE-based power management chip test system, the multiple golden samples are determined based on data stability of no less than 100 cycles to obtain at least 20 golden samples

[0037] By adopting the development method and development platform of the ATE-based power management chip test system of the present invention, through establishing test specifications, designing test boards, debugging and optimizing chip test programs, and then verifying the consistency and stability of the chip test system. Thus, it is ensured that the chip test system developed using the method and platform of the present invention can effectively complete batch testing of chips, ensuring the accuracy, precision, performance integrity, and reliability of the chips after testing. The present invention provides a comprehensive and systematic power management chip test development architecture, meeting the ATE automation test development requirements of chips, and the development method and platform of the present invention are standardized and simplified, facilitating relevant technical personnel to use them for test system development work, and can be specifically applied to chip batch automation test fields such as CP (wafer) test, FT (package) test, reliability test, and three-temperature test of chips Brief Description of the Drawings

[0038] Figure 1 It is the overall block diagram of the ATE-based power management chip test development method of the present invention

[0039] Figure 2 Schematic diagrams of three components of the first part of the chip test development system method, namely chip test specifications

[0040] Figure 3 Schematic diagram of the detailed content of the test architecture of the test board in the second part of the chip test development system method

[0041] Figure 4 Schematic diagram of the detailed content of the test architecture of the test program in the third part of the chip test development system method

[0042] Figure 5 Schematic diagram of the breakdown content of the test architecture of the test sample in the fourth part of the chip test development system method;

[0043] Figure 6 Test development flowchart of the specific implementation method 1 of the ATE-based power management chip test development method of the present invention;

[0044] Figure 7 Test development flowchart of the specific implementation method 2 of the ATE-based power management chip test development method of the present invention. Specific implementation method

[0045] In order to more clearly understand the technical content of the present invention, the following specific examples are given for detailed description.

[0046] Please refer to Figure 1 As shown, it is the overall block diagram of the ATE-based power management chip test development method of the present invention.

[0047] The main body is divided into four parts: (A) The first part is the chip test specification; (B) The second part is the chip test board; (C) The third part is the chip test program; (D) The fourth part is the test sample.

[0048] The four parts of the overall architecture of the present invention have a sequential connection relationship. The chip test specification in the first part is to make the chip test specification according to the specific functions and performance parameters of the chip before the ATE test development work of the chip. This specification includes the test parameter requirements of the chip, the test implementation method, the parameters of the test development peripheral circuits and devices, and the test precautions. The first part is the overview and basic framework of the entire ATE test system architecture, and all subsequent work is based on the test specification of the first part. Based on the completed chip test specification, the work content is divided into three parts according to the test requirements: the second part of the chip test board, the third part of the chip test program, and the fourth part of the chip test sample.

[0049] The chip test specification in the first part is the main component of this framework, the most important technical indicator for chip ATE test development, the guiding document for test development, the parameter test indicator of the chip, the judgment standard for whether the chip is qualified, and the reference system for subsequent chip test improvement and data summary.

[0050] As Figure 2 shown, the first part of the chip test specification consists of the following three aspects: test parameter indicators and grading requirements; test circuit diagrams and package forms; version definitions and chip descriptions and others.

[0051] Test parameter indicators and grading requirements: Define the functional parameters of the chip here; mark the compliance identification; indicate the meaning of each parameter; write in detail the specific test methods for each parameter and the referenced circuit structure diagrams; write the lower limit value, upper limit value, and typical value of the test values of this parameter; write the specific hardware bins, software bins, etc. in the corresponding program. This part is the main part of the chip test specification, taking into account all aspects, providing a theoretical basis and clear performance indicators for subsequent chip test development.

[0052] Test circuit diagram and package form: The parameter tests of the test parameter indicators need to be implemented on a specific test circuit. This part gives the specific test circuit diagram and the specific model of the device according to the detailed test methods of the test parameters. If there are multiple circuit diagrams at the same time, they all need to be marked one by one, and the specific circuit diagram corresponding to the specific item should be clearly indicated. If there are timing-related tests, relevant timing signal diagrams also need to be provided to facilitate the test reference of test engineers during test development. Finally, the package form, pin definition, etc. of the chip also need to be given.

[0053] Version definition, chip description, and others: Each chip test specification also needs to indicate the version number, production time, production personnel, review personnel, etc. of this specification, so that the specific reasons and times for upgrades can be traced after subsequent test specification upgrades and iterations. Other information can also be indicated in the test specification, such as specific package information, schematic diagrams of test boards, selection of test models, configuration of test sites, test time UPH, etc.

[0054] The formulation of the chip test specification needs to set a relatively fixed standard content, and the standard content should include the three aspects described above. The formulation of the chip test specification is not only the work of test engineers. The formulation of this part of the content needs to comprehensively consider various factors on the existing framework, such as the specific parameter performance of the chip, the special test requirements of designers for the chip, the equipment conditions for chip test development, packaging factors, etc. At the same time, the judgment and trade-off criteria also need to be comprehensively considered. Some special test requirements of designers for the chip will increase the chip test time, and some chip test development equipment conditions do not meet certain test contents, and correspondingly, some parameter tests will also be reduced as appropriate.

[0055] The subsequent chip test development work can only be carried out after the chip test specification is formulated. At this time, the formulated chip test specification is not the complete version, and subsequent version iterations and upgrades will be carried out according to the specific test and debugging situations and chip revisions. Generally, the first formulated test specification is called the engineering version to distinguish it from the official version during batch testing. At the same time, it is necessary to understand that both the engineering version and the official version will be continuously iterated and upgraded. The initial engineering version of the chips are all tested and developed for the first time. Facing many unknown factors, preliminary specifications can be formulated based on theoretical simulations or by referring to the reference specifications. In the preliminary specifications, all aspects of the chips need to be considered, including the verification of the test conditions for each parameter, the requirements of parameter testing for equipment, and other details. The batch testing standards and requirements for chip testing, as well as the requirements for testing efficiency, etc.

[0056] The factor that most affects the test cost is the test efficiency. The specific indicator reflecting this is the UPH value of the test. The higher the UPH, the higher the test efficiency, and correspondingly, the lower the chip test cost. On the basis of ensuring the chip function test, improving the chip test efficiency is to reduce the chip test cost, which is a major consideration in test development. In the engineering batch, in order to verify the chip performance, comprehensive tests of the chips can be carried out regardless of cost, and some demanding test items can also be arranged for testing. However, when entering the batch production test, a certain cost-effectiveness needs to be pursued. The replacement of some test items and version iterations are for continuously improving the test efficiency and preparing for reducing the test cost.

[0057] The formulation of the chip test specification is in the preliminary preparation stage of the entire chip test development process. This stage can be carried out during the chip tape-out stage or the project determination stage before tape-out. The earlier the preparation, the more beneficial it is for the subsequent test development work. After the specification is formulated, it is necessary to comprehensively consider what tests need to be carried out during the entire packaging and testing process of the chip, as well as the equipment situation and application circuits to be used, and experimental circuits, etc.

[0058] In the packaging and testing requirements of analog chips, CP testing and FT testing are essential in the chip test specification. Even the chip reliability testing or three-temperature testing, etc., can be upgraded and referenced according to the FT test specification. Therefore, the chip test specification can be mainly divided into CP test specification and FT test specification. For CP testing, since it uses a needle card probe for contact, the number of test items that can be tested is relatively less than that of FT. The main reason is that the probes of the needle card are very thin and the load-carrying current capacity is limited, which poses a great challenge to the testing of high-current load-carrying projects. Most of the strong load-carrying projects are tested and verified at the FT stage.

[0059] The second part of the ATE-based power management chip test development method is the test board. It includes the pin card board for CP test welding probes and the test board in the FT test stage (the test board that connects the test machine resources and the sorter socket). The test board is a hardware connection device, the material basis for supporting the entire ATE test development work, and also the physical architecture of the entire architecture. On this basis, the entire ATE test of the chip is completed through a series of software program development and hardware device calls.

[0060] As Figure 3 Shown is the detailed breakdown of the architecture of the test board in the second part of the present invention. The test board can also be referred to as the test hardware development part, which needs to be prepared in both the CP test and FT test stages, and the preparation contents for both are basically the same. There are mainly three aspects: one is the schematic diagram and PCB layout of the test board; the second is the socket of the test board, the test verification demo board, and the test fixture board; the third is the quantity of the test board, for multi-site testing during mass production and subsequent board maintenance and repair, etc. The test board is the bridge connecting the chip and the test platform, as well as the bridge connecting the test machine and the sorter, and is even the most important hardware support part of the entire test development part. This part of the structure is the central structure of the entire test development architecture, providing basic hardware support for the entire development test.

[0061] The first aspect of the detailed breakdown of the test board architecture: the schematic diagram and PCB layout of the test board. This is the hardware structure of the entire test development system architecture, belonging to the hardware support part for realizing the test function of the chip. According to the specific test parameter items of the chip test specification, the test methods and conditions for each test item, the peripheral device conditions used during testing, etc., combined with the socket structure of the test sorter and the interface channel structure of the test machine platform, the specific test board is formulated. The test principle diagram and PCB layout of the board are formulated in this link. Only after using the completed PCB layout to produce the corresponding test board in the PCB factory can subsequent software program development and chip test debugging work be carried out.

[0062] The second aspect of the architecture breakdown of the test board: the socket of the test board, the test verification demo board, and the test fixture board. These three test tools are used to assist in the subsequent test development of the test board. The socket is used for the test program development of the test board; the test verification demo board is used for the test verification of certain parameter performances; the function of the test fixture board is equivalent to that of the test verification demo board. The difference is that the demo board solders the chip on the PCB board for parameter test verification, while the fixture board uses a test fixture to test the chip performance. The advantages and disadvantages of the two are as follows: the demo board has good contact and is suitable for high-current load testing; the fixture board is convenient for testing, does not require chip soldering, and is suitable for the verification of defective products and sample proofing in the later stage. The test performances of the two are consistent most of the time, and there are differences in a few cases that need to be analyzed according to the special situation of the chip.

[0063] The third aspect of the architecture breakdown of the test board: the number of test boards. In the test development of the chip, in order to improve the test efficiency, batch ATE tests are generally carried out at multiple sites. Specifically, whether it is 2 sites, 4 sites, 8 sites or 16 sites can be flexibly selected according to the test situation of the chip. Generally, as many sites as possible are selected for mass production testing under the condition that test resources permit. Therefore, as many test boards as possible must be prepared in advance in the link of preparing the test board. At the same time, the test boards will also be maintained and repaired during the subsequent mass production testing, and it is also necessary to back up multiple test boards.

[0064] As Figure 4 shown is the breakdown content of the architecture of the third part of the test program of a power management chip test development system based on ATE. The test program can also be called the test software development part, which mainly includes two aspects: one is test program debugging, and the other is test program optimization. Test program debugging is the main part, which includes many contents such as parameter configuration, test binning, hardware configuration information, program name and version information, test program compilation and time optimization. Test program optimization includes some detailed parts, such as chip Cont test, chip multi-site test program, site resistance configuration, etc. The two parts complement each other, perfect the entire test program part in the chip test program part, take the resource configuration of the test platform as the main body, and finally complete the purpose of the entire chip automated test through the test debugging call of the program software. The test program plays a connecting role in the entire test development system architecture.

[0065] The first aspect in the architectural breakdown of the test program: test program debugging. The content of this part is to establish the chip test program and conduct one-by-one test debugging according to the test parameter items specified in the chip test specification. By calling the resources of the test platform through the program, the parameter test of the chip is implemented on the test board, and the test values are output to determine whether the test values meet the expected goals and are within the theoretical value range, and finally confirm whether the test results of the parameters are qualified. This process not only includes the test of all parameters, but also needs to pay attention to the overall status of the chip parameters, the hardware configuration information of the test platform, the test binning and grading settings, the version information of the program, the specific compilation information, and the time efficiency optimization after debugging, etc.

[0066] The parameter test of the entire chip is involved in the test program debugging. All kinds of discrepancies from the theoretical values and test anomalies that occur during the test debugging require the test engineer to conduct some test verifications to confirm the specific failure reasons. The verification method can be to compare with the verification test data on the Demo board or fixture board proposed in the previous test board part. Find the specific failure reasons through comparison verification, and then optimize and improve through corresponding improvement plans.

[0067] The second aspect in the architectural breakdown of the test program, test program optimization, includes details such as Cont test, chip multi-site test program, site resistance program, etc. The purpose of this part is to improve the test efficiency and perfect the mass production test. Among them, the Cont test is the contact resistance test between the pins of the chip and the socket to ensure good contact between the pins of the chip inside the socket. There are also changes between the multi-site test program and the single-site test program, aiming to improve and perfect the test efficiency. The final site resistance configuration aims to bind site information, avoid misinsertion of boards and programs of different sites caused by operator errors, and also ensure the stability and accuracy of site testing.

[0068] The content of the test program part is the software program design part in the overall chip test development system architecture. This part of the work is based on the test board, and the two also complement and influence each other. For test development personnel, both the test board and the test program are integrated. When preparing the test board, a general understanding and planning of the test program content of all test parameters are required. Debugging the test program and optimizing the test program in the test program part are both specific implementations of the test scheme for the parameters in the previous test specification. This requires a certain level of technical proficiency for test development personnel. They not only need to be familiar with the test functions and parameter performance of the chip, but also need to be familiar with and understand the structure of the test platform and the test program compilation method, and more importantly, they need to accumulate practical hands-on experience.

[0069] Such asFigure 5 Shown is the architecture breakdown of the fourth part of the test sample of an ATE-based power management chip test development system. The verification of the test sample is mainly carried out in the form of test data verification, which is the verification stage of the test results. There are mainly three aspects: one is 20 golden samples with 100-loop stability data; the second is the test consistency of different boards at multiple sites of the same chip, and the consistency of different sites on the same board; the third is the consistency between the laboratory test values and the tester test values. The role of the test sample part as a part of the chip test development system architecture is to ensure the test accuracy of the chip. The test development results of the chip are output in the form of data, and confirming the test accuracy of the chip in the output result of the data is an important part of the chip ATE test work.

[0070] The test data of the first part of 20 golden samples with 100 loops is to confirm the stability of the chip test. The test consistency of different boards at multiple sites of one chip in the second part and the consistency of different sites on the same board ensure the accuracy of the chip in multi-site testing and multi-board testing during mass production. The consistency between the laboratory test values and the tester test values in the third part is also to confirm that the test debugging results are accurate and reliable.

[0071] The fourth part of the test sample is the test data confirmation stage of the entire chip test development system architecture. Here, it serves as a bridge connecting engineering batch testing and mass production testing. After the test debugging is completed, in order to ensure the accuracy and stability of the test, the proofreading work of the test sample is essential. The proofreading of the test sample is also a necessary consideration in the batch testing process of the chip, because during the mass production testing of the chip, due to various factors in the large number of chip tests, the test results of some chip parameters will gradually deviate over time. Regular proofreading of the sample will improve the test results and increase the test accuracy and test yield.

[0072] An ATE-based power management chip test development system architecture of the present invention is based on an ATE test platform, and shows in the form of a system architecture the main contents and composition architecture forms required for the test development of the chip, providing a general architecture form of a complete test development plan in the field of chip batch testing to realize the program development and test development process plan for the ATE automation test of the chip. The chip test development system architecture covers all aspects of chip test development, highlighting the engineering key points and usage conditions of chip test development. It provides a concise and detailed structural plan and application plan framework for the ATE test of the chip. It can enable relevant personnel to quickly familiarize themselves with the task requirements and key working directions of chip test development.

[0073] The following illustrates the actual application of the present invention through specific embodiments. Specific Embodiment 1

[0075] As Figure 6 shown, the specific scheme of a method for testing and developing a power management chip based on ATE according to the present invention is as follows: The complete implementation scheme is implemented in the entire chip processing flow, and the composition of the system architecture is embedded in the entire process from chip design to final packaging. The test and development system architecture shown in the present invention is applied to the chip ATE test link in the chip design, development, and test industry.

[0076] As Figure 6 shown, in the preparation stage of step 1 when the chip is established, the design circuit work, layout design work, etc. of the chip can be carried out synchronously. According to the specific performance of the chip, or the reference sample, or the theoretical performance, or based on simulation data, etc., the parameter performance and working principle of the chip can be initially confirmed. Based on this, a chip test specification is initially made.

[0077] Step 2: Make the chip test specification. During the making process, the content of the test specification needs to be continuously corrected, and the corresponding test specification content is formulated according to the existing test specification format. The specific chip test specification consists of the following three aspects: 1) Test parameter indicators and grading requirements, 2) Test circuit diagram and packaging form, 3) Version definition, chip description, and others. The above three aspects constitute the main content of the chip test specification. According to the specific parameter performance of the chip, combined with the actual equipment resource test conditions, each parameter to be tested in the chip test specification, as well as the specific test methods, conditions, and the upper and lower limit ranges of the test values, are formulated. Test parameters with special requirements need to be treated specially, and if grading is required, it also needs to be specially stated.

[0078] In addition to the parameter items of the chip test, the chip test specification also needs to provide the remaining conditions for the chip test, such as the parameter settings of the periphery of the test circuit and peripheral devices for the chip test, and the initial version number of the chip test, so as to facilitate subsequent test specification changes and upgrades.

[0079] The chip test can include two parts: CP test and FT test of the chip. The CP test and FT test are for the test requirements at different stages during the chip manufacturing and packaging process. Whether to conduct the CP test and FT test is confirmed according to the specific requirements of the chip.

[0080] During the chip design process, considering the technical parameter fluctuations of the manufacturing process, test trimming (Trim) is designed to trim and correct the key parameters of the chip. Therefore, the trimming (Trim) method of the chip and whether it is trimmed in the CP stage or the FT stage also need to be noted in the test specification. The trimming (Trim) of some parameters also requires special technical support, and there are certain requirements for the equipment of the test machine and the compilation of the test program.

[0081] The chip test specification can be divided into two parts in the subsequent steps. On the one hand, it is the wafer off-line in step 3 after the normal chip manufacturing process. This process is controlled by equipment machines and wafer manufacturers. For the entire test development system, steps 2-1 to 2-4 are the main components to be embedded in the chip manufacturing process.

[0082] As Figure 6 As shown in step 2-1, the production of the CP test probe card is a step after the chip test specification is completed and it is confirmed that CP testing will be carried out. The production of the CP test probe card is mainly based on the test requirements inside the chip test specification and the equipment resources of the CP test manufacturer. At the same time, considering the test parameter requirements, it needs to be completed before the wafer off-line in step 3.

[0083] As shown in step 2-2, the production of the FT test board is carried out after the chip test specification is completed. At the same time, considering the chip packaging form, the corresponding socket structure, the test machine platform used, etc., after comprehensively considering the above conditions, the FT test board of the chip is produced.

[0084] As shown in step 2-3, for the test program debugging, after the step of the test board is completed, the test machine of the test platform is used to test and debug the chip. This debugging needs to be carried out in both the CP test stage and the FT test stage, and the test development and debugging are carried out according to the corresponding test specification. Chip test debugging is a verification and confirmation of the chip performance parameters.

[0085] As shown in step 2-4, for the test sample proofreading, this step is a data confirmation that must be carried out before the chip test. Through this step, it is ensured that the data tested by the test machine is accurate. At the same time, it is also necessary to verify the test impact of different sites and different boards on the chip to ensure that the test values of the chip are accurate.

[0086] As shown in step 3, the wafer off-line means that the chip wafer is completed. There are thousands of chip dies concentrated on one wafer, which are generally called dies. Each die is a chip, and here the wafer is the chip integration for the subsequent middle test.

[0087] As shown in step 4, for the CP test, the CP test probe card made in step 2-1 is needed for testing. Before testing, the specific test items need to be debugged. A series of parameter tests are carried out on the chip, and the test data is analyzed to judge whether the test results meet the theoretical values. There may also be trimming items during the CP test. Necessary trimming basis must be provided for the trimming test during the trimming item test. CP test is the preliminary verification of the chip and also a guarantee for the packaging quality of the chip.

[0088] The chip packaging as shown in Step 5. This step includes dicing, dispensing, wire bonding, encapsulation, electroplating, trimming, etc. in the whole chip packaging process. Packaging is a process of encapsulating the die of the bare chip into a solderable one. Whether the chip packaging is completed and can be used requires further testing and verification in the next step.

[0089] The FT test as shown in Step 6 is a test process after the chip packaging is completed. The FT test is carried out using the FT test board made in Step 2-2. In the test process, the test program is also debugged first, and the test can be carried out on the machine only after the test sample is confirmed. The test result data needs to be analyzed and verified to further confirm the performance and function improvement of the chip and meet the design requirements.

[0090] The packaging and shipping as shown in Step 7 are carried out after the test and verification are completed. The packaged chips can then enter the market for sale.

[0091] As Figure 6 shown, the implementation method of the test system architecture flowchart mainly takes the chip manufacturing and packaging process as the main body, and embeds the system architecture of test development into this process, so that relevant personnel can understand that the test development of the chip is part of the chip manufacturing process, and also understand what work is carried out at what stage of the chip and the specific content of the test. Specific Embodiment 2

[0093] As Figure 7 shown, the second mode of the specific embodiment of the test development system architecture of a power management chip based on ATE shown in the present invention. This mode takes the test development system as the main, and shows the entire process content of the test development system architecture of the chip in a comprehensive and detailed manner.

[0094] Step 11 Chip project establishment. From the start of chip project establishment, the work preparation for chip test development needs to be carried out, which is a work task that can be carried out simultaneously and coordinated with the circuit design and layout design of the chip.

[0095] Step 12 Requirement analysis and planning. The main content is the formulation of the chip test specification, which is the first part of the test development system architecture. There are mainly three parts of content. In addition to formulating the chip test specification, formulating the chip test plan and evaluating the cost and resources of chip testing are also included. Taking the chip test specification as the main body, more detailed evaluations are carried out around this main body, providing a good theoretical and practical operation basis for the subsequent test development work.

[0096] The test specification content shown in Step 12. It includes three aspects: 1) test parameter indicators and grading requirements, 2) test circuit diagrams and packaging forms, 3) version definition, chip description, and others. The above three aspects constitute the main content of the chip test specification. According to the specific parameter performance of the chip and combined with the actual device resource test conditions, each parameter to be tested in the chip test specification, as well as the specific test methods, conditions, and upper and lower limit ranges of the test values, are formulated. The circuit schematic diagram and related timing diagrams during chip testing also need to be presented in the chip test specification. At the same time, in the FT test specification, the packaging form diagram of the chip, pin definition of the chip, and other contents also need to be provided. The specification version number of the last part is for subsequent version iteration and upgrade.

[0097] Step 13 is hardware development. Specifically, it can be divided into the development of the CP test probe card and the test board card for FT test. Both are the main test verification requirements in the chip packaging and manufacturing process. The hardware part in the test system is mainly the production of the test board card, which is respectively applied in the CP test and FT test stages. The resource configuration and test site allocation during testing are determined at this time. To cooperate with the completion of the entire chip test development, the test demo board, fixture board, application board, etc. of the chip are also prepared simultaneously.

[0098] In the hardware development of Step 13, if the chip needs to conduct reliability verification, automotive-grade verification, etc., then the reliability test plan and the three-temperature test plan for automotive-grade verification also need to be arranged in Step 13. Hardware development is the material basis of the entire test development system, cooperating with the entire chip test verification to confirm that the performance meets the design and application requirements.

[0099] Step 14 is software development. Software development is mainly the software program compilation work carried out with the help of the test machine platform. The work content includes program debugging, simulation, and timing debugging verification. Different test platforms use different programming environments for test programs, and the requirements for the working ability of test personnel are also different. They not only need to be familiar with the relevant parameter performance of the chip but also need to understand the programming methods and skills of the test machine platform. The program compilation work of the software part is the test program part of the test development system architecture, which is the internal driving force for constructing the entire development test system architecture and is the underlying logical basis for improving chip testing.

[0100] The specific details of software development need to consider the test conditions, test methods, and verification of test results for each parameter in the chip test specification; the allocation of test resources, supply of test conditions, configuration of test environment, optimization of test time, etc. for different test machine platforms are all aspects that must be considered in the software development process. Attention also needs to be paid to the grading, binning, program debugging for multi-site testing in the chip performance, the iteration of the test program version number, the accuracy of test results for extreme parameters, and protective measures, etc.

[0101] Step 15 is test execution and optimization. Before all tests, in order to ensure the accuracy and stability of chip testing, it is necessary to repeatedly confirm that the performance test results developed and debugged in chip testing are correct. This process is essential and requires continuous calibration of the correctness of test data from time to time. Therefore, the proofreading step is carried out when testing the data after debugging is completed.

[0102] As shown in Step 15, proofreading with physical samples is crucial in the entire test development system architecture. For each developed test board, proofreading between boards is required. Proofreading between different sites is also needed. Even after a certain period of chip testing, calibration with physical samples is required. At the same time, proofreading with physical samples not only needs to proofread the correct numerical values of chip parameters, but also the incorrect numerical values. It also needs to proofread whether there is a phenomenon of defective products entering the good product management belt.

[0103] As shown in Step 15, in the entire chip packaging and manufacturing process, places where test execution is required include CP testing, FT testing. Reliability testing and three-temperature testing of automotive-grade chips can also be carried out according to needs. Each of these test processes requires corresponding boards and programs for support. Specific test operations must also have relevant test processes and test operation specifications. Corresponding execution standards must be provided to perform relevant test actions. Therefore, the execution of tests in the entire test development system is the focus of actual work.

[0104] As shown in Step 15, after CP testing, FT testing, and reliability testing are completed, the test machine will generate corresponding test data. Therefore, data acquisition and analysis is the most important step after all tests are completed. The test data provides an intuitive understanding of the overall performance parameters of the chip. By analyzing the data, the overall yield rate of the chip, the CPK distribution of parameter values, the normal distribution of parameters, etc. can be confirmed to improve the test performance of chip parameters and increase the yield rate, etc.

[0105] As shown in Step 15, the purpose of fault diagnosis and optimization is to analyze the faults that are bound to occur during chip testing. For example, faults such as incorrect chip parameters, non-concentrated distribution, batch failures, chip damage during testing, and unqualified yield rate occur. The specific reasons need to be diagnosed, whether it is due to the chip itself, equipment failure, or problems with the test board, etc. By continuously improving the problems, the test efficiency of the chip is improved, the problems of the chip are improved, and the performance of the chip is continuously optimized, etc.

[0106] As shown in step 15, upgrade the program and hardware. Through the above-mentioned fault diagnosis and optimization, continuously discover and solve problems, which can be specifically reflected in the continuous upgrade of the chip test specification. The test board and test program will also be continuously improved and upgraded. The continuous progress and upgrade during this process are the progress manifestations of the self-optimization of the chip test system architecture.

[0107] As Figure 7 shown, step 16 is mass production and data analysis. The final stage of chip testing must be the mass production testing of the chips. Mass production is the final link after all the work of chip test development is completed. Due to the fluctuations in chip manufacturing processes, individual parameter values will show fluctuations, so the test yield of the chips will also show a low yield phenomenon. This requires long-term tracking of the chip test yield and data. Establish control links for yield monitoring, failure analysis, data analysis, and process analysis. Solve problems through continuous analysis of the processing situation. Continuously optimize the chips and iterate the test versions to meet the various working environments of the chips at the consumer application end.

[0108] By adopting the development method and development platform of the ATE-based power management chip test system of the present invention, establish test specifications; design test boards; debug and optimize chip test programs; and then verify the consistency and stability of the chip test system. Thus, it is ensured that the chip test system developed by using the method and platform of the present invention can effectively complete the batch testing of chips, and ensure the accuracy, precision, performance integrity, and reliability of the chips after testing. The present invention provides a comprehensive and systematic power management chip test development architecture, which meets the ATE automation test development requirements of the chips. Moreover, this development method and platform have achieved standardization and simplification, facilitating relevant technical personnel to use it for test system development work, and can be specifically applied to chip batch automation test fields such as CP (wafer) test, FT (package) test, reliability test, and three-temperature test of chips.

[0109] In this specification, the present invention has been described with reference to its specific embodiments. However, it is obvious that various modifications and transformations can still be made without departing from the spirit and scope of the present invention. Therefore, the specification and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A development method for a power management chip test system based on ATE, characterized in that The method includes: (A) Establishing test specifications, which include test parameter indicators and grading requirements, test circuit diagrams and packaging forms, version definitions, and chip descriptions; (B) Designing a test board according to the test specifications, including the schematic diagram and PCB layout of the test board, as well as the design of the socket and quantity of the test board; (C) Debugging and optimizing the chip test program applied to the test board; (D) Verifying the consistency and stability of the chip test system using test samples.

2. The development method of the ATE-based power management chip test system according to claim 1, wherein The specific steps of step (A) include: (A1) Establishing test parameter indicators and grading requirements, including marking compliance identifications; indicating the meaning of each parameter; determining the specific test methods for each parameter and the referenced circuit structure diagrams; determining the lower limit value, upper limit value, and typical value of the test numerical values for each parameter; determining the hardware bin and software bin in the specific test program; (A2) Establishing test circuit diagrams and packaging forms, determining the corresponding test circuit diagrams and device models according to the specific test methods of the test parameters, providing relevant timing signal diagrams for timing-related tests, and determining the chip packaging form and pin definitions; (A3) Determining the version definition and chip description, clarifying the version number, production time, packaging information, test board schematic diagram, test machine model selection, test site configuration, and test time UPH of each test specification.

3. The development method of the ATE-based power management chip test system according to claim 2, characterized in that Determining the chip packaging form includes CP test specifications and FT test specifications.

4. The development method of the ATE-based power management chip test system according to claim 1, characterized in that, The specific steps of step (B) include: (B1) Designing the schematic diagram and PCB layout of the test board according to the test specifications, specifically referring to formulating the schematic diagram and PCB layout of the test board based on the test parameter indicators and corresponding test methods and conditions in the test specifications, combined with the socket structure of the test sorter and the interface channel structure of the test machine platform; (B2) Determining the socket of the test board for test program development of the test board; testing and validating the demo board and test fixture board for parameter performance testing and verification; (B3) Determining the quantity of the test board according to multi-site testing to adapt to multi-site batch ATE testing.

5. The development method of the ATE-based power management chip test system according to claim 1, characterized in that, The specific steps of step (C) include: (C1) Debugging the chip test program, including implementing parameter configuration and testing on the test board, outputting test numerical values to determine whether the test numerical values are within the theoretical range, and finally confirming whether the test results of the parameters are qualified. The test content includes hardware configuration information, test binning and grading, hardware configuration information, program version information, test program compilation, and time efficiency optimization; (C2) Optimizing the chip test program, including chip Cont testing to test the contact resistance between the chip pins and the socket; changes in the chip multi-site test program and single-site test program; site resistance configuration to bind site information.

6. The development method of the ATE-based power management chip test system according to any one of claims 1 to 5, characterized in that The specific steps of step (D) include: (D1) Determining multiple gold samples; (D2) Verifying the test consistency of different boards at multiple sites of the same chip and the test consistency of different sites of the same board using the gold samples. (D3) Verify the consistency of laboratory test values and the test values of the test system developed by this development method.

7. The development method of the ATE-based power management chip test system according to claim 6, characterized in that The step (D1) is specifically: determine at least 20 golden samples based on the data stability of no less than 100 cycles.

8. A development platform for a power management chip test system based on ATE, characterized in that, This platform includes: A test specification establishment module for establishing test specifications, including test parameter indicators and grading requirements, test circuit diagrams and packaging forms, version definitions and chip descriptions; A test board design module for designing a test board according to the test specifications, including designing the schematic diagram and PCB diagram of the test board and designing the socket and quantity of the test board; A test program debugging module for debugging and optimizing the chip test program applied to the test board; A verification module for verifying the consistency and stability of the chip test system using test samples.

9. The development platform of the ATE-based power management chip test system according to claim 8, characterized in that, The verification module specifically includes: Multiple golden samples; A consistency verification unit for verifying the test consistency of different boards at multiple sites of the same chip and the test consistency of different sites on the same board using the golden samples; and verifying the consistency of laboratory test values and the test values of the test system developed by this development method.

10. The development platform of the ATE-based power management chip test system according to claim 9, characterized in that The multiple golden samples are at least 20 golden samples determined based on the data stability of no less than 100 cycles.

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