Time calibration precision test method and system based on bidirectional timestamp statistical analysis

Abstract

The invention provides a timing precision test method and system based on bidirectional timestamp statistical analysis. The method comprises the following steps: defining initial clock skew and drift rate as state vectors; constructing an observation equation by using the uplink delay, the downlink delay, the initial clock skew at the current moment and the observation noise; constructing an RLS weight matrix by applying the state vector; calculating an estimated value of a state vector by applying the output of the observation equation, the updating result of the RLS weight matrix and the current state vector; calculating a predicted value of the initial clock skew at the next moment by applying the predicted value of the state vector; and correcting the bidirectional timestamp of the next moment according to the predicted value of the initial clock skew of the next moment. According to the scheme provided by the invention, the timing precision is evaluated under the condition that a high-precision reference clock is not needed, the influence of network delay can be effectively eliminated, and the accuracy of precision evaluation is improved by utilizing a statistical method.

Description

Technical Field

[0001] The present invention belongs to the technical field of time synchronization, and in particular relates to a time calibration accuracy test method and system based on bidirectional timestamp statistical analysis. Background Art

[0002] Generally, testing accuracy may require a high-precision reference clock, such as an atomic clock or a GPS time source, but this may be costly. What users need is easy to implement, so a method that does not require a high-cost reference clock may be needed. By using bidirectional timestamp exchange, calculating the round-trip time, and assuming path symmetry, the one-way delay is estimated, and then the time difference is calculated. After multiple measurements, statistical methods are used to estimate the clock offset and delay, so as to evaluate the accuracy.

[0003] The existing time calibration accuracy test methods are as follows: 1. Let the master device and the slave device perform time synchronization, and then by measuring the time difference after synchronization multiple times, statistically analyze the distribution of these time differences, and evaluate the accuracy by calculating the standard deviation or variance; 2. Use two different time calibration methods of the same device to compare the differences. For example, the device uses NTP and GPS for time calibration at the same time, and then compares the differences between the two to evaluate the accuracy of one of the methods; 3. The hardware characteristics can be utilized, such as the stability of the crystal oscillator. If the crystal oscillator of the device's local clock is relatively stable, the external time source can be disconnected after time calibration, and the drift of the local clock can be observed to infer the time calibration accuracy. The above existing clock accuracy test methods are relatively complex to implement, costly, and vulnerable to external influences, such as time calibration errors, network delays, environmental temperature and other factors. Summary of the Invention

[0004] In order to solve the above technical problems, the present invention proposes a technical solution of a time calibration accuracy test method based on bidirectional timestamp statistical analysis to solve the above technical problems.

[0005] The first aspect of the present invention discloses a time calibration accuracy test method based on bidirectional timestamp statistical analysis, and the method includes: Step S1, collecting bidirectional timestamps: the time when the master device sends a Sync message to the slave device, the time when the slave device receives the Sync message, the time when the slave device sends a Delay_Req message, and the time when the master device receives the Delay_Req message, and forming a timestamp sequence; performing data preprocessing on the timestamp sequence; Step S2: Calculate the uplink delay and downlink delay based on the preprocessed timestamp sequence and the initial clock offset; calculate the mean ratio of the uplink delay and downlink delay within the window; determine that the network path is significantly asymmetric based on the mean ratio and trigger adaptive compensation; if the uplink delay mean and downlink delay mean are stable, apply the delay mean difference and the initial clock offset to obtain a direct compensation value, and then apply the direct compensation value and the initial clock offset to obtain the compensated initial clock offset; correct the two-way timestamp according to the compensated initial clock offset. Step S3: If the uplink delay mean and downlink delay mean are unstable, define the initial clock offset and the drift rate as the state vector; construct an observation equation using the uplink delay, downlink delay, the initial clock offset at the current moment, and the observation noise; construct an RLS weight matrix using the state vector; calculate the predicted value of the state vector using the output of the observation equation, the updated result of the RLS weight matrix, and the current state vector. Step S4: Apply the predicted value of the state vector to calculate the predicted value of the initial clock offset at the next moment; correct the two-way timestamp at the next moment according to the predicted value of the initial clock offset at the next moment; calculate the residual according to the predicted value of the initial clock offset at the next moment and the actual value of the initial clock offset; determine whether to trigger the RLS weight reset according to the residual.

[0006] In the method according to the first aspect of the present invention, in the step S2, the calculation of the mean ratio of the uplink delay and downlink delay within the window includes: R = mean( ) / mean( ) where R represents the mean ratio; represents the mean of the uplink delay; represents the mean of the downlink delay; Determining that the network path is significantly asymmetric based on the mean ratio includes: If R > threshold, determine that the network path is significantly asymmetric; The application of the delay mean difference and the initial clock offset to obtain a direct compensation value includes: =

[0007] where, represents the direct compensation value; represents the initial clock offset; represents the delay mean difference; = -

[0008] where, Represents the mean of the uplink delay; Represents the mean of the downlink delay.

[0009] According to the method of the first aspect of the present invention, in the step S3, constructing the observation equation by using the uplink delay, downlink delay, initial clock deviation at the current moment, and observation noise includes:

[0010] Wherein, Represents the output of the observation equation; Represents the initial clock deviation at the current moment; Represents the uplink delay; Represents the downlink delay; Represents the observation noise.

[0011] According to the method of the first aspect of the present invention, in the step S3, constructing the RLS weight matrix by using the state vector includes:

[0012] Wherein, Represents the RLS weight at the current moment; Represents the RLS weight at the previous moment; Represents the state vector at the current moment.

[0013] According to the method of the first aspect of the present invention, in the step S3, calculating the predicted value of the state vector by using the output of the observation equation, the updated result of the RLS weight matrix, and the current state vector includes:

[0014] Wherein, Represents the predicted value of the state vector at the current moment; Represents the predicted value of the state vector at the previous moment; Represents the updated result of the RLS weight matrix; Represents the output of the observation equation.

[0015] According to the method of the first aspect of the present invention, in the step S4, calculating the predicted value of the initial clock deviation at the next moment by using the predicted value of the state vector includes:

[0016] Wherein, Represents the predicted value of the initial clock deviation at the next moment; Represents the initial clock deviation in the predicted value of the state vector; _ k represents the drift rate in the predicted value of the state vector; Indicates the message interval time.

[0017] According to the method of the first aspect of the present invention, in the step S4, calculating the residual according to the predicted value of the initial clock deviation at the next moment and the actual value of the initial clock deviation includes: e = -

[0018] where e represents the residual; represents the actual value of the initial clock deviation; represents the predicted value of the initial clock deviation at the next moment; Judging whether to trigger RLS weight reset according to the residual includes: If |e| > tolerance threshold, trigger RLS weight reset to prevent overfitting.

[0019] The second aspect of the present invention discloses a time calibration accuracy test system based on bidirectional timestamp statistical analysis. The system includes: The first processing module is configured to collect bidirectional timestamps: the moment when the master device sends a Sync message to the slave device, the moment when the slave device receives the Sync message, the moment when the slave device sends a Delay_Req message, and the moment when the master device receives the Delay_Req message, and form a timestamp sequence; perform data preprocessing on the timestamp sequence; The second processing module is configured to calculate the uplink delay and the downlink delay according to the preprocessed timestamp sequence and the initial clock deviation; calculate the mean ratio of the uplink delay and the downlink delay within the window; judge that the network path is significantly asymmetric according to the mean ratio and trigger adaptive compensation; if the uplink delay mean and the downlink delay mean are stable, apply the delay mean difference and the initial clock deviation to obtain a direct compensation value, and then apply the direct compensation value and the initial clock deviation to obtain the compensated initial clock deviation; correct the bidirectional timestamp according to the compensated initial clock deviation; The third processing module is configured to, if the uplink delay mean and the downlink delay mean are unstable, define the initial clock deviation and the drift rate as the state vector; construct an observation equation by applying the uplink delay, the downlink delay, the initial clock deviation at the current moment, and the observation noise; construct an RLS weight matrix by applying the state vector; calculate the predicted value of the state vector by applying the output of the observation equation, the update result of the RLS weight matrix, and the current state vector; The fourth processing module is configured to calculate the predicted value of the initial clock deviation at the next moment by applying the predicted value of the state vector; correct the bidirectional timestamp at the next moment according to the predicted value of the initial clock deviation at the next moment; calculate the residual according to the predicted value of the initial clock deviation at the next moment and the actual value of the initial clock deviation; judge whether to trigger RLS weight reset according to the residual.

[0020] In the third aspect of the present invention, an electronic device is disclosed. The electronic device includes a memory and a processor. The memory stores a computer program. When the processor executes the computer program, the steps in any one of the time calibration accuracy testing methods based on bidirectional timestamp statistical analysis in the first aspect of the present disclosure are implemented.

[0021] In the fourth aspect of the present invention, a computer-readable storage medium is disclosed. A computer program is stored on the computer-readable storage medium. When the computer program is executed by a processor, the steps in any one of the time calibration accuracy testing methods based on bidirectional timestamp statistical analysis in the first aspect of the present disclosure are implemented.

[0022] In summary, the solution proposed by the present invention can evaluate the time calibration accuracy without the need for a high-precision reference clock, can effectively eliminate the influence of network delay, and uses statistical methods to improve the accuracy of accuracy evaluation. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0024] Figure 1 FIG. is a flowchart of a time calibration accuracy testing method based on bidirectional timestamp statistical analysis according to an embodiment of the present invention; Figure 2 FIG. is a structural diagram of a time calibration accuracy testing system based on bidirectional timestamp statistical analysis according to an embodiment of the present invention; Figure 3 FIG. is a structural diagram of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0026] In the first aspect of the present invention, a time calibration accuracy testing method based on bidirectional timestamp statistical analysis is disclosed. Figure 1A flowchart of a time calibration accuracy test method based on bidirectional timestamp statistical analysis according to an embodiment of the present invention is as follows Figure 1 shown, and the method includes: Step S1: Collect bidirectional timestamps: the time when the master device sends a Sync message to the slave device, the time when the slave device receives the Sync message, the time when the slave device sends a Delay_Req message, and the time when the master device receives the Delay_Req message, and form a timestamp sequence; perform data preprocessing on the timestamp sequence; Step S2: Calculate the uplink delay and the downlink delay according to the preprocessed timestamp sequence and the initial clock deviation; calculate the mean ratio of the uplink delay and the downlink delay within the window; determine that the network path is significantly asymmetric according to the mean ratio and trigger adaptive compensation; if the uplink delay mean and the downlink delay mean are stable, apply the delay mean difference and the initial clock deviation to obtain a direct compensation value, and then apply the direct compensation value and the initial clock deviation to obtain the compensated initial clock deviation; correct the bidirectional timestamp according to the compensated initial clock deviation; Step S3: If the uplink delay mean and the downlink delay mean are unstable, define the initial clock deviation and the drift rate as the state vector; construct an observation equation by using the uplink delay, the downlink delay, the initial clock deviation at the current moment, and the observation noise; construct an RLS weight matrix by using the state vector; calculate the predicted value of the state vector by using the output of the observation equation, the updated result of the RLS weight matrix, and the current state vector; Step S4: Apply the predicted value of the state vector to calculate the predicted value of the initial clock deviation at the next moment; correct the bidirectional timestamp at the next moment according to the predicted value of the initial clock deviation at the next moment; calculate the residual according to the predicted value of the initial clock deviation at the next moment and the actual value of the initial clock deviation; determine whether to trigger the RLS weight reset according to the residual.

[0027] In step S1, collect bidirectional timestamps: the time when the master device sends a Sync message to the slave device, the time when the slave device receives the Sync message, the time when the slave device sends a Delay_Req message, and the time when the master device receives the Delay_Req message, and form a timestamp sequence; perform data preprocessing on the timestamp sequence.

[0028] Specifically, T1: the moment when the master device sends a Sync message to the slave device (the time when the master device sends the message). The master device sends a Sync_Request, generates a sequence number Seq, and records the T1_i timestamp (MAC layer timestamp). It sends the message to the slave device and starts the retransmission timer. T2: the moment when the slave device receives the Sync message (the time when the slave device receives the message). The slave device processes the Sync_Request and records the reception time T2_i (MAC layer timestamp). It generates a Sync_Response, fills in T2_i and T3_i (the sending moment), and returns to the master clock. T3: the moment when the slave device sends a Delay_Req message (the time when the slave device sends the message). T4: the moment when the master device receives the Delay_Req message (the time when the master device receives the message). The master device receives the Sync_Response and records the reception time T4_i.

[0029] Parse the custom time synchronization message and visualize the timestamp sequence.

[0030] Data collection: Repeat N rounds (N ≥ 1000) to form a timestamp sequence

[0031] Data preprocessing: Calculate the initial clock deviation:

[0032] Calculate the single - up - link delay: D_up = T2_i - T1_i -

[0033] Calculate the single - down - link delay: D_down = T4_i - T3_i +

[0034] Use a sliding window (e.g., the latest 100 data points) to detect outliers: Calculate the mean of the up - link delay within the window: , where is the mean of the up - link delay.

[0035] Calculate the mean of the down - link delay within the window: = , where is the mean of the down - link delay.

[0036] Delay mean difference: = - , which is used to compensate for the fixed asymmetric network delay.

[0037] Calculate the variance of within the window (D_up is the single - delay).

[0038] Within the calculation window of the variance = (where D_down is the single delay).

[0039] Exclude data points outside the range of -3 , +3 , and output the processed data set .

[0040] Exclude data points outside the range of -3 , +3 and output the processed data set .

[0041] In step S2, based on the preprocessed timestamp sequence and the initial clock deviation, calculate the uplink delay and the downlink delay; calculate the mean ratio of the uplink delay and the downlink delay within the calculation window; based on the mean ratio, determine that the network path is significantly asymmetric and trigger adaptive compensation; if the mean values of the uplink delay and the downlink delay are stable, apply the delay mean difference and the initial clock deviation to obtain a direct compensation value, and then apply the direct compensation value and the initial clock deviation to obtain the compensated initial clock deviation; correct the two-way timestamp according to the compensated initial clock deviation.

[0042] In some embodiments, in the step S2, the mean ratio of the uplink delay and the downlink delay within the calculation window includes: R = mean( ) / mean( ) where R represents the mean ratio; represents the mean value of the uplink delay; represents the mean value of the downlink delay; Based on the mean ratio, determining that the network path is significantly asymmetric includes: If R > threshold, determine that the network path is significantly asymmetric; The application of the delay mean difference and the initial clock deviation to obtain a direct compensation value includes: =

[0043] where represents the direct compensation value; represents the initial clock deviation; represents the delay mean difference; = -

[0044] Among them, represents the average value of the uplink delay; represents the average value of the downlink delay.

[0045] In step S3, if the average values of the uplink delay and the downlink delay are unstable, define the initial clock deviation and the drift rate as the state vector; construct an observation equation by applying the uplink delay, the downlink delay, the initial clock deviation at the current moment, and the observation noise; construct an RLS weight matrix by applying the state vector; calculate the predicted value of the state vector by applying the output of the observation equation, the updated result of the RLS weight matrix, and the current state vector.

[0046] In some embodiments, in the step S3, the constructing an observation equation by applying the uplink delay, the downlink delay, the initial clock deviation at the current moment, and the observation noise includes:

[0047] Among them, represents the output of the observation equation; represents the initial clock deviation at the current moment; represents the uplink delay; represents the downlink delay; represents the observation noise.

[0048] The constructing an RLS weight matrix by applying the state vector includes:

[0049] Among them, represents the RLS weight at the current moment; represents the RLS weight at the previous moment; represents the state vector at the current moment.

[0050] The calculating the predicted value of the state vector by applying the output of the observation equation, the updated result of the RLS weight matrix, and the current state vector includes:

[0051] Among them, represents the predicted value of the state vector at the current moment; represents the predicted value of the state vector at the previous moment; represents the updated result of the RLS weight matrix; represents the output of the observation equation.

[0052] Specifically, the state transition matrix is: F = , where is the sampling period.

[0053] The corresponding state evolution equation is:

[0054] = + ( and is the process noise).

[0055] Wherein _k, is the value after dynamic compensation of the initial clock deviation and frequency deviation in real-time tracking.

[0056] In step S4, apply the predicted value of the state vector to calculate the predicted value of the initial clock deviation at the next moment; correct the two-way timestamp at the next moment according to the predicted value of the initial clock deviation at the next moment; calculate the residual according to the predicted value of the initial clock deviation at the next moment and the actual value of the initial clock deviation; determine whether to trigger the RLS weight reset according to the residual.

[0057] In some embodiments, in the step S4, the applying the predicted value of the state vector to calculate the predicted value of the initial clock deviation at the next moment includes:[[]]

[0058] Wherein represents the predicted value of the initial clock deviation at the next moment; represents the initial clock deviation in the predicted value of the state vector; _ k represents the drift rate in the predicted value of the state vector; represents the message interval time.

[0059] The calculating the residual according to the predicted value of the initial clock deviation at the next moment and the actual value of the initial clock deviation includes:[[]] e = -

[0060] Wherein, e represents the residual; represents the actual value of the initial clock deviation; represents the predicted value of the initial clock deviation at the next moment; The determining whether to trigger the RLS weight reset according to the residual includes:[[]] If |e| > tolerance threshold, trigger the RLS weight reset to prevent overfitting.

[0061] Specifically, in the next round of timestamp interaction, the master device modifies the sent time T1_i to:[[]] = T1_i + .

[0062] The time T2_i received from the device is corrected to: = T2_i - .

[0063] In some embodiments, it further includes data stability monitoring: Calculate the residual fluctuation within the monitoring window: _up = ; _down =

[0064] The N - time residual fluctuations within the monitoring window _up, _down.

[0065] Calculate the mean value of the residual fluctuations within the window: =

[0066] = .

[0067] Set the confidence interval: _up = + 3 _up; _down = + 3 .

[0068] If < _up (convergence threshold), < (convergence threshold), it is determined that the system enters the steady state.

[0069] Accuracy evaluation metrics: Time - domain analysis: Mean Offset, Max Offset, Root Mean Square Error (RMSE).

[0070] Frequency - domain analysis: Allan variance (evaluating clock stability), phase noise spectral density.

[0071] Statistical distribution: Delay histogram, 99.9% confidence interval, Skewness, and Kurtosis.

[0072] Calculation of the data deviation for accuracy evaluation: = .

[0073] Calculation of Root Mean Square Error (RMSE): RMSE =

[0074] Allan variance: Segment the sequence (segment length τ = 1 s, 10 s, 100 s), and calculate the mean variance of each segment: .

[0075] where θ i is the initial deviation of the system, and θ is the clock error.

[0076] Statistical distribution modeling: Use kernel density estimation (KDE) to fit the i distribution of θ, and calculate the 99.9% confidence interval: CI = .

[0077] Precision evaluation output: Logic for plotting the curve of clock deviation over time: X-axis: Timestamp (cumulative time calculated from the start of the test, unit: second).

[0078] Y-axis: Clock deviation (unit: μs).

[0079] Mark key points: maximum value, minimum value, convergence time (when the deviation first enters the range of ±5 μs).

[0080] Logic for plotting the curve of clock stability analysis: X-axis: τ (logarithmic scale), Y-axis: Allan variance (logarithmic scale).

[0081] Mark typical noise regions (e.g., slope -1 / 2 corresponds to white noise, 0 corresponds to flicker noise).

[0082] Statistics of deviation probability density data: Mark the mean line, 99.9% confidence interval (CI), skewness, and kurtosis.

[0083] The hardware of the above method includes: High-precision timestamp unit: The FPGA core directly marks the message transceiver timestamps (T1 / T4 on the master side, T2 / T3 on the slave side), uses a hardware interrupt signal to trigger timestamp recording, and directly stores the original timestamp in a hardware register to achieve precise interrupt processing.

[0084] Bidirectional communication protocol stack: Supports embedding timestamps in custom fields and two-way message interaction between the master clock and slave devices (such as UDP / TCP messages).

[0085] Statistical analysis engine: Based on the bidirectional timestamp sequence, calculate the statistical characteristics of path delay (mean, variance, skewness), clock deviation, and confidence interval.

[0086] Adaptive Compensation Controller: Responsible for dynamically adjusting network delay compensation parameters and clock deviation correction strategies to cope with real-time network fluctuations and clock drifts. Its core functions are as follows: Real-time Monitoring: Tracking the statistical characteristics of bidirectional timestamp data (such as delay mean, variance, skewness) Dynamic Parameter Adjustment: Optimizing the compensation model parameters to reduce the impact of path asymmetry and clock drift.

[0087] Closed-loop Feedback: Iteratively updating the control strategy based on the compensation effect to ensure system stability Accuracy Evaluation Module: Generating an evaluation report containing time-domain / frequency-domain analysis results and supporting visual display.

[0088] Implementation Method Timestamp Recording Mechanism: Timestamp Recording for Packet Transmission: When a packet enters the network card DMA queue, the MAC layer triggers a hardware counter and writes the current clock value (CLK) into the descriptor register.

[0089] Timestamp Recording for Packet Reception: When a packet arrives at the MAC layer, the network card automatically captures the RX timestamp and stores it in the receive descriptor.

[0090] Timestamp Reading: The driver reads the timestamp in the descriptor through the bus and stores it in a shared memory circular buffer (to avoid lock contention).

[0091] Hierarchical Classification of Bidirectional Communication Protocol: Physical Layer: Supporting Ethernet (IEEE 802.3) or optical fiber (such as 100G LR4) to ensure low-jitter transmission.

[0092] Data Link Layer: Integrating IEEE 1588 PTP hardware timestamp (timestamping at the MAC layer), with an accuracy ≤ 10 ns.

[0093] Network Layer: Based on IPv4 / IPv6, supporting ToS (Type of Service) marking priority (DSCP = EF, accelerated forwarding).

[0094] Transport Layer: UDP protocol (low overhead) + custom reliable transmission extension (sequence number, ACK / NACK).

[0095] Application Layer: Customized time synchronization message format, supporting bidirectional timestamp exchange and dynamic parameter negotiation.

[0096] In summary, the solution proposed by the present invention enables hardware to implement MAC layer timestamp recording. The present application provides an implementation method for bidirectional timestamp recording and error decomposition model based on the path detection-based asymmetric delay correction method. The present application can be hardware-compatible, supporting two modes: software timestamp (low cost) or hardware timestamp (high precision), and visualizing in real time. Specifically, it provides visual outputs such as error distribution histograms and trend curves, which are convenient for quick diagnosis.

[0097] In a second aspect of the present invention, a time synchronization accuracy testing system based on bidirectional timestamp statistical analysis is disclosed. Figure 2 FIG. is a structural diagram of a time synchronization accuracy testing system based on bidirectional timestamp statistical analysis according to an embodiment of the present invention; as Figure 2 shown, the system 100 includes: A first processing module 101, configured to collect bidirectional timestamps: the moment when the master device sends a Sync message to the slave device, the moment when the slave device receives the Sync message, the moment when the slave device sends a Delay_Req message, and the moment when the master device receives the Delay_Req message, and form a timestamp sequence; perform data preprocessing on the timestamp sequence; A second processing module 102, configured to calculate the uplink delay and the downlink delay according to the preprocessed timestamp sequence and the initial clock deviation; calculate the mean ratio of the uplink delay and the downlink delay within a window; determine that the network path is significantly asymmetric according to the mean ratio, and trigger adaptive compensation; if the uplink delay mean and the downlink delay mean are stable, apply the delay mean difference and the initial clock deviation to obtain a direct compensation value, and then apply the direct compensation value and the initial clock deviation to obtain the compensated initial clock deviation; correct the bidirectional timestamp according to the compensated initial clock deviation; A third processing module 103, configured to, if the uplink delay mean and the downlink delay mean are unstable, define the initial clock deviation and the drift rate as state vectors; construct an observation equation by applying the uplink delay, the downlink delay, the initial clock deviation at the current moment, and the observation noise; construct an RLS weight matrix by applying the state vectors; calculate the predicted value of the state vector by applying the output of the observation equation, the updated result of the RLS weight matrix, and the current state vector; A fourth processing module 104, configured to calculate the predicted value of the initial clock deviation at the next moment by applying the predicted value of the state vector; correct the bidirectional timestamp at the next moment according to the predicted value of the initial clock deviation at the next moment; calculate the residual according to the predicted value of the initial clock deviation at the next moment and the actual value of the initial clock deviation; determine whether to trigger RLS weight reset according to the residual.

[0098] For the system according to the second aspect of the present invention, the first processing module 101 is specifically configured as follows: T1: The moment when the master device sends a Sync message to the slave device (the time when the master device sends the message). The master device sends a Sync_Request, generates a sequence number Seq, records the T1_i timestamp (MAC layer timestamping). Sends the message to the slave device and starts a retransmission timer. T2: The moment when the slave device receives the Sync message (the time when the slave device receives the message). The slave device processes the Sync_Request, records the reception time T2_i (MAC layer timestamp). Generates a Sync_Response, fills in T2_i and T3_i (the sending moment), and returns to the master clock. T3: The moment when the slave device sends a Delay_Req message (the time when the slave device sends the message). T4: The moment when the master device receives the Delay_Req message (the time when the master device receives the message). The master device receives the Sync_Response and records the reception time T4_i.

[0099] Parse the custom time synchronization message and visualize the timestamp sequence.

[0100] Data acquisition: Repeat N rounds (N≥1000) to form a timestamp sequence

[0101] Data preprocessing: Calculate the initial clock deviation:

[0102] Calculate the single-hop upstream delay: D_up = T2_i - T1_i -

[0103] Calculate the single-hop downstream delay: D_down = T4_i - T3_i +

[0104] Use a sliding window (e.g., the latest 100 data points) to detect outliers: Calculate the mean of the upstream delay within the window: , where is the mean of the upstream delay.

[0105] Calculate the mean of the downstream delay within the window: = , where is the mean of the downstream delay.

[0106] Delay mean difference: = - , which is used to compensate for the fixed asymmetric network delay.

[0107] Calculate the variance within the window (D_up is the single - time delay).

[0108] Calculate the variance within the calculation window = = (D_down is the single - time delay).

[0109] Eliminate the data points outside the range of - 3 , + 3 , and output the processed data set .

[0110] Eliminate the data points outside the range of - 3 , + 3 and output the processed data set .

[0111] For the system according to the second aspect of the present invention, the second processing module 102 is specifically configured that the mean ratio of the uplink delay and the downlink delay within the calculation window includes: R = mean( ) / mean( ) where R represents the mean ratio; represents the mean of the uplink delay; represents the mean of the downlink delay; Determining that the network path is significantly asymmetric according to the mean ratio includes: If R > threshold, determine that the network path is significantly asymmetric; Obtaining the direct compensation value by applying the mean difference of the application delay and the initial clock deviation includes: =

[0112] where, represents the direct compensation value; represents the initial clock deviation; represents the mean difference of the delay; = -

[0113] where, represents the mean of the uplink delay; represents the mean of the downlink delay.

[0114] For the system according to the second aspect of the present invention, the third processing module 103 is specifically configured to construct an observation equation by using the uplink delay, downlink delay, initial clock deviation at the current moment, and observation noise, including:

[0115] Wherein, represents the output of the observation equation; represents the initial clock deviation at the current moment; represents the uplink delay; represents the downlink delay; represents the observation noise.

[0116] Constructing the RLS weight matrix by using the state vector includes:

[0117] Wherein, represents the RLS weight at the current moment; represents the RLS weight at the previous moment; represents the state vector at the current moment.

[0118] Calculating the predicted value of the state vector by using the output of the observation equation, the updated result of the RLS weight matrix, and the current state vector includes:

[0119] Wherein, represents the predicted value of the state vector at the current moment; represents the predicted value of the state vector at the previous moment; represents the updated result of the RLS weight matrix; represents the output of the observation equation.

[0120] Specifically, the state transition matrix is: F = , where is the sampling period.

[0121] The corresponding state evolution equation is:

[0122] = + ( and are process noises).

[0123] Wherein _k, are the values after dynamic compensation of real-time tracking of the initial clock deviation and frequency deviation.

[0124] For the system according to the second aspect of the present invention, the fourth processing module 104 is specifically configured that calculating the predicted value of the initial clock deviation at the next moment based on the predicted value of the application state vector includes:

[0125] Wherein, represents the predicted value of the initial clock deviation at the next moment; represents the initial clock deviation in the predicted value of the state vector; _ k represents the drift rate in the predicted value of the state vector; represents the message interval time.

[0126] Calculating the residual based on the predicted value of the initial clock deviation at the next moment and the actual value of the initial clock deviation includes: e = -

[0127] Wherein, e represents the residual; represents the actual value of the initial clock deviation; represents the predicted value of the initial clock deviation at the next moment; Judging whether to trigger RLS weight reset according to the residual includes: If |e| > tolerance threshold, trigger RLS weight reset to prevent overfitting.

[0128] Specifically, in the next round of timestamp interaction, the time T1_i sent by the master device is corrected to: = T1_i + .

[0129] The time T2_i received by the slave device is corrected to: = T2_i - .

[0130] The third aspect of the present invention discloses an electronic device. The electronic device includes a memory and a processor. When the processor executes the computer program stored in the memory, the steps in any one of the time calibration accuracy test methods based on two-way timestamp statistical analysis in the first aspect disclosed by the present invention are implemented.

[0131] Figure 3 FIG. is a structural diagram of an electronic device according to an embodiment of the present invention, as Figure 3As shown in the figure, the electronic device includes a processor, a memory, a communication interface, a display screen, and an input device connected through a system bus. Among them, the processor of the electronic device is used to provide computing and control capabilities. The memory of the electronic device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The communication interface of the electronic device is used to communicate with external terminals in a wired or wireless manner. The wireless manner can be achieved through WIFI, a carrier network, near-field communication (NFC), or other technologies. The display screen of the electronic device can be a liquid crystal display screen or an electronic ink display screen. The input device of the electronic device can be a touch layer covering the display screen, or keys, a trackball, or a touchpad provided on the housing of the electronic device, or an external keyboard, touchpad, or mouse, etc.

[0132] Those skilled in the art can understand that Figure 3 the structure shown in the figure is only the structural diagram of the part related to the technical solution of the present disclosure, and does not constitute a limitation on the electronic device to which the solution of the present application is applied. The specific electronic device may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0133] The fourth aspect of the present invention discloses a computer-readable storage medium. A computer program is stored on the computer-readable storage medium. When the computer program is executed by a processor, the steps in a time calibration accuracy test method based on bidirectional timestamp statistical analysis according to any one of the first aspect of the present invention are implemented.

[0134] Please note that the technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification. The above embodiments only represent several implementation manners of the present application. Their descriptions are relatively specific and detailed, but they should not be construed as a limitation on the scope of the invention patent. It should be pointed out that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A time calibration accuracy test method based on bidirectional timestamp statistical analysis, characterized in that, The method includes: Step S1: Collect bidirectional timestamps, namely, the time when the master device sends a Sync message to the slave device, the time when the slave device receives the Sync message, the time when the slave device sends a Delay_Req message, and the time when the master device receives the Delay_Req message, and form a timestamp sequence; perform data preprocessing on the timestamp sequence; Step S2: Calculate the uplink delay and downlink delay according to the preprocessed timestamp sequence and the initial clock offset; calculate the mean ratio of the uplink delay and downlink delay within the window; determine that the network path is significantly asymmetric according to the mean ratio and trigger adaptive compensation; if the mean values of the uplink delay and downlink delay are stable, apply the delay mean difference and the initial clock offset to obtain a direct compensation value, and then apply the direct compensation value and the initial clock offset to obtain the compensated initial clock offset; correct the bidirectional timestamps according to the compensated initial clock offset; Step S3: If the mean values of the uplink delay and downlink delay are unstable, define the initial clock offset and drift rate as the state vector; construct an observation equation by applying the uplink delay, downlink delay, the initial clock offset at the current moment, and the observation noise; construct an RLS weight matrix by applying the state vector; calculate the predicted value of the state vector by applying the output of the observation equation, the updated result of the RLS weight matrix, and the current state vector; Step S4: Calculate the predicted value of the initial clock offset at the next moment by applying the predicted value of the state vector; correct the bidirectional timestamps at the next moment according to the predicted value of the initial clock offset at the next moment; calculate the residual according to the predicted value of the initial clock offset at the next moment and the actual value of the initial clock offset; determine whether to trigger the RLS weight reset according to the residual.

2. The time calibration accuracy test method based on two-way timestamp statistical analysis according to claim 1, wherein In the step S2, the mean ratio of the uplink delay and downlink delay within the window includes: wherein, R represents the mean ratio; represents the mean value of the uplink delay; represents the mean value of the downlink delay; Determining that the network path is significantly asymmetric according to the mean ratio includes: If R > threshold, determine that the network path is significantly asymmetric; Applying the delay mean difference and the initial clock offset to obtain a direct compensation value includes: Among them, represents the direct compensation value; represents the initial clock deviation; represents the delay mean difference; Among them, represents the average value of the uplink delay; represents the average value of the downlink delay.

3. A time calibration accuracy test method based on bidirectional timestamp statistical analysis according to claim 1, characterized in that In the step S3, constructing an observation equation by applying the uplink delay, downlink delay, the initial clock offset at the current moment, and the observation noise includes: Among them, represents the output of the observation equation; represents the initial clock deviation at the current moment; represents the uplink delay; represents the downlink delay; represents the observation noise.

4. A time calibration accuracy test method based on two-way timestamp statistical analysis according to claim 1, characterized in that, In the step S3, constructing an RLS weight matrix by applying the state vector includes: Among them, represents the RLS weight at the current moment; represents the RLS weight at the previous moment; represents the state vector at the current moment.

5. A time calibration accuracy test method based on bidirectional timestamp statistical analysis according to claim 1, characterized in that, In the step S3, calculating the predicted value of the state vector by applying the output of the observation equation, the updated result of the RLS weight matrix, and the current state vector includes: Among them, represents the predicted value of the state vector at the current moment; represents the predicted value of the state vector at the previous moment; represents the updated result of the RLS weight matrix; represents the output of the observation equation.

6. The calibration accuracy test method based on two-way timestamp statistical analysis according to claim 1, wherein, In the step S4, calculating the predicted value of the initial clock offset at the next moment by applying the predicted value of the state vector includes: Among them, represents the predicted value of the initial clock deviation at the next moment; represents the initial clock deviation in the predicted value of the state vector; represents the drift rate in the predicted value of the state vector; represents the message interval time.

7. A time calibration accuracy test method based on bidirectional timestamp statistical analysis according to claim 1, characterized in that In the step S4, calculating the residual according to the predicted value of the initial clock offset at the next moment and the actual value of the initial clock offset includes: where e represents the residual; represents the actual value of the initial clock deviation; represents the predicted value of the initial clock deviation at the next moment; Determining whether to trigger the RLS weight reset according to the residual includes: If |e| > tolerance threshold, trigger the RLS weight reset to prevent overfitting.

8. A time calibration accuracy test system for bidirectional timestamp statistical analysis, characterized in that, The system includes: The first processing module is configured to collect bidirectional timestamps: the moment when the master device sends a Sync message to the slave device, the moment when the slave device receives the Sync message, the moment when the slave device sends a Delay_Req message, and the moment when the master device receives the Delay_Req message, and form a timestamp sequence; perform data preprocessing on the timestamp sequence; The second processing module is configured to calculate the uplink delay and the downlink delay according to the preprocessed timestamp sequence and the initial clock offset; calculate the mean ratio of the uplink delay and the downlink delay within the window; determine that the network path is significantly asymmetric according to the mean ratio and trigger adaptive compensation; if the uplink delay mean and the downlink delay mean are stable, apply the delay mean difference and the initial clock offset to obtain a direct compensation value, and then apply the direct compensation value and the initial clock offset to obtain the compensated initial clock offset; correct the bidirectional timestamps according to the compensated initial clock offset; The third processing module is configured to, if the uplink delay mean and the downlink delay mean are unstable, define the initial clock offset and the drift rate as state vectors; construct an observation equation by applying the uplink delay, the downlink delay, the initial clock offset at the current moment, and the observation noise; construct an RLS weight matrix by applying the state vectors; calculate the predicted value of the state vector by applying the output of the observation equation, the updated result of the RLS weight matrix, and the current state vector; The fourth processing module is configured to calculate the predicted value of the initial clock offset at the next moment by applying the predicted value of the state vector; correct the bidirectional timestamps at the next moment according to the predicted value of the initial clock offset at the next moment; calculate the residual according to the predicted value of the initial clock offset at the next moment and the actual value of the initial clock offset; determine whether to trigger RLS weight reset according to the residual.

9. An electronic device, characterized in that, The electronic device includes a memory and a processor. When the processor executes the computer program stored in the memory, the steps in any one of claims 1 to 7 of a time calibration accuracy test method based on bidirectional timestamp statistical analysis are implemented.

10. A computer-readable storage medium, characterized in that, A computer program is stored on the computer-readable storage medium. When the computer program is executed by the processor, the steps in any one of claims 1 to 7 of a time calibration accuracy test method based on bidirectional timestamp statistical analysis are implemented.

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