Chip, electronic equipment and power consumption control method of chip

Abstract

The invention relates to a chip, electronic equipment and a power consumption control method of the chip, and belongs to the field of electronic circuits. The chip comprises a plurality of functional modules and an interconnection module, the plurality of function modules comprise a power consumption management module; any two function modules in the plurality of function modules are connected through an interconnection module, and the interconnection module is used for monitoring the path bandwidth between the interconnection module and a target module connected with the interconnection module within a period of time; and the power consumption management module is used for acquiring the bandwidth of each path monitored by the interconnection module and adjusting the working frequency of the interconnection module according to the bandwidth of each path. The power consumption of the interconnection module is reduced by adjusting the working frequency of the interconnection module in the data path, so that the overall power consumption of the chip is reduced.

Description

Technical Field

[0001] This application belongs to the field of electronic circuits, and particularly relates to a chip, an electronic device, and a method for controlling the power consumption of the chip. Background Art

[0002] With the improvement of the computing power of chips, the power consumption of chips is getting higher and higher. If the growth of power consumption cannot be effectively controlled, the energy efficiency of chips will become a bottleneck restricting the improvement of computing power. Therefore, how to reduce the power consumption of chips has become an important direction for the development of chips. Currently, chip power management mainly relies on technologies such as dynamic voltage and frequency scaling and low-power mode switching. Among them, a software and hardware collaborative management framework with the ACPI (Advanced Configuration and Power management Interface) protocol as the core is widely used in modern processors, such as CPUs (Central Processing Units). Under this framework, the operating system (OS) monitors the load of the CPU core in real time and controls the CPU core to enter different working modes according to the power consumption strategy of the ACPI protocol to achieve a balance between power consumption and performance.

[0003] Although the dynamic power management technology with the ACPI protocol as the core has played a key role in optimizing the energy efficiency of chips, with the improvement of chip computing power and the growth of energy efficiency requirements, there is still much room for optimization in the overall power consumption of chips. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a chip, an electronic device, and a method for controlling the power consumption of the chip, which reduces the power consumption of the interconnection module by adjusting the working frequency of the interconnection module in the data path, thereby reducing the overall power consumption of the chip.

[0005] The embodiments of this application are implemented as follows:

[0006] In a first aspect, an embodiment of this application provides a chip, including: a plurality of functional modules and an interconnection module; the plurality of functional modules include a power management module; any two of the plurality of functional modules are connected through the interconnection module, and the interconnection module is configured to monitor the path bandwidth between the interconnection module and the target module connected to the interconnection module within a period of time; the power management module is configured to obtain each path bandwidth monitored by the interconnection module and adjust the working frequency of the interconnection module according to each path bandwidth.

[0007] In the above embodiments, since the ACPI protocol does not define the working state of the interconnection module that connects each functional module within the chip, and the interconnection bus in the data path is transparent to software such as the operating system, when the software sends an address, the address is routed to a predetermined location to access the corresponding device. The software does not care which modules the address passes through to reach the target device, resulting in poor management of the power consumption of the data path, high power consumption of the chip, and power consumption waste. In this application, by monitoring the path bandwidth between the interconnection module and the target module within a period of time, and dynamically adjusting the working frequency of the interconnection module in the data path, it is possible to reduce the power consumption of the interconnection module and the overall power consumption of the chip; at the same time, hardware control (power management module) has a faster response speed than software control.

[0008] Combined with a possible implementation manner of the first aspect embodiment, the power management module is configured to obtain the maximum path bandwidth among the respective path bandwidths monitored by the interconnection module, and adjust the working frequency of the interconnection module according to the maximum path bandwidth.

[0009] In the above embodiments, by obtaining the maximum path bandwidth among the respective path bandwidths and adjusting the working frequency of the interconnection module according to the maximum path bandwidth, it is beneficial to better control the power consumption of the interconnection module, achieving the goal of reducing power consumption while being compatible with the bandwidth requirements of the target module with high bandwidth requirements.

[0010] Combined with a possible implementation manner of the first aspect embodiment, the path bandwidth includes the number of transmission cycles within a preset time window. The power management module is configured to: determine the required minimum frequency according to the number of transmission cycles in the maximum path bandwidth, and adjust the working frequency of the interconnection module according to the minimum frequency.

[0011] In the above embodiments, determining the required minimum frequency according to the number of transmission cycles in the maximum path bandwidth and adjusting the working frequency of the interconnection module accordingly can minimize power consumption to the greatest extent while ensuring that data can be transmitted within the specified time. For example, assuming that the current clock frequency of the interconnection module is 1 GHz, the corresponding time period is 1 nanosecond, the preset time window is 1 microsecond (corresponding to 1000 cycles), and 10 cycles (corresponding time period is 10 nanoseconds) are used to transmit data, then it can be determined that the minimum frequency of the interconnection module required to transmit 10 cycles within the preset time window (1 microsecond) is 10 MHz. After configuring the clock frequency of the interconnection module to 10 MHz, there are 10 cycles within the same time, all of which are used to transmit data, and the data can still be transmitted within the specified time (such as 1 microsecond), but the power consumption will decrease due to the slower frequency.

[0012] In a possible implementation manner combining with the embodiments of the first aspect, the path bandwidth includes the number of transmission cycles within a preset time window. The power consumption management module is configured to: obtain the available cycle numbers at different frequencies; select a target available cycle whose available cycle number is greater than the number of transmission cycles in the maximum path bandwidth and has the smallest difference from the number of transmission cycles in the maximum path bandwidth; and adjust the operating frequency of the interconnection module according to the frequency corresponding to the target available cycle.

[0013] In the above embodiment, the available cycle numbers at different frequencies can be obtained, and a target available cycle can be selected. Then, the operating frequency of the interconnection module is adjusted according to the frequency corresponding to the target available cycle. Since when selecting the target available cycle, the available cycle number selected is greater than the number of transmission cycles in the maximum path bandwidth and has the smallest difference from the number of transmission cycles in the maximum path bandwidth, the number of idle cycles (i.e., the cycles without transmitting data) can be reduced as much as possible. In this way, the above data can be transmitted within the specified time, and the power consumption of the interconnection module can be reduced to the greatest extent.

[0014] In a possible implementation manner combining with the embodiments of the first aspect, the chip includes multiple interconnection modules operating in the same clock domain; the power consumption management module is further configured to obtain a target path bandwidth and adjust the operating frequencies of the multiple interconnection modules according to the target path bandwidth; where the target path bandwidth is the maximum path bandwidth among the maximum path bandwidths of the multiple interconnection modules respectively.

[0015] In the above embodiment, when the chip includes multiple interconnection modules operating in the same clock domain, the maximum path bandwidth among the maximum path bandwidths of the multiple interconnection modules is selected as the target path bandwidth, and the operating frequencies of the multiple interconnection modules are adjusted accordingly. In this way, it can ensure that the interconnection modules with high bandwidth requirements always obtain sufficient bandwidth, avoid data transmission blockage caused by insufficient frequency, and achieve the purpose of reducing power consumption on the premise of meeting the bandwidth requirements of the interconnection modules with high bandwidth requirements.

[0016] In a possible implementation manner combining with the embodiments of the first aspect, the interconnection module includes an AON unit; the power consumption management module is configured to control other units in the interconnection module except the AON unit to be in a power-off state when the interconnection module is in an idle state, so that the interconnection module is in a low-power mode.

[0017] In the above embodiment, when the interconnection module is in an idle state, the power consumption management module controls other units in the interconnection module except the AON unit to be in a power-off state. By turning off the power supply of most of the logic in the interconnection module and only retaining a small amount of logic power supply for wake-up, power consumption can be saved as much as possible.

[0018] In combination with a possible implementation manner of the first aspect, the AON unit in the interconnection module is used to control other units in the interconnection module except the AON unit to be in a power-off state when the interconnection module is in an idle state, so as to put the interconnection module in a low power consumption mode.

[0019] In the above embodiment, when the interconnection module is in an idle state, the AON unit in the interconnection module controls the other units in the interconnection module except the AON unit to be in a power-off state. By shutting down the power supply of most of the logics in the interconnection module, only a small amount of logic power supply is retained for wake-up, thereby saving power consumption as much as possible.

[0020] In combination with a possible implementation manner of the first aspect, the AON unit is used to control the other units to reset when the interconnection module is in an idle state, and to isolate the other units from the AON unit after the reset is completed, and to control the other units to power off after the isolation is completed.

[0021] In the above embodiment, when the interconnection module is in an idle state, the power-off of other units is controlled in the order of first resetting → then isolating → then powering off. This can take into account both functional safety and power consumption optimization. Resetting can ensure that the module state is controllable, and isolation can prevent electrical interference and current backflow. It can reduce the confusion of logical states and leakage safety caused by not resetting and isolating, thereby ensuring the logic correctness of the interconnection module.

[0022] In combination with a possible implementation manner of the first aspect, the AON unit in the interconnection module is also used to, when receiving a data request from the target module, control other units in the interconnection module to power on if it is monitored that the interconnection module is currently in a low power consumption mode, and after power-on, release the isolation of the other units from the AON unit, and after the isolation is released, control the other units to release the reset state and resume the operating state.

[0023] In the above embodiment, when a data request is received from the target module, other units are powered on in the order of power on → then isolation release → then reset release. This can take into account both functional safety and power consumption optimization, and prevent the power-off area from affecting the normal operation of the non-power-off area during the power-on process.

[0024] In a second aspect, an embodiment of the present application further provides an electronic device, comprising: a chip provided in the embodiment of the first aspect described above and / or in any possible implementation manner in combination with the embodiment of the first aspect.

[0025] In a third aspect, an embodiment of the present application further provides a method for controlling the power consumption of a chip, including: obtaining the path bandwidth between an interconnect module and a target module connected to the interconnect module in the chip within a period of time; adjusting the operating frequency of the interconnect module according to the respective path bandwidths of the interconnect module.

[0026] Combined with a possible implementation manner of the third aspect embodiment, the method further includes: when the interconnect module is in an idle state, controlling other units in the interconnect module except the AON unit to be in a power-off state, so that the interconnect module is in a low power consumption mode.

[0027] Combined with a possible implementation manner of the third aspect embodiment, the method further includes: when a data request from the target module is received, if it is monitored that the interconnect module is currently in a low power consumption mode, controlling other units in the interconnect module to be powered on, after power-on, releasing the isolation between the other units and the AON unit, and after releasing the isolation, controlling the other units to release the reset state and resume the operating state.

[0028] The effective effects of the above third aspect embodiment can refer to the effective effects of the same part in the first aspect embodiment.

[0029] Other features and advantages of the present application will be described in the subsequent description. The objectives and other advantages of the present application can be achieved and obtained through the structures specifically pointed out in the written description and the accompanying drawings. Description of the Drawings

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the following described drawings are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained according to these drawings. Through the shown drawings, the above-mentioned and other objectives, features, and advantages of the present application will become clearer.

[0031] Figure 1 Shows a schematic structural diagram of a chip provided by an embodiment of the present application.

[0032] Figure 2 Shows a schematic structural diagram of a chip connected to other modules or devices provided by an embodiment of the present application.

[0033] Figure 3 Shows a schematic diagram of the principle of adjusting the operating frequency of an interconnect module in a chip provided by an embodiment of the present application.

[0034] Figure 4 Shows a schematic diagram of the principle of controlling the power-on and power-off of an interconnect module in a chip provided by an embodiment of the present application.

[0035] Figure 5 The structural schematic diagram of an electronic device provided by an embodiment of the present application is shown.

[0036] Figure 6 The flowchart of a power consumption control method for a chip provided by an embodiment of the present application is shown. Detailed implementation manners

[0037] Next, the technical solutions in the embodiments of the present application will be described with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The following embodiments can be used as examples to more clearly illustrate the technical solutions of the present application, but cannot be used to limit the protection scope of the present application. Those skilled in the art can understand that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0038] It should be noted that similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of the present application, relational terms such as "first", "second", etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover a non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not expressly listed, or elements inherent to such process, method, article or device.

[0039] Furthermore, the term "and / or" in the present application is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone.

[0040] In the description of the embodiments of the present application, unless otherwise clearly specified and limited, the technical term "connection" can be a direct connection or an indirect connection through an intermediate medium.

[0041] With the improvement of chip computing power, the data throughput becomes larger, the area of the data path becomes larger, and the power consumption becomes higher. In order to reduce the power consumption of the chip, the present application provides a power consumption control method for a chip, which monitors the path bandwidth of the interconnection module in the chip and adjusts the operating frequency of the interconnection module according to the monitored path bandwidth to achieve the purpose of reducing power consumption.

[0042] Next, in conjunction withFigure 1 The chip provided by the embodiments of the present application will be described. As Figure 1 shown, the chip includes a plurality of functional modules and an interconnection module. Among them, the functional modules include a power management module.

[0043] Any two of the plurality of functional modules are connected by at least one interconnection module. For example, functional module A can be connected to functional module B through a plurality of cascaded interconnection modules. The functional modules in the chip refer to independent hardware modules designed to achieve specific functions in an integrated circuit. These functional modules work together to complete the overall task of the chip. The types of functional modules in different chips can be different.

[0044] In addition to the above-mentioned power management module, the functional module may further include, but is not limited to, at least one of the following modules in some possible implementation manners: a CPU core, a GPU (Graphics Processing Unit) core, a System Management Processor (SMP), a Memory Controller (MC), a Multimedia HUB, an Input / Output HUB (IO HUB), etc. These modules are all connected through a Data Fabric Cross Bus (which is an interconnection module), and its schematic diagram is as Figure 2 shown. Among them, the MC can be connected to a memory, such as a DDR (Double Data Rate) memory. The Multimedia HUB can be used to connect multimedia units or devices, such as connecting audio, display and other units or devices. The IO (Input / Output) HUB is used to connect IO devices. In some implementation manners, the DDR may also belong to the chip.

[0045] Among the above-mentioned functional modules, some functional modules can be request initiators, some functional modules can be request receivers, and some functional modules can be both request initiators and request receivers. The request initiator and the request receiver communicate through the interconnection module.

[0046] The interconnection module is a basic module responsible for coordinating the communication between the functional modules in the chip and is used to connect the functional modules. As the complexity of the chip increases, the area and power consumption of the interconnection module are also getting higher and higher. Controlling the power consumption of the interconnection module is beneficial to reducing power consumption. The interconnection module includes, but is not limited to, a Network-on-Chip (NoC), a Crossbar, a Data Fabric, etc.

[0047] The interconnection module is used to monitor the path bandwidth between the interconnection module and the target module within a configurable period of time. The time window for the interconnection module to monitor the path bandwidth can be configured. For example, it can monitor the path bandwidth of the path where the interconnection module is located within 1 s (second). Among them, the path bandwidth is used to measure the amount of information transmitted by a communication link or a data path per unit time. For example, the path bandwidth can include the data traffic transmitted, or can also include the number of transmission cycles within a preset time window, etc.

[0048] The target module is a module connected to the interconnection module. The target module can be a functional module or an interconnection module. Since an interconnection module can be interconnected with many target modules, there can be multiple path bandwidths monitored by the interconnection module. For example, for Figure 1 the interconnection module located on the left in, which has 4 path ports and 4 target modules connected to it, and each path port corresponds to a path bandwidth.

[0049] The power consumption management module is used to obtain the respective path bandwidths monitored by the interconnection module, and adjust the working frequency of the interconnection module according to the respective path bandwidths. The power consumption management module can dynamically adjust the working frequency of the interconnection module in the data path according to the power consumption policy (such as the power consumption priority policy, the efficiency priority policy, etc.) and the current path bandwidth. That is, when the path bandwidth requirement of the interconnection module decreases, the working frequency of the interconnection module can be appropriately reduced, and when the path bandwidth requirement of the interconnection module increases, the working frequency of the interconnection module can be appropriately increased to meet the bandwidth requirement. The working frequency of the interconnection module can be the clock frequency when the interconnection module is working.

[0050] In some embodiments, the interconnection module can record the respective path bandwidths monitored into a register or a memory, and the power consumption management module can obtain the respective path bandwidths monitored by the interconnection module by reading the data in the register or the memory.

[0051] A bandwidth monitoring module (which can be firmware) can be added to the interconnection module to monitor in real time the path bandwidth of the interconnection module flowing through the data path. In view of the fact that the ACPI protocol does not define the working state of the interconnection module connecting each functional module within the chip, and the interconnection bus, etc. in the data path are transparent to software such as the operating system. The software sends an address, and the address is routed to a predetermined location to access the corresponding device. The software does not care which modules the address passes through to reach the target device, resulting in the inability to manage the power consumption of the data path well, making the power consumption of the chip very high and causing the problem of power consumption waste. In this application, a bandwidth monitoring module is added to the data path to monitor in real time the path bandwidth of the data path, and the working frequency of the interconnection module in the data path is dynamically adjusted according to the current path bandwidth.

[0052] In a possible implementation, the power consumption management module is used to obtain the maximum path bandwidth among the path bandwidths monitored by the interconnection module, and adjust the operating frequency of the interconnection module according to the maximum path bandwidth. In this implementation, when the power consumption management module adjusts the operating frequency of the interconnection module according to the path bandwidths, the process may include: obtaining the maximum path bandwidth among the path bandwidths monitored by the interconnection module, and adjusting the operating frequency of the interconnection module according to the maximum path bandwidth.

[0053] In some other implementations, when the power consumption management module adjusts the operating frequency of the interconnection module according to the path bandwidths, the process may include: obtaining the sum of the path bandwidths monitored by the interconnection module, and adjusting the operating frequency of the interconnection module according to the total path bandwidth.

[0054] The path bandwidth includes the number of transmission cycles within a preset time window. When adjusting the operating frequency of the interconnection module according to the maximum path bandwidth, the process may include: determining the required minimum frequency according to the number of transmission cycles in the maximum path bandwidth, and adjusting the operating frequency of the interconnection module according to the minimum frequency. For example, setting the operating frequency of the interconnection module to the minimum frequency. In this implementation, the power consumption management module is used to: determine the required minimum frequency according to the number of transmission cycles in the maximum path bandwidth, and adjust the operating frequency of the interconnection module according to the minimum frequency.

[0055] For example, assume that the current clock frequency of the interconnection module is 1 GHz, then the corresponding time period is 1 nanosecond, the preset time window is 1 microsecond (corresponding to 1000 cycles), and 10 cycles (corresponding time period is 10 nanoseconds) are used to transmit data. Then the minimum frequency of the interconnection module required to transmit 10 cycles within the preset time window (1 microsecond) is 10 MHz. Among them, since the clock cycle corresponding to 10 MHz is 100 nanoseconds, there are 10 cycles within the same time (i.e., 1 microsecond), that is, 1 GHz (corresponding time is 1 nanosecond) * 1000 cycles = 10 MHz (corresponding time is 100 nanoseconds) * 10 cycles. By configuring, the clock frequency of the interconnection module is adjusted to 10 MHz. Because the frequency slows down and the power consumption decreases, but the data can still be transmitted within the specified time (such as 1 microsecond).

[0056] When adjusting the operating frequency of the interconnection module according to the minimum frequency, the operating frequency of the interconnection module can also be set to an operating frequency greater than the minimum frequency. For example, if the clock frequency of the interconnection module is adjusted to 500 MHz, there are 500 cycles in the same time period, and only 10 cycles are used for data transmission; if the clock frequency of the interconnection module is adjusted to 100 MHz, there are 100 cycles in the same time period, and only 10 cycles are used for data transmission; if the clock frequency of the interconnection module is adjusted to 10 MHz, there are 10 cycles in the same time period, and 10 cycles are used for data transmission. Thus, when the clock frequency of the interconnection module decreases, such as when the clock frequency of the interconnection module is adjusted to 100 MHz, there are 100 cycles in the same time period, and 10 cycles are used for data transmission. It can be seen that in the same time period, as the frequency slows down, the power consumption decreases, and the number of cycles required for data transmission remains unchanged (all 10 cycles), and the data can still be transmitted within the specified time (such as 1 microsecond), but the number of idle cycles (i.e., the number of cycles without data transmission) decreases.

[0057] In some possible implementation manners, when the path bandwidth includes the number of transmission cycles within a preset time window, when adjusting the operating frequency of the interconnection module according to the maximum path bandwidth, the process may further include: calculating the available cycles at different frequencies under the preset time window; selecting a target available cycle whose available cycle number is greater than the number of transmission cycles in the maximum path bandwidth and has the smallest difference from the number of transmission cycles in the maximum path bandwidth; adjusting the operating frequency of the interconnection module according to the frequency corresponding to the target available cycle. For example, the operating frequency of the interconnection module is adjusted to the frequency corresponding to the target available cycle. In this implementation manner, the power management module is configured to: obtain the available cycle numbers at different frequencies; select a target available cycle whose available cycle number is greater than the number of transmission cycles in the maximum path bandwidth and has the smallest difference from the number of transmission cycles in the maximum path bandwidth; adjust the operating frequency of the interconnection module according to the frequency corresponding to the target available cycle.

[0058] Assume that the preset time window is 1 microsecond, and the current clock frequency of the interconnection module is 1 GHz. Only 10 cycles out of 1000 cycles (corresponding to 1 microsecond) are used for data transmission. If the clock frequency of the interconnection module is adjusted to 500 MHz, there are 500 available cycles; if the clock frequency of the interconnection module is adjusted to 100 MHz, there are 100 available cycles; if the clock frequency of the interconnection module is adjusted to 10 MHz, there are 10 available cycles; if the clock frequency of the interconnection module is adjusted to 5 MHz, there are 5 available cycles; if the clock frequency of the interconnection module is adjusted to 1 MHz, there is 1 available cycle. When selecting the target available cycle according to the above rules, the 10 available cycles in the above example can be selected as the target available cycle, and thus the frequency corresponding to the target available cycle is 10 MHz.

[0059] In some possible embodiments, the power consumption management module may also adjust the operating frequency of the interconnection module in combination with the historically recorded path bandwidth information. For example, when the power consumption management module adjusts the operating frequency of the interconnection module according to the maximum path bandwidth, the power consumption management module can be used to: if the maximum path bandwidth is greater than the maximum path bandwidth at a historical moment, adjust the operating frequency of the interconnection module from the current first frequency to a second frequency; wherein, the first frequency is less than the second frequency; if the maximum path bandwidth is less than the maximum path bandwidth at a historical moment, adjust the operating frequency of the interconnection module from the current first frequency to a third frequency; wherein, the first frequency is greater than the third frequency.

[0060] By adjusting the operating frequency of the interconnection module in combination with the historical maximum path bandwidth, it is possible to avoid the frequency adjustment being too low or too high and affecting the efficiency. The above-mentioned first frequency, second frequency, and third frequency are all the clock frequencies when the interconnection module is operating.

[0061] Among them, the maximum path bandwidth at the above-mentioned historical moment can be the maximum path bandwidth recorded within a period of time. For example, record the path bandwidth situation every 1 ms within the previous 10 ms (configurable), and use the highest path bandwidth within these 10 ms as the basis for frequency modulation. In some embodiments, when adjusting the operating frequency of the interconnection module in combination with the historically recorded path bandwidth information, it can also be in combination with the maximum path bandwidth of the previous preset number of times (such as 5 times). If the difference in the maximum path bandwidth of these preset number of times is relatively large, indicating large bandwidth jitter, the frequency may not be adjusted temporarily; or the frequency can be adjusted according to the maximum path bandwidth in the preset number of times; in addition, if the maximum path bandwidth in the preset number of times shows a downward trend, the frequency can be adjusted as soon as possible, etc.

[0062] Among them, when recording the maximum path bandwidth each time in the preset number of times, different recording precisions can be used according to the time distance. For example, for the time before 10 ms, only the maximum 1 ms bandwidth record is retained every 10 ms, and the 1 ms record is used as the record result for these 10 ms; while for the time before 100 ms, only the maximum 1 ms bandwidth record is retained every 100 ms, and the 1 ms record is used as the record result for these 100 ms. For the first 90 ms, since there is a record result corresponding to every 10 ms, there are 9 maximum path bandwidths. When the time reaches the previous 100 ms, the maximum path bandwidth corresponding to the first 90 ms and the maximum path bandwidth corresponding to the subsequent 10 ms will be selected, and the larger one will be used as the record result for these 100 ms.

[0063] In some possible embodiments, the chip includes multiple interconnect modules operating in the same clock domain. At this time, the power management module is further configured to obtain the target path bandwidth and adjust the operating frequencies of the multiple interconnect modules according to the target path bandwidth, where the target path bandwidth is the maximum path bandwidth among the maximum path bandwidths of the multiple interconnect modules. For example, assume that the number of interconnect modules operating in the same clock domain is 3, namely interconnect module 1, interconnect module 2, and interconnect module 3. Each interconnect module corresponds to a maximum path bandwidth, then the target path bandwidth is the maximum of the 3 maximum path bandwidths corresponding to these 3 interconnect modules.

[0064] Among them, when adjusting the operating frequencies of the multiple interconnect modules according to the target path bandwidth, the operating frequencies of the multiple interconnect modules can be adjusted to the same operating frequency. The adjustment process can refer to the process of adjusting the operating frequency of the interconnect module according to the maximum path bandwidth above, which will not be elaborated here.

[0065] In some possible embodiments, when the power management module manages the power consumption of the interconnect module, its principle can be as Figure 3 shown. The power management module monitors the effective data traffic of the interconnect module within a period of time, and judges whether to adjust its clock frequency according to the monitored data traffic and the current clock frequency of the interconnect module. If necessary, on the premise of meeting the bandwidth requirements, it adjusts the clock frequency of the interconnect module. After the clock frequency is adjusted, it continues to monitor the effective path bandwidth of the interconnect module, that is, continues to monitor the effective data traffic of the interconnect module within a period of time.

[0066] When judging whether to adjust the clock frequency according to the monitored data traffic and the current clock frequency of the interconnect module, it can be judged according to power consumption strategies (such as power consumption priority strategy, efficiency priority strategy, etc.) and the current clock frequency of the interconnect module. When calculating the clock frequency that needs to be adjusted, various algorithms such as machine learning can also be used according to the historical record of the effective bandwidth to calculate an appropriate clock frequency, so that the clock frequency can not only meet the bandwidth requirements but also be optimal in terms of power consumption. In addition, the above-described method can also be used for adjustment. For example, if only 10 cycles transmit data in the current 1000 cycles, the clock frequency can be adjusted to 1 / 10 of the original frequency by configuration.

[0067] In some possible embodiments, the power consumption management module is further configured to control the interconnection module to be in a low-power mode when the interconnection module is in an idle state. If a certain interconnection module in the data path is in an idle state, the power supply of the interconnection module can be controlled to be cut off by hardware, and only a small amount of wake-up logic is retained. When a data request arrives, it is controlled to power on automatically. By controlling the power-off or power-on by hardware without the participation of software, the response speed is fast, and the power consumption can be further saved. In this way, it can be avoided that the interconnection module is also in a working state during idle time, resulting in power consumption waste.

[0068] For example, some application devices occasionally initiate DMA (Direct Memory Access) access. At this time, there is only a small amount of data transmission in the data path, but it still operates in the full-speed mode, resulting in power consumption waste. Another example is the CPU memory access scenario. The IO device has no data access, but the entire interconnection module is still in a working state, resulting in power consumption waste. In this case, the power supply of the interconnection module is controlled to be cut off by hardware, and only a small amount of wake-up logic is retained. When a data request arrives, it is controlled to power on automatically, so that the power consumption can be saved as much as possible.

[0069] Among them, the interconnection module includes an AON (Always On Domain) unit; the AON unit is not a single module, but a collection of core modules that maintain basic functions in a low-power system. For example, it can include a real-time clock, an interrupt controller, a power management unit, a communication interface, etc. It is a key module in the embedded system, mainly used to maintain the continuous operation of specific functions when the main system is in a sleep or off state, ensuring that critical tasks are not interrupted. For example, it keeps time synchronization when the system is in a sleep state, is responsible for handling wake-up events, and maintains basic functions.

[0070] In some possible embodiments, the AON unit can be independently powered. The AON unit and other units in the interconnection module except the AON unit can be in different power domains. For example, Figure 2 the power supply of the AON unit in is from power domain 2, and the power supply of other units is from power domain 1. The AON unit can control the power supply of other units by power domain 1. For example, a switch can be set on the power supply line of other units, and the power supply control of other units can be realized by controlling the on / off of the switch. Or, the AON unit and other units can also be in the same power domain instead of being independently powered, but the AON unit always remains powered on by default, and the power supply of other units is controlled by the AON unit. For example, a switch can be set on the power supply line of other units, and the power supply control of other units can be realized by controlling the on / off of the switch.

[0071] When the power consumption management module controls the interconnection module to be in a low power consumption mode, it is used to control the other units in the interconnection module except the AON unit to be in a power-off state, so that the interconnection module is in a low power consumption mode, that is, when the interconnection module is in an idle state, the power supply of most of the logic in the interconnection module is turned off, and only a small amount of logic power supply is reserved for wake-up. For example, when the interconnection module is in an idle state, the power consumption management module can send a power-off instruction to the AON unit in the interconnection module to control the interconnection module to be in a low power consumption mode.

[0072] The AON unit in the interconnection module may control the other units in the interconnection module except the AON unit to be in a power-off state after receiving the power-off instruction sent by the power consumption management module. In some other possible implementations, the AON unit in the interconnection module itself may control the other units in the interconnection module except the AON unit to be in a power-off state when the interconnection module is in an idle state, so that the interconnection module is in a low power consumption mode.

[0073] The AON unit can control other units to reset when the interconnection module is in an idle state, and isolate other units from the AON unit after the reset is completed, and control other units to power off after the isolation is completed. For example, the AON unit can control other units to reset by sending a reset signal to other units to put them in a reset state, and after the reset is completed, send an isolation valid signal to other units to isolate other units from the AON unit, and then control other units to power off.

[0074] The AON unit is also used to control other units in the interconnected module to power on if it is detected that the interconnected module is currently in a low-power mode when receiving a data request from the target module, and to release the isolation of other units from the AON unit after powering on, and to control other units to release the reset state and resume the operation state after the isolation is released. For example, when the interconnected module is in a low-power state, the AON unit therein will monitor the data request from the target module in real time. When receiving a data request from the target module, if it is detected that the interconnected module is currently in a low-power mode, the AON unit controls other units in the interconnected module to power on, and then can send an isolation invalidation signal to other units to release the isolation of other units from the AON unit. Finally, a reset release signal can be sent to other units to release the reset state of other units and resume the operation state.

[0075] Among them, whether the interconnection module is in an idle state can be determined based on the path bandwidth monitored over a period of time. If the path bandwidth over a period of time indicates no or very little data transmission, the interconnection module can be considered to be in an idle state.

[0076] For the power-on or power-off principle of other units in the above control interconnection module except the AON unit, reference can be made to Figure 4 the flowchart shown. By monitoring the path bandwidth of the interconnection module for a period of time, when it is determined that the interconnection module is in an idle state based on the monitored path bandwidth, the power supply to most of the logic of the interconnection module is turned off, and only a small amount of logic power supply is retained for wake-up. That is, other units in the control interconnection module except the AON unit are in a power-down state. Then, when a data request from the target module is received, the power supply to most of the logic (i.e., other units) in the interconnection module is restored and the configuration is restored. In this way, the interconnection module returns to the working state and can process the data request.

[0077] The above chip can be, but is not limited to, a processor. It can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), a Graphics Processing Unit (GPU), an Accelerated Processing Unit, a Multimedia Application Processor (MAP), a microprocessor, etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. It can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present application. Or the processor can also be any conventional processor, etc.

[0078] In addition, a chip including the above interconnection module, power consumption management module, etc. can also include a memory controller chip, a wireless communication chip, an Internet of Things chip, and an automotive electronic control unit, etc.

[0079] The embodiments of the present application also provide an electronic device, and this electronic device includes the above chip. When the chip is a processor, in a possible implementation manner, as Figure 5 shown, the electronic device includes: a transceiver, a memory, a communication bus, and a processor.

[0080] The transceiver, the memory, and the processor are electrically connected to each other directly or indirectly to realize data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses or signal lines. Among them, the transceiver is used to send and receive data. The memory is used to store computer programs, and the processor is used to execute software function modules or computer programs stored in the memory.

[0081] Among them, the memory can be, but is not limited to, random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), etc.

[0082] Among them, the above-mentioned electronic devices include, but are not limited to, mobile phones, tablets, computers, network devices, vehicle-mounted devices, servers, etc.

[0083] The embodiment of the present application also provides a power consumption control method for a chip. The principle will be described below in conjunction with Figure 6 The power consumption control method includes: S1 and S2.

[0084] S1: Obtain the path bandwidth between the interconnect module and the target module connected to the interconnect module in the chip for a period of time.

[0085] Since one interconnect module can interconnect many target modules, when obtaining the path bandwidth between the interconnect module and the target module connected to the interconnect module in the chip for a period of time, multiple path bandwidths of the interconnect module can be obtained.

[0086] In some possible implementation manners, the power consumption management module in the chip can be used to obtain the path bandwidth between the interconnect module and the target module connected to the interconnect module in the chip for a period of time.

[0087] S2: Adjust the operating frequency of the interconnect module according to each path bandwidth of the interconnect module.

[0088] After obtaining each path bandwidth of the interconnect module, the operating frequency of the interconnect module can be adjusted according to each path bandwidth of the interconnect module in combination with the power consumption strategy.

[0089] In some possible embodiments, the power management module in the chip may adjust the operating frequency of the interconnect module according to the bandwidths of the respective channels of the interconnect module.

[0090] In some possible embodiments, the implementation process of S2 may include: obtaining the maximum channel bandwidth among the respective channel bandwidths, and adjusting the operating frequency of the interconnect module according to the maximum channel bandwidth.

[0091] In some possible embodiments, when adjusting the operating frequency of the interconnect module according to the maximum channel bandwidth, the process may include: determining the required minimum frequency according to the number of transmission cycles in the maximum channel bandwidth, and adjusting the operating frequency of the interconnect module according to the minimum frequency.

[0092] In some possible embodiments, when adjusting the operating frequency of the interconnect module according to the maximum channel bandwidth, the process may include: obtaining the available cycle numbers at different frequencies; selecting a target available cycle number whose available cycle number is greater than the number of transmission cycles in the maximum channel bandwidth and whose difference from the number of transmission cycles in the maximum channel bandwidth is the smallest; and adjusting the operating frequency of the interconnect module according to the frequency corresponding to the target available cycle number.

[0093] In some possible embodiments, the chip includes multiple interconnect modules operating in the same clock domain. The implementation process of S2 may include: determining a target channel bandwidth from the respective channel bandwidths of the multiple interconnect modules operating in the same clock domain, and adjusting the operating frequencies of the multiple interconnect modules operating in the same clock domain according to the target channel bandwidth. Among them, the target channel bandwidth is the maximum channel bandwidth among the respective maximum channel bandwidths of these multiple interconnect modules.

[0094] In some possible embodiments, the above method further includes: when the interconnect module is in an idle state, controlling other units in the interconnect module except the AON unit to be in a power-off state, so that the interconnect module is in a low-power mode.

[0095] In some possible embodiments, the power management module in the chip may control other units in the interconnect module except the AON unit to be in a power-off state, so that the interconnect module is in a low-power mode. In some other possible embodiments, the AON unit in the interconnect module may control other units except the AON unit to be in a power-off state, so that the interconnect module is in a low-power mode.

[0096] In some possible embodiments, when controlling other units in the interconnect module except the AON unit to be in a power-off state, the process may include: controlling other units to be reset, isolating other units from the AON unit after the reset is completed, and controlling other units to be powered off after the isolation is completed.

[0097] In some possible embodiments, the above method further includes: when a data request from a target module is received, if it is monitored that the interconnect module is currently in the low-power mode, controlling other units in the interconnect module to power on, after powering on, releasing the isolation between the other units and the AON unit, and after releasing the isolation, controlling the other units to release the reset state and resume the operating state.

[0098] In some possible embodiments, when the AON unit in the interconnect module monitors that the interconnect module is currently in the low-power mode and receives a data request from a target module, it can control other units in the interconnect module to power on, after powering on, release the isolation between the other units and the AON unit, and after releasing the isolation, control the other units to release the reset state and resume the operating state.

[0099] The implementation principle and the technical effects generated by the method embodiments are the same as those of the foregoing chip embodiments. For a brief description, for parts not mentioned in the method embodiments, reference may be made to the corresponding content in the foregoing chip embodiments.

[0100] It should be noted that the embodiments in this specification are all described in a progressive manner, and the key point of each embodiment is to describe the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other.

[0101] In several embodiments provided in the present application, it should be understood that the disclosed apparatus and method can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the drawings show the possible architectures, functions, and operations of apparatuses, methods, and computer program products according to multiple embodiments of the present application. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of code, and the module, program segment, or part of code includes one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order from that marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

[0102] In addition, in each embodiment of the present application, the functional modules can be integrated together to form an independent part, or each module can exist separately, or two or more modules can be integrated to form an independent part.

[0103] As described above, it is only the specific implementation manner of the present application. However, the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A chip, characterized in that, include: A plurality of functional modules, wherein the plurality of functional modules include a power consumption management module; An interconnection module, through which any two functional modules among the plurality of functional modules are connected, and the interconnection module is used to monitor the path bandwidth between the interconnection module and a target module connected to the interconnection module over a period of time; The power consumption management module is used to obtain the bandwidth of each channel monitored by the interconnection module, and adjust the working frequency of the interconnection module according to the bandwidth of each channel.

2. The chip according to claim 1, characterized in that, The power consumption management module is used to obtain the maximum path bandwidth among the path bandwidths monitored by the interconnection module, and adjust the working frequency of the interconnection module according to the maximum path bandwidth.

3. The chip according to claim 2, wherein The path bandwidth includes the number of transmission cycles within a preset time window, and the power consumption management module is used to: The required minimum frequency is determined according to the number of transmission cycles in the maximum path bandwidth, and the operating frequency of the interconnection module is adjusted according to the minimum frequency.

4. The chip according to claim 2, wherein, The path bandwidth includes the number of transmission cycles within a preset time window, and the power consumption management module is used to: Get the number of available cycles at different frequencies; Select a target available cycle whose number of available cycles is greater than the number of transmission cycles in the maximum path bandwidth and whose difference with the number of transmission cycles in the maximum path bandwidth is the smallest; The operating frequency of the interconnection module is adjusted according to the frequency corresponding to the target available period.

5. The chip according to claim 1, characterized in that, The chip includes a plurality of interconnected modules operating in the same clock domain; the power consumption management module is further used to obtain a target path bandwidth and adjust the operating frequency of the plurality of interconnected modules according to the target path bandwidth; The target path bandwidth is the maximum path bandwidth among the maximum path bandwidths of the plurality of interconnected modules.

6. The chip according to claim 1, wherein The interconnection module includes an AON unit; The power consumption management module is used to control other units in the interconnection module except the AON unit to be in a power-off state when the interconnection module is in an idle state, so as to put the interconnection module in a low power consumption mode.

7. The chip according to claim 1, wherein The AON unit in the interconnect module is used to control other units in the interconnect module except the AON unit to be in a power-off state when the interconnect module is in an idle state, so that the interconnect module is in a low power consumption mode.

8. The chip according to claim 7, characterized in that, The AON unit is used to control the other units to reset when the interconnection module is in an idle state, and to isolate the other units from the AON unit after the reset is completed, and to control the other units to power off after the isolation is completed.

9. The chip according to claim 7 or 8, characterized in that, The AON unit in the interconnection module is also used to control other units in the interconnection module to power on when receiving a data request from the target module, if it is monitored that the interconnection module is currently in a low power consumption mode, and to release the isolation of the other units from the AON unit after power-on, and to control the other units to release the reset state and resume the operating state after the isolation is released.

10. An electronic device, characterized in that, include: A chip as claimed in any one of claims 1 to 9.

11. A method for controlling the power consumption of a chip, characterized in that, include: Obtaining a path bandwidth between an interconnection module in a chip and a target module connected to the interconnection module within a period of time; The operating frequency of the interconnection module is adjusted according to the bandwidth of each path of the interconnection module.

12. The method according to claim 11, wherein The method further comprises: When the interconnection module is in an idle state, other units in the interconnection module except the AON unit are controlled to be in a power-off state, so that the interconnection module is in a low power consumption mode.

13. The method according to claim 12, wherein The method further comprises: In the case of receiving a data request from the target module, if it is monitored that the interconnection module is currently in a low power consumption mode, other units in the interconnection module are controlled to be powered on, and after power-on, the isolation of the other units from the AON unit is released, and after the isolation is released, the other units are controlled to be released from the reset state and resume the operating state.

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