Storage controller and storage device including same

Abstract

A storage device configured to communicate with a first host, a second host, and a supervisor, includes: a non-volatile memory device that may include a first namespace allocated to the first host, a second namespace allocated to the second host, and a plurality of address mapping tables; and a storage controller configured to: access a first namespace based on an input / output request from a first host based on the plurality of address mapping tables; and accessing the second namespace based on an input / output request from the second host. The storage controller may include a first dedicated cache region partitioned to cache an address mapping table having a first table type corresponding to a first namespace among the plurality of address mapping tables.

Description

Cross - reference to related applications

[0001] This application claims priority to Korean Patent Application No. 10 - 2024 - 0004408, filed with the Korean Intellectual Property Office on January 10, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0002] The present disclosure relates to a storage device. More specifically, the present disclosure relates to a storage controller supporting multiple hosts and a storage device including the storage controller. Background art

[0003] Flash - based storage devices do not allow overwriting. Thus, a storage controller of a flash - based storage device can store an address mapping table that maps a logical address managed by a host and a physical address managed by the storage device. However, if the storage controller of an ultra - large - capacity storage device stores the address mapping table of all physical addresses, the address mapping table may consume an excessive amount of capacity. Thus, an ultra - large - capacity storage device can store multiple address mapping tables in a non - volatile memory device and then can operate by caching some of the address mapping tables in the storage controller.

[0004] Recently, multi - host storage systems have been developed in which a single storage device is configured to communicate with multiple hosts or multiple tenants. Generally, if multiple hosts access a single storage device, there may be a problem of deteriorated performance provided for each of the multiple hosts due to limited resources of a single storage controller. Summary of the invention

[0005] Embodiments of the present disclosure provide a storage controller and a storage device including the storage controller, the storage controller being configured to prevent exclusive use of resources by a specific host.

[0006] According to an aspect of the present disclosure, a storage device configured to communicate with a first host, a second host, and a supervisor may include: a non - volatile memory device that may include a first namespace assigned to the first host, a second namespace assigned to the second host, and multiple address mapping tables; and a storage controller configured to, based on the multiple address mapping tables: access the first namespace based on an input / output request from the first host; and access the second namespace based on an input / output request from the second host. The storage controller may include a first dedicated cache area partitioned to cache address mapping tables of a first table type corresponding to the first namespace among the multiple address mapping tables.

[0007] According to one aspect of the present disclosure, a storage controller configured to control a non-volatile memory device that may include a first namespace and a second namespace, the storage controller may include: a mapping data memory device that may include: a first dedicated cache area storing a first plurality of address mapping tables of the first namespace; and a second dedicated cache area storing a second plurality of address mapping tables of the second namespace; and a cache manager configured to manage the capacity of each of the first dedicated cache area and the second dedicated cache area.

[0008] According to one aspect of the present disclosure, a storage device configured to communicate with a first host and a second host may include: a non-volatile memory device configured to store a global address mapping table that may include a first plurality of address mapping tables and a second plurality of address mapping tables respectively corresponding to the first host and the second host; and a storage controller that may include: a mapping data memory device configured to cache at least one address mapping table of the first plurality of address mapping tables or the second plurality of address mapping tables; and a cache manager configured to manage a first occupancy guarantee ratio of the first plurality of address mapping tables of the mapping data memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram showing a storage system according to one or more embodiments of the present disclosure;

[0011] Figure 2 is shown in more detail Figure 1 of the storage controller;

[0012] Figure 3 is shown in Figure 1 of the method of caching an address mapping table in the mapping data memory device;

[0013] Figure 4 is shown in Figure 1 of the method of partitioning the mapping data memory device;

[0014] Figure 5 is shown in more detail Figure 2 of the cache allocation table;

[0015] Figure 6 is shown in more detail Figure 3 of one of the address mapping tables;

[0016] Figure 7 shows according to one or more embodiments ofFigure 1 Method for a storage device to perform input / output operations;

[0017] Figure 8 Shows, according to one or more embodiments, Figure 1 Method for a storage device to perform input / output operations;

[0018] Figure 9 Shows, according to one or more embodiments, Figure 1 Method for a storage device to perform input / output operations;

[0019] Figure 10 Is a flowchart showing the operations of a storage controller that performs input / output operations; Figure 1 Of;

[0020] Figure 11 Is a more detailed illustration of Figure 10 Flowchart of operation S140;

[0021] Figure 12 Is a more detailed illustration of Figure 11 Flowchart of operation S143;

[0022] Figure 13 Shows, according to one or more embodiments, the operations of a storage device according to a request from a supervisor; Figure 1 Of;

[0023] Figure 14 Shows, according to one or more embodiments, the operations of a storage device according to a request from a supervisor; Figure 1 Of;

[0024] Figure 15 Is a more detailed illustration of a method for updating a cache allocation table according to an embodiment; Figure 14 Of;

[0025] Figure 16 Is a flowchart showing the operations of a storage controller operating in response to a ratio allocation configuration request; Figure 14 Of;

[0026] Figure 17 Is a more detailed illustration of Figure 16 Flowchart of operation S230;

[0027] Figure 18 Is a more detailed illustration of Figure 17 Flowchart of operation S232; and

[0028] Figure 19 Shows, according to one or more embodiments, the operations of a storage system; Figure 1 Of; Detailed Description

[0029] Hereinafter, embodiments of the present disclosure will be described clearly and in detail so that those of ordinary skill in the art of the present disclosure can easily implement the present disclosure. The provision of details such as detailed configurations and structures is only for facilitating a comprehensive understanding of the embodiments of the present disclosure. Therefore, modifications to the embodiments described in the present disclosure can be made by those of ordinary skill in the art without departing from the technical spirit and scope of the present disclosure. In addition, descriptions of well-known functions and structures are omitted for clarity and conciseness. The configurations in the drawings or the specific embodiments of the present disclosure may be connected to elements other than those shown in the drawings or described in the specific embodiments. The terms used in the present disclosure are defined in consideration of the functions of the present disclosure and are not limited to specific functions. The definitions of the terms can be determined based on the details described in the specific embodiments.

[0030] Elements described with reference to terms such as drivers, blocks, etc. used in the specific embodiments may be implemented in the form of software, hardware, or a combination thereof. For example, the software may be machine code, firmware, embedded code, and application software. For example, the hardware may include circuits, electronic circuits, processors, computers, integrated circuit cores, pressure sensors, inertial sensors, microelectromechanical systems (MEMS), passive components, or a combination thereof.

[0031] Figure 1 is a block diagram showing a storage system according to one or more embodiments of the present disclosure. Refer to Figure 1 , the storage system SS may include a supervisor SV, first host 11 to nth host 1n, and a storage device 100. In one or more embodiments, the storage system SS may be included in one of various information processing devices, such as a personal computer, a laptop computer, a server, a workstation, a smart phone, a tablet PC, etc.

[0032] Each of the supervisor SV and the first host 11 to the nth host 1n may access the storage device 100. In one or more embodiments, each of the supervisor SV and the first host 11 to the nth host 1n may be a single-core or multi-core processor included in each different computing node. Alternatively, at least some of the supervisor SV and the first host 11 to the nth host 1n may be different processors included in the same computing node. However, the scope of the present disclosure is not limited thereto, and each of the supervisor SV and the first host 11 to the nth host 1n may be a processor configured to process different applications or different virtual machines driven in a computing system.

[0033] The storage device 100 may include a storage controller 110 and a non-volatile memory device 120.

[0034] The storage device 100 can be configured to support multiple hosts or multiple tenants. In other words, the storage controller 110 can operate in response to the control of multiple hosts. For example, the storage controller 110 can store data in the non-volatile memory device 120 or can read data from the non-volatile memory device 120 based on requests issued from the first host 11 to the nth host 1n.

[0035] The storage device 100 can allocate different storage spaces for each of the multiple hosts. For example, the non-volatile memory device 120 can include a first namespace NS1 to an nth namespace NSn. The storage controller 110 can allocate the first namespace NS1 to the nth namespace NSn to the first host 11 to the nth host 1n, respectively.

[0036] The storage device 100 can allocate different namespace identifiers (NSIDs) for each of the first namespace NS1 to the nth namespace NSn. For example, the namespace identifiers '1' to 'n' can be allocated to the first namespace NS1 to the nth namespace NSn, respectively.

[0037] Each of the first host 11 to the nth host 1n can only access the namespace allocated by the storage device 100. For example, the first host 11 can access the first namespace NS1 by providing the namespace identifier '1' to the storage controller 110, and the second host 12 can access the second namespace NS2 by providing the namespace identifier '2' to the storage controller 110. However, the scope of the present disclosure is not limited thereto.

[0038] In one or more embodiments, the storage device 100 can communicate with the supervisor SV and the first host 11 to the nth host 1n based on a peripheral component interconnect express (PCIe) interface or a PCIe-based non-volatile memory express (NVMe) interface.

[0039] The storage controller 110 can include a mapping data memory device 113 and a cache manager 115.

[0040] The first host 11 to the nth host 1n may access the storage device 100 based on logical addresses. On the other hand, the storage device 100 may perform read operations and programming operations on the non-volatile memory device 120 based on physical addresses. Accordingly, the storage controller 110 may distinguish and manage logical addresses and physical addresses. For example, the mapping data storage device 113 may store a plurality of address mapping tables indicating mapping information between logical addresses and physical addresses. The storage controller 110 may perform an address mapping operation based on the plurality of address mapping tables stored in the mapping data memory device 113. In other words, the storage controller 110 may perform input / output operations on each of the first host 11 to the nth host 1n based on the plurality of address mapping tables stored in the mapping data memory device 113.

[0041] The storage device 100 may be an ultra-large capacity solid state drive (SSD). For example, the storage device 100 may be an ultra-large capacity SSD having a capacity of 64 TB or more. However, the scope of the present disclosure is not limited to the capacity of the storage device 100.

[0042] The capacity of the address mapping tables managed by the storage controller 110 may be determined according to the capacity of the storage device 100. For example, the storage controller 110 included in the storage device 100 having a relatively large capacity may need to manage mapping information of a relatively large number of physical addresses. Accordingly, the storage controller 110 included in the storage device 100 having a relatively large capacity may need to manage an address mapping table having a relatively large capacity. In particular, if the storage device 100 is an ultra-large capacity SSD, the storage controller 110 will need to manage an address mapping table having an ultra-large capacity. However, the capacity of the mapping data memory device 113 included in the storage controller 110 may not be sufficient to store an address mapping table having an ultra-large capacity. For example, in terms of the design of the storage device 100 and the cost of the storage device 100, it may be difficult to apply a mapping data memory device 113 having an infinite large capacity.

[0043] Accordingly, the storage controller 110 may operate by caching a plurality of address mapping tables in the mapping data memory device 113. Hereinafter, one or more embodiments in which a plurality of address mapping tables are cached in the mapping data memory device 113 will be representatively described.

[0044] The non-volatile memory device 120 may include a global address mapping table GAMT. The global address mapping table GAMT may include a plurality of address mapping tables AMT used in the storage device 100.

[0045] In one or more embodiments, the global address mapping table GAMT may include all address mapping tables AMT used in the storage device 100. However, the scope of the present disclosure is not limited thereto.

[0046] The cache manager 115 may cache some of the multiple address mapping tables AMT stored in the global address mapping table GAMT in the mapped data storage device 113. For example, the cache manager 115 may read the address mapping table AMT from the non-volatile memory device 120 and may store the address mapping table AMT in the mapped data storage device 113. In this case, the storage controller 110 may perform an address mapping operation based on the address mapping table AMT cached in the mapped data storage device 113. That is, in response to an input / output request issued from the first host 11 to the nth host 1n, the storage controller 110 may perform an input / output operation based on the address mapping table AMT cached in the mapped data storage device 113.

[0047] The following will refer to Figures 7 to 12 The input / output operation of the storage device 100 based on the address mapping table AMT cached in the mapped data storage device 113 will be described in more detail.

[0048] The cache manager 115 may manage the occupancy guarantee ratio of the mapped data storage device 113 for each table type of the address mapping table AMT. For example, the cache manager 115 may allocate some areas of the mapped data storage device 113 for caching the address mapping table AMT for input / output operations for the first namespace NS1 (e.g., input / output operations for the first host 11), or may allocate another area of the mapped data storage device 113 for caching the address mapping table AMT for input / output operations for the second namespace NS2 (e.g., input / output operations for the second host 12). In this way, the cache manager 115 may allocate different areas of the mapped data storage device 113 for each table type of the address mapping table AMT. In this case, even if some hosts issue random access input / output requests at a high frequency (e.g., even when some hosts are noisy neighbors), the address mapping table AMT for the input / output operations of a host may not monopolize the entire mapped data storage device 113. In other words, even if random access input / output requests occur frequently by some hosts, some areas of the mapped data storage device 113 may store the address mapping table AMT for the input / output operations of another host (e.g., a host that performs input / output operations at a relatively low frequency but requires a relatively high quality of service (QoS)). In this case, the phenomenon that some hosts over-occupy the mapped data storage device 113 (e.g., monopoly or cache exhaustion phenomenon) can be prevented, so that the QoS of other hosts can be guaranteed. Therefore, the overall operation performance of the storage system SS can be improved.

[0049] In one or more embodiments, the size of the region of the mapping data storage device 113 allocated by the cache manager 115 for each table type of the address mapping table AMT may be determined based on the quality of service (QoS) required by each of the first host 11 to the nth host 1n.

[0050] In one or more embodiments, the supervisor SV may request information about the ratio of the mapping data storage device 113 allocated for each table type of the address mapping table AMT to the storage device 100.

[0051] In one or more embodiments, the supervisor SV may request the storage device 100 to change the capacity of each region of the mapping data storage device 113 managed by the cache manager 115 based on the QoS required by each of the first host 11 to the nth host 1n.

[0052] The following will refer to Figures 13 to 19 The operation of the storage device 100 according to the request of the supervisor SV will be described in more detail.

[0053] Figure 2 is a more detailed block diagram showing Figure 1 of the storage controller. Referring to Figure 1 and Figure 2 The storage controller 110 may include a processor 111, a buffer memory device 112, a mapping data storage device 113, a host interface circuit 114, a cache manager 115, and a non-volatile memory interface circuit 116. The processor 111, the buffer memory device 112, the mapping data storage device 113, the host interface circuit 114, the cache manager 115, and the non-volatile memory interface circuit 116 may be connected to each other via a bus.

[0054] The processor 111 may control the overall operation of the storage controller 110. For example, the processor 111 may execute various types of programs, applications, and firmware executed in the storage controller 110.

[0055] The buffer memory device 112 may be used as a buffer memory or an operating memory of the storage controller 110. For example, the buffer memory device 112 may be implemented as a static random access memory (SRAM), a dynamic random access memory (DRAM), etc.

[0056] The mapping data storage device 113 may cache multiple address mapping tables AMT. For example, the mapping data storage device 113 may store some of the multiple address mapping tables AMT included in the global address mapping table GAMT. In this case, the storage controller 110 may perform an address mapping operation based on the address mapping table AMT cached in the mapping data storage device 113.

[0057] In one or more embodiments, the mapping data storage device 113 may be implemented as a volatile memory device, such as a dynamic random access memory (DRAM) or the like.

[0058] In one or more embodiments, the buffer memory device 112 and the mapping data storage device 113 may be implemented as a single volatile memory device. However, the scope of the present disclosure is not limited thereto. For example, the buffer memory device 112 and the mapping data storage device 113 may be implemented as different volatile memory devices.

[0059] The storage controller 110 may communicate with the supervisor SV and the first host 11 to the nth host 1n through the host interface circuit 114. For example, the host interface circuit 114 may communicate with the supervisor SV and the first host 11 to the nth host 1n based on at least one of various host interfaces such as a peripheral component interconnect express (PCIe) interface, a non-volatile memory express (NVMe) interface, a serial advanced technology attachment (SATA) interface, a serial attached SCSI (SAS) interface, a universal flash storage (UFS) interface, etc. For a more concise description, hereinafter, it is assumed that the host interface circuit 114 communicates with the supervisor SV and the first host 11 to the nth host 1n based on the PCIe interface.

[0060] The cache manager 115 may control the caching of multiple address mapping tables AMT. For example, if the first host 11 to the nth host 1n provides an input / output request for any logical address, but the address mapping table AMT indicating the physical address corresponding to the logical address is not cached in the mapping data storage device 113, the cache manager 115 may read the address mapping table AMT indicating the physical address corresponding to the logical address from the non-volatile memory device 120. Thereafter, the cache manager 115 may perform an input / output operation by caching the read address mapping table AMT in the mapping data storage device 113. The operation of the cache manager 115 in response to an input / output request from the first host 11 to the nth host 1n will be described in more detail below with reference to Figures 7 to 12 The operation of the cache manager 115 in response to an input / output request from the first host 11 to the nth host 1n will be described in more detail.

[0061] The cache manager 115 may control the caches of multiple address mapping tables AMT based on the QoS required by each of the first host 11 to the nth host 1n. For example, the cache manager 115 may include a cache allocation table CAT. The cache manager 115 may manage the occupancy guarantee ratio of the mapped data storage device 113 of each of the first host 11 to the nth host 1n based on the cache allocation table CAT. A more detailed configuration of the cache allocation table CAT will be described in more detail below with reference to Figure 5 The more detailed configuration of the cache allocation table CAT will be described in more detail.

[0062] The cache manager 115 may manage the mapped data storage device 113 by dividing the mapped data storage device 113 into multiple cache regions of different types based on the cache allocation table CAT. For example, the cache manager 115 may divide the mapped data storage device 113 into multiple dedicated cache regions and one shared cache region. A method by which the cache manager 115 divides the mapped data storage device 113 based on the cache allocation table CAT will be described in more detail below with reference to Figure 4 The method by which the cache manager 115 divides the mapped data storage device 113 based on the cache allocation table CAT will be described in more detail.

[0063] In one or more embodiments, the cache manager 115 may be implemented by hardware, software, or a combination of hardware and software. For example, at least a part of the cache manager 115 may be included in the storage controller 110 in the form of a separate circuit, a separate device, or a separate chip. Additionally, at least a part of the cache manager 115 may be implemented as a firmware or software module executed by the processor 111. That is, for a more concise description, the cache manager 115 is shown as a separate component in Figure 2 However, some or all of the cache manager 115 may be included in one or more other components.

[0064] The storage controller 110 may communicate with the non-volatile memory device 120 through the non-volatile memory interface circuit 116. For example, the non-volatile memory interface circuit 116 may communicate with the non-volatile memory device 120 based on the NAND interface.

[0065] Figure 3 is a diagram showing a method of caching an address mapping table in the mapped data storage device of Figure 1 Referring to Figures 1 to 3 , the global address mapping table GAMT may include multiple address mapping tables AMT used in the storage device 100. For example, the multiple address mapping tables AMT included in the global address mapping table GAMT may represent the mapping information of all pages included in the first namespace NS1 to the nth namespace NSn.

[0066] In one or more embodiments, the capacity of an address mapping table AMT may be equal to the capacity of one page included in the non-volatile memory device 120. For example, the capacity of an address mapping table AMT may be approximately 4KB. However, the scope of the present disclosure is not limited thereto.

[0067] In one or more embodiments, each of the plurality of address mapping tables AMT may represent mapping information of a namespace. In other words, each of the plurality of address mapping tables AMT may represent mapping information for input / output operations of one host. For example, each of the plurality of address mapping tables AMT may include a plurality of address mapping entries of a namespace. For a more detailed example, the address mapping table AMT shown as diagonal stripes may represent mapping information of a plurality of pages included in the first namespace NS1; the address mapping table AMT shown as a grid may represent mapping information of a plurality of pages included in the second namespace NS2; and the address mapping table AMT shown as horizontal stripes may represent mapping information for a plurality of pages included in the nth namespace NSn. That is, hereinafter, it is assumed that one address mapping table AMT represents mapping information of a plurality of pages included in one namespace. A more detailed configuration of one address mapping table AMT will be described in more detail with reference to Figure 6 a more detailed configuration of one address mapping table AMT will be described in more detail.

[0068] The mapping data memory device 113 may cache some of the address mapping tables AMT included in the global address mapping table GAMT. For example, the mapping data memory device 113 may cache some of the address mapping tables AMT included in the global address mapping table GAMT such that the storage controller 110 performs input / output operations in response to input / output commands from the first host 11 to the nth host 1n.

[0069] In one or more embodiments, the capacity of the mapping data memory device 113 may be less than the total capacity of the address mapping tables AMT included in the global address mapping table GAMT. In other words, the mapping data memory device 113 may not store the entire global address mapping table GAMT.

[0070] Figure 4 is a diagram showing a method of partitioning Figure 1 the mapping data memory device. Referring to Figures 1 to 4 , the cache manager 115 may partition the mapping data memory device 113 into a plurality of cache regions of different types based on the cache allocation table CAT. For example, the cache manager 115 may partition the mapping data memory device 113 into a first dedicated cache region DCA1 to an nth dedicated cache region DCAn and a shared cache region SCA.

[0071] Each of the first dedicated cache area DCA1 to the n-th dedicated cache area DCAn may cache a plurality of address mapping tables AMT having one table type. For example, the first dedicated cache area DCA1 may exclusively cache a plurality of address mapping tables AMT having a first table type (i.e., the address mapping tables shown as diagonal stripes). In other words, the address mapping tables for performing input / output operations on namespaces other than the first namespace NS1 may not be cached in the first dedicated cache area DCA1. In a similar manner, the second dedicated cache area DCA2 to the n-th dedicated cache area DCAn may exclusively cache the address mapping tables for performing input / output operations on the second namespace NS2 to the n-th namespace NSn, respectively.

[0072] The capacities of the first dedicated cache area DCA1 to the n-th dedicated cache area DCAn may be different from each other. For example, the number of address mapping tables that can be stored in the second dedicated cache area DCA2 may be greater than the number of address mapping tables that can be stored in the first dedicated cache area DCA1. However, the scope of the present disclosure is not limited thereto.

[0073] In one or more embodiments, the capacities of some of the first dedicated cache area DCA1 to the n-th dedicated cache area DCAn may be '0'. In other words, the cache manager 115 may set the occupancy guarantee ratio of the mapping data storage device 113 of some hosts to "0". For example, the cache manager 115 may set the capacity of the third dedicated cache area DCA3 to "0". However, the scope of the present disclosure is not limited thereto.

[0074] In one or more embodiments, the first dedicated cache area DCA1 to the n-th dedicated cache area DCAn may be respectively used to guarantee the QoS of the first host 11 to the n-th host 1n. For example, even if input / output requests from the first host 11 occur at a high frequency, the address mapping table AMT for the input / output operations of the first host 11 may not be stored in the second dedicated cache area DCA2. Therefore, the address mapping table AMT for the input / output requests of the second host 12 may be sufficiently stored in the second dedicated cache area DCA2. In this case, when an input / output request from the second host 12 occurs, the possibility that the address mapping table for performing the input / output operation is cached in the mapping data storage device 113 (i.e., the possibility of a cache hit occurring) may increase.

[0075] The shared cache area SCA can cache multiple address mapping tables AMT, regardless of the table type. For example, some of the address mapping tables AMT cached in the shared cache area can be the address mapping tables AMT of the first namespace NS1; and others can be the address mapping tables AMT of the second namespace NS2. In other words, the table types of the address mapping tables AMT cached in the shared cache area SCA can be the same or different. That is to say, the shared cache area SCA can cache the address mapping tables of any namespace.

[0076] In one or more embodiments, if the first dedicated cache area DCA1 is in a full state (e.g., if the first dedicated cache area DCA1 is in a state where it no longer stores address mapping tables), the cache manager 115 can cache the address mapping table with the first table type (i.e., the address mapping table of the first namespace NS1) in the shared cache area SCA. Similarly, if the second dedicated cache area DCA2 is in a full state, the cache manager 115 can cache the address mapping table with the second table type (i.e., the address mapping table of the second namespace NS2) in the shared cache area SCA.

[0077] Figure 5 is shown in more detail Figure 2 of the cache allocation table. Referring to Figures 1 to 5 , the cache manager 115 can store the cache allocation table CAT. The cache manager 115 can manage the capacities of the first dedicated cache area DCA1 to the nth dedicated cache area DCAn and the shared cache area SCA based on the cache allocation table CAT. For example, the cache manager 115 can determine the capacity ratio of the mapped data memory device 113 for each of the first dedicated cache area DCA1 to the nth dedicated cache area DCAn and the shared cache area SCA based on the cache allocation table CAT.

[0078] In one or more embodiments, the capacity ratio of the mapped data memory device 113 of the dedicated cache area DCA can also be referred to as the occupancy guarantee ratio of the mapped data memory device 113 of the address mapping table of the namespace corresponding to the dedicated cache area DCA. For example, the capacity ratio of the mapped data memory device 113 of the first dedicated cache area DCA1 can also be referred to as the occupancy guarantee ratio of the mapped data memory device 113 of the address mapping table of the first namespace NS1. However, the scope of the present disclosure is not limited to this term.

[0079] The cache allocation table CAT can represent a table type of the address mapping table AMT that can be stored in each of the first dedicated cache area DCA1 to the nth dedicated cache area DCAn and the shared cache area SCA. For example, the cache allocation table CAT can represent a namespace identifier (NSID) corresponding to the address mapping table, and the address mapping table can be stored in each of the first dedicated cache area DCA1 to the nth dedicated cache area DCAn and the shared cache area SCA. For a more detailed example, the cache allocation table CAT can represent that the address mapping table corresponding to any NSID can be stored in the shared cache area SCA; and the address mapping table corresponding to the namespace identifier "1" (i.e., the address mapping table of the first namespace NS1) can be stored in the first dedicated cache area DCA1. Similarly, the cache allocation table CAT can represent the type of the address mapping table (e.g., the namespace identifier of the namespace) that can be stored in each of the second dedicated cache area DCA2 to the nth dedicated cache area DCAn.

[0080] The cache allocation table CAT can represent the capacity ratio of the mapped data memory device 113 allocated to each of the first dedicated cache area DCA1 to the nth dedicated cache area DCAn and the shared cache area SCA. For example, the cache allocation table CAT can represent that the capacity of the shared cache area SCA is 15% of the capacity of the mapped data memory device 113; and the capacity of the first dedicated cache area DCA1 is 20% of the capacity of the mapped data memory device 113. Similarly, the cache allocation table CAT can represent the capacity of each of the second dedicated cache area DCA2 to the nth dedicated cache area DCAn.

[0081] In one or more embodiments, the cache manager 115 can manage the sum of the capacity ratios of the mapped data memory device 113 allocated to each of the first dedicated cache area DCA1 to the nth dedicated cache area DCAn and the shared cache area SCA as 100%. For example, if the capacity of the first dedicated cache area DCA1 increases, the cache manager 115 can decrease the capacity of the shared cache area SCA. Conversely, if the capacity of the first dedicated cache area DCA1 decreases, the cache manager 115 can increase the capacity of the shared cache area SCA. However, the scope of the present disclosure is not limited thereto.

[0082] Figure 6 is shown in more detail Figure 3 of one of the address mapping tables. Refer to Figures 1 to 6, the address mapping table AMT may include a plurality of address mapping entries AME. For example, the address mapping table AMT may include a first address mapping entry AMEa to a fourth address mapping entry AMEd.

[0083] An address mapping table AMT may correspond to an address mapping table type. That is, an address mapping table AMT may correspond to a namespace (or a namespace identifier). For example, each of the plurality of address mapping entries AME included in an address mapping table AMT may represent mapping information of the same namespace. For a more detailed example, the first address mapping entry AMEa to the fourth address mapping entry AMEd may represent mapping information of different pages included in the first namespace NS1.

[0084] Each of the plurality of address mapping entries AME may represent a namespace identifier, a logical address, a physical address mapped to the namespace identifier and the logical address, and the validity of the mapping. For example, the first address mapping entry AMEa may represent that the mapping between the logical address '0x0000A1' and the physical address '0x0000F1' within the first namespace NS1 is valid. Similarly, the second address mapping entry AMEb may represent that the mapping between the logical address '0x0000A2' and the physical address '0x0000F2' within the first namespace NS1 is invalid. In this way, the plurality of address mapping entries AME included in a single address mapping table AMT may represent different mapping information of the same namespace.

[0085] In one or more embodiments, each of the plurality of address mapping entries AME may include an update flag bit. The update flag bit of each of the plurality of address mapping entries AME may indicate whether the address mapping entry AME cached in the mapping data storage device 113 has been changed after the time point when the address mapping table AMT from the global address mapping table GAMT is cached in the mapping data storage device 113. For example, if the third address mapping entry AMEc is changed (e.g., if the physical address or validity of the third address mapping entry AMEc is changed), the cache manager 115 may change the update flag bit of the third address mapping entry AMEc to 1.

[0086] In one or more embodiments, if the address mapping table AMT including the address mapping entry AME in which the update flag bit is set to "1" is deleted (i.e., uncached) from the mapping data storage device 113, the cache manager 115 may update the address mapping table corresponding to the uncached address mapping table among the plurality of address mapping tables AMT stored in the global address mapping table GAMT. The following will refer to Figure 12 and Figure 18The operation of the cache manager 115 based on the update flag is described in more detail.

[0087] Figures 7 to 9 is a diagram showing a method for a Figure 1 storage device according to one or more embodiments to perform input / output operations. Hereinafter, reference will be made to Figures 1 to 9 representatively describe the operation of the storage device 100 operating in response to an input / output request REQ_IO from the first host 11. However, the scope of the present disclosure is not limited thereto, and the storage device 100 may operate in a similar manner for the second host 12 to the nth host 1n.

[0088] First, referring to Figures 1 to 7 , the first host 11 can access the first namespace NS1 by sending a first input / output request REQ_IOa to the storage controller 110. In this case, the first input / output request REQ_IOa may include a namespace identifier "1" and a logical address "0x0000A4".

[0089] The first address mapping table AMT1 corresponding to the first input / output request REQ_IOa can be cached in the mapping data memory device 113. In this case, the storage controller 110 can identify the first address mapping table AMT1 based on the namespace identifier and the logical address included in the first input / output request REQ_IOa. For example, the storage controller 110 can identify the first address mapping table AMT1, and the first address mapping table AMT1 includes an address mapping entry AME corresponding to the namespace identifier "1" and the logical address "0x0000A4" in the mapping data memory device 113. In other words, a cache hit for the first input / output request REQ_IOa may occur.

[0090] In one or more embodiments, if the address mapping table AMT corresponding to the first input / output request REQ_IOa is cached in the mapping data memory device 113, the address mapping table AMT may be referred to as a "hit address mapping table". For example, the first address mapping table AMT1 may be referred to as a hit address mapping table.

[0091] The storage controller 110 can access the non-volatile memory device 120 based on the hit address mapping table. For example, if the first address mapping table AMT1 is referred to Figure 5For the described address mapping table AMT, the storage controller 110 can identify the physical address "0x0000F4" corresponding to the namespace identifier "1" and the logical address "0x0000A4" based on the fourth address mapping entry AMEd. In this case, the storage controller 110 can perform an input / output operation on the physical address '0x0000F4'. In other words, the storage controller 110 can program the data provided from the first host 11 at the physical address "0x0000F4", or can read the data stored at the physical address "0x0000F4".

[0092] On the other hand, referring to Figure 8 , the first host 11 can access the first namespace NS1 by sending a second input / output request REQ_IOb to the storage controller 110. In this case, the second input / output request REQ_IOb can include the namespace identifier "1" and the logical address "0x0000B2".

[0093] However, different from the description referred to above Figure 7 , the address mapping table AMT corresponding to the second input / output request REQ_IOb may not be cached in the mapping data storage device 113. For example, the address mapping table AMT including the address mapping entry AME corresponding to the namespace identifier "1" and the logical address "0x0000B2" may not be cached in the mapping data storage device 113. In other words, a cache miss of the second input / output request REQ_IOb may occur. In this case, the storage controller 110 may not access the non-volatile memory device 120.

[0094] Next, referring to Figure 9, the storage controller 110 may obtain an address mapping table AMT for the second input / output request REQ_IO b from the non-volatile memory device 120. For example, the cache manager 115 may read the address mapping table AMT from the global address mapping table GAMT, and the address mapping table AMT includes an address mapping entry AME corresponding to the namespace identifier "1" and the logical address "0x0000B2" included in the second input / output request REQ_IO b. Thereafter, the cache manager 115 may store the read address mapping table AMT in the mapped data memory device 113. In this case, the storage controller 110 may perform the input / output operation of the second input / output request REQ_IO b based on the address mapping table AMT for the second input / output request REQ_IO b stored in the mapped data memory device 113. For example, the storage controller 110 may perform an input / output operation on the physical address corresponding to the namespace identifier "1" and the logical address "0x0000B2".

[0095] In one or more embodiments, the cache manager 115 may store the address mapping table AMT read from the global address mapping table GAMT in a dedicated cache area DCA or a shared cache area SCA. For example, if the address mapping table AMT read from the global address mapping table GAMT corresponds to the first namespace NS1, the cache manager 115 may store the address mapping table AMT in the first dedicated cache area DCA1 or the shared cache area SCA.

[0096] In one or more embodiments, if the first dedicated cache area DCA1 is not in a full state, the cache manager 115 may store the address mapping table AMT read from the global address mapping table GAMT in the first dedicated cache area DCA1.

[0097] In one or more embodiments, if the first dedicated cache area DCA1 is not in a full state and the shared cache area SCA is not in a full state, the cache manager 115 may store the address mapping table AMT read from the global address mapping table GAMT in the shared cache area SCA.

[0098] In one or more embodiments, when both the first dedicated cache area DCA1 and the shared cache area SCA are in a full state, the cache manager 115 may delete one of the address mapping tables AMT stored in the first dedicated cache area DCA1, and then may store the address mapping table AMT read from the global address mapping table GAMT in the first dedicated cache area DCA1.

[0099] In one or more embodiments, the cache manager 115 may select and delete one of the plurality of address mapping tables AMT stored in the first dedicated cache area DCA1 based on the least recently used (LRU) algorithm. However, the scope of the present disclosure is not limited to a particular algorithm by which the cache manager 115 selects the address mapping table AMT to be deleted.

[0100] In one or more embodiments, the address mapping table AMT stored in the first dedicated cache area DCA1 that the cache manager 115 deletes may include an address mapping entry AME having an update flag bit of "1". In this case, the cache manager 115 may store the address mapping table AMT in the non-volatile storage device 120 before deleting the address mapping table AMT from the mapping data storage device 113.

[0101] That is, according to an embodiment of the present disclosure, if the address mapping table AMT corresponding to the input / output request provided from the host is cached in the mapping data storage device 113 (i.e., if a cache hit occurs), the storage controller 110 may immediately perform the input / output operation based on the cached address mapping table AMT. On the other hand, if the address mapping table AMT corresponding to the input / output request provided from the host is not cached in the mapping data storage device 113 (i.e., if a cache miss occurs), the storage controller 110 may perform the input / output operation after reading the address mapping table AMT from the global address mapping table GAMT. In this case, when a cache miss occurs, the time required to perform the input / output operation after receiving the input / output request from the host may be longer than the time when a cache hit occurs.

[0102] In one or more embodiments, as the number of address mapping tables AMT for the input / output operation of a specific host cached in the mapping data storage device 113 increases, the probability of a cache hit when an input / output request from the host occurs may increase. For example, as the number of address mapping tables AMT for the input / output operation of the first host 11 cached (i.e., the address mapping tables AMT of the first namespace NS1) increases, the probability that the storage device 100 will operate in the manner described above in response to an input / output request from the first host 11 may increase. In this case, the time required for the storage device 100 to perform the input / output operation in response to an input / output request from the first host 11 may be reduced. Figure 7 is a flowchart showing the operation of the storage controller that performs the input / output operation. Refer to

[0103] Figure 10 is a flowchart showing the operation of the storage controller that performs the input / output operation. Refer to Figure 1 the aboveFigures 1 to 10 , in operation S110, the storage controller 110 may receive an input / output request REQ_IO. For example, the storage controller 110 may receive an input / output request REQ_IO from one of the first host 11 to the nth host 1n through the host interface circuit 114. In this case, the input / output request REQ_IO may include a namespace identifier and a logical address.

[0104] In operation S120, the storage controller 110 may determine whether an address mapping table AMT corresponding to the input / output request REQ_IO exists in the mapped data storage device 113. For example, the cache manager 115 may determine whether an address mapping table AMT including an address mapping entry AME corresponding to the namespace identifier and the logical address included in the input / output request REQ_IO received previously in operation S110 is cached in the mapped data storage device 113.

[0105] If it is determined that the address mapping table AMT corresponding to the input / output request REQ_IO exists in the mapped data storage device 113, the following operation S150 may be executed. If it is determined that the address mapping table AMT corresponding to the input / output request REQ_IO does not exist in the mapped data storage device 113, the following operations S130 to S140 may be executed.

[0106] In operation S130, the storage controller 110 may read the address mapping table AMT corresponding to the input / output request REQ_IO from the non-volatile memory device 120. For example, the cache manager 115 may read the address mapping table AMT from the global address mapping table GAMT, and the address mapping table AMT includes an address mapping entry AME corresponding to the namespace identifier and the logical address included in the input / output request REQ_IO.

[0107] In operation S140, the storage controller 110 may store the read address mapping table AMT in the mapped data storage device 113. For example, the cache manager 115 may store the address mapping table AMT read previously through operation S130 in the mapped data storage device 113. Operation S140 will be described in more detail below with reference to Figure 11 and Figure 12 more specifically.

[0108] In operation S150, the storage controller 110 may perform an input / output operation based on the address mapping entry AME included in the address mapping table AMT. For example, the storage controller 110 may identify a physical address corresponding to the namespace identifier and the logical address included in the input / output request REQ_IO provided in operation S110 based on the address mapping entry AME included in the address mapping table AMT. Thereafter, the storage controller 110 may perform an input / output operation on the identified physical address.

[0109] Figure 11 is a flowchart that shows in more detail Figure 10 operation S140. Refer to Figures 1 to 11 , operation S140 may include the following operations S141 to S145.

[0110] In operation S141, the storage controller 110 may determine whether the corresponding dedicated cache area DCA is in a full state. For example, the cache manager 115 may determine whether the dedicated cache area DCA for the namespace corresponding to the input / output request REQ_IO of operation S110 (i.e., the namespace corresponding to the address mapping table AMT read in operation S130) is in a full state. For a more detailed example, if the namespace identifier "1" of the first namespace NS1 is included in the input / output request REQ_IO of the above operation S110 (i.e., if the address mapping table AMT read in the above operation S130 corresponds to the first namespace NS1), the cache manager 115 may determine whether more address mapping tables AMT can be stored in the first dedicated cache area DCA1.

[0111] If it is determined that the dedicated cache area DCA is in a full state, the following operation S142 may be performed, and if it is determined that the dedicated cache area DCA is not in a full state, the following operation S145 may be performed.

[0112] In operation S142, the storage controller 110 may determine whether the shared cache area SCA is in a full state. For example, the cache manager 115 may determine whether more address mapping tables AMT can be stored in the shared cache area SCA.

[0113] If it is determined that the shared cache area SCA is in a full state, the following operation S143 may be performed, and if it is determined that the shared cache area SCA is not in a full state, the following operation S144 may be performed.

[0114] In operation S143, the storage controller 110 may delete the victim address mapping table from the dedicated cache area DCA. For example, if the address mapping table AMT read in the above operation S130 corresponds to the first namespace NS1, the cache manager 115 may delete the victim address mapping table included in the first dedicated cache area DCA1. Thereafter, the first dedicated cache area DCA1 may not be in a full state.

[0115] In one or more embodiments, the address mapping table AMT deleted from the mapping data storage device 113 may be referred to as a 'victim address mapping table'.

[0116] In operation S144, the storage controller 110 may store the address mapping table AMT in the shared cache area SCA. For example, the cache manager 115 may store the address mapping table AMT previously read through operation S130 in the shared cache area SCA.

[0117] In operation S145, the storage controller 110 may store the address mapping table AMT in the dedicated cache area DCA. For example, if the address mapping table AMT read in the above operation S130 corresponds to the first namespace NS1, the cache manager 115 may store the address mapping table AMT previously read through operation S130 in the first dedicated cache area DCA1.

[0118] Figure 12 is shown in more detail Figure 11 Flowchart of operation S143. Refer to Figures 1 to 12 , operation S143 may include operations S143a to S143d.

[0119] In operation S143a, the cache manager 115 may select a victim address mapping table. For example, the cache manager 115 may select one of the multiple address mapping tables AMT stored in the first dedicated cache area DCA1 as the victim address mapping table.

[0120] In one or more embodiments, the cache manager 115 may select the victim address mapping table based on the LRU algorithm. For example, the cache manager 115 may select the address mapping table AMT that was used earliest for input / output operations as the victim address mapping table. However, the scope of the present disclosure is not limited to the specific manner in which the cache manager 115 selects the victim address mapping table.

[0121] In operation S143b, the cache manager 115 may determine whether the victim address mapping table is updated. For example, the cache manager 115 may determine whether one or more update flag bits among a plurality of address mapping entries AME included in the victim address mapping table are set to "1".

[0122] If it is determined that the victim address mapping table is updated, the following operation S143c may be performed, and if it is determined that the victim address mapping table is not updated, the following operation S143d may be performed.

[0123] In operation S143c, the cache manager 115 may update the global address mapping table GAMT based on the victim address mapping table. For example, the cache manager 115 may update one address mapping table AMT corresponding to the victim address mapping table among a plurality of address mapping tables AMT included in the global address mapping table GAMT based on the victim address mapping table. In this case, the global address mapping table GAMT may be synchronized with the victim address mapping table before the victim address mapping table is deleted.

[0124] In operation S143d, the cache manager 115 may delete the victim address mapping table from the dedicated cache area DCA. For example, the cache manager 115 may delete the victim address mapping table included in the first dedicated cache area DCA1.

[0125] Figure 13 and Figure 14 are diagrams showing operations of a storage device in response to requests from a supervisor according to one or more embodiments. Figure 1 of the supervisor.

[0126] First, referring to Figures 1 to 6 and Figure 13 , the supervisor SV may send a cache allocation table request REQ_CAT to the storage controller 110. In this case, the storage controller 110 may send the cache allocation table CAT managed by the cache manager 115 to the supervisor SV in response to the cache allocation table request REQ_CAT.

[0127] The supervisor SV may identify the capacity ratios of the mapped data storage devices 113 allocated to each of the shared cache area SCA and the first dedicated cache area DCA1 to the nth dedicated cache area DCAn based on the cache allocation table CAT.

[0128] In one or more embodiments, the supervisor SV may adjust the capacity ratio of the mapped data storage devices 113 allocated to the shared cache area SCA and each of the first dedicated cache areas DCA1 to the nth dedicated cache areas DCAn based on the QoS required by each of the first host 11 to the nth host 1n. This will be described in more detail below with reference to Figure 14 A method by which the supervisor SV adjusts the capacity ratio of the mapped data storage devices 113 allocated to the shared cache area SCA and each of the first dedicated cache areas DCA1 to the nth dedicated cache areas DCAn will be described in more detail.

[0129] Next, with reference to Figures 1 to 6 and Figure 14 , the supervisor SV may send an allocation ratio configuration request REQ_ARC to the storage controller 110. For example, the supervisor SV may request an adjustment to the capacity ratio of the mapped data storage device 113 allocated to the first dedicated cache area DCA1 through the allocation ratio configuration request REQ_ARC. For a more detailed example, the supervisor SV may request, through the allocation ratio configuration request REQ_ARC, to adjust the capacity ratio of the mapped data storage device 113 allocated to the first dedicated cache area DCA1 to 25%.

[0130] The storage controller 110 may update the cache allocation table CAT in response to the allocation ratio configuration request REQ_ARC. For example, the cache manager 115 may change the capacity ratio of the mapped data storage device 113 allocated to the first dedicated cache area DCA1 from 20% to 25%.

[0131] The cache manager 115 may decrease the capacity ratio of the mapped data storage device 113 allocated to the shared cache area SCA by the capacity ratio of the mapped data storage device 113 additionally allocated to the first dedicated cache area DCA1. For example, the cache manager 115 may change the capacity ratio of the mapped data storage device 113 allocated to the shared cache area SCA from 15% to 10%.

[0132] In one or more embodiments, if the storage controller 110 successfully updates the cache allocation table CAT in response to the allocation ratio configuration request REQ_ARC, the storage controller 110 may back up the updated cache allocation table CAT in the non-volatile memory device 120. In this case, even if the storage device 100 loses power, the storage controller 110 may restore the cache allocation table CAT. However, the scope of the present disclosure is not limited thereto.

[0133] In one or more embodiments, the storage controller 110 may not update the cache allocation table CAT according to the allocation ratio configuration request REQ_ARC. For example, a minimum limit (e.g., 10%) of the capacity ratio of the mapped data storage device 113 assigned to the shared cache area SCA may be predetermined. In this case, as the capacity ratio of the mapped data storage device 113 assigned to the first dedicated cache area DCA1 increases according to the allocation ratio configuration request REQ_ARC, if the capacity ratio of the mapped data storage device 113 assigned to the shared cache area SCA decreases to less than the predetermined minimum, the storage controller 110 may not update the cache allocation table CAT.

[0134] The storage controller 110 may send an allocation ratio configuration response RSP_ARC corresponding to the allocation ratio configuration request REQ_ARC to notify the supervisor SV whether the cache allocation table CAT has been updated based on the allocation ratio configuration request REQ_ARC. For example, the storage controller 110 may send an allocation ratio configuration response RSP_ARC indicating successful update of the cache allocation table CAT to the supervisor SV, or may send an allocation ratio configuration response RSP_ARC indicating failed update of the cache allocation table CAT to the supervisor SV.

[0135] In one or more embodiments, if the storage controller 110 sends an allocation ratio configuration response RSP_ARC indicating failed update of the cache allocation table CAT to the supervisor SV, the storage controller 110 may notify the supervisor SV of the reason for the failed update of the cache allocation table CAT. For example, the storage controller 110 may notify that the allocation ratio configuration request REQ_ARC requests an overly large allocation ratio.

[0136] In one or more embodiments, the supervisor SV may, in response to an allocation ratio configuration response RSP_ARC indicating failed update of the cache allocation table CAT, read the cache allocation table CAT from the storage controller 110 in the manner described above with reference to Figure 13 In this case, the supervisor SV may resend the allocation ratio configuration request REQ_ARC to the storage controller 110 based on the read cache allocation table CAT.

[0137] Figure 15 is a diagram showing more details of a method for updating a cache allocation table according to an embodiment of Figure 14 Referring to Figures 1 to 6 and Figures 14 to 15, the cache manager 115 may update the cache allocation table CAT in response to an allocation ratio configuration request REQ_ARC. For example, the cache manager 115 may increase the capacity ratio of the mapped data storage device 113 allocated to the first dedicated cache area DCA1 and may decrease the capacity ratio of the mapped data storage device 113 allocated to the shared cache area SCA. In other words, the cache manager 115 may switch the conversion area CVA, which is part of the shared cache area SCA, to be part of the first dedicated cache area DCA1. That is, in response to the allocation ratio configuration request REQ_ARC, the cache manager 115 may change the conversion area CVA from the shared cache area SCA to the first dedicated cache area DCA1.

[0138] In one or more embodiments, the address mapping table AMT included in the conversion area CVA may correspond to a namespace different from the namespace of the first dedicated cache area DCA1. For example, the address mapping table AMT included in the conversion area CVA may be the address mapping table of the third namespace NS3 instead of the address mapping table of the first namespace NS1. In this case, only the address mapping table of the first namespace NS1 may be stored in the first dedicated cache area DCA1, such that the address mapping table AMT included in the conversion area CVA may not be stored in the first dedicated cache area DCA1.

[0139] Hereinafter, for more concise description, the address mapping table (i.e., the address mapping table corresponding to another namespace) that may not be stored in the dedicated cache area DCA extended in response to the allocation ratio configuration request REQ_ARC among the address mapping tables included in the conversion area CVA may be referred to as the range over address mapping table AMT_RO.

[0140] In one or more embodiments, before updating the cache allocation table CAT, it may be necessary to delete the range over address mapping table AMT_RO from the conversion area CVA. For example, the method of deleting the range over address mapping table AMT_RO will be described in more detail below with reference to Figure 17 and Figure 18 the method of deleting the range over address mapping table AMT_RO will be described in more detail below with reference to

[0141] Figure 16 is a flowchart showing the operations of the storage controller operating in response to Figure 14 the allocation ratio configuration request. Referring to Figures 1 to 6 and Figures 14 to 16 , in operation S210, the storage controller 110 may receive an allocation ratio configuration request REQ_ARC from the supervisor SV.

[0142] In operation S220, the storage controller 110 may determine whether the requested allocation ratio is appropriate. For example, if the capacity ratio of the mapped data storage device 113 allocated to the shared cache area SCA in response to the allocation ratio configuration request REQ_ARC decreases to less than a predetermined minimum limit as the capacity ratio of the mapped data storage device 113 allocated to the first dedicated cache area DCA1 increases, the cache manager 115 may determine that the requested allocation ratio is inappropriate (i.e., too large).

[0143] If it is determined that the requested allocation ratio is appropriate, the following operations S230 and S240 may be performed. If the requested allocation ratio is determined to be inappropriate, the following operation S250 may be performed.

[0144] In operation S230, the storage controller 110 may update the cache allocation table CAT in response to the allocation ratio configuration request REQ_ARC. For example, in response to the allocation ratio configuration request REQ_ARC, the cache manager 115 may change the capacity ratio of the mapped data storage device 113 allocated to the dedicated cache area DCA and the shared cache area SCA.

[0145] In operation S240, the storage controller 110 may send an allocation ratio configuration response RSP_ARC indicating successful configuration in response to the allocation ratio configuration request REQ_ARC to the supervisor SV.

[0146] In operation S250, the storage controller 110 may send an allocation ratio configuration response RSP_ARC indicating configuration failure in response to the allocation ratio configuration request REQ_ARC to the supervisor SV.

[0147] Figure 17 is a flowchart showing operation S230 in more detail. Referring to Figure 16 and Figures 1 to 6 and Figures 14 to 17 operation S230 may include the following operations S231 to S233.

[0148] In operation S231, the cache manager 115 may determine whether a roaming address mapping table AMT_RO has occurred. For example, the cache manager 115 may identify, in the address mapping table included in the conversion area CVA determined based on the allocation ratio configuration request REQ_ARC, an address mapping table that may not be stored in the dedicated cache area DCA extended in response to the allocation ratio configuration request REQ_ARC (i.e., the address mapping table corresponding to another namespace).

[0149] If it is determined that the roaming address mapping table AMT_RO has occurred, the following operation S232 can be executed, and if it is determined that the roaming address mapping table AMT_RO has not occurred, the following operation S233 can be executed.

[0150] In operation S232, the cache manager 115 can delete the roaming address mapping table AMT_RO. For example, the cache manager 115 can delete the roaming address mapping table AMT_RO from the mapping data storage device 113.

[0151] In operation S233, the cache manager 115 can update the cache allocation table CAT in response to the allocation ratio configuration request REQ_ARC. For example, in response to the allocation ratio configuration request REQ_ARC, the cache manager 115 can change the capacity ratio of the mapping data storage device 113 allocated to the dedicated cache area DCA and the shared cache area SCA.

[0152] Figure 18 is a flowchart showing operation S232 in more detail. Refer to Figure 17 and Figures 1 to 6 and Figures 14 to 18 Operation S232 may include the following operations S232a to S232c.

[0153] In operation S232a, the cache manager 115 can determine whether the roaming address mapping table AMT_RO has been updated. For example, the cache manager 115 can determine whether one or more update flag bits included in the multiple address mapping entries AME in the roaming address mapping table AMT_RO are set to "1".

[0154] If it is determined that the roaming address mapping table AMT_RO has been updated, the following operation S232b can be executed, and if it is determined that the roaming address mapping table AMT_RO has not been updated, the following operation S232c can be executed.

[0155] In operation S232b, the cache manager 115 can update the global address mapping table GAMT based on the roaming address mapping table AMT_RO. For example, the cache manager 115 can update one address mapping table AMT corresponding to the roaming address mapping table AMT_RO among the multiple address mapping tables AMT included in the global address mapping table GAMT based on the address range mapping table AMT_RO. In this case, before deleting the roaming address mapping table AMT_RO, the global address mapping table GAMT can be synchronized with the roaming address mapping table AMT_RO.

[0156] In operation S232c, the cache manager 115 may delete the roaming address mapping table AMT_RO from the mapped data storage device 113. For example, the cache manager 115 may delete the roaming address mapping table AMT_RO from the translation area CVA.

[0157] Figure 19 is a diagram showing the operation of a Figure 1 storage system according to one or more embodiments. Referring to Figures 1 to 19 , the supervisor SV may commonly set the allocation ratio of the mapped data storage device 113 for each of the shared cache area SCA and the first dedicated cache area DCA1 to the nth dedicated cache area DCAn. For example, the supervisor SV may send an allocation ratio batch configuration request REQ_ARBC to the storage controller 110.

[0158] The storage controller 110 may update the cache allocation table CAT in response to the allocation ratio batch configuration request REQ_ARBC. For a more concise description, an embodiment in which the supervisor SV commonly sets the allocation ratio of the mapped data storage device 113 for each of the shared cache area SCA and the first dedicated cache area DCA1 to the nth dedicated cache area DCAn is representatively described in Figure 19 , but the scope of the present disclosure is not limited thereto. For example, the supervisor SV may issue an allocation ratio batch configuration request REQ_ARBC to commonly set the allocation ratio of the mapped data storage device 113 for two or more of the shared cache area SCA and the first dedicated cache area DCA1 to the nth dedicated cache area DCAn.

[0159] Although the present disclosure has been specifically shown and described with reference to embodiments of the present disclosure, it should be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A storage device configured to communicate with a first host, a second host, and a supervisor, the storage device comprising: A non-volatile memory device including a first namespace allocated for the first host, a second namespace allocated for the second host, and a plurality of address mapping tables; And A storage controller configured to, based on the plurality of address mapping tables: Access the first namespace based on an input / output request from the first host; And Access the second namespace based on an input / output request from the second host, Wherein the storage controller includes a first dedicated cache area, and the first dedicated cache area is partitioned to cache the address mapping tables of a first table type corresponding to the first namespace among the plurality of address mapping tables.

2. The storage device according to claim 1, wherein, The storage controller further includes a shared cache area, and the shared cache area is partitioned to cache one or more address mapping tables among the plurality of address mapping tables having different table types from each other.

3. The storage device according to claim 2, wherein, The capacity of the first dedicated cache area is determined based on a first allocation ratio configuration request provided by the supervisor.

4. The storage device according to claim 3, wherein, The capacity of the shared cache area is determined based on the capacity of the first dedicated cache area.

5. The storage device according to claim 2, wherein, The storage controller is further configured to: Based on a first input / output request provided by the first host and including a first logical address, perform a first input / output operation on the non-volatile memory device based on a first address mapping entry of the first logical address cached in the first dedicated cache area or the shared cache area.

6. The storage device according to claim 5, wherein, The storage controller is further configured to: Read a first address mapping table including the first address mapping entry from the non-volatile memory device, and store the first address mapping table in the storage controller based on the first address mapping entry not being in the first dedicated cache area and the shared cache area.

7. The storage device according to claim 6, wherein, The storage controller is further configured to: Based on the first dedicated cache area not being full, store the first address mapping table in the first dedicated cache area; Based on the first dedicated cache area being full and the shared cache area not being full, store the first address mapping table in the shared cache area; And After deleting a second address mapping table in the first dedicated cache area based on the first dedicated cache area and the shared cache area being full, store the first address mapping table in the first dedicated cache area.

8. The storage device according to claim 7, wherein The storage controller is further configured to: Update the second address mapping table in the non-volatile memory device based on the second address mapping table being updated after a first time point when the second address mapping table is cached in the first dedicated cache area.

9. The storage device according to claim 1, wherein, The capacity of each address mapping table among the plurality of address mapping tables is the same as the capacity of a unit page of the non-volatile memory device.

10. A storage controller configured to control a non-volatile memory device including a first namespace and a second namespace, the storage controller comprising: A mapping data memory device including: A first dedicated cache area storing a first plurality of address mapping tables of the first namespace; and A second dedicated cache area storing a second plurality of address mapping tables of the second namespace; and A cache manager, configured to manage the capacity of each of a first dedicated cache area and a second dedicated cache area.

11. The storage controller according to claim 10, wherein: A first address mapping table among the first plurality of address mapping tables includes a first plurality of address mapping entries that map physical addresses and logical addresses of a first plurality of pages in a first namespace; And A second address mapping table among the second plurality of address mapping tables includes a second plurality of address mapping entries that map physical addresses and logical addresses of a second plurality of pages in a second namespace.

12. The storage controller according to claim 10, wherein, The mapping data storage device further includes: A shared cache area, configured to store a third plurality of address mapping tables of the first namespace and a fourth plurality of address mapping tables of the second namespace.

13. The storage controller according to claim 12, wherein: A third address mapping table among the third plurality of address mapping tables includes a third plurality of address mapping entries that map physical addresses and logical addresses of a third plurality of pages in the first namespace; And A fourth address mapping table among the fourth plurality of address mapping tables includes a fourth plurality of address mapping entries that map physical addresses and logical addresses of a fourth plurality of pages in the second namespace.

14. The storage controller according to claim 12, wherein, The cache manager is further configured to convert a first conversion area, which is part of the shared cache area, into a first dedicated cache area based on a first allocation ratio configuration request from an external device.

15. The storage controller according to claim 14, wherein, The cache manager is further configured to store an address range mapping table, which is in the first conversion area and corresponds to a second namespace in the non-volatile memory device.

16. The storage controller according to claim 12, wherein, The cache manager is further configured to perform a first input / output operation on the non-volatile memory device based on a first input / output request including a first logical address of the first namespace provided by an external device and based on a first address mapping entry of the first logical address stored in the mapping data storage device.

17. The storage controller according to claim 16, wherein, The cache manager is further configured to: Based on the first address mapping entry not being in the first plurality of address mapping tables and the third plurality of address mapping tables, read a fifth address mapping table including the first address mapping entry from the non-volatile memory device and store the fifth address mapping table in the mapping data storage device.

18. The storage controller according to claim 17, wherein, The cache manager is configured to: Based on the first dedicated cache area not being full, store the fifth address mapping table in the first dedicated cache area; Based on the first dedicated cache area being full and the shared cache area not being full, store the fifth address mapping table in the shared cache area; And Based on the first dedicated cache area and the shared cache area being full, after deleting a sixth address mapping table that is one of the first plurality of address mapping tables, store the fifth address mapping table in the first dedicated cache area.

19. A storage device, configured to communicate with a first host and a second host, the storage device includes: A non-volatile memory device configured to store a global address mapping table, the global address mapping table including a first plurality of address mapping tables and a second plurality of address mapping tables corresponding to a first host and a second host, respectively; and a storage controller including: a mapping data memory device configured to cache at least one of the first plurality of address mapping tables or the second plurality of address mapping tables; and a cache manager configured to manage a first occupancy guarantee ratio of the first plurality of address mapping tables of the mapping data memory device.

20. The storage device according to claim 19, wherein: the mapping data memory device includes a first dedicated cache area corresponding to the first occupancy guarantee ratio, and the first dedicated cache area is configured to exclusively cache the first plurality of address mapping tables among the first plurality of address mapping tables and the second plurality of address mapping tables.

Images