Watchdog device and monitoring method

Abstract

The invention relates to a watchdog device and a monitoring method. The watchdog device comprises a system chip, a dog feeding path, a reset circuit and a watchdog chip, a first input / output interface on the system chip is connected with a watchdog chip based on a dog feeding path; the reset circuit is respectively connected with a first reset interface on the system chip and a second reset interface of the watchdog chip; wherein the reset circuit is used for controlling an access between a first reset interface on a system chip and a second reset interface of a watchdog chip to be in a disconnected state in the power-on starting process of the system chip and the watchdog chip; the reset circuit is further used for controlling a path between the first reset interface on the system chip and the second reset interface of the watchdog chip to be in a connected state after the system chip and the watchdog chip are powered on and started. The watchdog device can accurately monitor the running state of the system chip, and can improve the running stability of the system chip.

Description

Technical Field

[0001] This application relates to the technical field of battery management systems, and particularly to a watchdog device and a monitoring method. Background Art

[0002] With the development of green energy, rechargeable batteries are used in more and more scenarios, and the number of required batteries is also increasing, which has led to a sharp increase in the complexity of battery management systems. As a result, multi-core system chips with operating systems are applied to battery management systems, and it is very important to ensure the stable operation of the entire system.

[0003] In related technologies, complex systems of core chips are prone to crashing and freezing during operation due to chip mechanisms, software, external interference, etc. Therefore, it is necessary to add a monitoring mechanism to ensure the stable and reliable operation of the system, and to reset the core chip in a timely manner when the system fails, power it on again to start and rectify the system, and avoid system freezing, so as to ensure the stable operation of the system. Currently, software watchdogs are usually used to monitor the stable operation of core chips.

[0004] However, the monitoring effect of software watchdogs is not good, resulting in low operating stability of the system. Summary of the Invention

[0005] Based on this, in view of the above technical problems, it is necessary to provide a watchdog device and a monitoring method, which can improve the system operation stability of system chips and the monitoring effect of the watchdog device.

[0006] In a first aspect, this application provides a watchdog device, which includes: a system chip, a dog-feeding path, a reset circuit, and a watchdog chip; a first input / output interface on the system chip is connected to the watchdog chip based on the dog-feeding path; the reset circuit is respectively connected to a first reset interface on the system chip and a second reset interface of the watchdog chip;

[0007] Wherein, the reset circuit is configured to control the path between the first reset interface on the system chip and the second reset interface of the watchdog chip to be in an open state during the power-on startup process of the system chip and the watchdog chip;

[0008] The reset circuit is further configured to control the path between the first reset interface on the system chip and the second reset interface of the watchdog chip to be in a connected state after the system chip and the watchdog chip are powered on and started up.

[0009] In some of these embodiments, the reset circuit includes: a reset path and a switching circuit; the reset path is disposed between a first reset interface on the system-on-chip and a second reset interface of the watchdog chip, and the switching circuit is connected to the reset path;

[0010] Wherein, the switching circuit is configured to control the reset path to be in an open state during the power-on startup process of the system-on-chip and the watchdog chip;

[0011] The switching circuit is further configured to control the reset path to be in a connected state after the system-on-chip and the watchdog chip are powered on and started up.

[0012] In some of these embodiments, the reset path includes a first MOS transistor, a first pull-up resistor, and a second pull-up resistor; one end of the first pull-up resistor is connected to a first power supply, the other end of the first pull-up resistor is respectively connected to the first reset interface and the drain of the first MOS transistor, the source of the first MOS transistor is respectively connected to one end of the second pull-up resistor and the second reset interface, and the other end of the second pull-up resistor is connected to the first power supply; the gate of the first MOS transistor is connected to the switching circuit;

[0013] Wherein, the switching circuit is specifically configured to control the first MOS transistor to disconnect the reset path during the power-on startup process of the system-on-chip and the watchdog chip;

[0014] The switching circuit is further configured to control the first MOS transistor to connect the reset path after the system-on-chip and the watchdog chip are powered on and started up.

[0015] In some of these embodiments, the switching circuit includes: a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a diode, a third pull-up resistor, a fourth pull-up resistor, a fifth pull-up resistor, a first resistor, a second resistor, and a third resistor;

[0016] Wherein, the source of the second MOS transistor is connected to one end of the third pull-up resistor, the other end of the third pull-up resistor is connected to a second power supply, the drain of the second MOS transistor is connected to the gate of the first MOS transistor, and the gate of the second MOS transistor is respectively connected to one end of the fourth pull-up resistor, one end of the diode, the drain of the third MOS transistor, and one end of the first resistor;

[0017] The other end of the fourth pull-up resistor is connected to the second power supply. The other end of the diode is connected to the second input / output interface on the system chip. The source of the third MOS transistor is grounded. The other end of the first resistor is connected to the gate of the fourth MOS transistor. The source of the fourth MOS transistor is connected to the fifth pull-up resistor. The drain of the fourth MOS transistor is respectively connected to one end of the second resistor and the third resistor. The other end of the second resistor is connected to the gate of the third MOS transistor. The other end of the third resistor is connected to the source of the third MOS transistor.

[0018] In some embodiments, the watchdog device further includes: a power control circuit; the power control circuit is respectively connected to the third input / output interface on the system chip, the chip power supply, and the power interface on the watchdog chip;

[0019] Wherein, the power control circuit is used to control the watchdog chip to power on and start after the system chip powers on and starts.

[0020] In some embodiments, the power control circuit includes a fifth MOS transistor, a sixth MOS transistor, and a pull-down resistor; the source of the fifth MOS transistor is connected to the chip power supply, and the drain of the fifth MOS transistor is connected to the power interface on the watchdog chip; the gate of the fifth MOS transistor is connected to the drain of the sixth MOS transistor, the gate of the sixth MOS transistor is respectively connected to the third input / output interface on the system chip and the pull-down resistor, and the source of the sixth MOS transistor is grounded.

[0021] In some embodiments, the watchdog device further includes: a shielding circuit; the shielding circuit is connected to the enable interface on the watchdog chip;

[0022] Wherein, the shielding circuit is used to control the watchdog chip to turn off the monitoring function when an external shielding signal is triggered.

[0023] In some embodiments, the shielding circuit includes a seventh MOS transistor, a fourth resistor, a fifth resistor, and a second pull-down resistor; the gate of the seventh MOS transistor is connected to one end of the fourth resistor, the source of the seventh MOS transistor is respectively connected to one end of the fifth resistor and the enable interface on the watchdog chip, and the drain of the seventh MOS transistor is grounded;

[0024] The other end of the fourth resistor is respectively connected to the second pull-down resistor and the external signal input port interface; the other end of the fifth resistor is connected to the chip power supply.

[0025] In a second aspect, the present application further provides a monitoring method, which is applied to the watchdog device described in the first aspect above. The method includes:

[0026] Control the power-on startup of the system chip and the watchdog chip in the watchdog device;

[0027] During the power-on startup process of the system chip and the watchdog chip in the watchdog device, control the path between the first reset interface on the system chip and the second reset interface on the watchdog chip to be in a disconnected state;

[0028] After the system chip and the watchdog chip are powered on and started, control the path between the first reset interface on the system chip and the second reset interface on the watchdog chip to be in a connected state.

[0029] In some embodiments, the controlling the power-on startup of the system chip and the watchdog chip in the watchdog device includes:

[0030] Control the power-on startup of the system chip in the watchdog device;

[0031] After the system chip is powered on and started, control the path between the chip power supply and the watchdog chip to be in a connected state, so that the chip power supply powers the watchdog chip for power-on startup.

[0032] In a third aspect, the present application further provides a monitoring device, the monitoring device includes:

[0033] A first control module, configured to control the power-on startup of the system chip and the watchdog chip in the watchdog device;

[0034] A second control module, configured to control the path between the first reset interface on the system chip and the second reset interface on the watchdog chip to be in a disconnected state during the power-on startup process of the system chip and the watchdog chip in the watchdog device;

[0035] A third control module, configured to control the path between the first reset interface on the system chip and the second reset interface on the watchdog chip to be in a connected state after the system chip and the watchdog chip are powered on and started.

[0036] In a fourth aspect, the present application further provides a computer device, including a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, the following steps are implemented:

[0037] Control the power-on startup of the system chip and the watchdog chip in the watchdog device;

[0038] During the power-on startup process of the system chip and the watchdog chip in the watchdog device, control the path between the first reset interface on the system chip and the second reset interface on the watchdog chip to be in a disconnected state;

[0039] After the system chip and the watchdog chip are powered on and started up, control the path between the first reset interface on the system chip and the second reset interface on the watchdog chip to be in a connected state.

[0040] In a fifth aspect, the present application also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0041] Control the system chip and the watchdog chip in the watchdog device to be powered on and started up;

[0042] During the power-on startup process of the system chip and the watchdog chip in the watchdog device, control the path between the first reset interface on the system chip and the second reset interface on the watchdog chip to be in a disconnected state;

[0043] After the system chip and the watchdog chip are powered on and started up, control the path between the first reset interface on the system chip and the second reset interface on the watchdog chip to be in a connected state.

[0044] In a sixth aspect, the present application also provides a computer program product, including a computer program, and when the computer program is executed by a processor, the following steps are implemented:

[0045] Control the system chip and the watchdog chip in the watchdog device to be powered on and started up;

[0046] During the power-on startup process of the system chip and the watchdog chip in the watchdog device, control the path between the first reset interface on the system chip and the second reset interface on the watchdog chip to be in a disconnected state;

[0047] After the system chip and the watchdog chip are powered on and started up, control the path between the first reset interface on the system chip and the second reset interface on the watchdog chip to be in a connected state.

[0048] The above watchdog device and monitoring method set a reset circuit between the system chip and the watchdog chip, and use this reset circuit to control the reset path between the system chip and the watchdog chip, so that the path between the system chip and the watchdog chip is always in a disconnected state during the power-on startup process of the system chip and the watchdog chip. In this case, even if the watchdog chip outputs a reset signal, the reset signal cannot be transmitted to the system chip, thus affecting the normal operation of the system chip, and the stability of the system chip operation can be improved. In addition, this reset circuit can also be used to control the reset path between the system chip and the watchdog chip, so that the path between the system chip and the watchdog chip is always in a connected state after the system chip and the watchdog chip are powered on and started. In this case, the reset signal output by the watchdog chip can be accurately transmitted to the system chip, enabling the system chip to be reset and run in time when the dog feeding times out, ensuring the stable operation of the system chip and improving the operation performance of the system chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following will briefly introduce the drawings required for use in the description of the embodiments of the present application or related technologies. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0050] Figure 1 One of the structural schematic diagrams of the watchdog device in some embodiments;

[0051] Figure 2 Another structural schematic diagram of the watchdog device in some embodiments;

[0052] Figure 3 Another structural schematic diagram of the watchdog device in some embodiments;

[0053] Figure 4 Another structural schematic diagram of the watchdog device in some embodiments;

[0054] Figure 5 Another structural schematic diagram of the watchdog device in some embodiments;

[0055] Figure 6 Another structural schematic diagram of the watchdog device in some embodiments;

[0056] Figure 7 One of the flow schematic diagrams of the monitoring method in some embodiments;

[0057] Figure 8 Another flow schematic diagram of the monitoring method in some embodiments;

[0058] Figure 9 Structural block diagram of a monitoring device in some embodiments;

[0059] Explanation of reference numerals:

[0060] 10, system-on-chip; 20, watchdog path; 30, reset circuit; 40, watchdog chip; 50, power control circuit; 60, shielding circuit; 101, first input / output interface; 102, second input / output interface; 103, third input / output interface; 104, first reset interface; 301, reset path; 302, switch circuit; 3011, first MOS transistor; 3012, first pull-up resistor; 3013, second pull-up resistor; 3021, second MOS transistor; 3022, third MOS transistor; 3023, fourth MOS transistor; 3024, diode; 3025, third pull-up resistor; 3026, fourth pull-up resistor; 3027, fifth pull-up resistor; 3028, first resistor; 3029, second resistor; 3030, third resistor; 401, second reset interface; 402, watchdog signal receiving interface; 403, power interface; 404, enable interface; 501, fifth MOS transistor; 502, sixth MOS transistor; 503, first pull-down resistor; 601, seventh MOS transistor; 602, fourth resistor; 603, fifth resistor; 604, second pull-down resistor; 605, external signal input interface. Detailed implementation manners

[0061] In the embodiments of the present application, the term "and / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after.

[0062] In the embodiments of the present application, the term "plurality" refers to two or more, and other quantifiers are similar thereto.

[0063] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0064] With the development of green energy, the usage scenarios of rechargeable batteries are increasing, and the number of required batteries is also increasing, resulting in a sharp increase in the complexity of the battery management system. Therefore, multi-core processing chips with operating systems are applied to the battery management system, and it is necessary to ensure the stable operation of the entire system. Among them, the commonly used watchdog circuit is used to monitor the stable operation of the core chip. In related technologies, the three-level architecture is the most common in energy storage battery management systems; the top layer is the Battery Array Management Unit (BAU), which undertakes the external connection, communication, calculation, and coordination of the entire system; within the cluster is the Battery Cluster Management Unit (BCU), which undertakes functions such as data acquisition, calculation, interface, and execution within the cluster; the bottom layer is the Battery Management Unit (BMU), which mainly undertakes functions such as sampling or processing of cell voltage, cell temperature, etc.; in the three-level architecture battery management system (Battery Management System, BMS), due to the requirements of functions such as communication, data recording, and external interaction of the BAU, a relatively high computing power is required. Usually, a System on Chip (SOC) is used and a software operating system is used to facilitate calculation and interaction of information. The complex SOC system is prone to crashing and freezing during operation due to the influence of chip mechanisms, software, external interference, etc. Therefore, a monitoring mechanism needs to be added to ensure the stable and reliable operation of the system, and when the system fails, the SOC is reset in time, the entire system is restarted by powering on again, and the BAU is prevented from being stuck in a certain process.Based on this problem, the currently more common solution is that the SOC chip comes with a hardware watchdog function module, and the monitoring function is realized through the parameters of the software watchdog. However, there are certain risks associated with the software watchdog, including system operation dependence risk, clock path dependence risk, being shut down risk, and being maliciously tampered with risk. Among them, the system operation dependence risk is that the operation of the software watchdog depends on the normal operation environment of the system. If the system encounters strong interference, it may cause the program to get out of control or enter an infinite loop. At this time, the software watchdog may not work properly and cannot detect the abnormality of the SOC in time, so as to perform a reset operation. As a result, the BAU may be in a fault state for a long time. The clock path dependence risk is that the timing of the software watchdog usually depends on the system clock. If the system clock fails or is interfered, resulting in unstable clock frequency or even stop working, the software watchdog will deviate or stop, and thus cannot accurately judge the timeout. As a result, the BAU may be in a fault state for a long time. The risk of being shut down is that the power-on startup and control of the software watchdog are both realized through software. Malicious code or program errors may shut down the software watchdog, and ultimately may also cause the BAU to be in a fault state for a long time. The risk of being maliciously tampered with is that the dog-feeding logic of the software watchdog is controlled by software. If the dog-feeding logic is maliciously tampered with, it may cause the watchdog to not work properly, and ultimately may also cause the BAU to be in a fault state for a long time. In summary, the current method of using a software watchdog to monitor the SOC system has the problem of poor monitoring effect, resulting in low operating stability of the SOC.

[0065] In view of this, the embodiments of the present application propose a watchdog device and a monitoring method. By locking the conduction of the reset signal before each power-on startup of the SOC operating system and completing the conduction of the reset signal after each power-on startup of the SOC operating system, and no longer being interfered by the level, the monitoring effect on the SOC system can be improved, and to a certain extent, the operating stability of the SOC operating system can be improved.

[0066] It should be noted that the beneficial effects or the technical problems solved by the embodiments of the present application are not limited to this one, and there may be other implicit or related problems. For specific details, please refer to the description of the following embodiments.

[0067] In some embodiments, such as Figure 1As shown in the figure, a watchdog device is provided, which includes: a system chip 10, a dog feeding path 20, a reset circuit 30, and a watchdog chip 40; a first input / output interface 101 on the system chip 10 is connected to the watchdog chip 40 based on the dog feeding path 20; the reset circuit 30 is respectively connected to a first reset interface 104 on the system chip 10 and a second reset interface 401 of the watchdog chip 40; wherein, the reset circuit 30 is used to control the path between the first reset interface 104 on the system chip 10 and the second reset interface 401 of the watchdog chip 40 to be in a disconnected state before the system chip 10 and the watchdog chip 40 are powered on and started, and during the power-on and startup process of the system chip 10 and the watchdog chip 40;

[0068] The reset circuit 30 is further used to control the path between the first reset interface 104 on the system chip 10 and the second reset interface 401 of the watchdog chip 40 to be in a connected state after the system chip 10 and the watchdog chip 40 are powered on and started.

[0069] Among them, the system chip 10 is an SOC chip, and this SOC chip is applied to the battery management system BMS. The SOC chip is a highly integrated chip that integrates an electronic system that originally required multiple independent chips into a single chip. The chip internally includes a processor core, a storage unit, input / output interfaces, and various dedicated functional modules, and it is a complex system that tightly combines hardware and software to achieve specific functions. The SOC chip includes multiple domains. For example, the SOC chip includes an RTC domain, an SFT domain, and an AP domain. Among them, the RTC domain is used to control the power-on and startup of the entire system; the AP domain is an A55 processor of the ARM core for application program processing. The main operating system of the SOC runs in the AP domain, but the power-on and startup time of the AP domain is relatively long. From the time when the RTC domain starts to supply power to the time when the AP is fully powered on and started to the time when the general-purpose input / output interface (General Purpose Input / Output, GPIO) of the AP domain can be operated, it takes about 20s. It is precisely because the power-on and startup duration of the AP domain on the SOC chip is relatively long that during this period, if the watchdog used to monitor the operation of the SOC system outputs a reset signal to the SOC, causing it to reset, the SOC system cannot operate normally. A corresponding nRESET interface is set in the RTC domain of the SOC chip, and interfaces such as GPIO84, GPIO85, and GPIO131 are set in the AP domain of the SOC chip.

[0070] The above watchdog chip 40 includes multiple functional pins, that is, multiple functional interfaces. Among them, VCC is its power supply pin, which is used to connect to an external chip power supply (SYS_3V3) to supply power to the watchdog chip; nMR is the manual reset pin, and nRESET is the reset signal output pin. When nMR is pulled low, nRESET will also be pulled low. When the chip is under-voltage, or the watchdog chip times out, or during the power-on process of the watchdog chip, a reset signal will be generated at the nRESET pin; WDI is the input pin of the watchdog chip, which is used to receive the dog-feeding signal sent by the SOC chip, and nWDO is the output pin of the watchdog chip. When it is detected that no valid dog-feeding signal sent by the SOC is received at the WDI pin within the set time, nWDO will output a low-level pulse. The SET pin is the enable control pin of the watchdog. When the level of the SET pin is high, the watchdog is enabled. When the level of the SET pin is low, the monitoring function of the watchdog is prohibited.

[0071] The above dog-feeding path 20 is set between the system chip 10 and the watchdog chip 40, and is used to connect the input / output interface of the dog-feeding signal on the system chip 10 and the dog-feeding signal receiving interface 402 on the watchdog chip 40. After the AP domain on the system chip 10 is powered on, the dog-feeding operation will be performed based on the dog-feeding path 20 under the software control of the operating system. Specifically, the first input / output interface on the system chip 10 can output a dog-feeding signal, and send the dog-feeding signal to the watchdog chip 40 through the dog-feeding path 20. The watchdog chip 40 receives the dog-feeding signal on WDI to implement the dog-feeding operation. Among them, the dog-feeding signal is a periodically switched high and low level. For example, initially output a high level for 10 ms, then switch to output a low level for 10 ms, and then switch to output a high level for 10 ms, and so on in a cycle. Each time the high level switches to the low level will be regarded as a valid dog-feeding signal. The design of the watchdog chip is that a valid dog-feeding signal must be received within 200 ms, otherwise the dog-feeding will time out, and thus nWDO will output a low-level pulse. The period of the above dog-feeding signal and the monitoring duration of the watchdog chip are only examples here and are not limiting. The specific design of the period of the dog-feeding signal and the monitoring duration of the watchdog chip can be set according to the limitations of the SOC chip and the watchdog chip.

[0072] The above first input / output interface 101 can be a GPIO interface, and this GPIO interface is set in the AP domain of the system chip 10. For example, the first input / output interface 101 can be GPIO85. The above first reset interface 104 is the interface corresponding to the nRESET pin set in the RTC domain of the system chip 10; the second reset interface 401 is the interface corresponding to the nRESET pin on the watchdog chip 40.

[0073] The above-mentioned reset circuit 30 is arranged between the system chip 10 and the watchdog chip 40 and is used to connect or disconnect the path between the system chip 10 and the watchdog chip 40. The input end of the reset circuit 30 is connected to the second reset interface 401 on the watchdog chip 40, and the output end of the reset circuit 30 is connected to the first reset interface 104 on the system chip 10. Optionally, the reset circuit 30 may include a switching device, and the switching device can be controlled by software and is controlled to be disconnected before the system chip 10 and the watchdog chip 40 are powered on and during the power-on startup process of the system chip 10 and the watchdog chip 40, so that the power-on reset signal during the power-on process of the watchdog chip 40 is ignored and will not cause the system chip 10 to reset. It can also be controlled to be closed after the system chip 10 and the watchdog chip 40 are powered on, so that the watchdog chip 40 can transmit the reset signal to the system chip 10 after power-on and let the system chip be normally reset.

[0074] Both the above-mentioned system chip 10 and watchdog chip 40 are domestic chips, with higher cost and security.

[0075] The working principle of the watchdog device described in the embodiment of the present application includes: before the system chip is powered on, the system is in a shutdown state and there is no need for the watchdog module to work; when the system chip starts to be powered on, the RTC domain on the system chip will be powered on. During this process, the reset circuit disconnects the first reset interface of the system chip from the second reset interface of the watchdog chip, so that the system chip will not receive a reset signal to reset during the power-on startup process.

[0076] After the power-on of the RTC domain on the system chip is completed, the output control signal of the RTC controls the external chips to supply power to each domain power supply in the system chip in sequence according to the set timing sequence. Thus, the chip will complete the power-on of each domain power supply in the system chip in sequence according to the SFT domain and the AP domain; when the AP domain on the system chip is powered on, one of the input / output interfaces will perform a dog feeding operation under the software control of the operating system. For example, a pulse signal with a high-low level switch is output at the GPIO85 interface to form a dog feeding signal and output it to the watchdog chip. On the side of the watchdog chip, it can detect whether a valid dog feeding signal is received within a preset time period. If it is received, it means that the system chip is running normally; if not, it means that the system chip is not running normally and needs to be reset for detection. The above-mentioned dog feeding signal has been described before and will not be elaborated here.

[0077] When the watchdog chip powers on and starts up, it can power on and start up simultaneously with the system chip, or it can power on and start up after the system chip has powered on. During the process of the watchdog chip powering on and starting up, since the path between the first reset interface of the system chip and the second reset interface on the watchdog chip is not conducting, the power-on reset signal (POR) during the power-on process of the watchdog chip is still ignored and will not cause the reset of the SOC. When the watchdog chip has completed power-on, the reset circuit is then controlled by software to conduct the path between the first reset interface of the system chip and the second reset interface on the watchdog chip. At this time, the conducting path between the first reset interface of the system chip and the second reset interface on the watchdog chip is hardware-locked by the reset circuit, so that regardless of any changes in the level at the interface of the system chip, the conducting path between the first reset interface of the system chip and the second reset interface on the watchdog chip still exists and will not be changed.

[0078] After the system chip and the watchdog chip have both powered on and started up, if a watchdog feed timeout occurs, at this time the watchdog chip will output a reset signal to the system chip to cause the system chip to perform a reset operation. Specifically, the process of the watchdog chip sending out the reset signal includes: nWDO on the watchdog chip will output a low-level pulse, then nMR recognizes this pulse and simultaneously triggers nRESET to output a low-level pulse. Finally, through the reset circuit, it is introduced into the nRESET of the system chip, and the system chip is reset. The system chip restarts the power-on timing sequence. In turn, the SFT domain powers on, the AP domain powers on, and the operating system of the AP domain powers on and starts up. The system chip starts the watchdog feed, and the watchdog chip powers on normally. During this process, the reset signal output by the watchdog chip is ignored, and the reset circuit controls the path between the first reset interface on the system chip and the second reset interface of the watchdog chip to conduct, and the watchdog chip enters the normal working process.

[0079] When the watchdog chip is under-voltage, the watchdog chip will also trigger the output of a reset signal. Specifically, a low-level pulse can be output at the second reset interface on the watchdog chip to transmit the reset signal to the system chip to cause the system chip to perform a reset.

[0080] When the system chip receives the reset signal transmitted by the watchdog chip, for example, Figure 1 when the nRESET pin of the SOC chip receives the reset signal output from the nRESET pin on the watchdog chip, the system of the system chip starts a process of restarting power-on, and this power-on process can repeat the above power-on process.

[0081] In the watchdog device described in the embodiments of the present application, a reset circuit is provided between the system chip and the watchdog chip, and the reset circuit is used to control the reset path between the system chip and the watchdog chip, so that the path between the system chip and the watchdog chip is always in a disconnected state during the power-on startup process of the system chip and the watchdog chip. In this case, even if the watchdog chip outputs a reset signal, the reset signal cannot be transmitted to the system chip, thus affecting the normal operation of the system chip, and the stability of the system chip operation can be improved. Additionally, the reset circuit can also be used to control the reset path between the system chip and the watchdog chip, so that the path between the system chip and the watchdog chip is always in a connected state after the system chip and the watchdog chip are powered on and started. In this case, the reset signal output by the watchdog chip can be accurately transmitted to the system chip, enabling the system chip to be reset and run in a timely manner when the dog feeding times out, ensuring the stable operation of the system chip and improving the operation performance of the system chip.

[0082] In some embodiments, a reset circuit 30 is provided. Refer to Figure 2 As shown, the reset circuit 30 includes a reset path 301 and a switch circuit 302; the reset path 30 is provided between a first reset interface 104 on the system chip 10 and a second reset interface 401 of the watchdog chip 40, and the switch circuit 302 is connected to the reset path 301; wherein, the switch circuit 302 is configured to control the reset path 301 to be in a disconnected state during the power-on startup process of the system chip 10 and the watchdog chip 40; the switch circuit 302 is further configured to control the reset path 301 to be in a connected state after the system chip 10 and the watchdog chip 40 are powered on and started.

[0083] The above-mentioned reset path 301 is provided between the system chip 10 and the watchdog chip 40 and is used to connect the path between the first reset interface 104 on the system chip 10 and the second reset interface 401 on the watchdog chip 40; the above-mentioned switch circuit 302 is used to control the connection or disconnection of the path between the first reset interface 104 on the system chip 10 and the second reset interface 401 on the watchdog chip 40. When the path between the first reset interface 104 on the system chip 10 and the second reset interface 401 on the watchdog chip 40 is connected, the watchdog chip 40 can output a reset signal and successfully transmit the reset signal to the system chip 10; when the path between the first reset interface 104 on the system chip 10 and the second reset interface 401 on the watchdog chip 40 is disconnected, the reset signal output by the watchdog chip 40 cannot be successfully transmitted to the system chip 10.

[0084] The working principle of the reset circuit described in the embodiments of the present application includes: Before the system chip is powered on, the system is in a shutdown state and there is no need for the watchdog module to work. At this time, the reset path is also in a disconnected state; When the system chip starts to be powered on, the RTC domain on the system chip will be powered on. During this process, the switch circuit controls the disconnection of the reset path, so that the first reset interface of the system chip and the second reset interface of the watchdog chip are not connected. In this way, the system chip will not receive a reset signal to be reset during the power-on startup process.

[0085] When the watchdog chip is powered on and started when the system chip is powered on and started, it can be powered on and started simultaneously, or it can be powered on and started after the system chip is powered on. During the process of the watchdog chip being powered on and started, since the reset path is not conducting, the power-on reset signal during the power-on process of the watchdog chip is still ignored and will not cause the reset of the SOC.

[0086] When the watchdog chip has completed power-on, the switch circuit is controlled by software to connect the reset path, and at this time, the reset path can also be hardware-locked by the switch circuit, so that no matter what changes occur in the level at the interface of the system chip, the reset path remains in a connected state, enabling the watchdog chip to successfully transmit the reset signal to the system chip to ensure the normal operation of the system of the system chip.

[0087] In some embodiments, as shown in Figure 3 A reset path 301 is also provided. The reset path 301 includes a first MOS transistor 3011, a first pull-up resistor 3012, and a second pull-up resistor 3013; One end of the first pull-up resistor 3012 is connected to the first power supply, and the other end of the first pull-up resistor 3012 is respectively connected to the first reset interface 104 and the drain of the first MOS transistor 3011. The source of the first MOS transistor 3011 is respectively connected to one end of the second pull-up resistor 3013 and the second reset interface 401, and the other end of the second pull-up resistor 3013 is connected to the first power supply; The gate of the first MOS transistor 3011 is connected to the switch circuit 302; Among them, the switch circuit 302 is specifically used to control the first MOS transistor 3011 to disconnect the reset path 301 before the system chip 10 and the watchdog chip 40 are powered on and started, and during the power-on startup process of the system chip 10 and the watchdog chip 40; The switch circuit 301 is also used to control the first MOS transistor 3011 to connect the reset path 301 after the system chip 10 and the watchdog chip 40 are powered on and started.

[0088] The above-mentioned first MOS transistor is turned on to connect the path between the system chip 10 and the watchdog chip 40, enabling signal or information transmission between the two; the above-mentioned first MOS transistor 3011 is turned off to disconnect the path between the system chip 10 and the watchdog chip 40, preventing signal or information transmission between the two. Optionally, the above-mentioned first MOS transistor is an NMOS transistor.

[0089] The above-mentioned first pull-up resistor 3012 is used to raise the voltage at the first reset interface 104 on the system chip 10 when the first MOS transistor 3011 is turned off, causing the first reset interface 104 to be released from the first power supply, thereby completing the power-on process of the RTC domain of the system chip; the second pull-up resistor 3013 is used to raise the voltage at the second reset interface 401 of the watchdog chip 40 when the first MOS transistor 3011 is turned off, causing the second reset interface 401 to be released from the first power supply; the first power supply can be a 1.8V power supply. For example, it can be represented by P_VCC_1V8.

[0090] The working principle of the reset path described in the embodiments of the present application is as follows: Before the system chip is powered on, the system is in a shutdown state and there is no need for the watchdog module to work. At this time, the first MOS transistor is in an off state; when the system chip starts to be powered on, the RTC domain on the system chip will be powered on. During this process, the switch circuit controls the first MOS transistor to be turned off, so that the first reset interface of the system chip and the second reset interface of the watchdog chip are not connected. In this way, the system chip will not receive a reset signal during the power-on startup process and will not be reset.

[0091] When the watchdog chip is powered on and starts up when the system chip is powered on and starts up, it can be powered on and start up simultaneously, or it can be powered on and start up after the system chip is powered on. During the power-on startup process of the watchdog chip, since the first MOS transistor is in an off state, the reset path is not conducted. Therefore, the power-on reset signal during the power-on process of the watchdog chip is still ignored and will not cause the reset of the SOC.

[0092] When the watchdog chip has completed power-on, the switch circuit is then controlled by software to control the first MOS transistor to be connected. Moreover, at this time, the first MOS transistor can also be hardware-locked by the switch circuit and is in a connected state. No matter how the level at the interface on the system chip changes, the first MOS transistor remains in a connected state, enabling the watchdog chip to successfully transmit the reset signal to the system chip to ensure the normal operation of the system of the system chip.

[0093] In some embodiments, refer to Figure 3As shown, a switching circuit 302 is also provided. The switching circuit 302 includes a second MOS transistor 3021, a third MOS transistor 3022, a fourth MOS transistor 3023, a diode 3024, a third pull-up resistor 3025, a fourth pull-up resistor 3026, a fifth pull-up resistor 3027, a first resistor 3028, a second resistor 3029, and a third resistor 3030. Among them, the source of the second MOS transistor 3021 is connected to one end of the third pull-up resistor 3025, the other end of the third pull-up resistor 3025 is connected to the second power supply, the drain of the second MOS transistor 3021 is connected to the gate of the first MOS transistor 3011, and the gate of the second MOS transistor 3021 is respectively connected to one end of the fourth pull-up resistor 3026, one end of the diode 3024, the drain of the third MOS transistor 3022, and one end of the first resistor 3028. The other end of the fourth pull-up resistor 3026 is connected to the second power supply, the other end of the diode 3024 is connected to the second input / output interface 102 on the system chip 10, the source of the third MOS transistor 3022 is grounded, the other end of the first resistor 3028 is connected to the gate of the fourth MOS transistor 3023, the source of the fourth MOS transistor 3023 is connected to the fifth pull-up resistor 3027, the drain of the fourth MOS transistor 3023 is respectively connected to one end of the second resistor 3029 and the third resistor 3030, the other end of the second resistor 3029 is connected to the gate of the third MOS transistor 3022, and the other end of the third resistor 3030 is connected to the source of the third MOS transistor 3022.

[0094] The above-mentioned second MOS transistor 3021 is a PMOS transistor, the third MOS transistor 3022 is an NMOS transistor, and the fourth MOS transistor 3023 is a PMOS transistor. The above-mentioned second MOS transistor 3021 is connected to the first MOS transistor 3011 to control the conduction or disconnection of the first MOS transistor 3011. The above-mentioned third MOS transistor 3022 and the above-mentioned fourth MOS transistor 3023 are used to lock the conduction state of the first MOS transistor 3011 after the second MOS transistor 3021 controls the first MOS transistor 3011 to conduct. The above-mentioned second power supply can be a 3.3V power supply. For example, it can be represented by P_VCC_3V1.

[0095] The above-mentioned second input / output interface 102 can be a GPIO interface, and this GPIO interface is set in the AP domain of the system chip 10. For example, the second input / output interface 102 can be GPIO131.

[0096] The working principle of the switch circuit 302 described in the embodiments of the present application includes: The second input / output interface 102 is initially at a low level. As the AP domain on the system chip is powered on, the second input / output interface 102 will change from a low level to a high level. During this process, the second power supply (P_VCC_3V3) starts to be powered on. Until the second power supply is fully powered on and the circuit is stable, during this process, the source voltage of the second MOS transistor 3021 changes from zero to 3.3V, the second MOS transistor 3021 is turned off, and the first MOS transistor 3011 is turned off. Then the path between the first reset interface on the system chip and the second reset interface on the watchdog chip will not conduct; After the watchdog chip is powered on, it can control the second input / output interface 102 on the system chip to output a low-level pulse. At this time, the diode conducts, and the voltage at the gate of the second MOS transistor is 0.7 volts. At this time, the second MOS transistor conducts, and then the second MOS transistor controls the first MOS transistor to conduct. Then the path between the first reset interface on the system chip and the second reset interface on the watchdog chip also conducts accordingly. Moreover, at this time, through the third MOS transistor and the fourth MOS transistor, the first MOS transistor and the second MOS transistor can be locked, so that the first MOS transistor is always in the off state and is not affected by the levels of other GPIOs on the system chip. For example, at this time, the second input / output interface on the system chip outputs a high-level pulse, and the first MOS transistor always remains in the off state, so that the reset signal output by the watchdog chip can be successfully transmitted to the system chip for reset, improving the stability of the system chip operation.

[0097] The values of the above-mentioned third pull-up resistor, fourth pull-up resistor, fifth pull-up resistor, first resistor, second resistor, and third resistor can be designed according to actual application requirements and are not limited here.

[0098] In some embodiments, referring to Figure 4 As shown, a watchdog device is further provided. Based on the watchdog device described in the foregoing embodiments, the watchdog device further includes: a power control circuit 50; The power control circuit 50 is respectively connected to the third input / output interface 103 on the system chip 10, the chip power supply, and the power supply interface 403 on the watchdog chip 40; Among them, the power control circuit 50 is used to control the watchdog chip 40 to be powered on after the system chip 10 is powered on and started.

[0099] The above-mentioned power control circuit 50 is used to connect or disconnect the path between the chip power supply (such as SYS_3V3) and the watchdog chip 40 to realize the control of the watchdog chip being powered on. One end of the power control circuit 50 is connected to the third input / output interface 103 on the system chip 10, and the other end of the power control circuit 50 is respectively connected to the third input / output interface 103 on the system chip 10, the chip power supply, and the power supply interface 403 on the watchdog chip 10.

[0100] The working principle of the power control circuit 50 described in the embodiments of the present application includes: when the AP on the system chip 10 is powered on, the power control circuit 50 can be controlled by software so that the chip power supply can supply power to the watchdog chip 40, and the watchdog chip 40 is powered on. Specifically, the third input / output interface 103 can be controlled by software to output a high-level pulse, so that the power control circuit 50 connects the path between the chip power supply and the watchdog chip 40, and the watchdog chip 40 can be powered on. Before the watchdog chip 40 is powered on and after the system chip 10 is powered on, that is, when not controlled by software, the power control circuit 50 defaults to disconnect the path between the chip power supply and the watchdog chip 40, so as not to be accidentally changed, thus ensuring that the watchdog 40 is only powered on after the operating system is powered on and started.

[0101] For the watchdog device described in the above embodiments, during the power-on startup process of the system chip, it controls not to power on and start the watchdog chip, simplifies the requirement for feeding the dog to the chip during the power-on startup process of the system chip, simplifies the monitoring process of the system chip, and improves the monitoring efficiency.

[0102] In some embodiments, as shown in Figure 5 a power control circuit 50 is further provided. The power control circuit 50 includes a fifth MOS transistor 501, a sixth MOS transistor 502, and a pull-down resistor 503. The source of the fifth MOS transistor 501 is connected to the chip power supply, and the drain of the fifth MOS transistor 501 is connected to the power interface 403 on the watchdog chip 40. The gate of the fifth MOS transistor 501 is connected to the drain of the sixth MOS transistor 502. The gate of the sixth MOS transistor 502 is respectively connected to the third input / output interface 103 on the system chip 10 and the pull-down resistor 503, and the source of the sixth MOS transistor 502 is connected to the ground.

[0103] The above-mentioned fifth MOS transistor 501 is a PMOS transistor, and the sixth MOS transistor 502 is an NMOS transistor. The above-mentioned sixth MOS transistor 502 is used to control the fifth MOS transistor 501 to conduct or disconnect. The sixth MOS transistor 502 is connected to the third input / output interface 103 on the system chip. When the third input / output interface 103 outputs a high level, the sixth MOS transistor 502 disconnects, and the fifth MOS transistor 501 conducts, so as to connect the path between the chip power supply and the watchdog chip, so that the chip power supply supplies power to the watchdog chip.

[0104] The above-mentioned third input / output interface 103 can be a GPIO interface, and this GPIO interface is set in the AP domain of the system chip 10. For example, the third input / output interface 103 can be GPIO84.

[0105] The working principle of the power control circuit 50 described in the embodiments of the present application includes: when the AP on the system chip 10 is powered on, the third input / output interface 103 can be pulled high through software control, so as to control the sixth MOS transistor 502 to turn off and the fifth MOS transistor 501 to turn on, thereby connecting the path between the chip power supply and the watchdog chip, so that the chip power supply supplies power to the watchdog chip. Specifically, the third input / output interface 103 can be controlled by software to output a high-level pulse, so that the power control circuit 50 connects the path between the chip power supply and the watchdog chip 40, and the watchdog chip 40 can be powered on. Before the watchdog chip 40 is powered on and after the system chip 10 is powered on, that is, when not controlled by software, the default state of the third input / output interface 103 is low level, so as not to be accidentally changed, thus ensuring that the watchdog 40 is only powered on after the operating system is powered on and started.

[0106] For the watchdog device described in the above embodiments, during the power-on startup process of the system chip, the power control circuit can be used to control the watchdog chip not to be powered on and started. And during the control process, only the output of the input / output interface of the system chip needs to be controlled to realize the power-on control of the watchdog chip, which simplifies the requirement for feeding the dog to the chip during the power-on startup process of the system chip, simplifies the monitoring process of the system chip, and improves the monitoring efficiency.

[0107] In some embodiments, as shown in Figure 6 shown, a watchdog device is further provided. Based on the watchdog device described in the foregoing embodiments, the watchdog device further includes: a shielding circuit 60, and the shielding circuit 60 is connected to the enable interface on the watchdog chip 40; wherein, the shielding circuit 60 is used to control the watchdog chip 40 to turn off the monitoring function when an external shielding signal is triggered. Specifically, the shielding circuit 60 includes a seventh MOS transistor 601, a fourth resistor 602, a fifth resistor 603, and a second pull-down resistor 604; the gate of the seventh MOS transistor 601 is connected to one end of the fourth resistor 602, the source of the seventh MOS transistor 601 is respectively connected to one end of the fifth resistor 603 and the enable interface 404 on the watchdog chip 40, the drain of the seventh MOS transistor 601 is connected to the ground; the other end of the fourth resistor 602 is respectively connected to the second pull-down resistor 604 and the external signal input port interface 605; the other end of the fifth resistor 603 is connected to the chip power supply.

[0108] The above seventh MOS transistor 601 is an NMOS transistor, which is used to transfer the external shielding signal received by the external signal input interface to the enable interface 404. After the enable interface 404 is enabled, the watchdog chip 40 is controlled to turn off the monitoring function. Specifically, when the level at the enable interface 404 is high, the watchdog chip 40 is enabled, and when the level of the enable interface 404 is low, the watchdog chip is prohibited.

[0109] The values of the fourth resistor 602, the fifth resistor 603, and the second pull-down resistor 604 described above can be designed according to actual application requirements, which are not limited herein.

[0110] The working principle of the shielding circuit described in the embodiments of the present application includes: after the watchdog chip 40 is powered on and works, the level at the enable interface 404 on the watchdog chip 40 presents a high level, the watchdog chip 40 is enabled, and the watchdog chip 40 works normally. If a low-level pulse, that is, a reset signal, is output from the nWDO pin of the system chip 10 when the dog feeding times out; when the watchdog chip 40 receives an external shielding signal through the external signal input port interface 605, the level at the enable interface 404 on the watchdog chip 40 presents a low level, the watchdog chip is disabled. At this time, even if the dog feeding times out, the nWDO of the system chip 10 will no longer output a low-level pulse. That is, at this time, no dog feeding operation is required, and the timeout function of the watchdog chip will not be triggered. That is to say, disabling the watchdog chip has the highest priority.

[0111] The shielding circuit described in the above embodiments combines an external watchdog disabling function. For example, when a USB is inserted into the program burning port, the watchdog can be disabled. At this time, no dog feeding operation is required, and the watchdog timeout function will not be triggered, improving the applicability of the watchdog chip.

[0112] Based on the watchdog device described in any of the above embodiments, the embodiments of the present application further provide a monitoring method, as Figure 7 shown, the method includes:

[0113] S101, controlling the system chip and the watchdog chip in the watchdog device to be powered on and started.

[0114] S102, during the power-on startup process of the system chip and the watchdog chip in the watchdog device, controlling the path between the first reset interface on the system chip and the second reset interface on the watchdog chip to be in a disconnected state.

[0115] S103, after the system chip and the watchdog chip are powered on and started, controlling the path between the first reset interface on the system chip and the second reset interface on the watchdog chip to be in a connected state.

[0116] The steps in the above embodiments have been described above. For detailed content, please refer to the foregoing content, which will not be repeated herein. This monitoring method can accurately monitor the operating state of the system chip, thereby improving the operating stability of the system chip.

[0117] In some embodiments, an implementation manner of the above S101 is further provided, as Figure 8 shown, the method includes:

[0118] S201, control the system chip in the watchdog device to power on and start up;

[0119] S202, after the system chip powers on and starts up, control the path between the chip power supply and the watchdog chip to be in a connected state, so that the chip power supply powers the watchdog chip for power-on startup.

[0120] The steps in the above embodiments have been described previously. For detailed content, please refer to the previous content and will not be elaborated here.

[0121] In some embodiments, based on the watchdog device described in the foregoing Figure 6 embodiment, a monitoring method is provided. The watchdog device is applied to the SOC chip. The method includes:

[0122] S1. Before the SOC chip powers on, the system chip is in a shutdown state and the watchdog chip does not need to work;

[0123] S2. When the SOC chip starts to power on and start up, the RTC domain in the system chip will be powered on. During this process, the nRESET of the SOC chip and the nRESET of the watchdog chip are not connected; after the RTC domain of the SOC chip is powered on, the nRESET of the SOC chip is released by the external P_VRTC_1V8, thus completing the power-on process of the RTC domain.

[0124] S3. After the power-on of the RTC domain on the SOC chip is completed, the output control signal of the RTC domain controls the external chips to supply power to each domain power supply of the SOC chip in accordance with the set time sequence. Thus, the chip will complete the power-on of each domain power supply of the SOC system in sequence according to SFT and AP.

[0125] S4. When the AP domain on the SOC chip is powered on, one of the GPIOs (GPIO85) will perform a dog feeding operation under the software control of the operating system. The specific dog feeding is to periodically switch between high and low levels. The following is the process: initially output a high level for 10 ms, then switch to output a low level for 10 ms, and then switch to output a high level for 10 ms, and so on in a loop. Each time the high level switches to the low level will be regarded as a valid dog feeding signal. The design of the watchdog module is that a valid dog feeding signal must be received within 200 ms, otherwise the dog feeding will time out, and thus nWDO will output a low level pulse; it should be noted here that the design parameters here are a design for actual application and can be parameterized according to specific situations and are not limited here.

[0126] S5. Control another GPIO (GPIO84) on the SOC chip, which will be pulled high under the software control of the operating system, thereby controlling the power control circuit to supply power to the watchdog chip. Before this and in the default state (when not controlled by the operating system software) after power-on, this pin (GPIO84) is in the default low-level state and will not be accidentally changed, thus ensuring that the watchdog chip is only powered after the operating system of the SOC chip is started.

[0127] S6. During the power-on process in S5 above, since the nRESET of the SOC chip and the nRESET of the watchdog chip are not conducting, the power-on reset signal during the power-on process of the watchdog chip is still ignored and will not cause the reset of the SOC.

[0128] S7. When the watchdog chip has completed power-on, then control the GPIO (GPIO131) to output

[0129] a low-level pulse, thereby realizing the conduction of the path between the nRESET of the SOC chip and the nRESET of the watchdog chip. At this time, the conduction between the two nRESETs is hardware-locked. Even if the level of the GPIO131 port changes (for example, becomes high level), the conduction between the two nRESETs still exists and will not be changed.

[0130] S8. If the dog feeding times out, at this time, the nWDO pin of the watchdog chip will output a low-level pulse, then the nMR pin can recognize this pulse, and at the same time trigger the nRESET to output a low-level pulse, and finally lead to the nRESET of the SOC chip. The SOC chip is reset, the SOC chip restarts the power-on timing sequence, sequentially powers on the SFT domain, powers on the AP domain, starts the operating system of the AP domain, GPIO85 enables dog feeding, GPIO84 controls the power supply to the watchdog chip, the watchdog powers on normally, POR is ignored, GPIO131 controls the conduction between the nRESET of the watchdog and the nRESET of the SOC, and the watchdog system enters the normal working process;

[0131] S9. When the VCC power supply of the watchdog chip is lower than the threshold, the chip will also trigger the nRESET to output a low-level pulse, and then reset the entire system through the nRESET of the SOC chip;

[0132] Among them, if the SOC chip receives the reset signal of nRESET, the system starts a power-on process again. At this time, whether it is GPIO84, GPIO85, or GPIO131 will be in the default state. The first two will be in the low-level state until the operating system starts normally and takes over the states of the two GPIOs for subsequent control. GPIO131 is initially at a low level and will change to a high level as the power supply of the chip's own AP domain. During this process, P_VCC_3V3 always maintains a 3.3V power supply, so the two nRESETs will not conduct. Subsequently, after P_VCC_3V3 is powered on and the circuit is stable, the two nRESETs will not conduct either. Until the POR timing of the watchdog is completed, then through the operating system, control GPIO131 to output a low-level pulse. At this time, the path between the two nRESETs is locked and conducted, and is not affected by the GPIO level, which can improve the system operation stability of the SOC chip.

[0133] The monitoring method described in the above embodiments can achieve that before the operating system of the SOC chip starts up, the reset signal of the watchdog chip cannot be transmitted to the SOC. After the operating system starts up, the reset signal of the watchdog chip is correctly transmitted to the SOC; after the watchdog chip starts up, ensure an effective dog feeding every time; when external dog feeding needs to be prohibited, the function of prohibiting the dog can be realized through the USB cable. First, this method does not depend on the operating environment of the SOC chip's operating system. The watchdog chip can work normally and can detect the abnormality of the SOC in time, so as to perform a reset operation. Therefore, it has strong anti-interference ability and will not cause the program to get out of control or enter an infinite loop, greatly improving the stability of the system operation. Second, this method also does not depend on the system clock and is not affected by the system clock failure or interference. If the system clock frequency is abnormal or even stops working, the above monitoring method will not deviate or stop working. When the dog feeding times out, the watchdog chip can accurately monitor the abnormal operation of the SOC, so the battery management system applying the SOC can also operate stably. Third, in this method, by controlling the hardware to connect or disconnect the reset path between the SOC and the watchdog chip, compared with the method where the startup and control of the software watchdog are both implemented by software parameters, this method can avoid the problem that the software watchdog is closed by malicious code or program errors and cannot work properly. In addition, it can also avoid the problem that the control logic is maliciously tampered with, which may cause the watchdog to not work properly.

[0134] It should be understood that although the steps in the flowcharts involved in the above-described embodiments are sequentially shown in the direction of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps has no strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-described embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.

[0135] Based on the same inventive concept, the embodiments of the present application also provide a monitoring device for implementing the above-mentioned monitoring method. The solution provided by this device to solve the problem is similar to the solution described in the above method. Therefore, the specific limitations in one or more embodiments of the following monitoring devices can refer to the limitations on the monitoring method in the above text, and will not be repeated here.

[0136] In an exemplary embodiment, as Figure 9 shown, a monitoring device is provided, including:

[0137] A first control module 91, configured to control the power-on startup of the system chip and the watchdog chip in the watchdog device.

[0138] A second control module 92, configured to control the path between the first reset interface on the system chip and the second reset interface on the watchdog chip to be in a disconnected state during the power-on startup process of the system chip and the watchdog chip in the watchdog device.

[0139] A third control module 93, configured to control the path between the first reset interface on the system chip and the second reset interface on the watchdog chip to be in a connected state after the system chip and the watchdog chip are powered on and started up.

[0140] In an exemplary embodiment, the above-mentioned first control module 91 includes:

[0141] A first control unit, configured to control the power-on startup of the system chip in the watchdog device;

[0142] A second control unit, configured to control the path between the chip power supply and the watchdog chip to be in a connected state after the system chip is powered on and started up, so that the chip power supply supplies power to the watchdog chip for power-on startup.

[0143] Each module in the above monitoring device can be implemented in whole or in part by software, hardware, and their combination. Each of the above modules can be embedded in or independent of the processor in the computer device in the form of hardware, or stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to each of the above modules.

[0144] In an exemplary embodiment, a computer device is provided, including a memory and a processor. A computer program is stored in the memory. When the processor executes the computer program, the following steps are implemented:

[0145] Control the system chip and the watchdog chip in the watchdog device to power on and start up;

[0146] During the power-on startup process of the system chip and the watchdog chip in the watchdog device, control the path between the first reset interface on the system chip and the second reset interface on the watchdog chip to be in a disconnected state;

[0147] After the system chip and the watchdog chip are powered on and started up, control the path between the first reset interface on the system chip and the second reset interface on the watchdog chip to be in a connected state.

[0148] In one embodiment, when the processor executes the computer program, the following steps are also implemented:

[0149] Control the system chip in the watchdog device to power on and start up;

[0150] After the system chip is powered on and started up, control the path between the chip power supply and the watchdog chip to be in a connected state, so that the chip power supply supplies power to the watchdog chip for power-on startup.

[0151] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by the processor, the following steps are implemented:

[0152] Control the system chip and the watchdog chip in the watchdog device to power on and start up;

[0153] During the power-on startup process of the system chip and the watchdog chip in the watchdog device, control the path between the first reset interface on the system chip and the second reset interface on the watchdog chip to be in a disconnected state;

[0154] After the system chip and the watchdog chip are powered on and started up, control the path between the first reset interface on the system chip and the second reset interface on the watchdog chip to be in a connected state.

[0155] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented:

[0156] Control the power-on startup of the system chip in the watchdog device;

[0157] After the system chip in the watchdog device is powered on and starts up, control the path between the chip power supply and the watchdog chip to be in a connected state, so that the chip power supply powers the watchdog chip for power-on startup.

[0158] In one embodiment, a computer program product is provided, including a computer program, which when executed by a processor implements the following steps:

[0159] Control the power-on startup of the system chip and the watchdog chip in the watchdog device;

[0160] During the power-on startup process of the system chip and the watchdog chip in the watchdog device, control the path between the first reset interface on the system chip and the second reset interface on the watchdog chip to be in a disconnected state;

[0161] After the system chip and the watchdog chip are powered on and start up, control the path between the first reset interface on the system chip and the second reset interface on the watchdog chip to be in a connected state.

[0162] In one embodiment, when the computer program is executed by the processor, it also implements the following steps:

[0163] Control the power-on startup of the system chip in the watchdog device;

[0164] After the system chip is powered on and starts up, control the path between the chip power supply and the watchdog chip to be in a connected state, so that the chip power supply powers the watchdog chip for power-on startup.

[0165] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, database, or other medium used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The databases involved in the embodiments provided in this application can include at least one of relational databases and non-relational databases. Non-relational databases can include distributed databases based on blockchain, etc., without limitation. The processors involved in the embodiments provided in this application can be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, data processing logics based on quantum computing, artificial intelligence (AI) processors, etc., without limitation.

[0166] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope recorded in this application.

[0167] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the patent scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims

1. A watchdog device, characterized in that, The watchdog device includes: a system chip, a dog-feeding path, a reset circuit, and a watchdog chip; a first input / output interface on the system chip is connected to the watchdog chip based on the dog-feeding path; the reset circuit is respectively connected to a first reset interface on the system chip and a second reset interface of the watchdog chip; Wherein, the reset circuit is configured to control the path between the first reset interface on the system chip and the second reset interface of the watchdog chip to be in an open state during the power-on startup process of the system chip and the watchdog chip; The reset circuit is further configured to control the path between the first reset interface on the system chip and the second reset interface of the watchdog chip to be in a connected state after the system chip and the watchdog chip are powered on and started up.

2. The watchdog device according to claim 1, characterized in that The reset circuit includes: a reset path and a switch circuit; the reset path is disposed between the first reset interface on the system chip and the second reset interface of the watchdog chip, and the switch circuit is connected to the reset path; Wherein, the switch circuit is configured to control the reset path to be in an open state during the power-on startup process of the system chip and the watchdog chip; The switch circuit is further configured to control the reset path to be in a connected state after the system chip and the watchdog chip are powered on and started up.

3. The watchdog device according to claim 2, wherein The reset path includes a first MOS transistor, a first pull-up resistor, and a second pull-up resistor; one end of the first pull-up resistor is connected to a first power supply, the other end of the first pull-up resistor is respectively connected to the first reset interface and the drain of the first MOS transistor, the source of the first MOS transistor is respectively connected to one end of the second pull-up resistor and the second reset interface, and the other end of the second pull-up resistor is connected to the first power supply; the gate of the first MOS transistor is connected to the switch circuit; Wherein, the switch circuit is specifically configured to control the first MOS transistor to disconnect the reset path during the power-on startup process of the system chip and the watchdog chip; The switch circuit is further configured to control the first MOS transistor to connect the reset path after the system chip and the watchdog chip are powered on and started up.

4. The watchdog device according to claim 3, wherein The switch circuit includes: a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a diode, a third pull-up resistor, a fourth pull-up resistor, a fifth pull-up resistor, a first resistor, a second resistor, and a third resistor; Wherein, the source of the second MOS transistor is connected to one end of the third pull-up resistor, the other end of the third pull-up resistor is connected to a second power supply, the drain of the second MOS transistor is connected to the gate of the first MOS transistor, and the gate of the second MOS transistor is respectively connected to one end of the fourth pull-up resistor, one end of the diode, the drain of the third MOS transistor, and one end of the first resistor; The other end of the fourth pull-up resistor is connected to the second power supply. The other end of the diode is connected to the second input / output interface on the system chip. The source of the third MOS transistor is grounded. The other end of the first resistor is connected to the gate of the fourth MOS transistor. The source of the fourth MOS transistor is connected to the fifth pull-up resistor. The drain of the fourth MOS transistor is respectively connected to one ends of the second resistor and the third resistor. The other end of the second resistor is connected to the gate of the third MOS transistor. The other end of the third resistor is connected to the source of the third MOS transistor.

5. The watchdog device according to any one of claims 1-4, characterized in that, The watchdog device further includes: a power control circuit; the power control circuit is respectively connected to the third input / output interface on the system chip, the chip power supply, and the power interface on the watchdog chip; Wherein, the power control circuit is used for controlling the watchdog chip to power on and start after the system chip powers on and starts.

6. The watchdog device according to claim 5, wherein The power control circuit includes a fifth MOS transistor, a sixth MOS transistor, and a pull-down resistor; the source of the fifth MOS transistor is connected to the chip power supply. The drain of the fifth MOS transistor is connected to the power interface on the watchdog chip. The gate of the fifth MOS transistor is connected to the drain of the sixth MOS transistor. The gate of the sixth MOS transistor is respectively connected to the third input / output interface on the system chip and the pull-down resistor. The source of the sixth MOS transistor is grounded.

7. The watchdog device according to any one of claims 1-4, characterized in that, The watchdog device further includes: a shielding circuit; the shielding circuit is connected to the enable interface on the watchdog chip; Wherein, the shielding circuit is used for controlling the watchdog chip to turn off the monitoring function when an external shielding signal is triggered.

8. The watchdog device according to claim 7, wherein The shielding circuit includes a seventh MOS transistor, a fourth resistor, a fifth resistor, and a second pull-down resistor; the gate of the seventh MOS transistor is connected to one end of the fourth resistor. The source of the seventh MOS transistor is respectively connected to one end of the fifth resistor and the enable interface on the watchdog chip. The drain of the seventh MOS transistor is grounded. The other end of the fourth resistor is respectively connected to the second pull-down resistor and the external signal input port interface. The other end of the fifth resistor is connected to the chip power supply.

9. A monitoring method, characterized in that, The monitoring method is applied to the watchdog device according to any one of claims 1-8, and the method includes: Controlling the system chip and the watchdog chip in the watchdog device to power on and start; During the power-on startup process of the system chip and the watchdog chip in the watchdog device, controlling the path between the first reset interface on the system chip and the second reset interface on the watchdog chip to be in a disconnected state; After the system chip and the watchdog chip power on and start, controlling the path between the first reset interface on the system chip and the second reset interface on the watchdog chip to be in a connected state.

10. The method according to claim 9, characterized in that, The controlling the system chip and the watchdog chip in the watchdog device to power on and start includes: Controlling the system chip in the watchdog device to power on and start; After the system-on-chip is powered on and starts up, the path between the chip power supply and the watchdog chip is controlled to be in a connected state, so that the chip power supply supplies power to the watchdog chip for power-on startup.

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