Image verification method and device based on high-speed bus, storage medium and chip
Through the image verification method based on high-speed bus, the calibration data comparison is performed using registers to match the size of the image target area, which solves the problem of insufficient accuracy and flexibility of the cyclic redundancy verification method in the prior art in the image transmission process, and improves the real-time verification sum accuracy of image transmission.
Patent Information
- Application Number
- CN202510276703.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-10
- Publication Date
- 2025-07-11
AI Technical Summary
The existing cyclic redundancy verification methods have low accuracy and flexibility in image transmission, and cannot adapt to multiple types or complex transmission environments.
The image verification method based on the high-speed bus obtains the first verification data of the target area of the image to be checked and stores it in a register of corresponding size, and uses the second verification data to judge the verification result, and supports flexible verification of the region of interest, row/column horizontal area and frame horizontal area. It uses 8-bit, 16-bit or 32-bit cyclic redundancy verification to adapt to different image data volumes, and uses the on-chip bus AXI protocol for data transmission.
Real-time verification of image transmission is realized, the accuracy of data transmission is improved, and a variety of image verification needs are applicable to avoid verification errors and resource waste, and flexible verification adaptation and precise error handling are supported.
Smart Images
Figure CN120295828A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the technical field of data transmission, and relates to an image verification method, device, storage medium, and chip based on a high-speed bus. Background Art
[0002] During the image transmission process, ensuring the integrity and accuracy of data is crucial. Due to the instability of the network environment and interference during the transmission process, data may be lost, damaged, or tampered with during transmission, affecting the image quality at the receiving end. Therefore, verifying the transmitted image data to ensure that the data has not been damaged during transmission is an important technical link in image communication. Cyclic Redundancy Check (CRC) is a commonly used error detection method and is widely used in the data transmission process. CRC has strong error detection capabilities and can effectively detect common transmission problems such as single-bit errors and burst errors.
[0003] However, the existing cyclic redundancy check methods have low accuracy and flexibility during the image transmission process and cannot adapt to multi-type or complex transmission environments. Summary of the Invention
[0004] The purpose of this application is to provide an image verification method, device, storage medium, and chip based on a high-speed bus to solve the problem of low accuracy and flexibility of the cyclic redundancy check method in the prior art during the image transmission process.
[0005] In a first aspect, this application provides an image verification method based on a high-speed bus. The image verification method based on a high-speed bus includes: when storing image data in a memory, obtaining first verification data for a target area of the image to be verified; storing the first verification data in a register, the size of the register matching the size of the target area of the image to be verified, the target area including a region of interest, a row / column horizontal area, and a frame horizontal area, and matching the type of the target area according to the type of the image data; when reading the image to be verified from the memory, obtaining second verification data for the target area of the image to be verified; using the first verification data and the second verification data to obtain a verification result for the target area of the image to be verified. If the verification result shows that the first verification data and the second verification data are the same, it indicates that the image transmission is correct. If the verification result shows that the first verification data and the second verification data are different, it indicates that the image transmission is incorrect.
[0006] In an implementation manner of the first aspect, the first verification data and the second verification data are verification data based on 8-bit, 16-bit, or 32-bit cyclic redundancy check, and the verification level of the cyclic redundancy check is determined according to the data volume of the image data.
[0007] In an implementation of the first aspect, the target area includes a region of interest. The verification of the region of interest includes: when storing image data in a memory, obtaining first verification data of the region of interest of the image to be verified; storing the first verification data in a register matching the region of interest; when reading the image to be verified from the memory, obtaining second verification data of the region of interest of the image to be verified; and obtaining a verification result of the region of interest of the image to be verified by using the first verification data and the second verification data.
[0008] In an implementation of the first aspect, the target area includes a row / column horizontal area. The verification of the row / column horizontal area includes: when storing image data in a memory, obtaining first verification data of the row / column horizontal area of the image to be verified; storing the first verification data in a register matching the row / column horizontal area; when reading the image to be verified from the memory, obtaining second verification data of the row / column horizontal area of the image to be verified; and obtaining a verification result of the row / column horizontal area of the image to be verified by using the first verification data and the second verification data.
[0009] In an implementation of the first aspect, the target area includes a frame horizontal area. The verification of the frame horizontal area includes: when storing image data in a memory, obtaining first verification data of the region of interest of the image to be verified; storing the first verification data in a register matching the frame horizontal area; when reading the image to be verified from the memory, obtaining second verification data of the frame horizontal area of the image to be verified; and obtaining a verification result of the frame horizontal area of the image to be verified by using the first verification data and the second verification data.
[0010] In an implementation of the first aspect, the image verification method based on a high-speed bus includes: performing image verification on the region of interest or the row / column horizontal area based on 16-bit cyclic redundancy check, and performing image verification on the frame horizontal area based on 32-bit cyclic redundancy check.
[0011] In an implementation of the first aspect, the image verification method based on a high-speed bus further includes performing data transmission based on the on-chip bus AXI protocol, and the data transmission includes storing and reading image data in a memory, obtaining verification data, and the verification result.
[0012] Second aspect, the present application provides an image verification device. The image verification device includes: an encoder, configured to process the image data when the image data is stored to obtain first verification data; a register, configured to store the first verification data and generate a control signal to be sent to a decoder, the size of the register matching the size of the image data verification area, the target area including a region of interest, a row / column horizontal area, and a frame horizontal area, and matching the type of the target area according to the type of the image data; a decoder, configured to process the image data when the image data is read to obtain second verification data; and configured to read the first verification data stored in the register, and obtain a verification result of the image data by using the first verification data and the second verification data. If the verification result is that the first verification data and the second verification data are the same, it indicates that the image transmission is correct. If the verification result is that the first verification data and the second verification data are different, it indicates that the image transmission is incorrect.
[0013] Third aspect, the present application provides a chip. The chip includes: an image signal processing module, configured to write a transmitted image into a memory or read the transmitted image from the memory by using an on-chip bus; an image verification device, configured to verify the transmitted image by using the image verification method based on a high-speed bus according to any one of the first aspect; and a memory, configured to receive and store the transmitted image.
[0014] Fourth aspect, the present application provides a computer-readable storage medium. A programmable logic program is stored on the computer-readable storage medium, and when the program is executed by a programmable logic device, it implements the image verification method based on a high-speed bus according to any one of the first aspect.
[0015] As described above, the image verification method, device, storage medium, and chip according to one or more embodiments of the present application have the following beneficial effects:
[0016] By using a register with a size matching the size of the target area of the image to be verified, and using the comparison result of the first verification data and the second verification data as the verification result, this image verification method based on a high-speed bus can be applicable to various image verification requirements, perform real-time verification on image transmission, and improve the accuracy of data transmission.
[0017] The first verification data and the second verification data are verification data for calculating cyclic redundancy check based on 8 bits, 16 bits, or 32 bits according to actual requirements. By flexibly selecting the number of bits of the corresponding cyclic redundancy check according to the size of the verification target area, flexible adaptation of image verification can be achieved, avoiding verification errors or waste of data resources.
[0018] The target area of the image data includes three cyclic redundancy check methods: the region of interest, the row / column horizontal region, and the frame horizontal region, making the data transmission check of the image signal processing module more flexible. When setting multiple regions of interest or row / column horizontal regions for real-time inspection, once an image transmission error is found, it can be immediately reported for processing without waiting for the end of a frame of image transmission. It is also possible to determine which region of interest or row / column horizontal region has a transmission error based on the check result, facilitating precise handling of the error.
[0019] The image check is performed using the on-chip bus AXI protocol interface, which is applicable to different burst transmission lengths. At the same time, the data received by the receiving end is transmitted by the sending end through the on-chip bus AXI protocol, and the processing is also based on the on-chip bus AXI protocol, making it more convenient for IP integration between modules. Brief Description of the Drawings
[0020] Figure 1A It shows a schematic diagram of an application scenario of the image check method based on a high-speed bus described in this application.
[0021] Figure 1B It shows a schematic diagram of the structure of the end-cloud interaction scenario of the image check method based on a high-speed bus.
[0022] Figure 2 It shows a schematic diagram of the flow of the image check method based on a high-speed bus described in an embodiment of this application.
[0023] Figure 3 It shows a schematic diagram of the flow of the region of interest check method based on a high-speed bus described in an embodiment of this application.
[0024] Figure 4 It shows a schematic diagram of the flow of the row / column horizontal region check method based on a high-speed bus described in an embodiment of this application.
[0025] Figure 5 It shows a schematic diagram of the flow of the frame horizontal region check method based on a high-speed bus described in an embodiment of this application.
[0026] Figure 6 It shows a schematic diagram of the structure of the image check device based on a high-speed bus described in an embodiment of this application.
[0027] Figure 7 It shows a schematic diagram of the structure of the encoder described in an embodiment of this application.
[0028] Figure 8 It shows a schematic diagram of the structure of the decoder described in an embodiment of this application.
[0029] Figure 9 It shows a schematic diagram of the structure of the chip described in an embodiment of this application.
[0030] Description of Component Labels
[0031] 1 Transmission Verification Device
[0032] 11 Image Transmission Device
[0033] 12 Image Verification Device
[0034] 13 Display Terminal
[0035] 2 Terminal-Cloud Interaction System
[0036] 20 Terminal
[0037] 21 Cloud Server
[0038] 100 Image Verification Device
[0039] 110 Encoder
[0040] 111 Encoding Control Module
[0041] 112 Encoding Calculation Module
[0042] 120 Register
[0043] 130 Decoder
[0044] 131 Decoding Control Module
[0045] 132 Decoding Calculation Module
[0046] 133 Verification Module
[0047] 200 Chip
[0048] 210 Image Signal Processing Module
[0049] 220 Memory
[0050] Steps S11 to S14
[0051] Steps S21 to S24
[0052] Steps S31 to S34
[0053] Steps S41 to S44 Specific Embodiments
[0054] The following describes the implementation manners of the present application through specific examples. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. The present application can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.
[0055] It should be noted that in the embodiments of the present application, words such as "optionally" or "for example" represent examples, illustrations or explanations. Any embodiment or design solution described as "optionally" or "for example" in the present application should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Exactly speaking, using words such as "optionally" or "for example" aims to present relevant concepts in a specific manner.
[0056] In the embodiments of the present application, "at least one" means one or more, and "a plurality of" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after. "At least one (item)" or its similar expression below refers to any combination of these items, including any combination of single item (item) or plural items (items). For example, at least one (item) of a, b or c can represent: a, b, c, a - b, a - c, b - c or a - b - c, where a, b, c can be single or multiple.
[0057] It should be noted that the drawings provided in the following embodiments only illustrate the basic concept of the present application in a schematic manner. Therefore, only the components related to the present application are shown in the drawings, rather than being drawn according to the number, shape and size of the components in actual implementation. The type, quantity and proportion of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.
[0058] To clearly describe the technical solutions of the embodiments of the present application, first, the nouns involved in the present application are defined:
[0059] AXI: Advanced eXtensible Interface (abbreviated as AXI), which is an advanced microcontroller bus architecture.
[0060] CRC: Cyclic Redundancy Check (abbreviated as CRC), which is a commonly used data transmission error detection technology in the field of data communication.
[0061] ISP: Image Signal Processor. It is a hardware or processing unit dedicated to processing image signals.
[0062] ROI: Region Of Interest. It refers to a specific region or object of particular interest in an image. These regions usually contain key information that one wants to identify, analyze, or process, and this region can be extracted for special processing.
[0063] IEEE: Institute of Electrical and Electronics Engineers. It is an international association of electronic technology and information science engineers.
[0064] IP: Intellectual Property. In the design of integrated circuits, it refers to an integrated circuit module that has been verified, can be reused, and has specific functions.
[0065] For automotive-related electronic products, unexpected failures may lead to various road accidents, seriously affecting the personal safety of drivers and passengers and having a huge social impact. Therefore, the functional safety design of automotive-related electronic products is very important. Image data may be interfered with during transmission and storage. To ensure the integrity and accuracy of the data read from the memory, it is necessary to perform error detection on the data when the image processing module receives the data. Cyclic redundancy check is a calculation method used to verify the accuracy of data transmission on a communication link. The communication parties agree on the verification standard. The sender first calculates the check code through the check polynomial, and the receiver performs the same calculation on the same data to obtain the check code. If the two check codes are inconsistent after comparison, it indicates that an error has occurred during the sending and storage processes. However, the conventional verification in the image transmission process has low stability and cannot adapt to different verification requirements.
[0066] At least for the above problems, an embodiment of the present application provides an image verification method based on a high-speed bus. The image verification method based on a high-speed bus includes: when storing image data in a memory, obtaining first verification data of a target area of the image to be verified; storing the first verification data in a register, the size of the register matching the size of the target area of the image to be verified, the target area including a region of interest, a row / column horizontal area, and a frame horizontal area, and matching the type of the target area according to the type of the image data; when reading the image to be verified from the memory, obtaining second verification data of the target area of the image to be verified; obtaining a verification result of the target area of the image to be verified by using the first verification data and the second verification data. If the verification result is that the first verification data and the second verification data are the same, it indicates that the image transmission is correct. If the verification result is that the first verification data and the second verification data are different, it indicates that the image transmission is incorrect.
[0067] In an embodiment of the present application, when the memory stores an image, the first verification data of the target area of the image to be verified is obtained and stored in a register. When the image is read from the memory, the second verification data of the target area of the image to be verified is obtained, and a verification result is obtained by analyzing the first verification data and the second verification data. The size of the register is matched with the size of the target area of the image to be verified, and the comparison result of the first verification data and the second verification data is used as the verification result. Such an image verification method based on a high-speed bus can meet various image verification requirements, perform real-time verification on image transmission, and improve the accuracy of data transmission.
[0068] Figure 1A Fig. shows a schematic diagram of an application scenario of the image verification method based on a high-speed bus according to the present application. The transmission verification device 1 can be used to implement the image verification method based on a high-speed bus provided by an embodiment of the present application, but the application scenario of the image verification method based on a high-speed bus provided by an embodiment of the present application is not limited to Figure 1A the shown transmission verification device 1. As Figure 1A shown, the transmission verification device 1 includes an image transmission device 11, an image verification device 12, and a display terminal 13. The image verification method based on a high-speed bus provided by an embodiment of the present application can be applied to the image verification device 12.
[0069] Among them, Figure 1A the image verification device 12 in includes an encoding device and a decoding device. The encoding device is used to obtain the first verification data. The decoding device includes a verification calculation unit and a result verification unit. The verification calculation unit is used to obtain the second verification data, and the result verification unit is used to obtain the verification result. The display terminal 13 is used to display the verification result. Although Figure 1AOnly one image transmission device 11, one image verification device 12, and one display terminal 13 are shown, but it should be understood that Figure 1A The examples in [the figure] are only for understanding the present solution. The specific numbers of the image verification device 12 and the display terminal 13 should be flexibly determined according to the actual situation, and the numbers of the specific encoding device and decoding device are not limited here either.
[0070] In some other implementation manners, the transmission verification device 1 may not include the display terminal 13, but only include the image verification device 12 with a display function and the image transmission device 11. The image verification method based on a high-speed bus provided in the embodiments of the present application can be applied to the image verification device 12. The image verification device 12 with a display function may include a tablet computer, a laptop computer, a personal digital assistant, a mobile phone, a personal computer, or may also be a monitoring device, a face recognition device, etc., which is not limited here.
[0071] In still some other implementation manners, the image verification method based on a high-speed bus described in the present application can be applied to an end-cloud interaction scenario. Figure 1B FIG. shows a schematic structural diagram of an end-cloud interaction scenario in the image verification method based on a high-speed bus. As Figure 1B shown, the end-cloud interaction system 2 includes a terminal 20 and a cloud server 21. Communication can be carried out between the terminal 20 and the cloud server 21, and the communication method is not limited to wired or wireless methods.
[0072] Among them, the terminal 20 can be mobile or fixed. For example, the terminal 20 can be a wireless terminal or a wired terminal. The wireless terminal can refer to a device with wireless transceiver functions, which can be deployed indoors, outdoors, and in industrial workshops. The terminal 20 can be a mobile phone, a tablet computer, a laptop computer, etc., which is not limited here. The cloud server 21 can include one or more servers, or include one or more processing nodes, or include one or more virtual machines running on the server. The cloud server 21 can also be referred to as a server cluster, a management platform, a data processing center, etc., which is not limited in the embodiments of the present application.
[0073] Next, the technical solutions in the embodiments of the present application will be described in detail with reference to the accompanying drawings in the embodiments of the present application.
[0074] The following embodiments of the present application provide an image verification method based on a high-speed bus. This method can be implemented, for example, by Figure 1A the image verification device 12 shown in [the figure] or Figure 1B the cloud server 21 shown in [the figure]. Figure 2 FIG. shows a schematic flow diagram of the image verification method based on a high-speed bus described in the embodiments of the present application. As Figure 2 shown, the image verification method based on a high-speed bus includes the following steps S11 to S14.
[0075] In step S11, when storing image data in the memory, obtain the first check data of the target area of the image to be checked.
[0076] In step S12, store the first check data in a register. The size of the register matches the size of the target area of the image to be checked. The target area includes the region of interest, the row / column horizontal area, and the frame horizontal area. Match the type of the target area according to the type of the image data.
[0077] In step S13, when reading the image to be checked from the memory, obtain the second check data of the target area of the image to be checked.
[0078] In step S14, use the first check data and the second check data to obtain the check result of the target area of the image to be checked. If the check result shows that the first check data and the second check data are the same, it indicates that the image transmission is correct. If the check result shows that the first check data and the second check data are different, it indicates that the image transmission is incorrect.
[0079] In some possible implementation manners, when the image signal processing module outputs image data and stores it in the memory, calculate the CRC value of the first check data for the target area of the image to be checked. Save the CRC value of the first check data to the corresponding register. The size of the register matches the size of the target area of the image to be checked. The target area includes the region of interest, the row / column horizontal area, and the frame horizontal area. Different types of image data indicate different amounts of data carried by the target area of the image to be checked. Match the type of the target area according to the type of the image data. For example, in the pedestrian / vehicle detection scenario, the image data is the data captured by the front-view camera, and the target area is matched to the region of interest for checking the region of interest where the pedestrian / vehicle is located. Another example is in the autonomous driving image verification scenario, the image data is the lidar point cloud data, and the target area is matched to the row / column horizontal area for checking the row / column horizontal area of the lidar point cloud data. Another example is in the autonomous driving image verification scenario, the image data is the panoramic fusion data, and the target area is matched to the frame horizontal area for checking the frame horizontal area of the panoramic fusion data. By flexibly configuring the register to match various image verification requirements and scenarios, the verification accuracy is improved while reducing the image verification cost. The above is only to illustrate the target area matching method of the present application, and the specific application scenarios are not limited thereto.
[0080] When the image signal processing module reads the image to be verified from the memory, it obtains the second verification data of the target area of the image to be verified. The first verification data and the second verification data are compared to determine whether they are consistent. If they are not consistent, it indicates that there is an error in the writing and reading processes of the image to be verified, and the error needs to be reported to the system for processing. If they are consistent, it indicates that there is no error in the writing and reading processes of the image to be verified.
[0081] In the embodiment of the present application, when the memory stores an image, the first verification data of the target area of the image to be verified is obtained and stored in a register. When the image is read from the memory, the second verification data of the target area of the image to be verified is obtained, and the verification result is obtained by analyzing the first verification data and the second verification data. A register of a corresponding size is used to match the size of the target area of the image to be verified, and the comparison result of the first verification data and the second verification data is used as the verification result. This image verification method can meet various image verification requirements, perform real-time verification on image transmission, and improve the accuracy of data transmission.
[0082] In an embodiment of the present application, the first verification data and the second verification data are verification data based on 8-bit, 16-bit, or 32-bit cyclic redundancy check, and the check level of the cyclic redundancy check is determined according to the data volume of the image data.
[0083] In some possible implementation manners, the first verification data and the second verification data calculate the CRC value based on 8 bits, 16 bits, or 32 bits according to actual requirements. For example, the data volume of a frame of image data can reach 256 Mbit, and the check bits of 32-bit CRC are 32 bits. Theoretically, the error ratio is 2 -32 , that is, an undetected error may occur in a data packet of 4.2 Gbit. Using CRC32 for detection can ensure the accuracy of image verification. Another example is that the error ratio that CRC16 cannot detect is 2 -16 , which is equivalent to that there is an undetectable error in about 66 Mbit of image data. Using CRC16 for row / column level or column level detection can also ensure the accuracy of image verification. Another example is that the error ratio that CRC8 cannot detect is 2 -8 , which is equivalent to that there is an undetectable error in about 256 bit of image data. Using CRC8 for detection of a small region of interest can also ensure the accuracy of image verification.
[0084] In the embodiment of the present application, the number of bits corresponding to the cyclic redundancy check is flexibly selected according to the size of the verification target area, which can realize flexible adaptation of image verification and avoid verification errors or waste of data resources.
[0085] Figure 3It is a schematic flowchart showing the method for verifying regions of interest based on a high-speed bus according to an embodiment of the present application. As Figure 3 shown, the target region includes a region of interest, and the method for verifying regions of interest based on a high-speed bus includes the following steps S21 to S24.
[0086] Step S21: When storing image data in a memory, obtain first verification data for the region of interest of the image to be verified.
[0087] Step S22: Store the first verification data in a register that matches the region of interest.
[0088] Step S23: When reading the image to be verified from the memory, obtain second verification data for the region of interest of the image to be verified.
[0089] Step S24: Use the first verification data and the second verification data to obtain a verification result for the region of interest of the image to be verified.
[0090] In some possible implementation manners, the target region includes a region of interest. When the image signal processing module outputs image data and stores it in the memory, calculate the CRC value of the first verification data for the region of interest of the image to be verified. Save the CRC value of the first verification data to the corresponding register. The size of the register matches the size of the region of interest of the image to be verified. Configure the window size of the region of interest using the register, and set the region of interest based on the row and column positions of one frame of the image to be verified.
[0091] When the image signal processing module reads the image to be verified from the memory, obtain second verification data for the region of interest of the image to be verified. Compare the first verification data and the second verification data to determine whether they are consistent. If they are not consistent, it indicates that there is an error in the writing and reading processes of the image to be verified, and the error needs to be reported to the system for processing. If they are consistent, it indicates that there is no error in the writing and reading processes of the image to be verified.
[0092] Figure 4 It is a schematic flowchart showing the method for verifying row / column horizontal region images based on a high-speed bus according to an embodiment of the present application. As Figure 4 shown, the target region includes a row / column horizontal region, and the method for verifying row / column horizontal region images based on a high-speed bus includes the following steps S31 to S34.
[0093] Step S31: When storing image data in a memory, obtain first verification data for the row / column horizontal region of the image to be verified.
[0094] Step S32: Store the first verification data in a register that matches the row / column horizontal region.
[0095] In step S33, when reading the image to be verified from the memory, obtain the second verification data of the row / column horizontal region of the image to be verified.
[0096] In step S34, obtain the verification result of the row / column horizontal region of the image to be verified by using the first verification data and the second verification data.
[0097] In some possible implementation manners, the target region includes the row / column horizontal region. When the image signal processing module outputs image data and stores it in the memory, calculate the CRC value of the first verification data for the row / column horizontal region of the image to be verified. Save the CRC value of the first verification data into the corresponding register, where the size of the register matches the size of the row / column horizontal region of the image to be verified, and determine the position of the row / column horizontal region by using the position of the row / column horizontal region in a frame of the image to be verified. When the image signal processing module reads the image to be verified from the memory, obtain the second verification data of the row / column horizontal region of the image to be verified.
[0098] Each time a verification data is calculated, it is saved in the corresponding register. When reading the image to be verified from the memory, obtain the second verification data of the corresponding row / column horizontal region, and compare the first verification data read from the register with the second verification data to determine whether the first verification data and the second verification data are consistent. If they are not consistent, it indicates that there is an error in the writing and reading processes of the image to be verified, and the error needs to be reported to the system for processing. If they are consistent, it indicates that there is no error in the writing and reading processes of the image to be verified.
[0099] Figure 5 Shown is a schematic flowchart of the frame horizontal region verification method based on a high-speed bus according to an embodiment of the present application. As Figure 5 shown, the target region includes the frame horizontal region, and the frame horizontal region verification method based on a high-speed bus includes the following steps S41 to S44.
[0100] In step S41, when storing image data in the memory, obtain the first verification data of the region of interest of the image to be verified.
[0101] In step S42, store the first verification data in a register that matches the frame horizontal region.
[0102] In step S43, when reading the image to be verified from the memory, obtain the second verification data of the frame horizontal region of the image to be verified.
[0103] In step S44, obtain the verification result of the frame horizontal region of the image to be verified by using the first verification data and the second verification data.
[0104] In some possible implementation manners, when the image signal processing module outputs image data and stores it in the memory, the first check data CRC value is calculated for the frame horizontal area of the image to be checked. The first check data CRC value is saved in the corresponding register, and the size of the register matches the size of the frame horizontal area of the image to be checked.
[0105] When the image signal processing module reads the image to be checked from the memory, the second check data of the frame horizontal area of the image to be checked is obtained. The first check data and the second check data are compared to determine whether the first check data and the second check data are consistent. If they are not consistent, it indicates that there is an error in the writing and reading processes of the image to be checked, and the error needs to be reported to the system for processing. If they are consistent, it indicates that there is no error in the writing and reading processes of the image to be checked.
[0106] In an embodiment of the present application, the image check method based on the high-speed bus includes: performing image check on the region of interest or the row / column horizontal area based on 16-bit cyclic redundancy check, and performing image check on the frame horizontal area based on 32-bit cyclic redundancy check.
[0107] In some possible implementation manners, the register occupied by the target area of the image to be checked, which is the region of interest or the row / column horizontal area, is relatively small, and the 16-bit cyclic redundancy check can meet the check requirements and avoid check errors. For example, the error ratio that cannot be detected by 16-bit CRC is 2 -16 which means that there will be an undetectable error in approximately 66 Mbit of image data. Using 16-bit CRC for detection of the region of interest, row / column horizontal or column horizontal can ensure the accuracy of image check. Another example is that the error ratio that cannot be detected by 32-bit CRC is 2 -32 which means that there will be an undetectable error in approximately 4.2 Gbit of image data. Using 32-bit CRC for detection of the frame horizontal area can also ensure the accuracy of image check.
[0108] In an embodiment of the present application, the image check method based on the high-speed bus further includes: performing data transmission based on the on-chip bus AXI protocol, and the data transmission includes storing and reading image data in the memory, obtaining check data and check results.
[0109] If the receiving end and the sending end adopt different communication protocols respectively, when the receiving end receives the image data and the first check data from the sending end, it is necessary to convert according to the data transmission timing of the sending end or add an interface for transmitting the check data to ensure that the timing of the second check data obtained at the receiving end is consistent with that of the first check data. This will increase additional resources. If the timing conversion is incorrect, the reliability of data verification cannot be guaranteed. In some possible implementation manners, when the image signal processing module outputs image data and stores it in the memory, when the image signal processing module reads image data from the memory, and when obtaining the first check data and the second check data, these four data paths are all based on the on-chip bus AXI protocol for data transmission. Adopting the on-chip bus AXI protocol ensures that the timing and coding method of the image data received when obtaining the first check data and the second check data are the same as those of the transmitted image data, without the need to agree on additional data transmission timing, which is more convenient for obtaining the first check data and the second check data. At the same time, the receiving end receives the data transmitted by the sending end through the on-chip bus AXI protocol, and the processing is also based on the on-chip bus AXI protocol, which is more convenient for IP integration between modules.
[0110] In some other possible implementation manners, the image verification method based on the high-speed bus is also applicable to two IP interfaces that use the same interface protocol for transmission, and the communication interface protocol includes but is not limited to on-chip and off-chip communication protocol buses.
[0111] In the embodiments of the present application, image verification is performed using the on-chip bus AXI protocol interface, which is applicable to different burst transmission lengths.
[0112] Figure 6 Shown is a schematic structural diagram of the image verification device according to the embodiments of the present application. As Figure 6 shown, the image verification device 100 includes an encoder 110, a register 120, and a decoder 130.
[0113] The encoder 110 is configured to process the image data when the image data is stored to obtain the first check data.
[0114] The register 120 is configured to store the first check data and generate a control signal to be sent to the decoder. The size of the register matches the size of the image data verification area. The target area includes the region of interest, the row / column horizontal area, and the frame horizontal area, and the type of the target area is matched according to the type of the image data.
[0115] The decoder 130 is configured to process the image data when the image data is read to obtain the second check data. And it is configured to read the first check data stored in the register, and use the first check data and the second check data to obtain the verification result of the image data.
[0116] In some possible implementation manners, the image verification device 100 includes an encoder 110, a register 120, and a decoder 130. The output image data of the image signal processing module first passes through an AXI buffer to generate two paths of image data. One path is stored in the memory, and the other path is sent to the encoder 110 of the image verification device 100. The encoder 110 is used to calculate the image data when the image data is stored in the memory to obtain first verification data for the target area of the image data. The register 120 is used to store the first verification data and generate a control signal to be sent to the decoder 130. When the image signal processing module reads the image data from the memory, it also first passes through the AXI buffer to generate two paths of image data. One path is sent into the image signal processing module, and the other path is sent to the decoder 130. The decoder 130 is used to process the image data when the image data is read to obtain second verification data. And it is used to read the first verification data stored in the register 120, and use the first verification data and the second verification data for comparison to determine whether the first verification data and the second verification data are consistent. If they are not consistent, it means that there is an error in the writing and reading processes of the image data, and the error needs to be reported to the system for processing. If they are consistent, it means that there is no error in the writing and reading processes of the image data.
[0117] In some other possible implementation manners, Figure 7 It shows a schematic structural diagram of the encoder described in the embodiment of the present application. As Figure 7 shown, the encoder 110 includes an encoding control module 111 and an encoding calculation module 112. The encoding control module 111 is used to select the target area to be verified in a frame of image, and control the CRC verification calculation process, such as the inversion of input data, calculating the first verification data according to the CRC32 polynomial, the inversion and exclusive OR operation of output data, etc. The encoding calculation module 112 is used to process the target area of the image data to obtain the first verification data.
[0118] Figure 8 It shows a schematic structural diagram of the decoder described in the embodiment of the present application. As Figure 8 shown, the decoder 130 includes a decoding control module 131, a decoding calculation module 132, and a verification module 133.
[0119] The decoding control module 131 is used to locate the target area of the image data that needs to be verified.
[0120] The decoding calculation module 132 is used to process the target area of the image data to obtain the second verification data.
[0121] The verification module 133 is used to read the first verification data in the register, and use the first verification data and the second verification data to obtain the verification result of the image data.
[0122] In some possible implementations, the decoder 130 includes a decoding control module 131, a decoding calculation module 132, and a verification module 133. The decoding control module 131 is used to select a target area in a frame of image that needs to be verified, and control the CRC verification calculation process, such as inversion of input data, calculation of second verification data according to the CRC32 polynomial, inversion and exclusive OR operation of output data, etc. The decoding calculation module 132 is used to process the target area of the image data to obtain the second verification data. The verification module 133 is used to read the first verification data in the register 120, and check whether there is an error in the image data by using the first verification data and the second verification data.
[0123] Figure 9 Shown is a schematic structural diagram of the chip described in the embodiments of the present application. As Figure 9 shown, the chip 200 includes an image signal processing module 210, an image verification device 100, and a memory 220.
[0124] The image signal processing module 210 is used to write the transmitted image into the memory or read the transmitted image from the memory by using the on-chip bus.
[0125] The image verification device 100 is used to verify the transmitted image by using the image verification method based on the high-speed bus according to any one of the embodiments of the present application.
[0126] The memory 220 is used to receive and store the transmitted image.
[0127] In some possible implementations, the chip 200 includes an image signal processing module 210, an image verification device 100, and a memory 220. The image signal processing module 210 is used to write the transmitted image into the memory or read the transmitted image from the memory by using the on-chip bus. The image verification device 100 is used to verify the transmitted image by using the image verification method based on the high-speed bus according to any one of the embodiments of the present application. The memory 220 is used to receive and store the transmitted image.
[0128] In some other possible implementation manners, in the image verification method based on a high-speed bus, the target area of the image data includes three CRC verification levels, namely the region of interest, the row / column horizontal region, and the frame horizontal region, making the data transmission verification of the image signal processing module more flexible. The CRC verification level is selected according to the image data type. For example, if there are areas in the image that require special attention or special processing, in the vehicle driving scenario, the image signal processing module 210 of the chip 200 performs target detection or object tracking tasks, and key information is identified, analyzed, or processed by setting the region of interest. Another example is that for image data distributed in rows or columns, such as barcodes and spectra, targeted verification of the image data can be performed by setting the CRC row / column verification level. Still another example is that if one wants to verify the image data of a frame, the CRC frame level verification can be set.
[0129] When setting multiple regions of interest or row / column horizontal regions, the image verification device 100 performs real-time checks on the corresponding regions of interest or row / column horizontal regions. Once an image transmission error is detected, it can be immediately reported for processing without waiting for the end of the transmission of a frame of image, realizing real-time monitoring of image transmission. When verifying multiple regions of interest or row / column horizontal regions, it is also possible to determine which region of interest or row / column horizontal region has a transmission error according to the verification result, facilitating precise processing of the error.
[0130] In several embodiments provided in the present application, it should be understood that the disclosed system, device, or method can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of modules / units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple modules or units can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed mutual coupling, direct coupling, or communication connection may be through some interfaces. The indirect coupling or communication connection of devices, modules, or units can be in an electrical, mechanical, or other form.
[0131] The modules / units described as separate components may or may not be physically separated. The components shown as modules / units may or may not be physical modules, that is, they can be located in one place or distributed to multiple network units. Some or all of the modules / units can be selected according to actual needs to achieve the purpose of the embodiments of the present application. For example, in each embodiment of the present application, the various functional modules / units can be integrated in a processing module, or each module / unit can exist physically alone, or two or more modules / units can be integrated in one module / unit.
[0132] Those of ordinary skill in the art should further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.
[0133] The embodiments of this application also provide a computer-readable storage medium. A programmable logic program is stored on the computer-readable storage medium, and when the program is executed by a programmable logic device, it implements the image verification method based on a high-speed bus described in any one of the embodiments of this application.
[0134] The terms "component", "module", "system", etc. used in this specification are used to represent computer-related entities, hardware, firmware, combinations of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. By way of illustration, both an application running on a computing device and the computing device can be components. One or more components can reside in a process and / or an execution thread, and the components can be located on one computer and / or distributed between two or more computers. In addition, these components can be executed from various computer-readable media on which various data structures are stored. Components can communicate, for example, through local and / or remote processes according to signals having one or more data packets (such as data from two components interacting with another component between a local system, a distributed system, and / or a network, such as the Internet interacting with other systems through signals).
[0135] The descriptions of the processes or structures corresponding to the above respective drawings have their own focuses. For parts not detailed in a certain process or structure, reference can be made to the relevant descriptions of other processes or structures.
[0136] The above embodiments are only illustrative of the principles and effects of this application, rather than limiting this application. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed in this application should still be covered by the claims of this application.
Claims
1. An image verification method based on a high-speed bus, characterized in that, Including: When storing image data in a memory, obtaining first check data of a target area of an image to be checked; Storing the first check data in a register, the size of the register matching the size of the target area of the image to be checked, the target area including a region of interest, a row / column horizontal area, and a frame horizontal area, and matching the type of the target area according to the type of the image data; When reading the image to be checked from the memory, obtaining second check data of the target area of the image to be checked; Obtaining a check result of the target area of the image to be checked by using the first check data and the second check data. If the check result shows that the first check data and the second check data are the same, it indicates that the image transmission is correct. If the check result shows that the first check data and the second check data are different, it indicates that the image transmission is incorrect.
2. The image verification method based on a high-speed bus according to claim 1, wherein The first check data and the second check data are check data based on 8-bit, 16-bit, or 32-bit cyclic redundancy check, and the check level of the cyclic redundancy check is determined according to the data volume of the image data.
3. The image verification method based on a high-speed bus according to claim 1, characterized in that The target area includes a region of interest. Checking the region of interest includes: When storing image data in a memory, obtaining first check data of the region of interest of the image to be checked; Storing the first check data in a register matching the region of interest; When reading the image to be checked from the memory, obtaining second check data of the region of interest of the image to be checked; Obtaining a check result of the region of interest of the image to be checked by using the first check data and the second check data.
4. The image verification method based on a high-speed bus according to claim 1, wherein The target area includes a row / column horizontal area. Checking the row / column horizontal area includes: When storing image data in a memory, obtaining first check data of the row / column horizontal area of the image to be checked; Storing the first check data in a register matching the row / column horizontal area; When reading the image to be checked from the memory, obtaining second check data of the row / column horizontal area of the image to be checked; Obtaining a check result of the row / column horizontal area of the image to be checked by using the first check data and the second check data.
5. The image verification method based on a high-speed bus according to claim 1, wherein The target area includes a frame horizontal area. Checking the frame horizontal area includes: When storing image data in a memory, obtaining first check data of the region of interest of the image to be checked; Storing the first check data in a register matching the frame horizontal area; When reading the image to be checked from the memory, obtaining second check data of the frame horizontal area of the image to be checked; Obtaining a check result of the frame horizontal area of the image to be checked by using the first check data and the second check data.
6. The image verification method based on a high-speed bus according to any one of claims 3 to 5, characterized in that Including: Performing image check on the region of interest or the row / column horizontal area based on 16-bit cyclic redundancy check, and performing image check on the frame horizontal area based on 32-bit cyclic redundancy check.
7. The image verification method based on a high-speed bus according to claim 1, wherein It also includes data transmission based on the on-chip bus AXI protocol, and the data transmission includes storing and reading image data in the memory, obtaining check data, and the check result.
8. An image verification device, characterized in that, Including: An encoder for processing the image data when the image data is stored to obtain first check data; A register for storing the first check data and generating a control signal to be sent to a decoder, the size of the register matching the size of the check area of the image data, the target area including a region of interest, a row / column horizontal area, and a frame horizontal area, and matching the type of the target area according to the type of the image data; A decoder for processing the image data when the image data is read to obtain second check data; And For reading the first check data stored in the register, obtaining a check result of the image data by using the first check data and the second check data. If the check result shows that the first check data and the second check data are the same, it indicates that the image transmission is correct. If the check result shows that the first check data and the second check data are different, it indicates that the image transmission is incorrect.
9. A chip, characterized in that, Comprising: An image signal processing module for writing a transmitted image into a memory or reading the transmitted image from the memory by using an on-chip bus; An image check device for checking the transmitted image by using the image check method based on a high-speed bus according to any one of claims 1 to 7; And A memory for receiving and storing the transmitted image.
10. A computer-readable storage medium having a programmable logic program stored thereon, characterized in that, When the program is executed by a programmable logic device, it implements the image check method based on a high-speed bus according to any one of claims 1 to 7.