Operating system memory management method compatible with multiprocessor architecture
By defining the page table structure and step-by-step mapping relationship, the memory management differences between different processor architectures are solved, and the compatibility and security improvement of cross-platform memory management is achieved.
Patent Information
- Application Number
- CN202510004728.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-02
- Publication Date
- 2025-07-11
AI Technical Summary
When existing operating systems support ARMv8 and RISC-V architectures across platforms, they face the problem of large differences in memory management mechanisms, which leads to difficulty in adaptation.
Define the page table structure and establish a mapping relationship between virtual addresses and physical addresses through step by step traversal, store it in the memory management unit, and start the memory management unit through registers for address conversion, supporting memory management in the multiprocessor architecture.
It realizes compatibility of different processor architectures, improves memory access speed and system security, and facilitates cross-platform memory management.
Smart Images
Figure CN120295933A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of memory management, and particularly to an operating system memory management method. Background Art
[0002] In the current embedded environment, in different processor architectures such as ARMv8, RISC-V, etc. in mainstream hardware platforms, as Figure 1 shown, their memory management mechanisms are all implemented by means of the processor core 1 and the Memory Management Unit (MMU) 2. The MMU includes two units, namely the Translation Lookaside Buffer (TLB) 21 and the Translation Walk Unit (TWU) 22. The TLB is a cache for caching the results of page table conversion, so as to shorten the time for page table query. The MMU translates the input virtual address into the corresponding physical address and corresponding page table attributes and memory access permissions and other information, and finally caches it in the main memory 3 at a high speed.
[0003] Although both the ARMv8 and RISC-V architectures provide memory management and protection functions, due to the differences in register naming, architecture exception levels, memory isolation protection mechanisms, etc. between the two, existing operating systems often face great challenges when performing cross-platform support. Specifically, when an operating system needs to support both the ARMv8 and RISC-V architectures at the same time, a large amount of time and resources are often required to implement the adaptation of the memory management function. Summary of the Invention
[0004] The purpose of the present invention is to provide an operating system memory management method compatible with multiple processor architectures to solve the above technical problems;
[0005] An operating system memory management method compatible with multiple processor architectures includes:
[0006] Step S1, defining a page table structure according to the virtual address bit width and paging model of the processor architecture, and the page table structure includes a plurality of page table entries;
[0007] Step S2, defining a page table data structure according to the width of the page table entry;
[0008] Step S3, establishing a page table mapping relationship from the virtual address to the physical address by traversing the page table data structure step by step;
[0009] Step S4, storing the page table mapping relationship in the memory management unit, and starting the memory management unit through a register to convert the virtual address into the physical address.
[0010] Preferably, the page table entry in step S1 includes a page global directory, a page upper directory, a page middle directory, and a page table;
[0011] The page global directory is the highest-level page table entry and is used to map the virtual address space to the physical address space;
[0012] The page upper directory is used to connect the page global directory and the page middle directory;
[0013] The page middle directory is used to connect the page upper directory and the page table;
[0014] The page table is the lowest-level page table entry.
[0015] Preferably, the width of the page table entry in step S2 is 64 bits, and the page table data structure is obtained by defining it with an unsigned integer type.
[0016] Preferably, step S3 includes
[0017] Step S31: Parse the virtual address step by step through the index entry of the page table data structure, and locate each level of the page table entry in turn;
[0018] Step S32: Traverse each level of the page table entry and initialize it to establish the page table mapping relationship from the virtual address to the physical address.
[0019] Preferably, in step S32,
[0020] When the page table entry is the page global directory, use the memory length corresponding to the index entry of the page global directory as the step size to check whether the entry content of the page global directory is empty. If it is, allocate a physical memory page for the next-level page table and store the physical memory page in the entry of the page global directory. If not, directly perform mapping through the page table entry.
[0021] Preferably, in step S32,
[0022] When the page table entry is the page upper directory, use the memory length corresponding to the index entry of the page upper directory as the step size to check whether the entry content of the page upper directory is empty. If it is, allocate the physical memory page for the next-level page table and store the physical memory page in the entry of the page upper directory. If not, directly perform mapping through the page table entry.
[0023] Preferably, in step S32,
[0024] When the page table entry is the page middle directory, taking the memory length corresponding to the index entry of the page middle directory as the step size, check whether the entry content of the page middle directory is empty. If it is, allocate the physical memory page for the next-level page table and store the physical memory page into the entry of the page middle directory. If not, directly perform mapping through the page table entry.
[0025] Preferably, in step S32,
[0026] When the page table entry is the page table, taking the page size as the step size, traverse each virtual page through a while loop, and map the virtual address to the corresponding physical address.
[0027] Preferably, the processor architecture in step S1 includes the ARM architecture and the RISC-V architecture.
[0028] Preferably, the registers in step S4 include a first register and a second register;
[0029] Start the memory management unit through the first register to perform address translation for the ARM architecture;
[0030] Start the memory management unit through the second register to perform address translation for the RISC-V architecture.
[0031] The beneficial effects of the present invention are: solving the problem that the memory management mechanisms in different processor architectures vary greatly, being able to be compatible with the memory management of different processor architectures, and improving convenience and security. Description of the Drawings
[0032] Figure 1 is the processor memory management structure of the prior art;
[0033] Figure 2 is the step diagram of the operating system memory management method for compatible multi-processor architectures of the present invention;
[0034] Figure 3 is the schematic diagram of step S3 of the present invention;
[0035] Figure 4 is the schematic diagram of the ARMv8 AArch64 page granularity and RISC-V Sv48 page table index of the present invention;
[0036] Figure 5 is the schematic diagram of the division of the paging model in a 64-bit virtual address of the present invention;
[0037] Figure 6 is the schematic diagram of the operation of the operating system memory management for compatible multi-processor architectures of the present invention.
[0038] In the accompanying drawings: 1. Processor core; 2. Memory management unit; 21. Translation lookaside buffer; 22. Page table traversal subunit; 3. Main memory; 4. First register; 5. Second register; 6. L0 page table; 61. L0 page table index; 62. PGD index; 7. L1 page table; 71. L1 page table index; 72. PUD index; 8. L2 page table; 81. L2 page table index; 82. PMD index; 9. L3 page table; 91. L3 page table index; 92. PT index; 10. Page offset. Detailed implementation manners
[0039] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.
[0040] It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments may be combined with each other.
[0041] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but it is not a limitation of the present invention.
[0042] An operating system memory management method compatible with a multi-processor architecture, as Figure 2 、 Figure 6 shown, includes
[0043] Step S1: Define a page table structure according to the virtual address bit width and paging model of the processor architecture, and the page table structure includes a plurality of page table entries;
[0044] Step S2: Define a page table data structure according to the width of the page table entry;
[0045] Step S3: Establish a page table mapping relationship from the virtual address to the physical address by traversing the page table data structure level by level;
[0046] Step S4: Store the page table mapping relationship into the memory management unit 2, and start the memory management unit 2 through the register to convert the virtual address into a physical address.
[0047] Specifically, the present invention provides an operating system memory management method compatible with multiple processor architectures. By storing the page table mapping relationship in the MMU and automatically completing address translation through hardware, the memory management work of the operating system is greatly reduced, reducing the computational burden of the operating system. The speed of memory access is improved, and the processor can access memory faster. It solves the problem of large differences in memory management mechanisms in different processor architectures, can be compatible with the memory management of different processor architectures, and improves convenience and security.
[0048] In a preferred embodiment, the processor architectures in step S1 include the ARM architecture and the RISC-V architecture.
[0049] Specifically, according to the virtual address bit width of the processor, the page sizes supported by the ARMv8 AArch64 execution state architecture are 4KB, 16KB, and 64KB, and the RISC-V architecture supports three address translation mechanisms, Sv32, Sv39, and SV48, when the page size is 4KB.
[0050] ARMv8 is a high-performance and widely used processor architecture, especially in the fields of mobile devices, embedded systems, and servers. In the ARMv8 architecture, the control registers related to address translation mainly include the translation control register, the system control register, and the translation page table base address register, etc.
[0051] RISC-V is an open-source and modular instruction set architecture designed to provide flexibility for academic research and industrial applications, and it is also a currently widely used processor architecture. In the RISC-V architecture, the control register related to address translation is mainly the address translation protection register (atp). In addition, RISC-V also provides physical memory attributes and physical memory protection technologies to check and protect physical memory access, and these two mechanisms can work simultaneously.
[0052] Among them, when the AArch64 page size is 4KB, the virtual address division is the same as that of the RISC-V Sv48 address mapping, as Figure 4 shown, and it is divided into L0 page table index 61, L1 page table index 71, L2 page table index 81, L3 page table index 91, and page offset 10 according to the common page table structure.
[0053] In a preferred embodiment, the page table entries in step S1 include the page global directory, the page upper directory, the page middle directory, and the page table;
[0054] The page global directory is the highest-level page table entry, used to map the virtual address space to the physical address space;
[0055] The page upper directory is used to connect the page global directory and the page middle directory;
[0056] The middle page directory is used to connect the upper page directory and the page table;
[0057] The page table is the lowest-level page table entry.
[0058] Specifically, referring to Figure 5 , a page table definition method similar to that of the Linux kernel is adopted, that is, a four-level paging model: Page Global Directory (PGD), Page Upper Directory (PUD), Page Middle Directory (PMD), and Page Table (PT).
[0059] Figure 5 In [reference], Bit[11:0] represents the page offset 10, Bit[20:12] represents the PT index 92, Bit[29:21] represents the PMD index 82, Bit[38:30] represents the PUD index 72, and Bit[47:39] represents the PGD index 62.
[0060] The four-level paging model makes the management of the virtual address space more flexible and efficient. Each level of the page table corresponds to a different range of the virtual address space. Through hierarchical mapping (from PGD to PUD, PMD, and then to PT), fine-grained management of the virtual address space is achieved. Each level of the paging table can be mapped with different granularities according to needs, thus effectively reducing memory fragmentation and waste.
[0061] Through hierarchical paging, each level of the page table can be optimized according to different requirements (such as mapping pages of different sizes). For example, the page table entry can map large pages (Huge Pages) such as 2MB and 1GB. These large pages can reduce TLB misses and the overhead of page lookup, thereby improving the memory access efficiency.
[0062] Under modern virtualization technologies and multi-core processor architectures, the four-level paging model can effectively support the address translation and memory isolation of virtual machines. The virtualization system needs to map the virtual address space to different physical memory regions, and through the multi-level page table, this conversion can be efficiently performed while ensuring the address space isolation between each virtual machine.
[0063] In a preferred embodiment, the width of the page table entry in step S2 is 64 bits, and the page table data structure is obtained through an unsigned integer type definition.
[0064] Specifically, in step S2, the page table is represented by pte_t, the middle page directory is represented by pmd_t, the upper page directory is represented by pud_t, and the global page directory is represented by pgd_t.
[0065] Since the width of the page table entries of the page tables from L0 to L3 is 64 bits, the unsigned long type in C language can be used to describe them. Use the data structure pte_t to represent a PT, pmd_t to represent a PMD page table entry, pud_t to represent a PUD page table entry, and pgd_t to represent a PGD page table entry.
[0066] In a preferred embodiment, referring to Figure 3 , step S3 includes
[0067] Step S31, gradually parse the virtual address through the index entries of the page table data structure, and locate each level of page table entry in turn;
[0068] Step S32, traverse each level of page table entry and initialize it to establish the page table mapping relationship from the virtual address to the physical address.
[0069] In a preferred embodiment, in step S32,
[0070] When the page table entry is a page global directory, use the memory length corresponding to the index entry of the page global directory as the step size to check whether the entry content of the page global directory is empty. If so, allocate a physical memory page for the next-level page table and store the physical memory page in the entry of the page global directory. If not, directly perform mapping through the page table entry.
[0071] Specifically, in the function for creating the page table mapping, use the memory length corresponding to each PGD index entry as the step size to traverse the virtual memory area to be mapped in the PGD page table. During the traversal, initialize the PGD page table entry content and PUD through the PGD index entry initialization function. In the PGD initialization function, if the content of the current PGD page table entry is empty, it means that the next-level page table has not been created yet. First, use the physical page allocation function to allocate a page for the PUD page table, and then set the page into the corresponding PGD page table entry.
[0072] In a preferred embodiment, in step S32,
[0073] When the page table entry is a page upper directory, use the memory length corresponding to the index entry of the page upper directory as the step size to check whether the entry content of the page upper directory is empty. If so, allocate a physical memory page for the next-level page table and store the physical memory page in the entry of the page upper directory. If not, directly perform mapping through the page table entry.
[0074] Specifically, taking the memory length corresponding to each PUD index entry as the step size, traverse the virtual memory area to be mapped in the PUD page table. During the traversal, initialize the content of the PUD page table entry and the PMD through the PUD index entry initialization function. In the PUD initialization function, if the content of the current PUD page table entry is empty, it indicates that the next-level page table has not been created yet. First, use the physical page allocation function to allocate a page for the PMD page table, and then set the page into the corresponding PUD page table entry.
[0075] In a preferred embodiment, in step S32,
[0076] When the page table entry is a page middle directory, taking the memory length corresponding to the index entry of the page middle directory as the step size, check whether the content of the entry in the page middle directory is empty. If it is, allocate a physical memory page for the next-level page table and store the physical memory page into the entry in the page middle directory. If not, directly perform mapping through the page table entry.
[0077] Specifically, taking the memory length corresponding to each PMD index entry as the step size, traverse the virtual memory area to be mapped in the PMD page table. During the traversal, initialize the content of the PMD page table entry and the PT through the PMD index entry initialization function. In the PMD initialization function, if the content of the current PMD page table entry is empty, it indicates that the next-level page table has not been created yet. First, use the physical page allocation function to allocate a page for the PT page table, and then set the page into the corresponding PMD page table entry.
[0078] In a preferred embodiment, in step S32,
[0079] When the page table entry is a page table, taking the page size as the step size, traverse each virtual page through a while loop, and map the virtual address to the corresponding physical address.
[0080] Specifically, taking PAGE_SIZE, that is, 4KB in size, as the step size, set the mapping of the PT index through a while loop.
[0081] In a preferred embodiment, in step S4, the register includes a first register and a second register;
[0082] Start the memory management unit 2 through the first register to perform address translation for the ARM architecture;
[0083] Start the memory management unit 2 through the second register to perform address translation for the RISC-V architecture.
[0084] Specifically, after creating the page table, it is necessary to set the system register to turn on the MMU and start the translation of virtual addresses.
[0085] Refer toFigure 6 The red arrow indicates ARM address translation, and the blue arrow indicates RISC-V address translation. The first register 4 is the TTBR (Translation Table Base Register), and the second register 5 is the atp (Address Translation Protection Register). The memory management unit 2 is started through the registers.
[0086] Taking the memory length corresponding to the L0 page table index 61 as the step size, traverse the virtual memory area to be mapped in the L0 page table 6. During the traversal, initialize the PGD page table entry content and PUD through the L0 page table index 61 initialization function. In the PGD initialization function, if the content of the current L0 page table 6 is empty, it indicates that the next-level page table has not been created. First, use the physical page allocation function to allocate a page for the L1 page table 7, and then set the page into the corresponding L0 page table 6.
[0087] Taking the memory length corresponding to the L1 page table index 71 as the step size, traverse the virtual memory area to be mapped in the L1 page table 7. During the traversal, initialize the L1 page table 7 content and PMD through the L1 page table index 71 initialization function. In the PUD initialization function, if the content of the current L1 page table 7 is empty, it indicates that the next-level page table has not been created. First, use the physical page allocation function to allocate a page for the L2 page table 8, and then set the page into the corresponding L1 page table 7.
[0088] Taking the memory length corresponding to the L2 page table index 81 as the step size, traverse the virtual memory area to be mapped in the L2 page table 8. During the traversal, initialize the L2 page table 8 content and PT through the L2 page table index 81 initialization function. In the PMD initialization function, if the content of the current L2 page table 8 is empty, it indicates that the next-level page table has not been created. First, use the physical page allocation function to allocate a page for the L3 page table 9, and then set the page into the corresponding L2 page table 8.
[0089] Finally, set the mapping of the L3 page table index 91 through a while loop.
[0090] The present invention provides a unified underlying software interface for memory management under different computer architectures, enabling cross-platform system software to call a unified software layer interface when implementing memory management functions, thereby shielding the hardware differences of different architecture development environments, bringing convenience to multi-platform system development, and at the same time enhancing the security and reliability of the system.
[0091] The above are only the preferred embodiments of the present invention, and do not limit the implementation manners and protection scope of the present invention. For those skilled in the art, it should be able to realize that all equivalent replacements and obvious changes made by using the description and illustrations of the present invention should be included in the protection scope of the present invention.
Claims
1. An operating system memory management method compatible with multiple processor architectures, characterized in that, including, Step S1, define a page table structure according to the virtual address bit width and paging model of the processor architecture, where the page table structure includes multiple page table entries; Step S2, define a page table data structure according to the width of the page table entries; Step S3, establish a page table mapping relationship from the virtual address to the physical address by traversing the page table data structure level by level; Step S4, store the page table mapping relationship into the memory management unit, and start the memory management unit through a register to convert the virtual address into the physical address.
2. The operating system memory management method compatible with a multi-processor architecture according to claim 1, wherein The page table entries in Step S1 include a page global directory, a page upper directory, a page middle directory, and a page table; The page global directory is the highest-level page table entry, used to map the virtual address space to the physical address space; The page upper directory is used to connect the page global directory and the page middle directory; The page middle directory is used to connect the page upper directory and the page table; The page table is the lowest-level page table entry.
3. The operating system memory management method compatible with a multi-processor architecture according to claim 1, wherein The width of the page table entries in Step S2 is 64 bits, and the page table data structure is defined by an unsigned integer type.
4. The operating system memory management method compatible with a multi-processor architecture according to claim 2, characterized in that Step S3 includes, Step S31, parse the virtual address level by level through the index entries of the page table data structure, and locate each level of page table entries in turn; Step S32, traverse each level of page table entries and initialize them to establish the page table mapping relationship from the virtual address to the physical address.
5. The operating system memory management method compatible with a multi-processor architecture according to claim 4, characterized in that In Step S32, When the page table entry is the page global directory, check whether the entry content of the page global directory is empty with the memory length corresponding to the index entry of the page global directory as the step size. If so, allocate a physical memory page for the next-level page table and store the physical memory page into the entry of the page global directory. If not, directly perform mapping through the page table entry.
6. The operating system memory management method compatible with a multi-processor architecture according to claim 4, characterized in that, In Step S32, When the page table entry is the page upper directory, check whether the entry content of the page upper directory is empty with the memory length corresponding to the index entry of the page upper directory as the step size. If so, allocate the physical memory page for the next-level page table and store the physical memory page into the entry of the page upper directory. If not, directly perform mapping through the page table entry.
7. The operating system memory management method compatible with a multi-processor architecture according to claim 4, characterized in that In Step S32, When the page table entry is the page middle directory, check whether the entry content of the page middle directory is empty with the memory length corresponding to the index entry of the page middle directory as the step size. If so, allocate the physical memory page for the next-level page table and store the physical memory page into the entry of the page middle directory. If not, directly perform mapping through the page table entry.
8. The operating system memory management method compatible with a multi-processor architecture according to claim 4, wherein In Step S32, When the page table entry is the page table, traverse each virtual page through a while loop with the page size as the step size, and map the virtual address to the corresponding physical address.
9. The operating system memory management method compatible with a multi-processor architecture according to claim 1, characterized in that, The processor architecture in Step S1 includes the ARM architecture and the RISC-V architecture.
10. The operating system memory management method compatible with a multi-processor architecture according to claim 9, characterized in that, The registers in Step S4 include a first register and a second register; Start the memory management unit through the first register to perform address translation for the ARM architecture; The memory management unit is started through the second register to perform address translation of the RISC-V architecture.