Data processing method, device, medium and computer equipment for storage device

Abstract

The present application proposes a data processing method, device, medium and computer equipment for a storage device. The data processing method of the present invention includes: parsing a read request initiated by a user to obtain a logical addresses to be read; determining the c L2P mapping tables associated with the a logical addresses according to the range of the a logical addresses, where c is a positive integer greater than or equal to 1; backing up the original mapping relationships of the c L2P mapping tables; updating the b latest mapping relationships of the temporary information layer to the c L2P mapping tables, overwriting their original mapping relationships; querying the updated c L2P mapping tables according to the read request, obtaining the physical addresses corresponding to the a logical addresses and reading the data; after the reading is completed, restoring the backed-up original mapping relationships to the c L2P mapping tables. The mapping management process of this solution can avoid redundant checks, achieve accurate locking of the update range, significantly reduce the number of checks, release the physical limitations of bandwidth, and greatly reduce delays.

Description

Technical Field

[0001] The present invention relates to a data processing method, device, medium and computer equipment of a storage device, belonging to the technical field of data processing methods of NandFlash memory. Background Art

[0002] Nand Flash is a non-volatile storage medium widely used in storage products such as SD, eMMC, UFS, and SSD. Its core management module is the Flash Translation Layer (FTL), which is responsible for translating the host's logical addresses into physical addresses and performing functions such as wear leveling and garbage collection. In the FTL algorithm, the mapping between logical addresses (e.g., 512B or 4KB) and physical addresses is typically divided into two layers: a temporary information layer, also known as temp info, which stores a small amount of recent logical-to-physical address mappings; and a logical-to-physical address mapping table, also known as the L2P table, which stores all mappings. If a mapping for a logical address exists in temp info, the data corresponding to the address in the L2P table becomes outdated. Traditionally, data reads first check whether the target logical address exists in temp info. If so, the mapping in temp info is used; otherwise, the L2P table is queried.

[0003] Traditional data reading logic has certain performance bottlenecks. For example, when a user reads a logical address and temp info records b mapping relationships, a × b check operations need to be performed, that is, it is necessary to traverse all target addresses to see whether they exist in temp info. When the number of mapping relationships b in temp info is very large, the number of checks also increases sharply, resulting in a serious decrease in the memory reading speed. This usually occurs in scenarios that affect the sequential reading of large amounts of data, such as streaming video playback, data transmission and installation of large files, etc. Summary of the Invention

[0004] In view of the above-mentioned deficiencies in the prior art, the object of the present invention is to provide a data processing method, device, medium and computer equipment for a storage device.

[0005] According to an embodiment of the present invention, a first solution is provided: a data processing method of a storage device, comprising the following steps:

[0006] Parse the read request initiated by the user and obtain a logical address to be read;

[0007] Determine c L2P mapping tables associated with a logical address range, where c is a positive integer greater than or equal to 1;

[0008] Backing up the original mapping relationships of the c L2P mapping tables;

[0009] Update the b latest mapping relationships of the temporary information layer to the c L2P mapping tables, overwriting their original mapping relationships;

[0010] querying the updated c L2P mapping tables according to the read request, obtaining the physical addresses corresponding to the a logical addresses and reading the data;

[0011] After the reading is completed, the backed-up original mapping relationship is restored to the c L2P mapping tables.

[0012] Furthermore, the a logical addresses are consecutive read logical addresses, and the c L2P mapping tables are determined by calculating the number of complete L2P mapping tables covered by the consecutive addresses according to the starting logical addresses and the ending logical addresses, ensuring that the value of c is minimized.

[0013] Furthermore, the c L2P mapping tables are determined in the following manner:

[0014] Set the logical address range size managed by a single L2P mapping table to M;

[0015] Calculate the block index of the starting logical address S: ;

[0016] Calculate the block index of the end logical address E: ;

[0017] Calculate the c value: c = Start_Index - End_Index + 1.

[0018] Furthermore, the a logical addresses are non-contiguous read logical addresses, and the c L2P mapping tables are determined by traversing the distribution range of all non-contiguous logical addresses, merging the L2P mapping tables covering these addresses, and ensuring that all target addresses are included.

[0019] Furthermore, the c L2P mapping tables are determined in the following manner:

[0020] Set the logical address range size managed by a single L2P mapping table to M;

[0021] Initialize the index set Index_Set={};

[0022] Traverse each logical address addr_i and calculate the block index: , add the index to the set Index_Set;

[0023] Calculate the c value: c=│Index_Set│.

[0024] Furthermore, the temporary information layer includes an L1 temporary layer and an L2 temporary layer, the L1 temporary layer stores an extremely high frequency mapping relationship, and the L2 temporary layer stores a sub-high frequency mapping relationship. The step of parsing the user-initiated read request further includes:

[0025] The read request first queries the L1 temporary layer. If it misses, the following steps are triggered: the b latest mapping relationships of the L2 temporary information layer are updated to the c L2P mapping tables.

[0026] Furthermore, the step of dynamically adjusting the size of the temporary information layer includes:

[0027] Count the I / O request frequency at a fixed period;

[0028] If the current I / O request frequency is greater than or equal to the high load threshold, increase the b value; if the current I / O request frequency is less than the low load threshold, decrease the b value;

[0029] Write the increased or decreased updated b value b_new into the control register and synchronize it to the temporary information management unit;

[0030] When b_new>b, the capacity is expanded to allocate a new buffer area and migrate the mapping relationship. When b_new<b, the capacity is reduced to release the redundant buffer area and retain the high-frequency mapping.

[0031] According to an embodiment of the present invention, using a data processing method of a storage device in the first solution provided by the present invention, a second solution is provided:

[0032] A data processing device for a storage device, comprising:

[0033] The read parsing module is used to parse the read request initiated by the user and obtain a logical address to be read;

[0034] an associated mapping table determination module, configured to determine c associated L2P mapping tables according to a range of logical addresses, where c is a positive integer greater than or equal to 1;

[0035] an original mapping backup module, configured to back up the original mapping relationships of the c L2P mapping tables;

[0036] a mapping table updating module, configured to update the b latest mapping relationships of the temporary information layer to the c L2P mapping tables, overwriting their original mapping relationships;

[0037] a reading module, configured to query the updated c L2P mapping tables according to the read request, obtain the physical addresses corresponding to the a logical addresses, and read the data;

[0038] The backup and recovery module is used to restore the backed-up original mapping relationship to the c L2P mapping tables after the reading is completed.

[0039] A computer device comprises a memory and a processor, wherein the memory stores a computer program, and when the computer program is executed by the processor, the processor performs the following steps:

[0040] Parse the read request initiated by the user and obtain a logical address to be read;

[0041] Determine c L2P mapping tables associated with a logical address range, where c is a positive integer greater than or equal to 1;

[0042] Backing up the original mapping relationships of the c L2P mapping tables;

[0043] Update the b latest mapping relationships of the temporary information layer to the c L2P mapping tables, overwriting their original mapping relationships;

[0044] querying the updated c L2P mapping tables according to the read request, obtaining the physical addresses corresponding to the a logical addresses and reading the data;

[0045] After the reading is completed, the backed-up original mapping relationship is restored to the c L2P mapping tables.

[0046] A computer-readable storage medium stores a computer program, which, when executed by a processor, causes the processor to perform the following steps:

[0047] Parse the read request initiated by the user and obtain a logical address to be read;

[0048] Determine c L2P mapping tables associated with a logical address range, where c is a positive integer greater than or equal to 1;

[0049] Backing up the original mapping relationships of the c L2P mapping tables;

[0050] Update the b latest mapping relationships of the temporary information layer to the c L2P mapping tables, overwriting their original mapping relationships;

[0051] querying the updated c L2P mapping tables according to the read request, obtaining the physical addresses corresponding to the a logical addresses and reading the data;

[0052] After the reading is completed, the backed-up original mapping relationship is restored to the c L2P mapping tables.

[0053] Compared with the existing technology, the technical solution provided by this application has the following unique beneficial effects: the mapping management process of this solution can avoid redundant checks, batch merge the b mapping relationships of the temporary information layer into the associated c L2P mapping tables, and only update the c L2P mapping tables related to the user request instead of global updates, thereby achieving precise locking of the update range, and the update process can be repeated cyclically to ensure data consistency. The number of checks is reduced from a × b to c × b, releasing the physical limitations of bandwidth and greatly reducing latency. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0055] in:

[0056] Figure 1 is a flow chart of a data processing method of a storage device in one embodiment;

[0057] Figure 2 is a structural block diagram of a data processing device of a storage device in one embodiment;

[0058] Figure 3 FIG. 1 is a structural block diagram of a computer device in one embodiment. DETAILED DESCRIPTION

[0059] In order to enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of this application.

[0060] Example 1

[0061] The technical problem solved by this embodiment is that the traditional data reading logic has certain performance bottlenecks. For example, when a user reads a logical address and b mapping relationships are recorded in temp info, a×b check operations need to be performed, that is, it is necessary to traverse to see whether all target addresses exist in temp info. When the number of mapping relationships b in temp info is very large, the number of checks also increases sharply, resulting in a serious decrease in the reading speed of the memory.

[0062] This embodiment provides a data processing method for a storage device, such as Figure 1 As shown, the following steps are included:

[0063] S101: Parse the read request initiated by the user and obtain a logical addresses to be read;

[0064] S102: Determine c L2P mapping tables associated with the range of a logical addresses, where c is a positive integer greater than or equal to 1;

[0065] S103: Backing up the original mapping relationships of the c L2P mapping tables;

[0066] S104: updating the b latest mapping relationships of the temporary information layer to the c L2P mapping tables, overwriting the original mapping relationships;

[0067] S105: querying the updated c L2P mapping tables according to the read request, obtaining the physical addresses corresponding to the a logical addresses and reading the data;

[0068] S106: After the reading is completed, the backed-up original mapping relationship is restored to the c L2P mapping tables.

[0069] The mapping management process of this solution can avoid redundant checks and batch merge the b mapping relationships of the temporary information layer into the c associated L2P mapping tables. Only the c L2P mapping tables related to the user request are updated instead of a global update, thus achieving precise locking of the update scope.

[0070] Specifically, a traditional read request checks the physical address a×b times, while this solution checks the physical address c×b times. Since a ≥ c, a×b ≥ c×b. When reading sequentially, a is much greater than c, so the performance improvement is particularly significant. However, in non-sequential reads, partial performance improvements can also be achieved through algorithm adjustments. Therefore, by reducing the number of physical address checks, this solution frees up bandwidth and reduces latency. This not only significantly improves the physical addressing efficiency in various sequential read scenarios, but also accommodates various typical non-sequential read scenarios, significantly improving the physical addressing capabilities of storage devices across all aspects.

[0071] Example 2

[0072] This embodiment provides a specific operation process of a data processing method for a storage device. The verification scenario uses a Yangtze Memory TiPro 7000 SSD, the main control chip is IG5236, and the interface is PCle.

[0073] S201: Parse the read request initiated by the user and obtain a consecutive read logical addresses 0-1023 to be read, that is, a=1024;

[0074] S202: Set the logical address size M managed by a single L2P mapping table to 1024;

[0075] Starting block index ,in, is the floor rounding symbol;

[0076] End block index ;

[0077] c=Start_Index-End_Index+1=1;

[0078] The output is: only L2P mapping table No. 0 needs to be operated;

[0079] S203: Load L2P mapping table No. 0 from Nand Flash and back up the original mapping relationship to the SRAM dedicated cache area;

[0080] S204: The temporary information layer stores the latest mapping relationships b=16, for example, the mapping of logical addresses 2048-2063, and the 16 latest mapping relationships are overwritten into the No. 0 L2P mapping table. The hardware is updated through the master bit operation.

[0081] S205: Directly access L2P mapping table No. 0 to obtain the physical addresses corresponding to 1024 logical addresses, and continuously read data from NandFlash. The physical addresses are: Block 10~13.

[0082] The traditional solution requires 1024×16=16,384 queries, while this solution only requires c×b=1×16=16 queries. The total read latency of the traditional solution is up to 800-1000us, while this solution is only less than 100ns.

[0083] Example 3

[0084] This embodiment provides a non-continuous reading operation process:

[0085] S301: Parse the read request initiated by the user and obtain a non-consecutive read logical addresses [100, 1500, 2500] to be read, that is, a=3 addresses.

[0086] S302: Set the logical address size M managed by a single L2P mapping table to 1024;

[0087] Initialize index set Index_Set={};

[0088] Traversal address:

[0089] ;

[0090] ;

[0091] ;

[0092] c=│Index_Set│=3, which means that L2P mapping tables 0, 1, and 2 need to be operated.

[0093] S303: Load three L2P mapping tables from Nand Flash, with physical addresses of Block 5 / 6 / 7; back up the original mapping relationships to the dedicated SRAM cache area;

[0094] S304: The temporary information layer stores the latest mapping relationships b=16, for example, the mapping of logical addresses 2048-2063, and overwrites the 16 latest mapping relationships in batches to three L2P mapping tables, with address ranges of: 0-1023, 1024-2047, and 2048-3071;

[0095] S305: Directly access the three L2P mapping tables to obtain the physical location of the target address:

[0096] Address 100 → Lookup table 0 → Physical address Block 10, page 1;

[0097] Address 1500 → Lookup table 1 → Physical address Block 20, page 3;

[0098] Address 2500 → Look up table 2 → Physical address Block 30, page 5;

[0099] Read discrete blocks of data from Nand Flash.

[0100] The traditional solution has 3×16=48 queries, while this solution maps queries to c×b=3×16=48. Although the number of queries is the same, this solution avoids a×b traversals by merging updates and only queries the L2P table directly. Without any additional overhead, the latency of the critical path is significantly improved, especially the CPU usage is greatly reduced.

[0101] Example 4

[0102] This embodiment discloses a method for implementing a multi-level temporary layer mechanism. The main principle is to reduce the delay of hotspot data locations through distributed caching and frequency-driven updates, and also has a certain control effect on the delay of non-hotspot data compared to traditional solutions.

[0103] Specifically, configure and initialize multi-level temporary information layers: the L1 temporary layer is an SRAM storage area with an address range of 0×8000~0×8100, a capacity of 8 mapping relationships, each mapping relationship is 16 bytes, and a total of 128B; the L2 temporary layer is a DRAM storage area with an address range of 0×10000~0×11000, a capacity of 64 mapping relationships, each mapping relationship is 16 bytes, and a total of 1KB. Each mapping relationship maintains a 4-bit direction frequency counter.

[0104] The user reads the requested roadbed address

[500] , and the address range of continuous read is 0~1023; first query the L1 temporary layer, the hardware comparator matches 8 mapping relationships in parallel, and directly returns the physical address if it hits. If it misses, it triggers the L2 update: record the miss event, and start the L2 to L2P mapping table merge process:

[0105] Calculate the c value: the address range is 0~1023 → M=1024 → c=1, which is L2P mapping table No. 0;

[0106] Back up the original mapping of L2P mapping table No. 0 to SRAM;

[0107] Extract b mapping relationships from the L2 temporary layer, select b=16 mapping relationships with the highest access frequency, and overwrite them to L2P mapping table No. 0;

[0108] Directly access L2P mapping table No. 0 to obtain the physical address of address 500, such as Block 10, page 1, and read data from NandFlash.

[0109] Compared with the traditional traversal mapping solution, this method significantly reduces the access latency of hot data through hierarchical caching and frequency-driven updates.

[0110] Example 5

[0111] The technical problem solved by this embodiment is that the fixed temporary information layer with static capacity has insufficient capacity under high load, resulting in frequent triggering of L2P updates, and excessive capacity under low load, wasting memory and power consumption. For example, maintaining 64 mappings during idle time wastes memory.

[0112] This embodiment maximizes load performance by preserving high-frequency mapping and releases the mapping relationship with the lowest access frequency when the load is low, so as to solve the problem of imperfect resource configuration of the static mapping layer.

[0113] Specifically, the preset parameters are high load threshold Th=50000, in IOPS, low load threshold Tl=10000, in IOPS, step size Δd=8 to match the 64-byte alignment of the cache line, capacity range d_min=4, d_max=64, and the fixed monitoring period is T=100ms, that is, the I / O request frequency is counted every T=100ms.

[0114] Read the hardware timer to obtain the IOPS value within a fixed period. For example, if period 1 is IOPS = 55,000, it indicates high load, and if period 2 is IOPS = 8000, it indicates low load.

[0115] The decision logic for dynamically adjusting the b value is:

[0116] If IOPS ≥ Th, then b_new = min(b_current + Δb, b_max), that is, b_new > b, and the decision result is to expand capacity;

[0117] If IOPS < Tl, then b_new = max(b_current - Δb, b_min), that is, b_new < b, and the decision result is to scale down;

[0118] Other conditions remain unchanged.

[0119] Write b_new into the control register, trigger the interrupt signal and synchronize it to the temporary information management unit to take effect of the new configuration.

[0120] When expanding capacity, allocate new SRAM blocks, migrate all mapping relationships to the new blocks, and update the temporary layer index table;

[0121] When scaling down, the mapping relationships are sorted by access frequency, and high-frequency mapping relationships, such as the first 16, are retained to release redundant SRAM blocks.

[0122] Through this solution, the delay of the dynamic adjustment scheme can be greatly improved when there is a sudden high load, and the power consumption is also effectively controlled when there is a continuous low load, solving the resource mismatch problem of the static mapping layer, and achieving maximum high-load performance and optimal low-load energy efficiency.

[0123] Example 6

[0124] This embodiment provides a data processing device for a storage device, such as Figure 2 Shown, including:

[0125] The read parsing module 100 is used to parse the read request initiated by the user and obtain a logical addresses to be read;

[0126] An associated mapping table determination module 200 is configured to determine c associated L2P mapping tables according to a range of logical addresses, where c is a positive integer greater than or equal to 1;

[0127] The original mapping backup module 300 is used to back up the original mapping relationships of the c L2P mapping tables;

[0128] A mapping table updating module 400 is configured to update the b latest mapping relationships of the temporary information layer to the c L2P mapping tables, overwriting their original mapping relationships;

[0129] A reading module 500 is configured to query the updated c L2P mapping tables according to the read request, obtain the physical addresses corresponding to the a logical addresses, and read the data;

[0130] The backup and recovery module 600 is configured to restore the backed-up original mapping relationship to the c L2P mapping tables after the reading is completed.

[0131] Figure 3 FIG1 shows an internal structure diagram of a computer device in an embodiment. The computer device can be a terminal or a server. Figure 3 As shown, the computer device includes a processor, a memory, and a network interface connected via a system bus. The memory includes a non-volatile storage medium and an internal memory. The non-volatile storage medium of the computer device stores an operating system and may also store a computer program. When the computer program is executed by the processor, the processor can implement the data processing method. The memory may also store a computer program. When the computer program is executed by the processor, the processor can implement the data processing method. It will be understood by those skilled in the art that Figure 3 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0132] In one embodiment, a computer device is provided, comprising a memory and a processor, wherein the memory stores a computer program, and when the computer program is executed by the processor, the processor performs the following steps:

[0133] Parse the read request initiated by the user and obtain a logical address to be read;

[0134] Determine c L2P mapping tables associated with a logical address range, where c is a positive integer greater than or equal to 1;

[0135] Backing up the original mapping relationships of the c L2P mapping tables;

[0136] Update the b latest mapping relationships of the temporary information layer to the c L2P mapping tables, overwriting their original mapping relationships;

[0137] querying the updated c L2P mapping tables according to the read request, obtaining the physical addresses corresponding to the a logical addresses and reading the data;

[0138] After the reading is completed, the backed-up original mapping relationship is restored to the c L2P mapping tables.

[0139] In one embodiment, a computer-readable storage medium is provided, storing a computer program. When the computer program is executed by a processor, the processor performs the following steps:

[0140] Parse the read request initiated by the user and obtain a logical address to be read;

[0141] Determine c L2P mapping tables associated with a logical address range, where c is a positive integer greater than or equal to 1;

[0142] Backing up the original mapping relationships of the c L2P mapping tables;

[0143] Update the b latest mapping relationships of the temporary information layer to the c L2P mapping tables, overwriting their original mapping relationships;

[0144] querying the updated c L2P mapping tables according to the read request, obtaining the physical addresses corresponding to the a logical addresses and reading the data;

[0145] After the reading is completed, the backed-up original mapping relationship is restored to the c L2P mapping tables.

[0146] Those skilled in the art will appreciate that all or part of the processes in the above-described method embodiments can be implemented by instructing the relevant hardware through a computer program. The program can be stored in a non-volatile computer-readable storage medium. When executed, the program can include the processes of the above-described method embodiments. Any reference to memory, storage, database, or other media used in the various embodiments provided herein may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct RAMbus dynamic RAM (DRDRAM), and RAMbus dynamic RAM (RDRAM).

[0147] The technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0148] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A data processing method for a storage device, characterized in that: The steps include: Parse the read request initiated by the user and obtain a logical address to be read; Determine c L2P mapping tables associated with a logical address range, where c is a positive integer greater than or equal to 1; Backing up the original mapping relationships of the c L2P mapping tables to a dedicated SRAM cache area; Update the b latest mapping relationships of the temporary information layer to the c L2P mapping tables, overwriting their original mapping relationships; Among them, the temporary information layer includes an L1 temporary layer and an L2 temporary layer, the L1 temporary layer stores an extremely high frequency mapping relationship, and the L2 temporary layer stores a sub-high frequency mapping relationship. The multi-level temporary information layer is configured and initialized, the L1 temporary layer is an SRAM storage area, and the L2 temporary layer is a DRAM storage area. The step of parsing the user-initiated read request also includes: the physical address of the roadbed address requested by the user is read, the address range of continuous read is 0~1023, the read request prioritizes querying the L1 temporary layer, the hardware comparator matches 8 mapping relationships in parallel, and when a miss occurs, the step is triggered: the b latest mapping relationships of the L2 temporary information layer are updated to c L2P mapping tables, the miss event is recorded, and the L2 to L2P mapping table merging process is started: Calculate the value of c: The address range is 0-1023. Calculate c=1, which is L2P mapping table No.

0. Back up the original mapping of L2P mapping table No. 0 to SRAM. Extract b mapping relationships from the L2 temporary layer, select the 16 mapping relationships with the highest access frequency, and overwrite them to L2P mapping table No.

0. Directly access L2P mapping table No. 0 to obtain the physical address of the roadbed address and read data from Nand Flash. querying the updated c L2P mapping tables according to the read request, obtaining the physical addresses corresponding to the a logical addresses and reading the data; After the reading is completed, the backed-up original mapping relationship is restored to the c L2P mapping tables.

2. The data processing method of a storage device according to claim 1, wherein: The a logical addresses are continuous read logical addresses, and the c L2P mapping tables are determined by calculating the number of complete L2P mapping tables covered by the continuous addresses according to the starting logical addresses and the ending logical addresses, ensuring that the value of c is minimized.

3. The data processing method of a storage device according to claim 2, wherein: The c L2P mapping tables are determined in the following manner: Set the logical address range size managed by a single L2P mapping table to M; Calculate the block index of the starting logical address S: ; Calculate the block index of the end logical address E: ; Calculate the c value: c = Start_Index - End_Index + 1.

4. The data processing method of a storage device according to claim 1, wherein: The a logical addresses are non-continuous read logical addresses, and the c L2P mapping tables are determined by traversing the distribution range of all non-continuous logical addresses, merging the L2P mapping tables covering these addresses, and ensuring that all target addresses are included.

5. The data processing method of a storage device according to claim 4, wherein: The c L2P mapping tables are determined in the following manner: Set the logical address range size managed by a single L2P mapping table to M; Initialize the index set Index_Set={}; Traverse each logical address addr_i and calculate the block index: , add the index to the set Index_Set; Calculate the c value: c=│Index_Set│.

6. The data processing method of the storage device according to claim 4, characterized in that: The step of dynamically adjusting the size of the temporary information layer includes: Count the I / O request frequency at a fixed period; If the current I / O request frequency is greater than or equal to the high load threshold, increase the b value; if the current I / O request frequency is less than the low load threshold, decrease the b value; Write the increased or decreased updated b value b_new into the control register and synchronize it to the temporary information management unit; When b_new>b, the capacity is expanded to allocate a new buffer area and migrate the mapping relationship. When b_new<b, the capacity is reduced to release the redundant buffer area and retain the high-frequency mapping.

7. A data processing device for a storage device, characterized in that: include: The read parsing module is used to parse the read request initiated by the user and obtain a logical address to be read; an associated mapping table determination module, configured to determine c associated L2P mapping tables according to a range of logical addresses, where c is a positive integer greater than or equal to 1; An original mapping backup module, configured to back up the original mapping relationships of the c L2P mapping tables and back up the original mapping relationships to a dedicated SRAM cache area; a mapping table updating module, configured to update the b latest mapping relationships of the temporary information layer to the c L2P mapping tables, overwriting their original mapping relationships; Among them, the temporary information layer includes an L1 temporary layer and an L2 temporary layer, the L1 temporary layer stores an extremely high frequency mapping relationship, and the L2 temporary layer stores a sub-high frequency mapping relationship. The multi-level temporary information layer is configured and initialized, the L1 temporary layer is an SRAM storage area, and the L2 temporary layer is a DRAM storage area. The step of parsing the user-initiated read request also includes: the physical address of the roadbed address requested by the user is read, the address range of continuous read is 0~1023, the read request prioritizes querying the L1 temporary layer, the hardware comparator matches 8 mapping relationships in parallel, and when a miss occurs, the step is triggered: the b latest mapping relationships of the L2 temporary information layer are updated to c L2P mapping tables, the miss event is recorded, and the L2 to L2P mapping table merging process is started: Calculate the value of c: The address range is 0-1023. Calculate c=1, which is L2P mapping table No.

0. Back up the original mapping of L2P mapping table No. 0 to SRAM. Extract b mapping relationships from the L2 temporary layer, select the 16 mapping relationships with the highest access frequency, and overwrite them to L2P mapping table No.

0. Directly access L2P mapping table No. 0 to obtain the physical address of the roadbed address and read data from Nand Flash. a reading module, configured to query the updated c L2P mapping tables according to the read request, obtain the physical addresses corresponding to the a logical addresses, and read the data; The backup and recovery module is used to restore the backed-up original mapping relationship to the c L2P mapping tables after the reading is completed.

8. A computer-readable storage medium, characterized in that A computer program is stored, and when the computer program is executed by a processor, the processor is caused to perform the steps of the method according to any one of claims 1 to 6.

9. A computer device, characterized in that: The method comprises a memory and a processor, wherein the memory stores a computer program, and when the computer program is executed by the processor, the processor executes the steps of the method according to any one of claims 1 to 6.

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