Data transmission synchronization method and device, equipment and storage medium

Abstract

The invention relates to the technical field of audio transmission, and provides a data transmission synchronization method, device and equipment and a storage medium, the method comprises the following steps: obtaining the memory capacity of a local memory, the local memory being the memory of any one of data transmission receiving and transmitting ends; and synchronizing the clock frequency of the data transmission receiving and transmitting end according to the memory capacity. By monitoring the memory capacity of the local memory of any one of the data receiving and transmitting ends, the clock frequency error of the data receiving and transmitting ends is determined, so that the clock frequencies of the data receiving and transmitting ends are synchronized, accumulation of the clock errors of the data receiving and transmitting ends is eliminated, and synchronization and accurate receiving of data transmission by the receiving and transmitting ends are ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of data transmission, and particularly to a data transmission synchronization method, apparatus, device, and storage medium. Background Art

[0002] I2S (Inter-IC Sound) is a serial interface standard widely used in digital audio transmission and also a synchronous serial data transmission protocol, which can transmit audio signals from one device to another. In traditional application scenarios such as high-definition video, the audio data transmitted through the I2S protocol can be stored in DDR (Double Data Rate, double-speed synchronous dynamic random access memory), and the soc (System on Chip) accesses the audio data from the DDR in a timely manner and sends it to the TX end. Since the DDR memory is large enough and there is the intervention of the soc main control software, the synchronization of the audio data transceiver ends can be achieved.

[0003] In long-distance high-speed transmission applications, the proportion of the time required for the intervention of the soc main control software is relatively large compared to the high-speed transmission time. Therefore, in ultra-high-speed long-distance transmission, it is necessary to reduce or avoid the intervention of the soc main control software. However, since the remote serial clock bclk is self-recovering and has a different clock source from the local bclk clock at the sending end, during long-term uninterrupted transmission of audio data, the clock error between the two ends will continuously accumulate, resulting in data overflow or interruption, and problems such as data asynchronization between the two ends, noise, and audio intermittence. Summary of the Invention

[0004] The present invention provides a data transmission synchronization method, apparatus, device, and storage medium to solve the defect that in the prior art, when transmitting audio data over long distances at ultra-high speeds, the data between the two ends is asynchronous due to the accumulation of clock errors between the transceiver ends.

[0005] The present invention provides a data transmission synchronization method, including the following steps: Obtain the memory capacity of the local memory, where the local memory is the memory at any end of the data transmission transceiver end; Synchronize the clock frequencies of the data transmission transceiver ends according to the memory capacity.

[0006] According to the data transmission synchronization method provided by the present invention, the synchronizing the clock frequencies of the data transmission transceiver ends according to the memory capacity includes: Compare the memory capacity with a preset data volume waterline to determine whether it is necessary to adjust the local clock frequency of the data transmission, where the local clock frequency is the clock frequency corresponding to the local memory; If it is determined that the local clock frequency needs to be adjusted, obtain the frequency modulation parameter corresponding to the data water line; Perform a frequency modulation operation on the local clock frequency according to the frequency modulation parameter to synchronize the clock frequencies of the data transmission transceiver.

[0007] According to the data transmission synchronization method provided by the present invention, the data water line includes a full water line. The performing a frequency modulation operation on the local clock frequency according to the frequency modulation parameter to synchronize the clock frequency of the data transmission includes: If the memory capacity reaches the full water line, obtain the frequency increase parameter corresponding to the full water line; Perform a frequency increase operation on the local clock frequency according to the frequency increase parameter to synchronize the local clock frequency with the opposite-end clock frequency of the data transmission.

[0008] According to the data transmission synchronization method provided by the present invention, the data water line includes a plurality of the full water lines, and the frequency increase parameters corresponding to the plurality of the full water lines are positively correlated with the full water line.

[0009] According to the data transmission synchronization method provided by the present invention, the data water line includes an empty water line. The performing a frequency modulation operation on the local clock frequency according to the frequency modulation parameter to synchronize the clock frequencies of the data transmission transceiver includes: If the memory capacity reaches the empty water line, obtain the frequency decrease parameter corresponding to the empty water line; Perform a frequency decrease operation on the local clock frequency according to the frequency decrease parameter to synchronize the local clock frequency with the opposite-end clock frequency of the data transmission.

[0010] According to the data transmission synchronization method provided by the present invention, the data water line includes a plurality of the empty water lines, and the frequency decrease parameters corresponding to the plurality of the empty water lines are positively correlated with the empty water line.

[0011] According to the data transmission synchronization method provided by the present invention, the data transmission synchronization method further includes: Perform data transmission according to the synchronized clock frequency.

[0012] The present invention further provides a data transmission synchronization device, including the following modules: A memory capacity monitoring module, configured to obtain the memory capacity of the local memory, where the local memory is the memory at any end of the data transmission transceiver; A clock frequency synchronization module, configured to synchronize the clock frequencies of the data transmission transceiver according to the memory capacity.

[0013] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, the data transmission synchronization method as described in any one of the above is implemented.

[0014] The present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the data transmission synchronization method as described in any one of the above is implemented.

[0015] The present invention also provides a computer program product, including a computer program. When the computer program is executed by a processor, the data transmission synchronization method as described in any one of the above is implemented.

[0016] The data transmission synchronization method, device, equipment, and storage medium provided by the present invention monitor the memory capacity of the local memory at any one of the data sending and receiving ends, synchronize the clock frequencies of the data sending and receiving ends according to the monitored memory capacity, eliminate the accumulation of clock errors at the data sending and receiving ends, and ensure the synchronization and accurate transmission of data sending and receiving at the data sending and receiving ends. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0018] Figure 1 is a flowchart of the data transmission synchronization method provided by the present invention.

[0019] Figure 2 is a flowchart of the adjustment of the clock frequency provided by the present invention.

[0020] Figure 3 is a structural schematic diagram of the data transmission synchronization device provided by the present invention.

[0021] Figure 4 is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0022] To make the objectives, technical solutions, and advantages of the present invention clearer, the following will clearly and completely describe the technical solutions in the present invention with reference to the drawings in the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art without creative efforts based on the embodiments in the present invention belong to the scope of protection of the present invention.

[0023] An embodiment of the present invention provides a data transmission synchronization method, which is applied to at least one of the data transmission transceiver ends. By monitoring the change in the memory capacity of the data receiving end or the data sending end, the clock frequency of the data transceiver for transmitting data is adaptively and dynamically adjusted, thereby compensating for the frequency difference between the two ends and enabling the data to be transmitted synchronously and correctly without loss.

[0024] Specifically, Figure 1 is a flowchart of the data transmission synchronization method provided by the present invention. As Figure 1 shown, the method includes the following steps: Step 100, obtain the memory capacity of the local memory, where the local memory is the memory of any one of the data transmission transceiver ends; Step 200, synchronize the clock frequency of the data transmission transceiver according to the memory capacity.

[0025] During data transmission, obtain the memory capacity of the local memory, and adjust the clock frequency of the data transmission transceiver according to the obtained memory capacity. The data transmitted by the data transmission transceiver can be audio data or other multimedia data, and no specific limitation is made thereto.

[0026] Among them, the local memory is the memory of any one of the data transmission transceiver ends. Specifically, the local memory refers to the memory of the application end of the data transmission synchronization method. If the data transmission synchronization method provided by the embodiment of the present invention is applied to the data sending end, the local memory refers to the memory of the data sending end. If the data transmission synchronization method provided by the embodiment of the present invention is applied to the data receiving end, the local memory refers to the memory of the data receiving end.

[0027] Optionally, based on the I2S protocol, during data transmission, the clock signal is crucial during data reception and is used to control the data transmission rate and synchronization to ensure accurate data transmission. In the scenario of long-term continuous data transmission, if the clock synchronization between the data sending end and the data receiving end is not performed in a timely manner, when the clock errors of the two ends accumulate, the transmitted data will overflow or be interrupted. And in serial communication, the transmission rate is usually measured by the number of bits transmitted per second (bit / s), that is, the baud rate. The frequency of the sending or receiving clock is an integer multiple of the baud rate, and this multiple is called the baud rate factor. That is, the clock frequency determines the data transmission frequency. The clock frequency of the data sending end affects the data sending frequency, and the clock frequency of the data receiving end affects the data receiving frequency.

[0028] Adjust the clock frequency of the data transceiver according to the storage capacity of the local memory, thereby synchronizing the clock frequency of the data transmission transceiver. Among them, adjusting the clock frequency means adjusting the transmission rate of the data transceiver.

[0029] Taking the transmission of audio data as an example, during the long-distance and ultra-high-speed transmission of audio data, both the sending end (S end) and the receiving end (D end) have memories for caching data locally. When the S end sends audio data to the D end, based on the I2S protocol, the audio data is input into the S end at the clock frequency of the S end from the outside of the S end. After receiving the audio data, the S end sends the audio data to the D end at the clock frequency of the S end according to the long-distance transmission protocol. Similarly, the D end transmits the audio data at the local clock frequency based on the long-distance transmission protocol. Both the S end and the D end need to cache the received audio data. When the S end performs long-distance transmission of audio data to the D end, it can transmit the clock frequency information of its own end to the D end, and the D end generates a clock signal with the same frequency according to the received clock frequency information for transmitting audio data. However, since the clock signal sources of the D end and the S end do not belong to the same clock source, there is an error in the frequencies of the clock signals generated at both ends, or the clock frequency of either end is unstable. During long-term continuous transmission, the clock errors at both ends will continuously accumulate, resulting in data overflow or interruption.

[0030] Specifically, the memory capacities of the S end and the D end for caching data are limited. If, after a period of error accumulation, the clock frequency of the S end is faster than that of the D end, then the rate at which the S end sends data to the D end is faster than the rate at which the D end sends the data out, that is, the rate at which the D end caches data in the memory is faster than the rate at which the data is taken out of the memory. The data cached in the D end's memory will gradually accumulate, and the memory capacity tends to be in a full state, easily leading to data overflow and loss. Similarly, if the clock frequency of the S end is slower than that of the D end, then the rate at which the D end caches data in the memory is slower than the rate at which it takes data from the memory. The data cached in the D end will gradually decrease and tend to be in an empty state. When the data cached in the memory is empty, the D end will take out empty data for transmission, resulting in an interruption of the audio data.

[0031] Based on this, in the embodiments of the present invention, by monitoring the memory capacity of the local memory of at least one end in the data transmission transceiver, the frequency difference between the data receiving end and the sending end is obtained according to the memory capacity, so as to adjust the clock frequency of the receiving end for transmitting data, and realize the synchronization of the clock frequencies of the data transmission transceiver.

[0032] Optionally, when the clock frequencies of the data sending end and the receiving end are the same, the amount of data cached in the local memory of the receiving end should remain unchanged. However, as the error between the clock frequencies of the sending end and the receiving end continuously accumulates, the amount of audio data cached in the local memory of the receiving end will tend to be full or emptied. According to the memory capacity of the local memory of at least one end in the transceiver, the change trend of the clock frequency error between the sending end and the receiving end can be determined, so as to determine the adjustment of the clock frequency for data transmission.

[0033] Adjust the clock frequency of the transmitted data, with different frequency modulation strategies. Specifically, according to the changing trend of the memory capacity, determine the frequency modulation strategy for the clock frequency. If the changing trend of the memory capacity is a full overflow trend, the frequency modulation strategy for the clock frequency is a frequency increase strategy. If the changing trend of the memory capacity is an empty state, the frequency modulation strategy for the clock frequency is a frequency decrease strategy. Among them, perform a frequency modulation operation on the clock frequency according to the frequency modulation strategy, and perform a frequency decrease operation on the clock frequency according to the frequency decrease strategy, so as to synchronize the clock frequency of the data receiving end with the clock frequency of the data sending end.

[0034] Optionally, if the application end of the data transmission synchronization method includes a receiving end, perform a frequency modulation operation on the clock frequency. Specifically, according to the memory capacity of the local memory of the receiving end, perform a frequency modulation operation on the clock frequency of the receiving end. When the memory capacity tends to be in a full overflow state, increase the clock frequency of the receiving end, so as to speed up the speed of the receiving end retrieving data from the local memory and reduce the amount of cached data. When the memory capacity tends to be in an empty state, reduce the clock frequency of the receiving end, so as to slow down the speed of the receiving end retrieving data from the local memory and increase the amount of cached data to prevent retrieving empty data.

[0035] Optionally, if the application end of the data transmission synchronization method includes a sending end, perform a frequency modulation operation on the clock frequency. Specifically, according to the memory capacity of the local memory of the sending end, perform a frequency modulation operation on the clock frequency of the sending end. When the memory capacity tends to be in a full overflow state, increase the clock frequency of the sending end, so as to speed up the speed of the sending end retrieving data for sending from the local memory and reduce the amount of cached data. When the memory capacity tends to be in an empty state, reduce the clock frequency of the sending end, so as to slow down the speed of the sending end retrieving data for sending from the local memory and increase the amount of cached data to prevent sending empty data.

[0036] In this embodiment, by monitoring the memory capacity of the local memory at any end of the data transceiver, synchronize the clock frequencies of the data transceiver at both ends according to the monitored memory capacity, eliminate the accumulation of clock errors at both ends of the data transceiver, and ensure the synchronization and accurate transmission of data transceiver at both ends for data transceiver.

[0037] In one embodiment, a data volume waterline is set for the memory capacity of the local memory of the data transmission transceiver, which is used to evaluate the memory capacity of the local memory, or evaluate the changing trend of the memory capacity of the local memory. Specifically, step 200 may further include: Step 201, compare the memory capacity with a preset data volume waterline to determine whether it is necessary to adjust the local clock frequency of the data transmission; Step 202, if it is determined that it is necessary to adjust the local clock frequency, obtain the frequency modulation parameter corresponding to the data volume waterline; Step 203: Perform a frequency modulation operation on the local clock frequency according to the frequency modulation parameter to synchronize the clock frequencies of the data transmission transceiver.

[0038] When synchronizing the clock frequencies of the data transmission transceiver according to the memory capacity of the local memory at either end of the data transceiver, first obtain the data volume water line corresponding to the local memory, and then compare the obtained memory capacity of the local memory with this data volume water line to determine whether it is necessary to adjust the local clock frequency corresponding to the local memory; where the local clock frequency is the clock frequency corresponding to the local memory, that is, the local clock frequency is the clock frequency of either end of the data transmission transceiver.

[0039] Optionally, when the memory capacity of the local memory reaches the preset data volume water line, or when the memory capacity of the local memory exceeds the preset data volume water line, it is necessary to adjust the local clock frequency corresponding to the local memory. When the memory capacity of the local memory does not reach the preset data volume water line, it is not necessary to adjust the local clock frequency for transmitting data.

[0040] Optionally, the preset data volume water lines include a full water line and an empty water line. Among them, the full water line is used to represent the overflow degree of the memory capacity, and the empty water line is used to represent the emptied degree of the memory capacity. And the frequency modulation operation on the clock frequency includes a frequency increase operation corresponding to the full water line and a frequency decrease operation corresponding to the empty water line. Moreover, during the continuous data transmission process, the frequency modulation operation on the clock frequency of the data transmission transceiver is dynamically adaptive.

[0041] Based on this, in step 203, performing a frequency modulation operation on the local clock frequency according to the frequency modulation parameter to synchronize the clock frequencies of the data transceiver may further include: Step 301: If the memory capacity reaches the full water line, obtain the frequency increase parameter corresponding to the full water line; Step 302: Perform a frequency increase operation on the local clock frequency according to the frequency increase parameter to synchronize the local clock frequency with the opposite-end clock frequency of the data transmission.

[0042] When comparing the memory capacity with the data volume water line and determining that it is necessary to adjust the local clock frequency for data transmission, specifically when the memory capacity reaches the full water line, obtain the frequency increase parameter corresponding to the full water line, and perform a frequency increase operation on the local clock frequency according to this frequency increase parameter to synchronize the local clock frequency with the opposite-end clock frequency of the data transmission, that is, to synchronize the local clock frequency with the opposite-end clock frequency corresponding to the local clock.

[0043] Further, after performing the frequency increase operation to adjust the local clock frequency, return and perform the step of obtaining the memory capacity of the local memory, determine whether further adjustment of the local clock frequency is required, and implement dynamic adjustment of the local clock frequency until all data transmission is completed.

[0044] Similarly, the data volume pipeline further includes an empty pipeline, and the frequency modulation parameter includes a frequency reduction parameter corresponding to the empty pipeline. If the memory capacity of the local memory reaches the empty pipeline, obtain the frequency reduction parameter corresponding to the empty pipeline, and perform a frequency reduction operation on the local clock frequency according to the obtained frequency reduction parameter to synchronize the local clock frequency with the peer clock frequency of the data transmission.

[0045] Based on this, in step 203, performing a frequency modulation operation on the local clock frequency according to the frequency modulation parameter to synchronize the clock frequencies of the data transceiver may further include: Step 401, if the memory capacity reaches the empty pipeline, obtain the frequency reduction parameter corresponding to the empty pipeline; Step 402, perform a frequency reduction operation on the local clock frequency according to the frequency reduction parameter to synchronize the local clock frequency with the peer clock frequency of the data transmission.

[0046] When comparing the memory capacity with the data volume pipeline and determining that the local clock frequency of the data transmission needs to be adjusted, specifically when the memory capacity reaches the empty pipeline, obtain the frequency reduction parameter corresponding to the empty pipeline, and perform a frequency reduction operation on the local clock frequency according to the frequency reduction parameter to synchronize the local clock frequency with the peer clock frequency of the data transmission, that is, to synchronize the local clock frequency with the peer clock frequency corresponding to the local clock.

[0047] Further, after performing the frequency reduction operation to adjust the local clock frequency, return and perform the step of obtaining the memory capacity of the local memory, determine whether further adjustment of the local clock frequency is required, and implement dynamic adjustment of the local clock frequency until all data transmission is completed.

[0048] Among them, the local clock frequency and the peer clock frequency respectively correspond to the transceiver ends of the data transmission. Among them, if the local clock frequency corresponds to the clock frequency of the data sending end, the peer clock frequency corresponds to the clock frequency of the data receiving end; if the local clock frequency corresponds to the clock frequency of the data receiving end, the peer clock frequency corresponds to the clock frequency of the data sending end.

[0049] After performing frequency modulation on the local clock frequency of data transmission, the change trend of the memory capacity of the local memory can be the same or different. In one embodiment, when the memory capacity reaches the full water line, the corresponding frequency increase parameter is obtained to perform a frequency increase operation on the memory capacity of the local memory, synchronize the clock frequencies of the receiving end and the sending end of the data transmission, and then continue to obtain the memory capacity of the local memory until all data transmission is completed. If the change trend of the memory capacity changes after the frequency increase operation, when the memory capacity reaches the empty water line, the corresponding frequency decrease parameter is obtained, and the local clock frequency is decreased according to the frequency decrease parameter, the clock frequencies of the receiving end and the sending end of the data transmission are synchronized, and then the memory capacity of the local memory is continuously obtained until the data transmission is completed.

[0050] In another embodiment, when the memory capacity reaches the empty water line, the corresponding frequency decrease parameter is obtained to perform a frequency decrease operation on the memory capacity of the local memory, synchronize the clock frequencies of the receiving end and the sending end of the data transmission, and then continue to obtain the memory capacity of the local memory until all data transmission is completed. If the change trend of the memory capacity changes after the frequency decrease operation, when the memory capacity reaches the full water line, the corresponding frequency increase parameter is obtained, and the local clock frequency is increased according to the frequency increase parameter, the clock frequencies of the receiving end and the sending end of the data transmission are synchronized, and then the memory capacity of the local memory is continuously obtained until the data transmission is completed.

[0051] Optionally, the data volume water line includes multiple full water lines. The frequency increase parameters corresponding to the multiple full water lines are positively correlated with the full water line. That is, there are multiple full water lines, and the multiple full water lines at least include a first full water line and a second full water line. The frequency increase parameters corresponding to the full water line at least include a first frequency increase parameter corresponding to the first full water line and a second frequency increase parameter corresponding to the second full water line. The frequency increase parameters corresponding to the multiple full water lines are positively correlated with the full water line.

[0052] Based on this, in step 302, performing a frequency increase operation on the local clock frequency of data transmission according to the frequency increase parameter to synchronize the clock frequencies of the data transceiver may further include: Step 312, if the memory capacity reaches the first full water line, perform a frequency increase operation on the clock frequency according to the first frequency increase parameter to synchronize the local clock frequency with the peer clock frequency of the data transmission; Step 322, if the memory capacity reaches the second full water line, perform a frequency increase operation on the local clock frequency according to the second frequency increase parameter to synchronize the local clock frequency with the peer clock frequency of the data transmission; the adjustment step of the second frequency increase parameter for the local clock frequency is greater than the adjustment step of the first frequency increase parameter for the local clock frequency.

[0053] If the memory capacity of the local memory reaches the first full water line, perform a frequency increase operation on the local clock frequency according to the first frequency increase parameter corresponding to the first full water line, so as to synchronize the local clock frequency with the peer clock frequency of data transmission. If the memory capacity of the local memory reaches the second full water line, perform a frequency increase operation on the local clock frequency according to the second frequency increase parameter corresponding to the second full water line, so as to synchronize the local clock frequency with the peer clock frequency of data transmission.

[0054] Optionally, the memory capacity threshold corresponding to the second full water line is greater than the memory capacity threshold corresponding to the first full water line, and the adjustment step of the second frequency increase parameter corresponding to the second full water line for the clock frequency is greater than the adjustment step of the first frequency increase parameter corresponding to the first full water line for the clock frequency. That is, the change amount of the clock frequency adjusted by performing the frequency increase operation according to the second frequency increase parameter is greater than the change amount of the clock frequency adjusted by performing the frequency increase operation according to the first frequency increase parameter.

[0055] In one embodiment, if the memory capacity of the local memory reaches the first full water line, perform a frequency increase operation on the local clock frequency according to the first frequency increase parameter, so as to synchronize the local clock frequency and the peer clock frequency of data transmission, and then return and execute the step of obtaining the memory capacity of the local memory to realize dynamic monitoring of the memory capacity. After performing the frequency increase operation on the clock frequency of the receiving end according to the first frequency increase parameter, if the change trend of the memory capacity does not change, generally, it is because the adjustment degree of the clock frequency is relatively low. At this time, the memory capacity still tends to be full until the memory capacity reaches the second full water line, and perform a frequency increase operation on the clock frequency of the receiving end according to the second frequency increase parameter, so as to reduce the amount of cached data more strongly and ensure that the local cached data will not overflow.

[0056] In another embodiment, after performing the frequency increase operation on the local clock frequency according to the first frequency increase parameter, the change trend of the memory capacity may change, and the amount of cached data will gradually decrease until the memory capacity reaches the empty water line, indicating that the adjustment degree of the local clock frequency is relatively large. Then, perform a frequency decrease operation on the local clock frequency according to the frequency decrease parameter corresponding to the empty water line to ensure that no empty data is generated.

[0057] Correspondingly, the data volume water line includes multiple empty water lines, and the frequency decrease parameters corresponding to the multiple empty water lines are positively correlated with the empty water line. That is, the empty water line can also include multiple ones. The multiple empty water lines at least include the first empty water line and the second empty water line. The frequency decrease parameters include the first frequency decrease parameter corresponding to the first empty water line and the second frequency decrease parameter corresponding to the second empty water line. The frequency decrease parameters corresponding to the multiple empty water lines are positively correlated with the empty water line.

[0058] Based on this, in step 402, performing a frequency decrease operation on the local clock frequency according to the frequency decrease parameter to synchronize the local clock frequency with the peer clock frequency of data transmission may further include: Step 412, if the memory capacity reaches the first empty water line, perform a down - frequency operation on the local clock frequency according to the first down - frequency parameter to synchronize the local clock frequency with the peer clock frequency of data transmission; Step 422, if the memory capacity reaches the second empty water line, perform a down - frequency operation on the local clock frequency according to the second down - frequency parameter to synchronize the local clock frequency with the peer clock frequency of data transmission; the adjustment step of the second down - frequency parameter for the clock frequency is greater than the adjustment step of the first down - frequency parameter for the clock frequency.

[0059] If the memory capacity of the local memory reaches the first empty water line, perform a down - frequency operation on the local clock frequency according to the first down - frequency parameter corresponding to the first empty water line, so as to synchronize the local clock frequency with the peer clock frequency of data transmission. If the memory capacity of the local memory reaches the second empty water line, perform a down - frequency operation on the local clock frequency according to the second down - frequency parameter corresponding to the second empty water line, so as to synchronize the local clock frequency with the peer clock frequency of data transmission.

[0060] Optionally, the memory capacity threshold corresponding to the second empty water line is less than the memory capacity threshold corresponding to the first empty water line, and the adjustment step of the second down - frequency parameter corresponding to the second empty water line for the clock frequency is greater than the adjustment step of the first down - frequency parameter corresponding to the first empty water line for the clock frequency. That is, the change amount of the clock frequency adjusted by performing the down - frequency operation according to the second down - frequency parameter is greater than the change amount of the clock frequency adjusted by performing the down - frequency operation according to the first down - frequency parameter.

[0061] In one embodiment, when the memory capacity of the local memory reaches the first empty water line, perform a down - frequency operation on the clock frequency for receiving audio data at the receiving end according to the first down - frequency parameter, so as to synchronize the local clock frequency and the peer clock frequency of data transmission, and then return and execute the step of obtaining the memory capacity of the local memory to realize dynamic monitoring of the memory capacity. After performing the down - frequency operation on the local clock frequency according to the first down - frequency parameter, if the change trend of the memory capacity does not change, it is generally because the adjustment degree of the clock frequency is relatively low. At this time, the memory capacity still tends to be in an empty state until the memory capacity reaches the second empty water line, and then perform a down - frequency operation on the local clock frequency according to the second down - frequency parameter, so as to increase the amount of cached data more strongly and ensure that no empty data is generated.

[0062] In another embodiment, after performing a down-frequency operation on the local clock frequency according to the first down-frequency parameter, the change trend of the memory capacity may change, and the amount of cached data will gradually increase. When the memory capacity reaches the first full waterline, it indicates that the adjustment degree of the local clock frequency is relatively large. Then, according to the first up-frequency parameter corresponding to the first full waterline, an up-frequency operation is performed on the local clock frequency to ensure that data does not overflow.

[0063] Referring to Figure 2 the adjustment process of the clock frequency shown, the local memory is provided with three full waterlines and three empty waterlines. Among them, the three full waterlines are respectively Figure 2 FULL1, FULL2, and FULL3 in Figure 2 , and the three empty waterlines are respectively

[0064] EMPTY1, EMPTY2, and EMPTY3 in Figure 2 . The local clock frequency is adjusted by monitoring the empty / full state of the memory capacity of the local memory. Specifically, when the trend of the memory capacity of the local memory is towards FULL, the local clock frequency needs to be increased; when the trend of the memory capacity of the local memory is towards EMPTY, the local clock frequency needs to be decreased, so as to perform adaptive dynamic frequency modulation. In this way, although the amount of data cached in the local memory changes dynamically, it will not reach the extreme EMPTY or FULL state, and thus will not cause data interruption or loss.

[0065] Furthermore, the greater the difference in memory capacity between two full waterlines or two empty waterlines, the longer the time required to move from one full waterline (empty waterline) to another full waterline (empty waterline), and thus the longer the time interval between two frequency modulation operations. Correspondingly, the smaller the difference in memory capacity between two full waterlines or two empty waterlines, the shorter the time required to move from one full waterline (empty waterline) to another full waterline (empty waterline), and thus the shorter the time interval between two frequency modulation operations.

[0066] In one embodiment, if the trend of the memory capacity of the local memory is towards FULL, for example, from HALF - FULL to FULL1, then to FULL2, and then to FULL3, a frequency increase operation is performed on the local clock frequency when the memory capacity reaches the first full waterline FULL1. If the trend of the memory capacity of the local memory still tends to be FULL, when it reaches the second full waterline FULL2, a frequency increase operation is performed on the local clock frequency again, and so on. When the memory capacity of the local memory reaches the third full waterline FULL3, a third frequency increase operation is performed on the local clock frequency. Similarly, if the trend of the memory capacity of the local memory is towards EMPTY, for example, from HALF - FULL to the first empty waterline EMPTY1, then to the second empty waterline EMPTY2, and then to the third empty waterline EMPTY3, a frequency decrease operation is performed on the local clock frequency whenever the memory capacity of the local memory reaches each empty waterline, so as to synchronize the local clock frequency with the peer clock frequency.

[0067] Furthermore, if after a frequency increase operation is performed when the memory capacity of the receiving end reaches the first full waterline FULL1, the clock frequency of the receiving end becomes greater than or equal to the clock frequency of the sending end, then the trend of the memory capacity of the receiving end will no longer tend towards the FULL state. Specifically, if the clock frequency of the receiving end is the same as that of the sending end, the memory capacity of the receiving end will be maintained between the first full waterline FULL1 and the first empty waterline EMPTY1. At this time, there is no need to perform a frequency modulation operation again. If, after a frequency increase operation is performed when the memory capacity of the receiving end reaches the first full waterline FULL1, the adjustment range of the clock frequency of the receiving end is too large, resulting in the clock frequency of the receiving end being greater than the clock frequency of the sending end, then the trend of the memory capacity of the receiving end will tend towards EMPTY. When the memory capacity of the receiving end reaches the first empty waterline EMPTY1, a frequency decrease operation is performed on the clock frequency of the receiving end. At this time, part or all of the frequency decrease operation performed at the first empty waterline EMPTY1 can cancel out part or all of the frequency increase operation performed at the first full waterline FULL1, and then the trend of the memory capacity of the receiving end will tend towards the first full waterline FULL1 again, and so on, to achieve dynamic adjustment of the memory capacity and clock frequency of the receiving end.

[0068] Optionally, the frequency step size adjusted during the frequency increase operation at the full water level is configurable, and the frequency step size adjusted during the frequency decrease operation at the empty water level is also configurable. The larger the adjusted frequency step size, the greater the increase or decrease in the clock frequency for each frequency modulation operation, which may cause greater clock oscillation, but the corresponding frequency modulation ability is also stronger, making the adjustment and application of the clock frequency more flexible.

[0069] Optionally, the adjustment of the clock frequency through the frequency modulation operation can be achieved by adjusting the division factor of the internal frequency divider. Therefore, in step 203, performing the frequency modulation operation on the local clock frequency according to the frequency modulation parameter may further include: Step 601, determining the adjustment amount of the division factor of the frequency divider according to the frequency modulation parameter; Step 602, adjusting the division factor according to the adjustment amount to perform the frequency modulation operation on the local clock frequency; the division factor is negatively correlated with the local clock frequency.

[0070] Determine the adjustment amount of the division factor of the frequency divider of the data transceiver according to the frequency modulation parameter, and adjust the division factor according to the adjustment amount, so as to realize the frequency modulation operation of the local clock frequency. The division factor is negatively correlated with the local clock frequency.

[0071] Specifically, for the internal frequency divider of the data transceiver, its division factor is negatively correlated with the clock frequency. The larger the division factor, the smaller the divided frequency. Therefore, if it is necessary to perform a frequency increase operation on the local clock frequency, the division factor can be selected to be adjusted smaller; if it is necessary to perform a frequency decrease operation on the local clock frequency, the division factor can be selected to be adjusted larger to achieve the purpose of frequency modulation.

[0072] During the frequency increase operation, determine the adjustment amount of the division factor of the frequency divider according to the frequency increase parameter, and adjust the division factor smaller according to the adjustment amount, so as to increase the clock frequency of the receiving end and realize the frequency increase of the local clock frequency. Correspondingly, during the frequency decrease operation, determine the adjustment amount of the division factor of the frequency divider according to the frequency decrease parameter, and adjust the division factor larger according to the adjustment amount, so as to increase the clock frequency of the receiving end and realize the frequency decrease of the local clock frequency.

[0073] Further, after step 200, it may further include: Step 300, performing data transmission according to the synchronized clock frequency.

[0074] Perform data transmission according to the synchronized clock frequency to realize the monitoring and dynamic adjustment of the memory capacity of the local memory.

[0075] In this embodiment, by monitoring the change in the capacity of the local memory at the receiving end, the clock frequency of data transmission is adjusted to eliminate the frequency difference between the data sending and receiving ends during long-distance transmission, thereby avoiding the problem of data desynchronization and achieving lossless data transmission. Moreover, since the adaptive frequency modulation of the clock frequency is an automatic operation without the intervention of an external SOC, it releases the memory and bandwidth of the SOC, speeds up the processing rate, and requires a small memory capacity, which can reduce the chip area and save hardware costs.

[0076] The data transmission synchronization device provided by the present invention will be described below. The data transmission synchronization device described below can be correspondingly referred to the data transmission synchronization method described above.

[0077] Refer to Figure 3 , the data transmission synchronization device provided by the embodiment of the present invention includes: A memory capacity monitoring module 10, configured to obtain the memory capacity of the local memory, where the local memory is the memory of any one of the data transmission sending and receiving ends; A clock frequency synchronization module 20, configured to synchronize the clock frequencies of the data transmission sending and receiving ends according to the memory capacity.

[0078] In one embodiment, the clock frequency synchronization module 20 is further configured to: Compare the memory capacity with a preset data volume waterline to determine whether it is necessary to adjust the local clock frequency of data transmission, where the local clock frequency is the clock frequency corresponding to the local memory; If it is determined that it is necessary to adjust the local clock frequency, obtain the frequency modulation parameter corresponding to the data volume waterline; Perform a frequency modulation operation on the local clock frequency according to the frequency modulation parameter to synchronize the clock frequencies of the data transmission sending and receiving ends.

[0079] In one embodiment, the data volume waterline includes a full waterline and an empty waterline; the clock frequency synchronization module 20 is further configured to: If the memory capacity reaches the full waterline, obtain the frequency increase parameter corresponding to the full waterline; Perform a frequency increase operation on the local clock frequency according to the frequency increase parameter to synchronize the local clock frequency with the clock frequency of the opposite end of the data transmission.

[0080] In one embodiment, there are multiple full waterlines, and the frequency increase parameters corresponding to the multiple full waterlines are positively correlated with the full waterlines.

[0081] In one embodiment, the data volume waterline includes an empty waterline; the clock frequency synchronization module 30 is further configured to: If the memory capacity reaches the empty water line, obtain the down - frequency parameter corresponding to the empty water line; Perform a down - frequency operation on the local clock frequency according to the down - frequency parameter to synchronize the local clock frequency with the peer clock frequency of the data transmission.

[0082] In one embodiment, the data volume water line includes a plurality of the empty water lines, and the down - frequency parameters corresponding to the plurality of the empty water lines are positively correlated with the empty water line.

[0083] In one embodiment, the data transmission synchronization device further includes a data transmission module for: Perform data transmission according to the synchronized clock frequency.

[0084] Figure 4 Illustrates a schematic physical structure diagram of an electronic device, as Figure 4 shown, the electronic device may include: a processor 410, a communication interface 420, a memory 430, and a communication bus 440. Among them, the processor 410, the communication interface 420, and the memory 430 complete mutual communication through the communication bus 440. The processor 410 can call the logical instructions in the memory 430 to execute the steps of the data transmission synchronization method, for example, including: Obtain the memory capacity of the local memory, where the local memory is the memory of any one end of the data transmission transceiver; Synchronize the clock frequencies of the data transmission transceiver according to the memory capacity.

[0085] In addition, when the logical instructions in the above - mentioned memory 430 are implemented in the form of software functional units and sold or used as an independent product, they can be stored in a computer - readable storage medium. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The foregoing storage medium includes: USB flash drives, mobile hard disks, read - only memories (ROM, Read - Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical disks and other various media that can store program codes.

[0086] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the steps of the data transmission synchronization method provided by each of the above methods, for example, including: Obtain the memory capacity of the local memory, where the local memory is the memory of either end of the data transmission transceiver; Synchronize the clock frequencies of the data transmission transceivers according to the memory capacity.

[0087] In another aspect, the present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements the steps of the data transmission synchronization method provided by each of the above methods, for example, including: Obtain the memory capacity of the local memory, where the local memory is the memory of either end of the data transmission transceiver; Synchronize the clock frequencies of the data transmission transceivers according to the memory capacity.

[0088] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art can understand and implement it without creative efforts.

[0089] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the essence of the above technical solution, or the part that contributes to the prior art, can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disc, etc., and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0090] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A data transmission synchronization method, characterized in that, Including: Obtain the memory capacity of the local memory, where the local memory is the memory at any end of the data transmission transceiver; Synchronize the clock frequency of the data transmission transceiver according to the memory capacity.

2. The data transmission synchronization method according to claim 1, wherein The synchronizing the clock frequency of the data transmission transceiver according to the memory capacity includes: Compare the memory capacity with a preset data volume waterline to determine whether to adjust the local clock frequency of data transmission, where the local clock frequency is the clock frequency corresponding to the local memory; If it is determined that the local clock frequency needs to be adjusted, obtain the frequency modulation parameter corresponding to the data volume waterline; Perform a frequency modulation operation on the local clock frequency according to the frequency modulation parameter to synchronize the clock frequency of the data transmission transceiver.

3. The data transmission synchronization method according to claim 2, characterized in that, The data volume waterline includes a full waterline. The performing a frequency modulation operation on the local clock frequency according to the frequency modulation parameter to synchronize the clock frequency of the data transmission transceiver includes: If the memory capacity reaches the full waterline, obtain the frequency increase parameter corresponding to the full waterline; Perform a frequency increase operation on the local clock frequency according to the frequency increase parameter to synchronize the local clock frequency with the opposite-end clock frequency of data transmission.

4. The data transmission synchronization method according to claim 3, wherein The data volume waterline includes a plurality of the full waterlines, and the frequency increase parameters corresponding to the plurality of full waterlines are positively correlated with the full waterline.

5. The data transmission synchronization method according to claim 2, wherein The data volume waterline includes an empty waterline. The performing a frequency modulation operation on the local clock frequency according to the frequency modulation parameter to synchronize the clock frequency of the data transmission transceiver includes: If the memory capacity reaches the empty waterline, obtain the frequency decrease parameter corresponding to the empty waterline; Perform a frequency decrease operation on the local clock frequency according to the frequency decrease parameter to synchronize the local clock frequency with the opposite-end clock frequency of data transmission.

6. The data transmission synchronization method according to claim 5, characterized in that The data volume waterline includes a plurality of the empty waterlines, and the frequency decrease parameters corresponding to the plurality of empty waterlines are positively correlated with the empty waterline.

7. The data transmission synchronization method according to claim 1, wherein The data transmission synchronization method further includes: Perform data transmission according to the synchronized clock frequency.

8. A data transmission synchronization device, characterized in that, Including: A memory capacity monitoring module, configured to obtain the memory capacity of the local memory, where the local memory is the memory at any end of the data transmission transceiver; A clock frequency synchronization module, configured to synchronize the clock frequency of the data transmission transceiver according to the memory capacity.

9. An electronic device, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the data transmission synchronization method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the data transmission synchronization method according to any one of claims 1 to 7.

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