Multi-core system-on-chip
By introducing the design of the kernel switching control unit and shared memory peripheral module in the multi-core system-level chip, the problem of high R&D cost of different CPU core chips is solved, and rapid mass production and cost savings are achieved.
Patent Information
- Application Number
- CN202510392669.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-28
- Publication Date
- 2025-07-11
AI Technical Summary
In the prior art, it takes a lot of manpower, process and verification costs to develop system-level chips with different CPU cores, and the R&D cycle is long.
Design a multi-core system-level chip, including at least two CPU cores, a core switching control unit, a memory module and a peripheral module. After power-on, a CPU core is selected as the current running core after power-on, and the memory and peripheral modules are configured to realize the sharing of multi-core SoC chips.
Reduced R&D costs, improved R&D efficiency, and achieved rapid mass production.
Smart Images
Figure CN120295964A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of integrated circuits, and more particularly to a multi-core system-on-chip. Background Art
[0002] As the application scenarios of electronic devices become more and more extensive, some electronic devices may need to adopt different Central Processing Unit (CPU) cores according to specific application scenarios. For example, RISC-V cores are used in the domestic market, and ARM Cortex cores are used in the foreign market. One approach is to separately develop System-on-Chip (SoC) chips based on different CPU cores for different application scenarios. However, the R & D costs and R & D cycle in terms of manpower, process, verification, etc. are almost twice that of developing a single SoC chip. Summary of the Invention
[0003] The multi-core system-on-chip according to an embodiment of the present invention includes at least two CPU cores, a core switching control unit, a memory module, a peripheral module, and a bus. Among them: The core switching control unit is configured to select one CPU core from at least two CPU cores as the currently running CPU core after the multi-core system-on-chip is powered on, configure the memory module and the peripheral module via the bus using the running parameters of the currently running CPU core, and start the currently running CPU core and turn off the CPU cores other than the currently running CPU core among at least two CPU cores after the configuration of the memory module and the peripheral module is completed. Brief Description of the Drawings
[0004] The present invention can be better understood from the following description of the specific embodiments in conjunction with the drawings, where:
[0005] Figure 1 Shows a schematic diagram of the overall solution of the multi-core SoC chip according to an embodiment of the present invention.
[0006] Figure 2 Shows a schematic diagram of an example implementation of the multi-core SoC chip according to an embodiment of the present invention.
[0007] Figure 3 Shows Figure 2 A schematic diagram of the storage space allocation of the program read-only memory shown.
[0008] Figure 4 Shows a schematic diagram of an example implementation of the multi-core SoC chip according to an embodiment of the present invention.
[0009] Figure 5 Shows an example flowchart of the static core switching process in the multi-core SoC chip according to an embodiment of the present invention.
[0010] Figure 6 It shows an example waveform diagram of relevant signals during the execution of the static core switching process after the multi-core SoC chip is powered on according to an embodiment of the present invention.
[0011] Figure 7 It shows an example flow chart of the initial core startup process during the dynamic core switching process in a multi-core SoC chip according to an embodiment of the present invention.
[0012] Figure 8 It shows an example flow chart of the running core switching process during the dynamic core switching process in a multi-core SoC chip according to an embodiment of the present invention.
[0013] Figure 9 It shows an example waveform diagram of relevant signals during the execution of the dynamic core switching process by a multi-core SoC chip according to an embodiment of the present invention. Detailed implementation manners
[0014] The features and exemplary embodiments of various aspects of the present invention will be described in detail below. In the following detailed description, many specific details are set forth in order to provide a comprehensive understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without some of these specific details. The following description of the embodiments is only intended to provide a better understanding of the present invention by showing examples of the present invention. The present invention is in no way limited to any specific configuration and algorithm proposed below, but covers any modification, replacement, and improvement of elements, components, and algorithms without departing from the spirit of the present invention. Well-known structures and technologies are not shown in the drawings and the following description in order to avoid unnecessarily obscuring the present invention. Additionally, it should be noted that the term "A is connected to B" used here may mean "A is directly connected to B" or "A is indirectly connected to B via one or more other elements".
[0015] In order to reduce the R & D cost and quickly achieve mass production, a multi-core SoC chip according to an embodiment of the present invention is proposed, which includes at least two CPU cores and realizes the sharing of internal modules of the multi-core SoC chip by at least two CPU cores through a core switching control unit.
[0016] Figure 1 It shows a schematic diagram of the overall solution of a multi-core SoC chip according to an embodiment of the present invention. As Figure 1As shown, the multi-core SoC chip 100 includes at least two CPU cores (e.g., CPU cores 102-1 and 102-2), a core switching control unit 104, a memory module 106, a peripheral module 108, and a bus 110, where: The core switching control unit 104 is configured to select one of the at least two CPU cores as the currently running CPU core after the multi-core SoC chip 100 is powered on, configure the memory module 106 and the peripheral module 108 via the bus 110 using the operating parameters of the currently running CPU core, and start the currently running CPU core and turn off the CPU cores other than the currently running CPU core among the at least two CPU cores after the configuration of the memory module 106 and the peripheral module 108 is completed. It should be noted that after the currently running CPU core is started, it will communicate with the memory module 106 and / or the peripheral module 108 via the core switching control unit 104 and the bus 110.
[0017] As Figure 1 shown, in some embodiments, the core switching control unit 104 may also be configured to select one of the at least two CPU cores as the currently running CPU core based on the status of a predetermined input / output pin of the multi-core SoC chip 100 or based on a preset value stored in the memory module 106.
[0018] As Figure 1 shown, in some embodiments, the currently running CPU core may be configured to send a switching request to the core switching control unit 104 when a core switching request is received from the outside during the operation of the multi-core SoC chip 100 or when it detects that the current state of the multi-core SoC chip 100 meets the core switching condition. Correspondingly, the core switching control unit 104 may also be configured to turn off the currently running CPU core when receiving the switching request from the currently running CPU core, select a CPU core different from the currently running CPU core among the at least two CPU cores as the switching target CPU core, configure the memory module 106 and the peripheral module 108 via the bus 110 using the operating parameters of the switching target CPU core, and start the switching target CPU core after the configuration of the memory module 106 and the peripheral module 108 is completed. Similarly, after the switching target CPU core is started, it will communicate with the memory module 106 and / or the peripheral module 108 via the core switching control unit 104 and the bus 110.
[0019] As Figure 1As shown, in some embodiments, the currently running CPU core may also be configured to receive a core switching request from the outside through a Universal Asynchronous Receiver / Transmitter (UART) interface, an Inter-Integrated Circuit (I2C) interface, or a Radio Frequency (RF) wireless communication interface, and / or detect whether the state of a predetermined input / output (I / O) pin of the multi-core SoC chip 100 or the software running state of the multi-core SoC chip 100 meets the core switching conditions. For example, during the operation of the multi-core SoC chip 100, the currently running CPU core may send a switching request when one or more of the following conditions are met: receiving external information or an interrupt request (this interrupt request may originate from a hardware-triggered interrupt, for example, the level at a predetermined IO pin is pulled low) from the outside that requests a core switch, or receiving a data packet containing specific content through the UART interface, the I2C interface, or the RF wireless communication interface, or when the current data processing volume of the multi-core SoC chip 100 is extremely large and it is necessary to switch from a CPU core with lower performance to a CPU core with higher performance, and after processing is completed, switch back to the CPU core with lower performance (for power saving).
[0020] Figure 2 FIG. shows an exemplary implementation schematic diagram of a multi-core SoC chip according to an embodiment of the present invention. As Figure 2 shown, the multi-core SoC chip 100-1 includes at least two CPU cores (for example, CPU cores 102-1 and 102-2), a core switching control unit 104, a memory module 106, a peripheral module 108, a bus 110, a clock and reset signal source 112, and a clock and reset switching unit 114, where: the clock and reset signal source 112 is configured to generate a system clock signal and a system reset signal based on a predetermined setting after the multi-core SoC chip 100-1 is powered on, and generate a system clock signal and a system reset signal based on the operation parameter information about the currently running CPU core or the switching target CPU core from the core switching control unit 104 after the currently running CPU core or the switching target CPU core is started; the clock and reset switching unit 114 is configured to generate a clock signal and a reset signal for the currently running CPU core or the switching target CPU core and a clock signal and a reset signal for other CPU cores in the at least two CPU cores that are different from the currently running CPU core or the switching target CPU core based on the system clock signal and the system reset signal from the clock and reset signal source 112 and the identification information for indicating the currently running CPU core or the switching target CPU core from the core switching control unit 104.
[0021] As Figure 2 shown, in some embodiments, the memory module 106 includes a program read-only memory and a data random access memory, and the program read-only memory stores only the program associated with the currently running CPU core or stores the programs associated with each of at least two CPU cores. In this case, the core switching control unit 104 can also be configured to, when the currently running CPU core is started, set the address offset of the read instruction for the program read-only memory of the memory module 106 based on the start address and the size of the storage space associated with the currently running CPU core in the program read-only memory of the memory module 106, or when the target CPU core to be switched is started, set the address offset of the read instruction for the program read-only memory of the memory module 106 based on the start address and the size of the storage space associated with the target CPU core to be switched in the program read-only memory of the memory module 106.
[0022] In Figure 2 shown, in some embodiments, the core switching control unit 104 can also be configured to operate based on the system clock signal and the system reset signal from the clock and reset signal source 112, and after selecting the currently running CPU core or the target CPU core to be switched, send the operation parameter information of the currently running CPU core or the target CPU core to be switched to the clock and reset signal source 112 and send the identification information of the currently running CPU core or the target CPU core to be switched to the clock and reset switching unit 114.
[0023] As Figure 2 shown, in some embodiments, the core switching control unit 104 can also be configured to, for any one of at least two CPU cores, start or shut down the CPU core by sending an enable signal to the CPU core, wherein when the enable signal is in the first level state, the CPU core is shut down, and when the enable signal is in the second level state, the CPU core is started.
[0024] As Figure 2 shown, in some embodiments, any one of at least two CPU cores can be configured to send a switching request by sending a request signal to the core switching control unit 102 during the process of running as the currently running CPU core.
[0025] Figure 3 Shows Figure 2 the schematic diagram of the allocation of the storage space of the program read-only memory shown. As Figure 3As shown, in the case where the multi-core SoC chip 100-1 includes two CPU cores (i.e., CPU cores 102-1 and 102-2), the storage space of the program read-only memory can be evenly allocated to the two CPU cores. For example, for CPU core 102-2, the associated storage space is from 0x10000 to 0x2FFFF, and the starting address is 0x10000. Therefore, during the operation of CPU core 102-2, the kernel switching control unit 104 adds 0x10000 to the address of the read instruction for the program read-only memory as the final address for accessing the program read-only memory. It should be understood that in practical applications, programs associated with different types of CPU cores have different code lengths, and the storage space of the program read-only memory may not necessarily be evenly allocated to the multiple CPU cores in the multi-core SoC chip 100-1, but rather the proportion of the storage space associated with each CPU core in the storage space of the program read-only memory can be determined according to the code length of the program associated with each CPU core.
[0026] Figure 4 FIG. shows an exemplary implementation schematic diagram of a multi-core SoC chip according to an embodiment of the present invention. As Figure 2 shown, the multi-core SoC chip 100-2 includes at least two CPU cores (e.g., CPU cores 102-1 and 102-2), a kernel switching control unit 104, a memory module 106, a peripheral module 108, a bus 110, a clock and reset signal source 112, and a clock and reset switching unit 114, where: the memory module 106 includes a code random access memory and a data random access memory, and the code random access memory is used to store programs associated with the currently running CPU core or the switching target CPU core; the kernel switching control unit 104 can also be configured to, after selecting the currently running CPU core, determine whether the multi-core SoC chip 100 is connected to an external program read-only memory, and in the case where the determination result is yes, load the program associated with the currently running CPU core from the external program read-only memory into the code random access memory; or after selecting the switching target CPU core, determine whether the multi-core SoC chip 100 is connected to an external program read-only memory, and in the case where the determination result is yes, clear the program associated with the currently running CPU core from the code random access memory and load the program associated with the switching target CPU core from the external program read-only memory into the code random access memory.
[0027] It should be noted that the content described in connection with Figure 1 the multi-core SoC chip 100 also applies to Figure 2 the multi-core SoC chip 100-1 shown in Figure 4 and the multi-core SoC chip 100-2 shown in Figure 2The content described for the multi-core SoC chip 100-1 also applies to Figure 4 the multi-core SoC chip 100-2 shown in the figure. For the sake of brevity, these contents will not be repeated here.
[0028] Figure 5 FIG. shows an example flowchart of the static core switching process in a multi-core SoC chip according to an embodiment of the present invention. Here, it is assumed that the memory module 106 includes a program read-only memory and the multi-core SoC chip 100 only includes two CPU cores 102-1 and 102-2. The static core switching process executed after the multi-core SoC chip 100 is powered on includes: S502, the core switching control unit 104 starts first, and the two CPU cores are powered on but do not run temporarily; S504, the core switching control unit 104 selects the CPU core to be started (i.e., the currently running CPU core); S506, the core switching control unit 104 configures the memory module 106 and the peripheral module 108 with the operating parameters of the selected CPU core (such as clock frequency, bus structure and bit width, program space size and start address, etc.); and S508, the core switching control unit 104 turns off the CPU core that does not need to be started to put it in the lowest power consumption state, and starts the selected CPU core, so that the multi-core SoC chip 100 enters normal operation.
[0029] Figure 6 FIG. shows an example waveform diagram of relevant signals during the execution of the static core switching process after the multi-core SoC chip according to an embodiment of the present invention is powered on, where: VDD represents the power supply voltage of the multi-core SoC chip 100, Reset represents the system reset signal of the multi-core SoC chip 100, Clock represents the system clock signal of the multi-core SoC chip 100, Reset_1 represents the reset signal for the CPU core 102-1, Clock_1 represents the clock signal for the CPU core 102-1, Reset_2 represents the reset signal for the CPU core 102-2, and Clock_2 represents the clock signal for the CPU core 102-2. As Figure 6 shown, when the multi-core SoC chip 100 is powered on, the system clock signal Clock starts to be generated, and then the system reset signal reset is released. At this time, the core switching control unit 104 starts first and selects the CPU core to be started; in the case where the core switching control unit 104 selects to start the CPU core 102-1 (i.e., selects the CPU core 102-2 as the currently running CPU core), the reset signal Reset_1 for the CPU core 102-1 is released, the clock signal Clock_1 for the CPU core 102-1 is maintained, the reset signal Reset_2 for the CPU core 102-2 is maintained, and the clock signal Clock_2 for the CPU core 102-2 is turned off.
[0030] Figure 7 FIG. shows an example flowchart of an initial core startup process during a dynamic core switching process in a multi-core SoC chip according to an embodiment of the present invention. Here, it is assumed that the memory module 106 includes a code random access memory and the multi-core SoC chip 100 includes only two CPU cores 102-1 and 102-2. The initial core startup process executed after the multi-core SoC chip 100 is powered on includes: S702, the core switching control unit 104 is first started, and the two CPU cores 102-1 and 102-2 are powered on but not running temporarily; S704, the core switching control unit 104 selects the CPU core to be started; S706, the core switching control unit 104 determines whether an external program read-only memory is connected to the multi-core SoC chip 100; S708, if no external program read-only memory is connected, the core switching control unit 104 generates a connection prompt signal for prompting to connect the external program read-only memory; S710, if an external program read-only memory is connected, the core switching control unit 104 loads the program associated with the selected CPU core from the external program read-only memory into the code random access memory; S712, the core switching control unit 104 configures the memory module 106 and the peripheral module 108 with the operating parameters (such as clock frequency, bus structure and bit width, program space size, etc.) of the selected CPU core; and S714, the core switching control unit 104 shuts down the CPU cores that do not need to be started to place them in the lowest power consumption state, and starts the selected CPU core, so that the multi-core SoC chip 100 enters normal operation.
[0031] Figure 8 FIG. shows an example flowchart of a running core switching process during a dynamic core switching process in a multi-core SoC chip according to an embodiment of the present invention. Here, it is assumed that the memory module 106 includes a code random access memory and the multi-core SoC chip 100 includes only two CPU cores 102-1 and 102-2. When the CPU core 102-1 is used as the currently running CPU core and is running, Figure 7The running kernel switching process executed after the initial kernel startup process shown includes: S802, after the kernel switching control unit 104 receives a switching request, it takes over the bus 110, shuts down the CPU core 102-1, and optionally configures the peripheral module 108 to an idle state to avoid malfunction; S804, the kernel switching control unit 104 determines whether an external program read-only memory is connected to the multi-core SoC chip 100; S806, if no external program read-only memory is connected, the kernel switching control unit 104 generates a connection prompt signal for prompting the connection of the external program read-only memory; S808, if an external program read-only memory is connected, the kernel switching control unit 104 clears the program associated with the CPU core 102-1 from the code random access memory, and loads the program associated with the CPU core 102-2 (i.e., the switching target CPU core) from the external program read-only memory into the code random access memory; S810, the kernel switching control unit 104 configures the memory module 106 and the peripheral module 108 with the operating parameters of the CPU core 102-2; and S812, the kernel switching control unit 104 releases the bus and starts the CPU core 102-2, so that the multi-core SoC chip 100 enters normal operation. It should be noted that since only two CPU cores 102-1 and 102-2 are included in the multi-core SoC chip 100, the kernel switching control unit 104 can execute the subsequent process by taking the CPU core 102-2 as the switching target CPU core without selection after receiving the switching request from the CPU core 102-1. Alternatively, in S806, if no external program read-only memory is connected, the kernel switching control unit 104 can also terminate the kernel switching process and restart the CPU core 102-1.
[0032] Figure 9 FIG. shows an example waveform diagram of related signals during the dynamic kernel switching process executed by the multi-core SoC chip according to an embodiment of the present invention, where: Clock_1 represents the clock signal for the CPU core 102-1, Enable_1 represents the enable signal for the CPU core 102-1, Clock_2 represents the clock signal for the CPU core 102-2, and Enable_2 represents the enable signal for the CPU core 102-2. As Figure 9 shown, when the kernel switching control unit 104 receives a switching request from the CPU core 102-1, it takes over the bus 110, shuts down the CPU core 102-1 through the enable signal Enable_1, loads the program associated with the CPU core 102-2 from the external program read-only memory into the code random access memory, configures the memory module 106 and the peripheral module 108 with the operating parameters of the CPU core 102-2, and then releases the bus 110 and turns on the CPU core 102-2.
[0033] It should be noted that the multi-core SoC chip according to the embodiments of the present invention may include various types of CPU cores. For example, RISC-V cores, ARM Cortex-M cores, and 8051 / PIC cores, etc.
[0034] As is known to those skilled in the art, in addition to including a CPU core, a single-core SoC chip will integrate many functional modules according to application requirements, such as a clock management unit, a power management unit, a memory unit, an analog interface unit, an input / output serial interface unit, a timer and a pulse width modulation unit, a hardware accelerator unit, a sensor unit, etc. Generally, the area occupied by the CPU core in a single-core SoC chip is relatively small. Integrating two CPU cores into one SoC chip can significantly save chip area compared to two single-core SoC chips including different CPU cores. Especially when using advanced manufacturing processes, the cost of masks is high, and making one set of masks can save half of the mask cost compared to making two sets of masks. Further, integrating more than two CPU cores into one SoC chip can further save chip area and mask cost.
[0035] The present invention may be implemented in other specific forms without departing from its spirit and essential features. For example, the algorithms described in specific embodiments may be modified without the system architecture departing from the basic spirit of the present invention. Therefore, the current embodiments are regarded as exemplary in all aspects rather than restrictive, and the scope of the present invention is defined by the appended claims rather than the above description, and all changes falling within the meaning and equivalents of the claims are thus included in the scope of the present invention.
Claims
1. A multi-core system-on-chip, comprising at least two CPU cores, a core switching control unit, a memory module, a peripheral module, and a bus, wherein: The core switching control unit is configured to select, after the multi-core system-on-chip is powered on, one of the at least two CPU cores as the currently running CPU core, configure the memory module and the peripheral module via the bus by using the operating parameters of the currently running CPU core, and start the currently running CPU core and turn off the CPU cores other than the currently running CPU core among the at least two CPU cores after the configuration of the memory module and the peripheral module is completed.
2. The multi-core system-on-chip according to claim 1, wherein The currently running CPU core is configured to send a switching request to the core switching control unit when a core switching request is received from the outside or the current state of the multi-core system-on-chip is detected to meet the core switching condition during the operation of the multi-core system-on-chip, and The core switching control unit is further configured to, when receiving the switching request, turn off the currently running CPU core, select one of the at least two CPU cores different from the currently running CPU core as the switching target CPU core, configure the memory module and the peripheral module via the bus by using the operating parameters of the switching target CPU core, and start the switching target CPU core after the configuration of the memory module and the peripheral module is completed.
3. The multi-core system-on-chip according to claim 1 or 2, wherein, The memory module includes a program read-only memory, and the program read-only memory stores only the program associated with the currently running CPU core or stores the program associated with each of the at least two CPU cores.
4. The multi-core system-on-chip according to claim 3, wherein, The core switching control unit is further configured to set an address offset for the read instruction of the program read-only memory based on the start address and the size of the storage space associated with the currently running CPU core in the program read-only memory when the currently running CPU core is started, or set an address offset for the read instruction of the program read-only memory based on the start address and the size of the storage space associated with the switching target CPU core in the program read-only memory when the switching target CPU core is started.
5. The multi-core system-on-chip according to claim 1 or 2, wherein, The memory module includes a code random access memory, and the code random access memory is used to store the program associated with the currently running CPU core or the switching target CPU core.
6. The multi-core system-on-chip according to claim 5, wherein, The kernel switching control unit is further configured to, after selecting the currently running CPU kernel, determine whether an external program read-only memory is connected to the multi-core system-on-chip, and if the determination result is yes, load the program associated with the currently running CPU kernel from the external program read-only memory into the code random access memory, or after selecting the switching target CPU kernel, determine whether the external program read-only memory is connected to the multi-core system-on-chip, and if the determination result is yes, clear the program associated with the currently running CPU kernel from the code random access memory and load the program associated with the switching target CPU kernel from the external program read-only memory into the code random access memory.
7. The multi-core system-on-chip according to claim 2, wherein, The kernel switching control unit is further configured to, in addition to shutting down the currently running CPU kernel, also configure the peripheral module to an idle state.
8. The multi-core system-on-chip according to claim 2, wherein, The currently running CPU kernel is further configured to receive the kernel switching request from the outside through a universal asynchronous receiver / transmitter interface, an inter-integrated circuit interface, or a radio frequency wireless communication interface, or detect whether the state of a predetermined input / output pin of the multi-core system-on-chip or the software running state of the multi-core system-on-chip meets the kernel switching condition.
9. The multi-core system-on-chip according to claim 1, further comprising: A clock and reset signal source, configured to generate a system clock signal and a system reset signal based on a predetermined setting after the multi-core system-on-chip is powered on, and generate the system clock signal and the system reset signal based on the operation parameter information about the currently running CPU kernel or the switching target CPU kernel from the kernel switching control unit after the currently running CPU kernel or the switching target CPU kernel is started; And A clock and reset switching unit, configured to generate a clock signal and a reset signal for the currently running CPU kernel or the switching target CPU kernel and a clock signal and a reset signal for other CPU kernels in the at least two CPU kernels different from the currently running CPU kernel or the switching target CPU kernel based on the system clock signal, the system reset signal, and the identification information from the kernel switching control unit indicating the currently running CPU kernel or the switching target CPU kernel.
10. The multi-core system-on-chip according to claim 9, wherein, The kernel switching control unit is further configured to operate based on the system clock signal and the system reset signal, and after selecting the currently running CPU kernel or the switching target CPU kernel, send the operation parameter information of the currently running CPU kernel or the switching target CPU kernel to the clock and reset signal source and send the identification information of the currently running CPU kernel or the switching target CPU kernel to the clock and reset switching unit.
11. The multi-core system-on-chip according to claim 1, wherein, The kernel switching control unit is further configured to start or shut down any one of the at least two CPU cores by sending an enable signal to that CPU core, wherein when the enable signal is in a first level state, that CPU core is shut down, and when the enable signal is in a second level state, that CPU core is started.
12. The multi-core system-on-chip according to claim 1, wherein, Any one of the at least two CPU cores is configured to send the switching request by sending a request signal to the kernel switching control unit when operating as the currently operating CPU core.
13. The multi-core system-on-chip according to claim 1, wherein, The kernel switching control unit may also be configured to select one of the at least two CPU cores as the currently operating CPU core based on the state of a predetermined input / output pin of the multi-core system-on-chip or based on a preset value stored in the memory module.