Reconfigurable hybrid PUF (Physical Unclonable Function) circuit capable of resisting reverse engineering and machine learning attacks
By designing a reconfigurable hybrid PUF circuit, combining delay unit blocks and state control units, security enhancement against machine learning and reverse engineering under white box attacks is achieved, suitable for resource-constrained devices.
Patent Information
- Application Number
- CN202510354893.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-25
- Publication Date
- 2025-07-11
AI Technical Summary
Existing PUF circuits have weak anti-machine learning attack capabilities under white box attacks and are vulnerable to reverse engineering attacks, resulting in security threats.
A reconfigurable hybrid PUF circuit that resists reverse engineering and machine learning attacks is designed, combining N-class delay unit blocks, response generation units and state control units to generate dynamic logic confusion through switching between weak PUF mode and strong PUF mode, increasing the difficulty of attacks.
Improves the security of PUF circuits, enhances resistance to machine learning modeling attacks, and reduces hardware overhead, suitable for resource-constrained devices.
Smart Images
Figure CN120296806A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the field of hardware security, and in particular to a reconfigurable hybrid PUF circuit resistant to reverse engineering and machine learning attacks. Background Art
[0002] As a brand-new security mechanism, Physical Unclonable Functions (PUFs) rely on the characteristics of physical hardware and have unique advantages. PUF generally represents the mapping relationship of standard input-output in the form of an excitation-response pair (CRP). According to the scale of CRPs, it can be divided into weak PUF and strong PUF. Strong PUF can generate more CRPs and is often applied to lightweight authentication of Internet of Things devices. However, with the rapid development of random Machine Learning (ML), attackers use a small amount of collected CRP data and use machine learning models to model the PUF, so as to predict the response of the PUF with extremely high accuracy, which poses a great security risk to the PUF. In particular, strong PUFs are extremely vulnerable to machine learning attacks, such as Arbiter PUF (APUF) and Ring oscillator PUF (RO PUF).
[0003] In recent years, to enhance the resistance of PUF to machine learning modeling attacks, researchers mainly prevent attacks by introducing non-linear operations to obscure the mapping relationship between CRPs. The most common response obfuscation technique is XOR APUF, which generates the final XOR APUF response bit by performing an exclusive OR operation on the response bits of multiple parallel APUFs. In addition, some studies further improve the security of XOR APUF by increasing the number of APUFs. Another type of research uses LFSR to obfuscate the excitation response, such as the FLAM-PUF design. This design realizes challenge obfuscation by performing an exclusive OR operation on the response of the previous round of APUF and the taps of the Galois linear feedback shift register (LFSR), and generates the final response through multiple iterations. Recently, some studies have also proposed a configurable three-state PUF (CT PUF). This design integrates the Arbiter PUF, Ring oscillator PUF (RO PUF), and Bistable ring PUF (BR PUF) to form a flexible configurable PUF hardware structure. The circuit performs an exclusive OR operation on the original challenge C and the response RArbiter generated by the APUF to hide the information of the original challenge C. Then, the hidden excitation is input into the RO PUF or BR PUF to generate the obfuscated response RXOR. By combining the obfuscated response RXOR with RArbiter, the mapping relationship between the excitation and the response is further complicated.
[0004] However, according to the current research, a mimicry attack method has been proposed. This method regards the target PUF as a white box and builds a dedicated ANN to imitate the working principle and structure of the target PUF, and has successfully broken through various PUF designs. It can be seen that at present, most anti-attack technologies will pose a great threat to the security of PUFs when the attacker obtains the internal circuit structure information of the PUF through means such as reverse engineering. Most anti-machine learning modeling attack technologies are analyzed based on the situation where the attacker can only obtain the original CRP, that is, black box attacks. However, with the development of reverse engineering technology, the attacker can further obtain the structure of the PUF circuit to achieve the white box attack scenario, which makes most of the PUF designs resistant to machine learning attacks ineffective. Existing research has not considered the anti-reverse engineering problem of the PUF itself, resulting in the attacker being able to easily obtain the specific structure of the PUF circuit and carry out targeted modeling attacks. In addition, due to the simple structure and small circuit scale of the PUF itself, traditional anti-reverse chip technologies are not applicable to the protection of the PUF. Summary of the Invention
[0005] An embodiment of the present application provides a reconfigurable hybrid PUF circuit that resists reverse engineering and machine learning attacks, so as to solve the problem that strong PUFs are less resistant to machine learning model attacks under white box attacks.
[0006] On the one hand, the present application provides a reconfigurable hybrid PUF circuit that resists reverse engineering and machine learning attacks, and the circuit includes:
[0007] An N-stage cascaded delay unit block, the delay unit block includes an upper input / output and a lower input / output, and an external excitation. The upper output passes through N-stage cascading to output an upper delay signal, and the lower output passes through N-stage cascading to output a lower delay signal;
[0008] A response generation unit, the response generation unit includes storage and computing circuits corresponding to the weak PUF mode and the strong PUF mode, and determines the target bit signal output in each round based on the delay signal of the delay unit block and the target working mode of the PUF circuit;
[0009] A state control unit, the state control unit receives the upper delay signal and the lower delay signal fed back and input by the N-stage delay unit block, and controls the generation of the upper input signal and the lower input signal based on the mode enable signal corresponding to the target working mode;
[0010] The upper input signal and the lower input signal are fed into the N-stage cascaded delay unit block; each stage of the delay unit block performs circuit equivalent reconstruction and output according to the corresponding external excitation.
[0011] Specifically, the weak PUF mode includes the static memory storage SRAM PUF mode, and the strong PUF mode includes the arbiter APUF mode, the ring oscillator RO PUF mode, and the bistable ring BR PUF mode.
[0012] Specifically, the i-th delay unit block includes an upper branch and a lower branch with the same structure. Each branch sequentially includes a first selector, an exclusive-OR gate, and a second selector. The first selector is a dual-input single-output selector, and the second selector is a dual-input dual-output selector.
[0013] The second input terminal of the first selector in each branch is the branch input. One input of the exclusive-OR gate in each branch is connected to the output terminal of the first selector, and the other input commonly receives the i-th external input signal.
[0014] The outputs of the exclusive-OR gate in the upper branch are respectively fed into the first input terminal of the second selector in the upper branch and the second input terminal of the second selector in the lower branch. The outputs of the exclusive-OR gate in the lower branch are respectively fed into the first input terminal of the second selector in the lower branch and the second input terminal of the second selector in the upper branch.
[0015] The first output terminal of the second selector in each branch is the branch output, which is connected to the corresponding branch input in the (i + 1)-th delay unit block. The first input terminal of the first selector in the upper branch is connected to the second output terminal of the second selector in the lower branch, and the first input terminal of the first selector in the lower branch is connected to the second output terminal of the second selector in the upper branch.
[0016] Specifically, in the i-th delay unit, the first selectors of the two branches are controlled by a shared first selection signal to gate the output. When the first selectors of the two branches in all delay units gate the first input terminals, the circuit enters the weak PUF mode. When the first selectors of the two branches in all delay units gate the second input terminals, the circuit enters the strong PUF mode.
[0017] In the i-th delay unit, the first input terminal of the second selector corresponds to the first output terminal, and the second input terminal corresponds to the second output terminal. The second selectors of the two branches are controlled by a shared second selection signal to gate the output. When one of the input terminals of the second selector is gated, the corresponding output terminal is gated to output, and the output of the other input terminal is set to 0.
[0018] Specifically, the response generation unit includes an arbitration calculation unit, a frequency counting unit, a BR register unit, and an SRAM register unit, corresponding to the outputs of the N-stage cascaded delay unit blocks in the APUF mode, RO PUF mode, BR PUF mode, and SRAM PUF mode respectively.
[0019] Specifically, in the weak PUF mode, when the input signals of all XOR gates in N delay cell blocks are at high level, and the second selector fully selects the first or second input terminals, the circuit is reconstructed into the SRAM PUF mode;
[0020] In the strong PUF mode, when the number of delay cell blocks with high-level external input signals of XOR gates is odd, and the number of delay cell blocks where the second selector selects the second input terminal is also odd, the circuit is reconstructed into the BR PUF mode;
[0021] When the number of delay cell blocks with high-level external input signals of XOR gates is odd, and the number of delay cell blocks where the second selector selects the second input terminal is even, the circuit is reconstructed into the RO PUF mode;
[0022] When the number of delay cell blocks with high-level external input signals of XOR gates is even, the circuit is reconstructed into the APUF mode.
[0023] Specifically, when the external input signal of the XOR gate is at high level, the XOR gate in the corresponding delay cell block is equivalent to an inverter;
[0024] In the weak PUF mode, the signals between adjacent delay cell blocks are isolated by virtual disconnection, and the outputs of each branch of the delay cell block are reversely cross-fed back to the branch inputs; in the strong PUF mode, the cross-feedback loops of each branch in the delay cell block are in virtual disconnection, and the signals between adjacent delay cell blocks are cascaded.
[0025] Specifically, the state control unit includes symmetric upper and lower delay branches, and each delay branch contains two AND gates and a multiplexer;
[0026] In the upper delay branch, the first AND gate inputs the upper delay signal and the RO PUF mode enable signal, and the output is connected to the first input terminal of the multiplexer; the second AND gate inputs the lower delay signal and the BR PUF mode enable signal, and the output is connected to the second input terminal of the multiplexer;
[0027] In the lower delay branch, the first AND gate inputs the lower delay signal and the RO PUF mode enable signal, and the output is connected to the first input terminal of the multiplexer; the second AND gate inputs the upper delay signal and the BR PUF mode enable signal, and the output is connected to the second input terminal of the multiplexer;
[0028] The APUF mode enable signal is respectively input to the third input terminals of the multiplexers in the two branches, and the multiplexers in the two branches are jointly controlled based on the mode signal, and respectively select and output the upper input signal and the lower input signal to the N-stage cascaded delay cell blocks.
[0029] Specifically, in the APUF mode, the two delayed signals are respectively sent to the arbitration calculation unit, and a single-bit signal is output after arbitration calculation;
[0030] In the RO PUF mode, the two delayed signals are respectively sent to the frequency counting unit, and the target bit signal is output through frequency comparison;
[0031] In the BR PUF mode, the upper delayed signal outputs the target bit signal and stores it in the BR register unit;
[0032] In the SRAM PUF mode, the upper delayed signal outputs the target bit signal and sequentially stores it in the SRAM register unit to form a circuit key.
[0033] Specifically, when the circuit is started, it is configured in the SRAM PUF mode, and the circuit key is formed by the output of the upper delayed signal; when the circuit key is consistent with the preset key, the circuit is reconstructed in the order of the APUF mode, the RO PUF mode, and the BR PUF mode in sequence. Each time a single-bit target signal is output, and after three loop sequences, a 9-bit target response is output.
[0034] The beneficial effects brought by the technical solutions provided in the embodiments of the present application at least include: the reconfigurable strong-weak hybrid PUF provided in the present application utilizes the innate immunity characteristics of SRAM PUF against machine learning modeling attacks to assist the strong PUF in generating responses, improving the security of the strong PUF. In addition, by implementing reconfigurable strong and weak PUFs under the same structure, it has the advantage of low hardware overhead compared to using an external SRAM PUF array, and is suitable for resource-constrained devices. Description of the Drawings
[0035] Figure 1 It is a schematic structural diagram of a reconfigurable hybrid PUF circuit for anti-reverse engineering and machine learning attacks provided by an embodiment of the present application;
[0036] Figure 2 It is a schematic diagram of the principle of the confusion mechanism of this hybrid PUF circuit;
[0037] Figure 3 It is a schematic circuit diagram of the delay unit provided by an embodiment of the present application;
[0038] Figure 4 It is a schematic structural diagram of the state control unit;
[0039] Figure 5 It is a schematic equivalent circuit diagram in the SRAM PUF mode;
[0040] Figure 6 It is a schematic equivalent circuit diagram in the APUF mode;
[0041] Figure 7 It is a schematic diagram of the equivalent circuit in the RO PUF mode;
[0042] Figure 8 It is a schematic diagram of the equivalent circuit in the BR PUF mode. Detailed implementation manners
[0043] To make the objectives, technical solutions and advantages of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.
[0044] As used herein, "a plurality of" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after.
[0045] Anti-chip reverse engineering technology: At the current stage, the protection technology against transmission microscopes and other reverse engineering equipment mainly defends from the aspects of hardware and circuit design. For example, the self-destruction technology based on MEMS (Micro-Electro-Mechanical System) induces the self-destruction of key components by integrating a micro-resistance heater, fundamentally preventing the circuit from being further analyzed. However, this circuit has extremely high requirements for reliability and may be mis-triggered by environmental changes. There is also a chip-level protection technology based on variable interconnections, which increases the difficulty of reverse engineering by changing the physical structure of the chip during intrusion detection. However, this method requires a large amount of hardware resources, which is difficult to achieve for devices with limited resources. At the same time, a new method based on logic obfuscation can increase the analysis difficulty through a dynamic key generation mechanism when the attacker obtains the complete netlist, but its high computational requirements and complexity make it unable to be widely applied in resource-constrained devices. Based on the above problems, the present application designs a PUF circuit that combines multiple modes to increase the difficulty of reverse engineering analysis.
[0046] Figure 1 It is a schematic diagram of the structure of a reconfigurable hybrid PUF circuit for anti-reverse engineering and machine learning attacks provided by an embodiment of the present application, which sequentially includes a state control unit, an N-stage cascaded delay unit block, and a response generation unit.
[0047] For the N-stage cascaded delay unit block delay unit, each delay unit block includes an upper input / output and a lower input / output, as well as an external excitation (C0 - C n-1 ), and the first delay unit block passed by the upper output respectively inputs the upper input signal U0 and the lower input signal D0. After N-stage cascaded delays on the upper path, the upper delay signal U1 is output, and after N-stage cascaded delays on the lower path, the lower delay signal D1 is output.
[0048] The response generation unit includes storage and computing circuits corresponding to the weak PUF mode and the strong PUF mode for various PUF modes, and determines the target bit signal output in each round based on the up and down path delay signals of the delay unit block and the target working mode of the PUF circuit in each round. The target working mode is set by switching according to the circuit working conditions, generating a key in the weak PUF mode and generating a response R in the strong PUF mode.
[0049] The state control unit is specifically used to control the feedback input of the delay signal, including the up and down path feedback inputs and a path mode enable signal input. The upper and lower two feedback input terminals correspond to the up path delay signal and the down path delay signal fed back by the N-stage delay unit block. The mode enable signal is used to select the target working mode and control the generation of the upper path input signal U0 and the lower path input signal D0 based on the up and down path delay signals. After U0 and D0 are sent into the N-stage cascaded delay unit block, each stage of the delay unit block performs circuit equivalent reconstruction and output according to the corresponding external excitations Cx and Cm.
[0050] The weak PUF mode designed in this application includes the static memory storage SRAM PUF mode, and the strong PUF mode includes the arbiter APUF mode, the ring oscillator RO PUF mode, and the bistable ring BR PUF mode. This is because the traditional strong PUF is vulnerable to machine learning modeling attacks, while the weak PUF units are independent of other PUF units and have no correlation, and have innate immunity to modeling attacks. Therefore, we use a weak PUF (SRAM PUF) to assist the strong PUF in generating a response, and propose a reconfigurable PUF structure integrating the strong and the weak. That is, when the circuit starts up, it is configured in the SRAM PUF mode, and a circuit key is formed by the output of the up path delay signal. Subsequently, according to the key matching situation, a single-bit target signal is switched and output in the APUF mode, the RO PUF mode, and the BR PUF mode, and finally a 9-bit target response is output through 9 rounds of iteration.
[0051] Figure 2It is a schematic diagram of the obfuscation mechanism principle of this hybrid PUF circuit. The dynamic logic obfuscation technology is adopted to prevent attackers from obtaining the circuit structure through reverse engineering and conducting white-box attacks on the PUF. First, when the system starts, the control logic will default to configure the circuit in the SRAM PUF mode, and the SRAM PUF circuit is used to generate a unique circuit key. This key will be processed through a hash algorithm and then matched and verified with the preset hash key initially stored in the circuit. If the key verification is successful (i.e., the key generated by the SRAM PUF is consistent with the preset key), the PUF module will be activated in the correct order (APUF → RO PUF → BRPUF). Each corresponding state PUF will generate a corresponding response and output after running three cycles (taking a 9-bit target response as an example in this embodiment). If the key verification fails, the system will activate the PUF module, but the order will become random, generating different response sequences. This out-of-order behavior increases the difficulty for attackers because they cannot infer the system state by observing the order of PUF responses. The introduction of the out-of-order mechanism makes it impossible for attackers to accurately establish a PUF model and collect effective CRP to train the corresponding PUF model even if they can obtain the specific structure of the circuit, greatly increasing the difficulty for attackers to obtain effective circuit information.
[0052] Figure 3 It is a schematic diagram of the circuit of the delay unit provided by the embodiment of this application. Taking the i-th delay unit block as an example, the i-th delay unit block includes an upper branch and a lower branch with the same structure. Each branch includes a first selector MUX1, an exclusive-OR gate, and a second selector MUX2. Here, the first selector MUX1 is a dual-input single-output selector, and the second selector MUX1 is a dual-input dual-output selector. The first input terminal corresponds to the first output terminal, and the second input terminal corresponds to the second output terminal.
[0053] It should be noted here that one of the dual outputs is a false output. For example Figure 3 for ports 0 and 1 in []. Assuming that the O6 signal output corresponding to port 0 is selected, the O5 signal corresponding to port 1 is set to the low level 0, which is equivalent to a virtual break state of the connection with O5. Correspondingly, assuming that the O5 signal output corresponding to port 1 is selected, the O6 signal corresponding to port 0 is set to the low level 0, and the connection with O6 is in a virtual break state.
[0054] The second input terminal (port 1) of MUX1 in each branch is the branch input. One input of the exclusive-OR gate in each branch is connected to the output terminal of MUX1, and the other input commonly receives the i-th external input signal ( Figure 3 the Cx signal of the blue line in []).
[0055] Specific to each branch, the outputs of the upper-branch XOR gates are respectively fed into the first input terminal (port 0) of the upper-branch MUX2 and the second input terminal (port 1) of the lower-branch MUX2. Correspondingly, the outputs of the lower-branch XOR gates are respectively fed into the first input terminal (port 0) of the lower-branch MUX2 and the second input terminal (port 1) of the upper-branch MUX2.
[0056] The first output terminal (O6) of MUX2 in each branch is the branch output, which is connected to the corresponding branch input in the (i + 1)-th delay unit block. The first input terminal (port 0) of the upper-branch MUX1 is connected to the second output terminal (O5) of the lower-branch MUX2, and the first input terminal (port 0) of the lower-branch MUX1 is connected to the second output terminal (O5) of the upper-branch MUX2.
[0057] In the above-mentioned delay unit, in the i-th delay unit, the MUX1s of the two branches respectively control the gated output through the shared first selection signal Cs, and the MUX2s respectively control the gated output through the shared second selection signal Cm.
[0058] When the MUX1s of the two branches in all delay units gate the first input terminal (port 0), the circuit enters the weak PUF mode. When the MUX1s of the two branches in all delay units gate the second input terminal (port 1), the circuit enters the strong PUF mode. In this application, a low level is used as the signal for selecting the first terminal (port 0), and a high level is used as the signal for selecting the second terminal (port 1).
[0059] As for how the state control unit generates the input signal according to the feedback loop, see Figure 4 As shown, it is a schematic circuit diagram of the state control unit.
[0060] The state control unit also includes symmetric upper and lower delay branches. Each delay branch contains two AND gates and a multiplexer. This multiplexer has a three-way output, and the three input terminals respectively correspond to the RO PUF mode output, the BR PUF mode output, and the APUF mode output.
[0061] In the upper delay branch, the first AND gate AND1 inputs the upper delay signal U1 and the RO PUF mode enable signal, and its output is connected to the first input terminal of the multiplexer; the second AND gate AND2 inputs the lower delay signal D1 and the BR PUF mode enable signal, and its output is connected to the second input terminal of the multiplexer;
[0062] In the lower delay branch, the first AND gate AND1 inputs the lower path delay signal and the RO PUF mode enable signal, and its output is connected to the first input terminal of the multiplexer; the second AND gate AND2 inputs the upper path delay signal and the BR PUF mode enable signal, and its output is connected to the second input terminal of the multiplexer;
[0063] The APUF mode enable signal is respectively input to the third input terminal of the multiplexer in the two branches. The multiplexers in the two branches are jointly controlled based on the mode signal Sctrl, and respectively select and output the upper path input signal and the lower path input signal to the N-stage cascaded delay unit block.
[0064] By connecting the above functional blocks, the U0 and D0 signals can be selectively generated according to the specific target working mode.
[0065] In this solution, the XOR gate of the delay unit is relatively special because it has two input terminals. When Cx = 1 in this application, according to the relationship of the truth table, the XOR gate is equivalent to a NOT gate circuit. Based on this, this application designs a hybrid PUF circuit.
[0066] Figures 5 - 8 It is a schematic diagram of the equivalent circuit of four equivalent hybrid PUF modes. Taking these four modes as examples, the response generation unit respectively includes an arbitration calculation unit, a frequency counting unit, a BR register unit, and an SRAM register unit, which respectively correspond to the outputs of the N-stage cascaded delay unit block in the APUF mode, RO PUF mode, BR PUF mode, and SRAM PUF mode. For the state control unit.
[0067] SRAM PUF mode: The input signals of all XOR gates in the N delay unit blocks are high level, and the second selector fully selects the first or second input terminal;
[0068] See Figure 5 , for the weak PUF premise, it is necessary to ensure that Cs = 0 in the N delay units, that is, select the port 0 output of MUX1. The Cm of MUX2 in the N delay units all select the same level signal value, such as all selecting port 0 or all selecting port 1, and the XOR gate Cx = 1 in the N delay units. The purpose here is to equivalent all the XOR gates to NOT gates.
[0069] Under this equivalent result, the gating signal of MUX1 is determined, equivalent to the wire being ignored, and the signal (O6 signal) between adjacent delay units is isolated with a virtual break. After the state control unit is equivalent, the outputs of MUX2 on each branch of the delay unit are cross - feedbacked in reverse to the inputs of the branch inverters. Specifically, the two outputs of the original exclusive - OR gate are respectively connected to the MUX2 on the upper and lower branches. However, due to the cross - feedback, the O6 signal has a virtual break, and the O5 signal cross - feedbacks and flows back to port 0 of MUX1. Therefore, the signal shunted to the other branch finally feedbacks back to this branch. After equivalence, the inverters and MUX2 on each branch have a one - to - one correspondence. APUF mode: The number of delay unit blocks with a high - level external input signal to the exclusive - OR gate is an even number;
[0070] See Figure 6 , for the strong PUF premise, it is necessary to ensure that Cs = 1 in N delay units, that is, the output of port 1 of MUX1 is selected. The number of exclusive - OR gates with Cx = 1 in N delay units is an even number. The purpose here is to delay the signal through an even number of NOT gates without changing the signal value, which is equivalent to the signal remaining unchanged. The effect of this is that the upper and lower path delay signals finally output by N cascaded delay units are directly arbitrated and calculated. The loop where the original upper and lower path delay signals U1 and D1 feedback to the state control unit is equivalent to not existing (an even number of NOT gates will not affect the delay signal value of the branch output no matter how they feedback).
[0071] RO PUF mode: The number of delay unit blocks with a high - level external input signal to the exclusive - OR gate is an odd number, and the number of delay unit blocks where the second selector selects the second input terminal is an even number;
[0072] See Figure 7 , for the strong PUF premise, it is necessary to ensure that Cs = 1 in N delay units, that is, the output of port 1 of MUX1 is selected. The number of exclusive - OR gates with Cx = 1 in N delay units is an odd number, and the number of MUX2s that select port 1 output (O5 signal) is an even number. Because the number of Cx = 1 here is an odd number, the feedback loop between the upper and lower path delay signals and the state control unit is still effective. Since the number of Cm = 1 is an even number, the loop formed by the control logic in the structure makes U1 connected to U0 in reverse and D1 connected to D0 in reverse, forming two independent RO oscillation circuits, and the oscillation frequencies of each are calculated by the frequency counting unit respectively. Finally, the target bit signal (output response) is output by comparing the two RO oscillation frequencies.
[0073] BR PUF mode: The number of delay unit blocks with a high - level external input signal to the exclusive - OR gate is an odd number, and the number of delay unit blocks where the second selector selects the second input terminal is also an odd number;
[0074] See Figure 8 , for the strong PUF premise, it is necessary to ensure that Cs = 1 in N delay units, that is, select the output of port 1 of MUX1. The number of XOR gates Cx = 1 in N delay units is odd, and the number of MUX2 selecting port 1 output (O5 signal) is also odd. Since the number of Cx = 1 here is odd, the feedback loop between the up / down delay signals and the loop of the state control unit remains effective. When finally outputting, the up delay signal is output as the target bit signal and stored in the BR register unit.
[0075] It should be noted that since the BR PUF mode needs to implement cross-feedback input, this function is realized by the state control unit. As can be seen from Figure 4 , after the output of the N-stage delay unit, U1 and D1 are cross-input under the action of AND2, that is, the feedback signal U1 is connected to D0, and D1 is connected to U0, forming a steady-state circuit composed of an even number of inverters. In fact, the Sctrl signal of this application is determined according to the number of 1s in Cx and Cm. That is to say, whether the circuit forms a loop is determined according to the parity of Cx = 1 and Cm = 1, so that state switching of different modes can be realized.
[0076] In summary, the reconfigurable strong / weak hybrid PUF provided by this application uses the innate immunity of SRAM PUF to machine learning modeling attacks to assist the strong PUF to generate responses, improving the security of the strong PUF. In addition, by implementing reconfigurable strong / weak PUFs under the same structure, it has the advantage of low hardware overhead compared with using an external SRAM PUF array and is suitable for resource-constrained devices. For reverse engineering attacks, the dynamic logic obfuscation technology proposed in this application makes the type of PUF dynamically configured by the excitation signal, so that the attacker cannot dynamically observe the running state of the system. At the same time, this design sets an out-of-order mechanism. The system will only obtain a valid response when the key is correct and executed in the correct order. Otherwise, the system is in an out-of-order state, so that the attacker cannot obtain whether the response is correct through the response mode, resulting in the inability to obtain valid CRPs for model training, effectively preventing this attack method. Whether the key generated by the SRAM PUF is correct or not, the circuit normally outputs a response. Compared with other technologies where the system will self-destruct and work abnormally when the key is incorrect, it increases the confusion for attackers.
[0077] This specific embodiment is only an explanation of the present invention, and it is not a limitation of the present invention. Those skilled in the art can make modifications without creative contributions to this embodiment according to needs after reading this specification, but as long as they are within the scope of the claims of the present invention, they are protected by the patent law.
Claims
1. A reconfigurable hybrid PUF circuit resistant to reverse engineering and machine learning attacks, characterized in that, The circuit includes: An N-stage cascaded delay unit block, the delay unit block includes an upper path input / output and a lower path input / output, and an external excitation. The upper path output outputs an upper path delay signal after N-stage cascading, and the lower path output outputs a lower path delay signal after N-stage cascading; A response generation unit, the response generation unit includes storage and calculation circuits corresponding to the weak PUF mode and the strong PUF mode, and determines the target bit signal output in each round based on the delay signals of the delay unit block and the target working mode of the PUF circuit; A state control unit, the state control unit receives the upper path delay signal and the lower path delay signal fed back by the N-stage delay unit block, and controls the generation of the upper path input signal and the lower path input signal based on the mode enable signal corresponding to the target working mode; The upper path input signal and the lower path input signal are fed into the N-stage cascaded delay unit block; each stage of the delay unit block performs circuit equivalent reconstruction and output according to the corresponding external excitation.
2. The reconfigurable hybrid PUF circuit resistant to reverse engineering and machine learning attacks according to claim 1, wherein The weak PUF mode includes the static memory storage SRAM PUF mode, and the strong PUF mode includes the arbiter APUF mode, the ring oscillator RO PUF mode, and the bistable ring BR PUF mode.
3. The reconfigurable hybrid PUF circuit resistant to reverse engineering and machine learning attacks according to claim 2, wherein The i-th delay unit block includes upper and lower branches with the same structure. Each branch is successively a first selector, an exclusive-OR gate, and a second selector; the first selector is a dual-input single-output selector, and the second selector is a dual-input dual-output selector; The second input terminal of the first selector in each branch is the branch input. One input of the exclusive-OR gate in each branch is connected to the output terminal of the first selector, and the other input commonly inputs the i-th external input signal; The output of the exclusive-OR gate in the upper branch is respectively fed into the first input terminal of the second selector in the upper branch and the second input terminal of the second selector in the lower branch; The output of the exclusive-OR gate in the lower branch is respectively fed into the first input terminal of the second selector in the lower branch and the second input terminal of the second selector in the upper branch; The first output terminal of the second selector in each branch is the branch output, which is connected to the corresponding branch input in the (i + 1)-th delay unit block; The first input terminal of the first selector in the upper branch is connected to the second output terminal of the second selector in the lower branch, and the first input terminal of the first selector in the lower branch is connected to the second output terminal of the second selector in the upper branch.
4. The reconfigurable hybrid PUF circuit resistant to reverse engineering and machine learning attacks according to claim 3, wherein In the i-th delay unit, the first selectors of the two branches are controlled by a common first selection signal to gate the output; when the first selectors of the two branches in all delay units gate the first input terminal, the circuit enters the weak PUF mode, and when the first selectors of the two branches in all delay units gate the second input terminal, the circuit enters the strong PUF mode; In the i-th delay unit, the first input terminal of the second selector corresponds to the first output terminal, and the second input terminal corresponds to the second output terminal. The second selectors of the two branches are controlled by a common second selection signal to gate the output; when one of the input terminals of the second selector is gated, the corresponding output terminal is gated to output, and the output of the output terminal corresponding to the other input terminal is set to 0.
5. The reconfigurable hybrid PUF circuit resistant to reverse engineering and machine learning attacks according to claim 2, wherein The response generation unit includes an arbitration calculation unit, a frequency counting unit, a BR register unit, and an SRAM register unit, which respectively correspond to the outputs of the N-stage cascaded delay cell blocks in the APUF mode, RO PUF mode, BR PUF mode, and SRAM PUF mode.
6. The reconfigurable hybrid PUF circuit resistant to reverse engineering and machine learning attacks according to claim 4, characterized in that, In the weak PUF mode, when the input signals of all the exclusive-OR gates in the N delay cell blocks are at high level and the second selector fully selects the first or second input terminals, the circuit is reconstructed into the SRAM PUF mode; In the strong PUF mode, when the number of delay cell blocks with the external input signal of the exclusive-OR gate at high level is odd and the number of delay cell blocks with the second selector selecting the second input terminal is also odd, the circuit is reconstructed into the BR PUF mode; When the number of delay cell blocks with the external input signal of the exclusive-OR gate at high level is odd and the number of delay cell blocks with the second selector selecting the second input terminal is even, the circuit is reconstructed into the RO PUF mode; When the number of delay cell blocks with the external input signal of the exclusive-OR gate at high level is even, the circuit is reconstructed into the APUF mode.
7. The reconfigurable hybrid PUF circuit resistant to reverse engineering and machine learning attacks according to claim 3, wherein When the external input signal of the exclusive-OR gate is at high level, the exclusive-OR gate in the corresponding delay cell block is equivalent to an inverter; In the weak PUF mode, the signals between adjacent delay cell blocks are isolated by virtual disconnection, and the outputs of each branch of the delay cell block are reversely cross-fed back to the branch input; in the strong PUF mode, the cross-feedback loops of each branch in the delay cell block are in virtual disconnection, and the signals between adjacent delay cell blocks are cascaded.
8. The reconfigurable hybrid PUF circuit resistant to reverse engineering and machine learning attacks according to claim 7, wherein, The state control unit includes symmetric upper and lower delay branches, and each delay branch contains two AND gates and a multiplexer; In the upper delay branch, the first AND gate inputs the upper path delay signal and the RO PUF mode enable signal, and its output is connected to the first input terminal of the multiplexer; the second AND gate inputs the lower path delay signal and the BR PUF mode enable signal, and its output is connected to the second input terminal of the multiplexer; In the lower delay branch, the first AND gate inputs the lower path delay signal and the RO PUF mode enable signal, and its output is connected to the first input terminal of the multiplexer; the second AND gate inputs the upper path delay signal and the BR PUF mode enable signal, and its output is connected to the second input terminal of the multiplexer; The APUF mode enable signal is respectively input to the third input terminals of the multiplexers in the two branches. The multiplexers in the two branches are jointly controlled based on the mode signal, and respectively select and output the upper path input signal and the lower path input signal to the N-stage cascaded delay cell blocks.
9. The reconfigurable hybrid PUF circuit resistant to reverse engineering and machine learning attacks according to claim 5, characterized in that, In the APUF mode, the two path delay signals are respectively sent to the arbitration calculation unit, and a single-bit signal is output after arbitration calculation; In the RO PUF mode, the two path delay signals are respectively sent to the frequency counting unit, and a target bit signal is output through frequency comparison; In the BR PUF mode, the upper path delay signal outputs a target bit signal and stores it in the BR register unit; In the SRAM PUF mode, the upper path delay signal outputs a target bit signal and sequentially stores it in the SRAM register unit to form a circuit key.
10. The reconfigurable hybrid PUF circuit resistant to reverse engineering and machine learning attacks according to claim 2, wherein When the circuit is started, it is configured in the SRAM PUF mode, and a circuit key is formed by outputting the upper path delay signal; when the circuit key is consistent with the preset key, the circuit is reconstructed in sequence according to the APUF mode, the RO PUF mode, and the BR PUF mode, outputting a single-bit target signal each time, and a 9-bit target response is output after three cycles are executed in sequence.