Asynchronous parallel multi-target Bayesian optimization method supporting constraint processing

Abstract

The invention belongs to the field of integrated circuit computer aided design / electronic design automation, and particularly relates to an asynchronous parallel multi-objective Bayesian optimization method supporting constraint processing for an analog circuit optimization problem. The method is used for solving the multi-objective optimization problem of an analog circuit with constraint. According to the method, an expected hyper-volume lifting function is used as an acquisition function, a dynamic reference point selection strategy is adopted to process constraints, and asynchronous parallel circuit simulation is used. The invention belongs to an asynchronous parallel multi-objective optimization algorithm supporting constraint processing, and has relatively high simulation time efficiency for multi-objective optimization of an analog circuit.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit computer-aided design / electronic design automation (CAD / EDA), and particularly relates to an asynchronous batch constrained multi-objective Bayesian optimization method for supporting constraint processing in analog circuit optimization problems. Background Art

[0002] With the continuous development of advanced integrated circuit processes, the feature size of devices has gradually decreased, and the circuit scale has increased day by day. Different from digital integrated circuits that can rely on mature automation tools for design, analog integrated circuits still require manual design by engineers. With the demand for rapid product iteration, the automated design of analog integrated circuits has received increasing attention.

[0003] Since a circuit will generate multiple different performance metrics, engineers usually need to make trade-offs among different performance metrics. In circuit optimization problems, people use the figure of merit (FOM) to weight each performance metric to obtain a single optimization objective. Such optimization problems are also called single-objective optimization problems. Many methods for single-objective optimization of analog circuits have been proposed internationally, such as methods based on particle swarm optimization (PSO) [1], methods based on differential evolution (DE) [2], methods based on multi-starting point (MSP) [3-5], and methods based on Bayesian optimization (BO) [6-10].

[0004] For system-level integrated circuit design, the industrial community usually adopts a hierarchical design method that divides the entire circuit into multiple units for processing. The design specifications of each unit are determined by the upper-level design. When the upper-level design specifications are changed or multiple different units are matched, the design specifications of the current unit need to be changed accordingly. For the single-objective optimization method of analog circuits, in this case, the optimization has to be re-executed. Therefore, multi-objective optimization (MOO) is introduced into the analog circuit optimization problem. Different from single-objective optimization that gives a unique optimal solution, multi-objective optimization gives a set of optimal solution sets, and engineers can select the most suitable optimization solution according to the requirements of performance indicators, thus avoiding repeated execution of optimization.

[0005] For multi-objective optimization problems, the currently mainstream methods internationally are evolutionary algorithm-based methods, such as NSGA-II

[11] and MOEA / D

[12] . These methods generate a population of simulation candidate points and iteratively optimize the candidate points in the population through crossover and mutation operators, thus effectively realizing the exploration of the optimal solution set. However, these methods often require consuming a large amount of circuit simulation resources. Under a limited optimization time budget, the cost of these methods is unacceptable. To address this problem, Lyu et al. proposed a multi-objective Bayesian optimization (MOBO) method for analog circuit optimization

[13] , which uses a Gaussian process regression model (GPR model) as a surrogate model to replace the actual simulation for evaluating circuit performance, thus avoiding the large demand for simulation resources. However, the MOBO method is a serial optimization method and does not support constraint handling.

[0006] In recent years, cloud computing based on data centers has enabled users to access rich computing resources without the high cost of purchasing expensive machines, which has promoted the development of parallel technologies. Parallel optimization methods can be divided into synchronous batch and asynchronous batch methods. The synchronous batch method waits for all simulation results of the same batch of parallel simulations to be returned before starting the next batch of parallel simulations. It can make full use of the existing data set, but there is a waste of idle time intervals in the case of different simulation times. The existing synchronous parallel multi-objective optimization method for analog circuits is LoCoMOBO

[14] . The asynchronous batch method does not wait for the simulation results to be returned and starts a new simulation as long as the number of simultaneously running simulations does not reach the maximum parallel limit. For the asynchronous batch method, there is no waiting for idle time, and simulation resources can be fully utilized. However, when selecting simulation candidate points, the results of the ongoing simulations have not been returned, resulting in a certain amount of information loss. The existing asynchronous parallel multi-objective optimization method for analog circuits is AEIM

[15] .

[0007] Based on the current situation of the existing technology, the inventors of the present application aim to address the problems of low optimization efficiency and poor optimization quality in the multi-objective optimization method for analog circuits by using the expected hypervolume improvement function as the acquisition function, adopting a dynamic reference point selection strategy to handle constraints, and using an asynchronous parallel overall framework, thereby improving the optimization efficiency and optimization quality of the algorithm. The proposed invention will help solve the multi-objective optimization problem of analog circuits with high simulation time costs.

[0008] References:

[0009] [1] R.Vural and T.Yildirim, “Analog circuit sizing via swarm intelligence,” AEU-International Journal of Electronics and Communications, vol. 66, no. 9, pp. 732–740, 2012.

[0010] [2] B.Liu, Y.Wang, Z.Yu, L.Liu, M.Li, Z.Wang, J.Lu, and F.V.Fern′andez, “Analog circuit optimization system based on hybrid evolutionary algorithms,” Integration, vol. 42, no. 2, pp. 137–148, 2009.

[0011] [3]W. Lv, F. Yang, C. Yan, D. Zhou, and X. Zeng, “Subgradient based multiple-starting-point algorithm for non-smooth optimization of analog circuits,” in Design, Automation Test in Europe Conference Exhibition (DATE), 2017, 2017, pp. 1195–1200.

[0012] [4]Z. Bi, D. Zhou, S.-G. Wang, and X. Zeng, “Optimization and quality estimation of circuit design via random region covering method,” ACM Trans. Des. Autom. Electron. Syst., vol. 23, no. 1, aug 2017.

[0013] [5]Y. Yang, H. Zhu, Z. Bi, C. Yan, D. Zhou, Y. Su, and X. Zeng, “Smartmsp: A self-adaptive multiple starting point optimization approach for analog circuit synthesis,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, no. 3, pp. 531–544, 2018.

[0014] [6]W. Lyu, P. Xue, F. Yang, C. Yan, Z. Hong, X. Zeng, and D. Zhou, “An efficient bayesian optimization approach for automated optimization of analog circuits,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 6, pp. 1954–1967, 2018.

[0015] [7]S.Zhang,W.Lyu,F.Yang,C.Yan,D.Zhou,X.Zeng,andX.Hu,“An efficientmulti-fidelity bayesian optimization approach for analog circuit synthesis,”in 2019 56thACM / IEEE Design Automation Conference(DAC),2019,pp.1–6.

[0016] [8]S.Zhang,W.Lyu,F.Yang,C.Yan,D.Zhou,and X.Zeng,“Bayesianoptimization approach for analog circuit synthesis using neural network,”in2019 Design,Automation Test in Europe Conference Exhibition(DATE),2019,pp.1463–1468.

[0017] [9]W.Lyu,F.Yang,C.Yan,D.Zhou,and X.Zeng,“Batch Bayesian optimizationvia multi-objective acquisition ensemble for automated analog circuitdesign,”in Proceedings of the 35th International Conference on MachineLearning,ser.Proceedings of Machine Learning Research,J.Dy andA.Krause,Eds.,vol.80.PMLR,2018,pp.3306–3314.

[0018]

[10] S.Zhang,F.Yang,D.Zhou,and X.Zeng,“An efficient asynchronous batchbayesian optimization approach for analog circuit synthesis,”in 2020 57thACM / IEEE Design Automation Conference(DAC),2020,pp.1–6.

[0019]

[11] K.Deb,A.Pratap,S.Agarwal,and T.Meyarivan,“A fast and elitistmulti-objective genetic algorithm:Nsga-ii,”IEEE Transactions on EvolutionaryComputation,vol.6,no.2,pp.182–197,2002.

[0020]

[12] B.Liu,F.V.Fern′andez,Q.Zhang,M.Pak,S.Sipahi,and G.Gielen,“Anenhanced moea / d-de and its application to multiobjective analog cell sizing,”in IEEE Congress on Evolutionary Computation,2010,pp.1–7.

[0021]

[13] W.Lyu,F.Yang,C.Yan,D.Zhou,and X.Zeng,“Multi-objective bayesianoptimization for analog / rf circuit synthesis,”in 2018 55 th ACM / ESDA / IEEEDesign Automation Conference(DAC),2018,pp.1–6.

[0022]

[14] K. Touloupas and P. P. Sotiriadis, “Locomobo: A local constrained multi-objective bayesian optimization for analog circuit sizing,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1–1, 2021.

[0023]

[15] S. Yin, R. Wang, J. Zhang, and Y. Wang, “Asynchronous parallel expected improvement matrix-based constrained multi-objective optimization for analog circuit sizing,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 9, pp. 3869–3873, 2022. Summary of the Invention

[0024] The objective of the present invention is to provide an asynchronous parallel Bayesian optimization method that supports constraint handling for the multi-objective optimization problem of analog circuits.

[0025] Specifically, this method uses Bayesian optimization as the optimization strategy and uses the Gaussian process regression model to give an estimate of the circuit performance, reducing the need for the number of actual circuit simulations. Subsequently, the expected hypervolume improvement function is used as the acquisition function. Since the optimal solution set of multi-objective optimization is better with a larger hypervolume, the candidate point with the largest expected hypervolume improvement is selected as the new simulation point, which can improve the optimization result.

[0026] To handle constraints, we use a dynamic reference point selection strategy. As the optimization iteration progresses, the strictness of the constraints is gradually increased, enabling this method to explore more regions in the initial stage of optimization and ensuring that strict constraint requirements are met in the later stage of optimization. To further improve the optimization efficiency, we adopt an asynchronous parallel optimization framework. When there are idle working points in the parallel pool, regardless of whether the remaining simulation results are returned, the next new simulation is started.

[0027] The method proposed by the present invention is applicable to general constrained multi-objective analog circuit optimization problems. It is defined as follows:

[0028] Minimize f (1) (x), …, f (M) (x).

[0029] s.t. f (i) (x) ≤ C i , i = 1, …, M.

[0030] Input parameters: Circuit optimization target performance f (i) : i = 1, …, M, circuit constraint performance C i : i = 1, …, M, optimization range S, parallel pool size B, number of initial points N init , maximum number of simulations N max ;

[0031] Output result: Optimized optimal design point set X * .

[0032] Step 1: Randomly sample N init points within the optimization range S and simulate them to obtain M initial data sets From this, establish M Gaussian process regression models;

[0033] Step 2: Update the reference point using the dynamic reference point selection strategy;

[0034] Step 3: According to the Gaussian process regression model, reference point, and all simulated data points (including those with returned and unreturned results), calculate the expected hypervolume improvement function, and take the position that maximizes it as the new candidate point to be simulated;

[0035] Step 4: Simulate the new candidate point at the idle working points in the parallel pool;

[0036] Step 5: Wait for simulation results to be returned in the parallel pool and for new idle working points to appear;

[0037] Step 6: Update the data set according to the newly returned simulation results;

[0038] Step 7: Update the Gaussian process regression model and return to Step 2 until the number of simulations reaches N max Stop the loop.

[0039] Specifically, the Gaussian process regression models established and updated in Steps 1 and 7 predict the mean and standard deviation of the i-th circuit performance at any point x and can be written in the following form

[0040]

[0041] where k(x * , X) = {k(x* , x i ), | i = 1, …, |X|}, K = k(X, X), k(X, x * ) = k(x * , X) T , k(·, ·) is a kernel function, and the Matern-5 / 2 function form is adopted in this method.

[0042] In step 2 of the method of the present invention, the following sub-steps are adopted to obtain the reference point, as Figure 1 shown:

[0043] Step 2.1: Take the worst value of each performance index in the initial data set as the initial reference point

[0044] Step 2.2: Calculate the reference point moving step size according to the circuit performance index constraint C i : i = 1, …, M and the step size coefficient k s In this method, k takes 0.1; s

[0045] Step 2.3: If there exists y in the current data set D t that satisfies * then update the reference point r = r t + Δr, otherwise skip this step; t-1

[0046] Step 2.4: If the new reference point r t satisfies then let otherwise skip this step;

[0047] Step 2.5: Return to Step 2.3 until there is no y in the current data set D t that satisfies * or or end the loop.

[0048] In step 3 of the method of the present invention, the following sub-steps are used to obtain the candidate points to be simulated.

[0049] First, this step involves some background concepts, which are introduced as follows:

[0050] For any data points a and b, if

[0051]

[0052] th.

[0053] then it is said that a dominates b, denoted as a < b.

[0054] The set of all non-dominated solutions is called the Pareto set. The performance corresponding to the Pareto set is called the Pareto front PF = {f(x)|x ∈ PS}.

[0055] Given a reference point r and the Pareto set PS, the hypervolume is the M-dimensional Lebesgue measure of the space dominated by PS, as Figure 2 shown.

[0056]

[0057] where, [r, y j represents the hyper-rectangle enclosed by r and y j .

[0058] The hypervolume improvement is defined by the following formula:

[0059] HVI(f(x * )|PS, r) = HV(PS ∪ x * , r) - HV(PS, r)

[0060] The expected hypervolume improvement is the expected value of the hypervolume improvement based on the posterior distribution of the Gaussian process regression model.

[0061]

[0062] Now, let's introduce the sub-steps of Step 3:

[0063] Step 3.1: Input the simulation points that have not yet returned results in the simulation into the Gaussian process regression model, and denote the mean estimate given by the model as Merge it with the current data set D to obtain the pseudo data set t From this, obtain the Pareto set and the Pareto front

[0064] Step 3.2: Sample N

[0064] MC functions f t from the Gaussian process regression model and use to estimate the expected hypervolume improvement;

[0065] Step 3.3: Use the BFGS algorithm to optimize within the optimization range Take the optimization result as the next candidate point to be simulated.

[0066] The advantages of the method of the present invention are:

[0067] (1) By adopting an asynchronous parallel method, the efficiency of multi-objective optimization of analog circuits is improved, and the time cost brought by circuit simulation is reduced;

[0068] (2) Through the dynamic reference point selection method, a larger area is explored in the early stage of optimization, providing more search directions for subsequent optimization and improving the efficiency of multi-objective optimization;

[0069] (3) By using the expected hypervolume improvement as the acquisition function, the effect of multi-objective optimization of analog circuits is improved, and the optimal solution set obtained by optimization is further advanced. Description of the Drawings

[0070] Figure 1 . Schematic diagram of dynamic reference point selection

[0071] Figure 2 . Schematic diagram of hypervolume and hypervolume improvement

[0072] Figure 3 . Schematic diagram of a second-order operational amplifier Detailed Implementation Manner

[0073] The method of the present invention is described below through the implementation process of specific examples.

[0074] Implementation Example

[0075] This method compares with the internationally advanced serial multi-objective Bayesian optimization method MOBO, the synchronous parallel multi-objective Bayesian optimization method LoCoMOBO, and the asynchronous parallel multi-objective Bayesian optimization method AEIM. All parallel methods adopt a parallel simulation strategy with a parallelism of 15. To compare different methods, the experiment was repeated 10 times. When the optimization method found a design that met the constraints, it was a successful experiment.

[0076] Here, an optimization problem of a second-order operational amplifier is given, and its circuit topology is as Figure 3 , where there are 10 dimensions of optimization parameters, including the width-to-length ratio of transistors, resistance values, etc. The requirements for transistor symmetry and matching have been taken into account. The optimization problem is as follows:

[0077] Maximize gain, unity-gain bandwidth, and phase margin

[0078] Constraints: gain > 80 dB, unity-gain bandwidth > 10 MHz, phase margin < 60°

[0079] It can be seen that in order to achieve a similar hypervolume, the simulation time efficiency of this method is 39.98 times higher than that of MOBO; compared with LoCoMOBO, the simulation time efficiency is 3.49 times higher; compared with AEIM, the simulation time efficiency is 8.18 times higher.

[0080] Table 1: Optimization results of different methods

[0081] Method Number of successes Hypervolume Simulation time (seconds) This method 10 / 10 2046±324 414 MOBO 10 / 10 2034±286 16552 LoCoMOBO 10 / 10 2006±167 1448 AEIM 10 / 10 2008±565 3391

Claims

1. An asynchronous parallel multi-objective Bayesian optimization method supporting constraint handling, characterized in that In the described method, the expected hypervolume improvement function is used as the acquisition function, a dynamic reference point selection strategy is adopted to handle constraints, and asynchronous parallelism is used for circuit simulation; It includes the steps: Input parameter: Circuit optimization target performance f (i) : i = 1, …, M, Circuit constraint performance C i : i = 1, …, M, Optimization range S, Parallel pool size B, Number of initial points N init , Maximum number of simulations N max ; Output Result: Optimize the optimal design point set X * ; Step 1: Randomly sample N init points within the optimization range S and simulate them to obtain M initial data sets Based on this, establish M Gaussian process regression models; Step 2: Update the reference point using the dynamic reference point selection strategy; Step 3: Calculate the expected hypervolume improvement function based on the Gaussian process regression model, the reference point, and all the simulated data points (including those with returned results and those without returned results), and take the position where it is maximized as the new candidate point to be simulated; Step 4: Simulate the new candidate point at the idle working points in the parallel pool; Step 5: Wait for simulation results to be returned in the parallel pool and for new idle working points to appear; Step 6: Update the data set according to the newly returned simulation results; Step 7: Update the Gaussian process regression model and return to Step 2 until the number of simulations reaches N max Stop the loop.

2. The method according to claim 1, characterized in that, In the described Step 2, global Bayesian optimization is performed using multi-modal recognition and the weighted expected improvement function, and its sub-steps are as follows: Step 2.1: Take the worst value of each performance metric in the initial dataset as the initial reference point Step 2.2: According to the circuit performance index constraint C i : for i = 1,..., M and the step coefficient k s Calculate the moving step of the reference point In this method, k s takes 0.1; Step 2.3: If there exists y in the current data set D t such that * it satisfies then update the reference point r t = r t-1 + Δr, otherwise skip this step; Step 2.4: If the new reference point r t satisfies then let Otherwise, skip this step; Step 2.5: Return to Step 2.3 until there is no y in the current data set D t in * which satisfies or end the loop.

3. The method according to claim 1, characterized in that, In the described Step 3, the expected hypervolume improvement is used to select the candidate point to be simulated, and its sub-steps are as follows; Step 3.1: Input the simulation points that have not returned results during the simulation to the Gaussian process regression model, and denote the mean estimate given by the model as Combine it with the current dataset D t to obtain the pseudo-dataset From this, the Pareto set and the Pareto front Step 3.2: Sample N MC functions f t from the Gaussian process regression model and use to estimate the expected hypervolume improvement; Step 3.3: Optimize within the optimization range using the BFGS algorithm Use the optimization result as the candidate point for the next simulation to be performed.

4. The method according to claim 1, characterized in that The described method is used for the optimization of constrained multi-objective analog circuit parameters.

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