Layout optimization method and device, electronic equipment and storage medium

Abstract

The invention provides a storage unit layout optimization method and device, electronic equipment and a storage medium, and relates to the technical field of semiconductors. The optimization method for the layout of the storage unit comprises the following steps: constructing an initial population based on a plurality of size variables in the layout and the size range of each size variable; configuring a required evaluation model based on the performance optimization requirement of the layout; calculating an evaluation value of the initial population based on the evaluation model; and performing preferential iterative evolution on the initial population based on the evaluation value of the initial population until a target value of each size variable is obtained based on an iterative evolution result. Through the technical scheme of the invention, the optimization of a plurality of size variables in the layout can be realized, the target value of each size variable is obtained, and the optimized storage unit layout is obtained based on the target values of the plurality of size variables, so that the influence of a layout dependency effect, a parasitic effect and the like is reduced, and the performance of the storage unit is improved.

Description

Background Art

[0002] The layout dependent effect refers to the degradation of the timing of standard cells when two specific standard cells on the chip layout are placed adjacent to each other in a certain direction and position. The parasitic effect refers to the capacitive, inductive or resistive behavior shown at positions on the chip layout where capacitors, inductors or resistors are not set. As the size of the chip becomes smaller and smaller, the impact of the layout dependent effect and parasitic effect on the chip becomes more and more obvious. Since the layout of the memory cell of the chip is relatively complex, there are many influencing parameters for the above effects, and the current layout design mainly relies on the experience of designers, which also makes it difficult to obtain an optimal layout design scheme that can minimize the impact of the above effects on the device. Therefore, an optimization scheme for the memory cell layout is urgently needed.

[0003] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0004] The purpose of the present disclosure is to provide an optimization method for a memory cell layout, an optimization device for a memory cell layout, and a computer-readable storage medium, which can at least overcome to some extent the problem that the memory cell layout in the related art is not reasonable enough, resulting in poor performance.

[0005] Other features and advantages of the present disclosure will become apparent through the following detailed description, or will be partially learned through the practice of the present disclosure.

[0006] According to one aspect of the present disclosure, there is provided an optimization method for a memory cell layout, including: constructing an initial population based on a plurality of size variables in the layout and the size range of each size variable; configuring an evaluation model required based on the performance optimization requirements for the layout; calculating the evaluation values of the initial population based on the evaluation model; and performing a preferential iterative evolution on the initial population based on the evaluation values of the initial population until the target values of each size variable are obtained based on the iterative evolution results.

[0007] In an embodiment of the present disclosure, the layout includes a plurality of transistors. Constructing an initial population based on a plurality of size variables in the layout and the size range of each size variable includes: for a single transistor, sorting the plurality of size variables in a specified order to obtain a variable sequence; for the plurality of transistors, configuring a plurality of variable sequences with the specified order into a variable matrix; and generating the initial population based on the variable matrix and the size range.

[0008] In one embodiment of the present disclosure, generating the initial population based on the variable matrix and the size range includes: determining the size range corresponding to each size variable; randomly assigning values to each size variable in the variable matrix within the corresponding size range to obtain encoded genes, where the number of times of the random assignment corresponds to a preset quantity; and generating the initial population based on the preset quantity of the encoded genes.

[0009] In one embodiment of the present disclosure, configuring an evaluation model required based on the performance optimization requirements of the layout includes: selecting target indicators associated with the performance optimization requirements from a plurality of candidate performance indicators; configuring corresponding weight coefficients for each of the target indicators based on the performance optimization requirements; and obtaining the evaluation model based on the target indicators and the corresponding weight coefficients.

[0010] In one embodiment of the present disclosure, the candidate performance indicators include: gate delay, dynamic power consumption, static power consumption, transistor saturation current, and parasitic capacitance of the storage unit.

[0011] In one embodiment of the present disclosure, calculating the evaluation value of the initial population based on the evaluation model includes: the initial population includes a preset quantity of encoded genes, and each encoded gene corresponds to a layout to be evaluated. Detecting whether the layout to be evaluated meets the design rules; for the layout to be evaluated that does not meet the design rules, the obtained evaluation value is 0; for the layout to be evaluated that meets the design rules, evaluating the evaluation value of the layout to be evaluated based on the evaluation model.

[0012] In one embodiment of the present disclosure, evaluating the evaluation value of the layout to be evaluated based on the evaluation model includes: performing performance simulation on the layout to be evaluated to obtain the index values of the target indicators associated with the performance optimization requirements; and inputting the index values into the evaluation model to obtain the evaluation value.

[0013] In one embodiment of the present disclosure, performing a preferential iterative evolution on the initial population based on the evaluation value of the initial population until the target values of each size variable are obtained based on the iterative evolution result includes: preferentially selecting a preset quantity of encoded genes based on a preferential strategy to obtain preferred genes; performing iterative evolution based on the preferred genes so that after each iterative evolution, a preset quantity of evolved genes are obtained as the iterative evolution result; detecting that the iterative evolution operation meets the termination condition, and selecting target genes from the evolved genes to determine the target values of each size variable based on the target genes.

[0014] In one embodiment of the present disclosure, before constructing an initial population based on a plurality of dimension variables in a layout and the dimension range of each of the dimension variables, it further includes: configuring the evolution parameters of the preset number, the selection strategy, the termination condition, and the iterative evolution based on the performance optimization objective of the layout.

[0015] In one embodiment of the present disclosure, preferentially selecting a preset number of encoded genes based on a selection strategy to obtain preferred genes includes: sorting the preset number of encoded genes based on the corresponding evaluation values; the selection strategy includes a survival probability, and the preferred genes are selected from the sorting result based on the survival probability.

[0016] In one embodiment of the present disclosure, the selection strategy includes one of a roulette wheel strategy, a tournament strategy, and an elitist retention strategy.

[0017] In one embodiment of the present disclosure, iterative evolution is performed based on the preferred genes, so that after each iterative evolution, a preset number of evolved genes are obtained, including: performing a hybridization operation based on the preferred genes until a preset number of hybrid genes are obtained; performing a mutation operation on the preset number of hybrid genes based on the evolution parameters to complete one iterative evolution and obtain the preset number of evolved genes.

[0018] In one embodiment of the present disclosure, when it is detected that the iterative evolution operation satisfies the termination condition, a target gene is selected from the evolved genes, including: the termination condition includes the number of generations of inheritance, and when it is detected that the number of times of iterative evolution reaches the number of generations of inheritance, multiple generations of the evolved genes are obtained; the evolved gene with the maximum evaluation value is determined as the target gene.

[0019] In one embodiment of the present disclosure, when it is detected that the iterative evolution operation satisfies the termination condition, a target gene is selected from the evolved genes, including: the termination condition includes an evaluation threshold, and when it is detected that the evaluation value of the evolved gene obtained based on the iterative evolution operation reaches the evaluation threshold, the evolved gene with the evaluation threshold is determined as the target gene.

[0020] In one embodiment of the present disclosure, the layout is provided with polysilicon, connection regions, and active regions of transistors, and the plurality of dimension variables include: the distances in a first direction between the polysilicon and the connection regions on both sides respectively; the distance in the first direction between two adjacent polysilicons; the distance in a second direction perpendicular to the first direction between two adjacent active regions; and the extending length in the second direction of one side edge of the polysilicon relative to the intersecting active region.

[0021] According to one aspect of the present disclosure, an optimization device for a storage cell layout is provided, including: a construction module configured to construct an initial population based on a plurality of dimension variables in the layout and the dimension range of each of the dimension variables; a configuration module configured to configure an evaluation model required based on the performance optimization requirements for the layout; a calculation module configured to calculate the evaluation values of the initial population based on the evaluation model; and an evolution module configured to perform a selective iterative evolution on the initial population based on the evaluation values of the initial population until target values of each of the dimension variables are obtained based on the iterative evolution results.

[0022] According to still another aspect of the present disclosure, an electronic device is provided, including: a processor; and a memory configured to store executable instructions of the processor; the processor is configured to execute the optimization method for the storage cell layout in the first aspect above by executing the executable instructions.

[0023] According to yet another aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the optimization method for the storage cell layout described above is implemented.

[0024] The optimization solution for the storage cell layout provided by the embodiments of the present disclosure, for a plurality of dimension variables involved in the design of the storage cell layout, by constructing an initial population composed of a plurality of dimension variables within a defined dimension range, combining with an evaluation model configured for performance optimization, and through steps such as evaluation value calculation and selective iterative evolution, can optimize a plurality of dimension variables in the layout and obtain the target values of each dimension variable, so as to obtain an optimized storage cell layout based on the target values of the plurality of dimension variables, realize the optimization of the size and position of the transistor in the layout, and thus based on the optimization of the size and position, reduce the influence of layout dependence effects and parasitic effects, etc., to improve the performance of the storage cell.

[0025] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings here are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can also obtain other drawings based on these drawings without creative efforts.

[0027] Figure 1 A schematic structural diagram of a storage cell in an embodiment of the present disclosure is shown;

[0028] Figure 2Schematic flowchart of an optimization method for a memory cell layout in an embodiment of the present disclosure;

[0029] Figure 3 Schematic diagram of a partial layout of a memory cell in an embodiment of the present disclosure;

[0030] Figure 4 Schematic flowchart of another optimization method for a memory cell layout in an embodiment of the present disclosure;

[0031] Figure 5 Schematic flowchart of yet another optimization method for a memory cell layout in an embodiment of the present disclosure;

[0032] Figure 6 Schematic flowchart of yet another optimization method for a memory cell layout in an embodiment of the present disclosure;

[0033] Figure 7 Schematic flowchart of yet another optimization method for a memory cell layout in an embodiment of the present disclosure;

[0034] Figure 8 Schematic flowchart of yet another optimization device for a memory cell layout in an embodiment of the present disclosure;

[0035] Figure 9 Schematic block diagram of an electronic device in an embodiment of the present disclosure. Detailed implementation manners

[0036] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be more complete and comprehensive, and will fully convey the concept of the example embodiments to those skilled in the art. The features, structures, or characteristics described may be combined in any suitable manner in one or more embodiments.

[0037] In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus their repeated description will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0038] The semiconductor chip includes SRAM (Static Random-Access Memory) and DRAM (Dynamic Random Access Memory), etc. Figure 1 Fig. shows a schematic structural diagram of a 6T SRAM, where T refers to Transistor, that is, the basic storage unit of SRAM is composed of 6 MOS transistors (Metal-Oxide-Semiconductor). MOS transistors are divided into P-type MOS transistors and N-type MOS transistors. As Figure 1 shown, M1, M3, M5, and M6 are NMOS transistors, which conduct when at high level; M2 and M4 are PMOS transistors, which conduct when at low level. BL (Bit Line) is the bit line for reading and writing data, WL (Word Line) is the word line for controlling the read and write operations, Vdd is used to provide the power supply voltage, and the optimization of the storage cell layout can optimize the positions and relative distances of these devices.

[0039] In addition, those skilled in the art can understand that Figure 1 only a schematic structural diagram of the 6T SRAM in the semiconductor chip is given, and the solution of the present disclosure is not limited to the optimization of the layout of this structure.

[0040] As Figure 2 shown, according to an optimization method of a storage cell layout in an embodiment of the present disclosure, it includes:

[0041] Step S202, constructing an initial population based on multiple size variables in the layout and the size range of each size variable.

[0042] In an embodiment of the present disclosure, as Figure 3As shown, the layout is provided with polysilicon (Poly) of transistors, connection areas (Contact, referring to the part where the device is connected to the metal wire), and active areas (Active Area, AA, used to establish the position of the transistor body). Assuming the first direction is longitudinal and the second direction is transverse, multiple size variables include: the distances in the first direction between the polysilicon and the connection areas on both sides, including the distance UCT between the Poly and the upper contact and the distance DCT between the Poly and the lower contact; the distances in the first direction between two adjacent polysilicons, including the distance SPA1 between the Poly and the upper poly and the distance SPB1 between the Poly and the lower poly; the distance in the second direction perpendicular to the first direction between two adjacent active areas, that is, the distance OSEX in the horizontal direction between the AA and the adjacent AA; and the extension length in the second direction of one side edge of the polysilicon relative to the intersecting active area, that is, the distance Poly_end where the Poly extends beyond the AA.

[0043] The size range can be understood as the size range composed of the maximum and minimum values allowed by the size variable, which can be obtained by collecting historical experience data and simulation data.

[0044] Exemplarily, according to the multiple size variables in the layout and the size range of each size variable, heuristic search algorithms such as genetic algorithms can be used to construct an initial population. For example, a group of individuals that meet the size range are randomly generated to form the initial population, which can be understood that the initial population corresponds to a layout design scheme.

[0045] Step S204, configure the required evaluation model based on the performance optimization requirements of the layout.

[0046] Among them, the performance optimization of the layout can be understood as reducing the influence of layout-dependent effects and parasitic effects, etc. In addition, the performance optimization of the layout can also be the optimization of low power consumption or the optimization of high performance, etc.

[0047] In order to optimize the performance of the layout, an evaluation model needs to be configured to measure the performance of the population. The evaluation model can calculate performance indicators based on size variables and other relevant factors. The configuration of the evaluation model will involve selecting appropriate indicators and establishing corresponding calculation methods.

[0048] Step S206, calculate the evaluation values of the initial population based on the evaluation model.

[0049] Among them, based on the configured evaluation model, calculate the evaluation values of the initial population. The initial population corresponds to a layout design scheme. The evaluation of the initial population can be understood as the evaluation value of the performance of the layout design scheme.

[0050] Step S208: Perform elitist iterative evolution on the initial population based on the evaluation values of the initial population until the target values of each size variable are obtained based on the iterative evolution results.

[0051] Exemplarily, to perform elitist iterative evolution on the initial population, it can be achieved by using operations such as selection, crossover, and mutation in the genetic algorithm according to the evaluation values of the initial population. For example, select better individuals for reproduction according to the evaluation values, generate new individuals through crossover and mutation operations, and iterate generation by generation until the stop condition is reached, such as reaching the maximum number of iterations or converging to a stable solution.

[0052] In addition, through the optimal individual obtained based on the iterative evolution results, the target values of each size variable can be obtained, which will be the values of each size variable after optimization to meet the performance optimization requirements of the layout.

[0053] In this embodiment, for multiple size variables involved in the design of the memory cell layout, by constructing an initial population composed of multiple size variables within the defined size range, combining with an evaluation model configured for performance optimization, and through steps such as evaluation value calculation and elitist iterative evolution, the optimization of multiple size variables in the layout can be achieved, and the target values of each size variable can be obtained. Based on the target values of multiple size variables, an optimized memory cell layout can be obtained, realizing the optimization of the size and position of the transistor in the layout, thereby reducing the influence of layout-dependent effects and parasitic effects, etc., to improve the performance of the memory cell.

[0054] In an embodiment of the present disclosure, the layout includes multiple transistors. Step S202, an implementation manner of constructing an initial population based on multiple size variables in the layout and the size range of each size variable, includes:

[0055] For a single transistor, sort the multiple size variables in a specified order to obtain a variable sequence.

[0056] Among them, for a single transistor, sort the multiple size variables in a specified order to obtain a variable sequence, and this order can be determined based on the structure and performance requirements of the transistor.

[0057] Exemplarily, the variable sequence can be expressed as: [OSEX, SPA1, SPB1, UCT, DCT, Poly_end].

[0058] For multiple transistors, configure multiple variable sequences with a specified order into a variable matrix.

[0059] Exemplarily, for the layout of a 6T SRAM, the basic unit constituting the SRAM is 4 NMOS (PD1, PG1, PD2, PG2) and 2 PMOS (PU1, PU2). For the NMOS and PMOS, UCT / DCT, OSEX, SPA1 / SPB1, and Poly_end are respectively selected as variables, and the remaining parameters are fixed values. The variable matrix can be expressed as:

[0060] G = {PD1[OSEX, SPA1, SPB1, UCT, DCT, Poly_end],

[0061] PD2[OSEX, SPA1, SPB1, UCT, DCT, Poly_end],

[0062] PG1[OSEX, SPA1, SPB1, UCT, DCT, Poly_end],

[0063] PG2[OSEX, SPA1, SPB1, UCT, DCT, Poly_end],

[0064] PU1[OSEX, SPA1, SPB1, UCT, DCT, Poly_end],

[0065] PU2[OSEX, SPA1, SPB1, UCT, DCT, Poly_end]}

[0066] In addition, those skilled in the art can understand that for the layout of an 8T SRAM, the variable matrix is composed of the size variables of eight basic units.

[0067] Based on the variable matrix and the size range, an initial population is generated. Exemplarily, it includes:

[0068] Determine the size range corresponding to each size variable; randomly assign values to each size variable in the variable matrix within the corresponding size range to obtain encoded genes, and the number of random assignments corresponds to a preset quantity; generate an initial population based on the preset quantity of encoded genes.

[0069] Exemplarily, based on the gene encoding scheme of the variable matrix, randomly generate a preset quantity N of genes within the value range of each variable to form a population P = {G1, G2, G3, … G N}, and the value range of each variable is the range allowed in the layout design rules of the process node adopted by the layout to be optimized.

[0070] In this embodiment, after the variable matrix is constructed, based on the variable matrix and the size range of each variable, methods such as a random generation algorithm can be used to generate an initial population, which involves randomly generating a plurality of transistors that meet the size range requirements. The initial population can be regarded as an initial set of data for subsequent evolutionary algorithms.

[0071] Furthermore, within the corresponding size range, random values are assigned to each size variable in the variable matrix to obtain encoded genes. Methods such as a random number generation algorithm can be used to randomly assign values within a reasonable range according to the size range. The number of repetitions of this process depends on the preset quantity, that is, the number of genes included in the initial population. By determining the size range, random assignment, and the process of generating the initial population, the generation of the initial population based on the preset quantity of encoded genes is achieved, which helps to further optimize the size variables in an iterative and evolutionary manner.

[0072] In an embodiment of the present disclosure, for step S204, an implementation manner of configuring the required evaluation model based on the performance optimization requirements of the layout includes:

[0073] Select target indicators associated with the performance optimization requirements from multiple candidate performance indicators.

[0074] Among them, the candidate performance indicators include: gate delay of the memory cell, dynamic power consumption, static power consumption, transistor saturation current, and parasitic capacitance.

[0075] Configure corresponding weight coefficients for each target indicator based on the performance optimization requirements.

[0076] Exemplarily, an evaluation model can be constructed using a fitness calculation model, and the fitness is used as the evaluation value of the genes in the population. In the genetic algorithm, the fitness is the main indicator describing the performance of individual genes.

[0077] For SRAM, the reciprocal of the gate delay delay = RC (picoseconds) can be used as the fitness. The larger the reciprocal of the gate delay, the better the fitness. Among them, R is the resistance of the transistor and the metal wire, and C is the parasitic capacitance of the transistor and the metal wire.

[0078] In addition, the reciprocal of the dynamic power consumption P ∝ VDD 2 *f*C can also be used as the fitness. The larger the reciprocal of the dynamic power consumption, the better the fitness. Among them, VDD is the power supply voltage, f is the frequency, and C is the parasitic capacitance of the transistor and the metal wire.

[0079] Alternatively, indicators such as gate delay, dynamic power consumption, Idsat (saturated drain current of the transistor), IDDQ (Integrated Circuit Quiescent Current), etc. can be defined as proportions, and the combination of these indicators can be used as the fitness, i.e., fitness = A*(1 / delay) + B*(1 / dynamic power consumption P) + D*Idsat + E*(1 / IDDQ) + F*(1 / capacitance).

[0080] Among them, A, B, D, E, and F are the corresponding weight coefficients.

[0081] An evaluation model is obtained based on the target indicators and the corresponding weight coefficients.

[0082] In this embodiment, by generating an evaluation model based on performance indicators and performance optimization requirements, multiple indicators can be comprehensively considered and appropriate weights can be assigned to them, which helps to obtain the target values of the corresponding size variables based on different performance requirements.

[0083] Such as Figure 4 As shown, in an embodiment of the present disclosure, step S206, an implementation manner of calculating the evaluation value of the initial population based on the evaluation model includes:

[0084] Step S402, the initial population includes a preset number of encoded genes, and each encoded gene corresponds to a layout to be evaluated, and it is detected whether the layout to be evaluated meets the design rules.

[0085] Among them, an initial population is generated, and the initial population includes a preset number of encoded genes. Each encoded gene can be regarded as a chromosome, representing the gene of a layout to be evaluated.

[0086] Design rule check (DRC) is to check whether the various dimensions of the graphics in each mask layer of the layout meet the requirements of the design rules. The design rules of the layout are determined according to the minimum graphic size, the thinnest line width, and the spacing between lines that can be produced by the corresponding process line. When performing the design rule check of the layout, it is mainly carried out in two aspects, including: the width and spacing of the geometric graphics in the same layer and the spacing and overlay spacing between the graphics in different layers.

[0087] Step S404, for the layout to be evaluated that does not meet the design rules, the obtained evaluation value is 0.

[0088] For the layout to be evaluated that meets the design rules, the evaluation value of the layout to be evaluated is evaluated based on the evaluation model.

[0089] In this embodiment, a layout is generated from the encoded genes, and the layout is screened and evaluated by design rules and an evaluation model. Through the detection of the design rules, layouts that do not meet the requirements can be excluded, thereby reducing unnecessary calculation and evaluation processes. The evaluation process based on the evaluation model can utilize the accuracy and efficiency of the model to quickly evaluate the layouts that meet the requirements, so as to find a better design solution.

[0090] In one embodiment of the present disclosure, evaluating the evaluation value of the layout to be evaluated based on the evaluation model includes:

[0091] Step S406, for the layout to be evaluated that meets the design rules, perform performance simulation on the layout to be evaluated to obtain the index value of the target index associated with the performance optimization requirement.

[0092] Step S408, input the index value into the evaluation model to obtain the evaluation value.

[0093] Exemplarily, by simulating the layout that meets the DR, calculate the fitness F = {F1, F2, F3, … F N} as the evaluation value.

[0094] In this embodiment, the layout to be evaluated that meets the design rules is evaluated through performance simulation and the evaluation model. Performance simulation can accurately simulate the performance of the layout to be evaluated under actual operating conditions, and obtain the index value of the target index related to the performance optimization requirement. The evaluation model can comprehensively evaluate the layout to be evaluated based on these index values to detect the performance of the layout to be evaluated.

[0095] Such as Figure 5 shown, in one embodiment of the present disclosure, step S208, perform elitist iterative evolution on the initial population based on the evaluation value of the initial population until the target value of each size variable is obtained based on the iterative evolution result, including:

[0096] Step S502, select the encoded genes with the best performance based on the elitist strategy to obtain the optimal genes.

[0097] Among them, a set of encoded genes with a preset quantity is given. Based on the preset elitist strategy, these encoded genes are evaluated and sorted. According to the requirements of the elitist strategy, the genes ranked at the top are selected as the optimal genes, that is, the genes with better fitness and optimization potential.

[0098] Step S504, perform iterative evolution based on the optimal genes to obtain a preset quantity of evolved genes after each iterative evolution as the iterative evolution result.

[0099] Among them, the selected optimal genes are used as the population for the first iterative evolution. After each iterative evolution, operations such as mutation and crossover are performed on the current population through genetic algorithms or other evolutionary algorithms to generate a new set of evolved genes. These evolved genes represent optimized gene combinations and can be used as the population for further evolution in the next iteration.

[0100] Step S506, it is detected that the iterative evolution operation meets the termination condition, and target genes are selected from the evolved genes to determine the target values of each size variable based on the target genes.

[0101] Among them, after each iterative evolution, it is detected whether the obtained evolved genes meet the termination condition. The termination condition can be reaching a preset number of evolutionary generations, reaching a certain fitness threshold, etc.

[0102] If the termination condition is met, target genes are selected from the evolved genes. The target genes are usually genes with the optimal fitness or closest to the target solution. By decoding the target genes, the target values of each size variable can be determined, that is, the optimal parameter configuration or solution corresponding to the optimization problem.

[0103] In this embodiment, through the selection strategy and iterative evolution method, the optimization of a preset number of encoded genes is achieved. By selecting genes with better fitness and optimization potential and undergoing multiple iterative evolutions, target genes that meet the termination condition are finally obtained. These target genes represent the optimal solution or the best parameter configuration of the optimization problem.

[0104] In an embodiment of the present disclosure, before constructing the initial population based on the size variables of multiple transistors in the layout and the size range of each size variable, it further includes: configuring the evolutionary parameters of the preset number, selection strategy, termination condition, and iterative evolution based on the performance optimization target of the layout.

[0105] Among them, the evolutionary parameters of the iterative evolution include the survival probability s% and the mutation probability m% etc.

[0106] In this embodiment, according to the performance optimization target, the preset number is configured to determine the number of transistors in the layout to be optimized. Then, according to the specific optimization target, the selection strategy is determined, such as minimizing power consumption, maximizing performance, etc. Additionally, the termination condition is set, such as reaching the preset number of evolutionary generations, reaching a certain optimization target value, etc., as the end condition of the iterative evolution, to construct the initial population and perform iterative evolution based on the initial population. The gene evolution algorithm is used to perform iterative evolution on the initial population, and through operations such as selection, crossover, and mutation, the size configuration of the transistors is gradually optimized to achieve the performance optimization target.

[0107] Such as Figure 6As shown, in an embodiment of the present disclosure, step S502, selecting a preset number of coding genes based on a selection strategy to obtain a preferred gene, one implementation includes:

[0108] Step S602, sorting a preset number of coding genes based on their corresponding evaluation values.

[0109] Among them, by evaluating each coding gene, its corresponding fitness value or evaluation value is calculated, and the coding genes are sorted according to the evaluation value, with genes having higher evaluation values ranked in the front and genes having lower evaluation values ranked in the back.

[0110] Step S604, the selection strategy includes a survival probability, and preferred genes are selected from the sorting result based on the survival probability.

[0111] Among them, the survival probability represents the probability that a gene is selected as the next generation during the evolution process. Preferred genes are selected from the sorting result in descending order of the survival probability and used as the parents for the next hybridization operation.

[0112] In an embodiment of the present disclosure, the selection strategy includes one of a roulette wheel strategy, a tournament strategy, and an elitist reservation strategy.

[0113] Among them, in the genetic algorithm, the roulette wheel strategy, the tournament strategy, and the elitist reservation strategy are all used for the selection operator. Under the roulette wheel strategy, the higher the individual fitness, the greater the probability of being selected. Under the tournament strategy, the worst individual will definitely be eliminated. Under the elitist reservation strategy, the best individual will definitely be retained.

[0114] In an embodiment of the present disclosure, iterative evolution is performed based on the preferred genes to obtain a preset number of evolved genes after each iterative evolution, including:

[0115] Step S606, performing a hybridization operation based on the preferred genes until a preset number of hybrid genes are obtained.

[0116] Exemplarily, the hybridization operation includes: randomly selecting two genes, randomly selecting a locus on the genes, and exchanging the parts of the two genes from this locus to the end to form 2 new genes. Repeat the hybridization process until the number of genes reaches the preset number N.

[0117] Step S608, performing a mutation operation on a preset number of hybrid genes based on the evolution parameters to complete one iterative evolution and obtain a preset number of evolved genes.

[0118] Among them, the mutation operation can be random gene exchange, gene insertion, or gene deletion, etc., to introduce a new solution space and prevent falling into a local optimal solution.

[0119] Exemplarily, the mutation operation includes: selecting genes according to m%, randomly selecting a site on the gene, and replacing the site with a random value within the value range to make it a new gene, thus generating the next-generation population P’={G’1, G’2, G’3, … G’ N}.

[0120] In an embodiment of the present disclosure, when it is detected that the iterative evolution operation satisfies the termination condition, selecting a target gene from the evolved genes includes:

[0121] Step S610, the termination condition includes the number of genetic generations. When it is detected that the number of iterations of the iterative evolution reaches the number of genetic generations, multiple generations of evolved genes are obtained.

[0122] Step S612, determining the evolved gene with the maximum evaluation value as the target gene.

[0123] In an embodiment of the present disclosure, when it is detected that the iterative evolution operation satisfies the termination condition, selecting a target gene from the evolved genes includes:

[0124] Step S614, the termination condition includes an evaluation threshold. When it is detected that the evaluation value of the evolved gene obtained based on the iterative evolution operation reaches the evaluation threshold, the evolved gene with the evaluation threshold is determined as the target gene.

[0125] In this embodiment, through the survival probability selection, hybridization operation, and mutation operation based on the evaluation value ranking and the optimal selection strategy, the optimization process based on evolution is realized. Through the ranking and selection operations, the better genes are selected as the parents for hybridization to retain the better traits and characteristics. Through the hybridization and mutation operations, more gene combinations and variations are introduced in the new generation, increasing the diversity of the solution space and the breadth of the search. Finally, according to the set termination condition, the evolved genes after iterative evolution are obtained, and the target gene is selected from them as the optimization result, which has good technical effects in the optimization problem, can gradually improve the quality of the target gene, and ensure the optimality of the obtained target gene.

[0126] As Figure 7 shown, the optimization method for the layout of the storage unit according to another embodiment of the present disclosure includes:

[0127] Step S702, configuring a preset number N, an optimal selection strategy, a termination condition, and evolution parameters for iterative evolution based on the performance optimization target of the layout.

[0128] Step S704, providing the layout to be optimized, selecting the size variables to be optimized, arranging them in order to form a variable matrix, and randomly assigning values to each size variable in the variable matrix within the specified size range of each size variable to obtain a preset number of encoded genes as the initial population.

[0129] Step S706, calculate the fitness of each encoded gene to obtain the evaluation value of the initial population.

[0130] Step S708, sort the N genes in descending order of fitness, and select the top s% of the genes.

[0131] Step S710, randomly select two genes from the top s% of the genes, randomly select a site on the genes, and exchange the parts of the two genes from this site to the end to form a new gene recombination process until the number of genes reaches N, and then return to step S706. At this time, the initial population is replaced by the newly generated population.

[0132] Step S712, when the termination condition is detected, take the gene with the largest fitness among the obtained genes as the target gene, and accordingly obtain the optimized layout scheme.

[0133] In this embodiment, the influence of layout-dependent effects and parasitic effects on device performance is calculated through simulation. Using a custom fitness, the layout of the memory cell is optimized directionally to achieve the best results. Among them, size parameters in the layout design are selected and encoded to form encoded genes, and an initial population is generated according to the value range. The fitness is defined according to requirements for performance evaluation, and its indicators include but are not limited to gate delay, dynamic power consumption, static power consumption, rise / fall edge slope, Vt, Idsat, IDDQ, and capacitance, or combinations of these indicators, etc. Since the fitness needs to be as large as possible, the monotonicity of these indicators can be changed by taking the reciprocal or taking the opposite number.

[0134] Furthermore, genes with large fitness are selected and new populations are formed through hybridization and mutation. Through iterative evolution, the optimal target gene can finally be determined, corresponding to the preferred layout scheme.

[0135] Exemplarily, the layout-dependent effects mainly include factors such as well-proximity effect (WPE), length of diffusion (LOD effects), OD space effect (OSE), and poly space effects (PSE), etc. Among them, the well-proximity effect describes how transistor characteristics are affected by the relative distance from other regions of the same doping type (N-well or P-well). These factors will affect the local doping concentration and stress, and thus affect device performance. Table 1 shows the relevant parameters of the layout-dependent effects obtained based on the original scheme and the optimized scheme of the present disclosure respectively.

[0136] Table 1

[0137]

[0138] As can be seen from Table 1, by optimizing the layout parameters through the optimization scheme of the memory cell layout, the delay of the memory cell can be reduced by 6%.

[0139] It should be noted that the above-mentioned drawings are only schematic illustrations of the processes included in the method according to the exemplary embodiments of the present invention, rather than for limiting purposes. It is easy to understand that the processes shown in the above-mentioned drawings do not indicate or limit the chronological order of these processes. Additionally, it is also easy to understand that these processes can be executed synchronously or asynchronously, for example, in multiple modules.

[0140] Those skilled in the art can understand that various aspects of the present invention can be implemented as a system, a method, or a program product. Therefore, various aspects of the present invention can be specifically implemented in the following forms, namely: a complete hardware implementation, a complete software implementation (including firmware, microcode, etc.), or an implementation combining hardware and software aspects, which can be collectively referred to as "circuitry", "module", or "system" here.

[0141] Next, refer to Figure 8 to describe the optimization device 800 for the memory cell layout according to the embodiments of the present invention. Figure 8 The shown optimization device 800 for the memory cell layout is merely an example and should not impose any limitation on the functions and usage scope of the embodiments of the present invention.

[0142] The optimization device 800 for the memory cell layout is presented in the form of a hardware module. The components of the optimization device 800 for the memory cell layout may include, but are not limited to: a construction module 802 for constructing an initial population based on multiple dimension variables in the layout and the dimension range of each dimension variable; a configuration module 804 for configuring the required evaluation model based on the performance optimization requirements for the layout; a calculation module 806 for calculating the evaluation values of the initial population based on the evaluation model; and an evolution module 808 for performing a selective iterative evolution on the initial population based on the evaluation values of the initial population until the target values of each dimension variable are obtained based on the iterative evolution results.

[0143] Those skilled in the art can understand that various aspects of the present invention can be implemented as a system, a method, or a program product. Therefore, various aspects of the present invention can be specifically implemented in the following forms, namely: a complete hardware implementation, a complete software implementation (including firmware, microcode, etc.), or an implementation combining hardware and software aspects, which can be collectively referred to as "circuitry", "module", or "system" here.

[0144] Next, refer to Figure 9 to describe the electronic device 900 according to this embodiment of the present invention. Figure 9The displayed electronic device 900 is merely an example and shall not impose any limitation on the functions and scope of use of the embodiments of the present invention.

[0145] As Figure 9 shown, the electronic device 900 is presented in the form of a general-purpose computing device. The components of the electronic device 900 may include, but are not limited to: at least one of the above-mentioned processing units 910, at least one of the above-mentioned storage units 920, and a bus 930 connecting different system components (including the storage unit 920 and the processing unit 910).

[0146] Among them, the storage unit stores program code, and the program code can be executed by the processing unit 910, so that the processing unit 910 executes the steps according to various exemplary embodiments of the present invention described in the above "Exemplary Method" section of this specification. For example, the processing unit 910 can execute the solution described in step S202 as Figure 2 shown.

[0147] The storage unit 920 may include a readable medium in the form of a volatile storage unit, such as a random access storage unit (RAM) 9201 and / or a cache storage unit 9202, and may further include a read-only storage unit (ROM) 9203.

[0148] The storage unit 920 may further include a program / utility 9204 having a set (at least one) of program modules 9205. Such program modules 9205 include, but are not limited to: an operating system, one or more application programs, other program modules, and program data. Each or some combination of these examples may include the implementation of a network environment.

[0149] The bus 930 may represent one or more of several types of bus structures, including a storage unit bus or a storage unit controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any bus structure in a variety of bus structures.

[0150] The electronic device 900 can also communicate with one or more external devices 970 (such as keyboards, pointing devices, Bluetooth devices, etc.), and can also communicate with one or more devices that enable a user to interact with the electronic device 900, and / or communicate with any device that enables the electronic device 900 to communicate with one or more other computing devices (such as routers, modems, etc.). Such communication can be carried out through the input / output (I / O) interface 950. Moreover, the electronic device 900 can also communicate with one or more networks (such as local area networks (LANs), wide area networks (WANs), and / or public networks, such as the Internet) through the network adapter 960. As shown in the figure, the network adapter 960 communicates with other modules of the electronic device 900 through the bus 930. It should be understood that although not shown in the figure, other hardware and / or software modules can be used in combination with the electronic device 900, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, etc.

[0151] Through the description of the above embodiments, those skilled in the art can easily understand that the exemplary embodiments described herein can be implemented by software, or can be implemented by a combination of software and necessary hardware. Therefore, the technical solutions according to the embodiments of the present disclosure can be embodied in the form of a software product, and the software product can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, including several instructions to enable a computing device (which can be a personal computer, a server, a terminal device, or a network device, etc.) to execute the method according to the embodiments of the present disclosure.

[0152] In an exemplary embodiment of the present disclosure, there is also provided a computer-readable storage medium on which a program product capable of implementing the above method of this specification is stored. In some possible implementation manners, various aspects of the present invention can also be implemented in the form of a program product, which includes program code. When the program product runs on an electronic device, the program code is used to cause the electronic device to execute the steps according to various exemplary embodiments of the present invention described in the above "Exemplary Method" section of this specification.

[0153] The program product for implementing the above method according to the embodiments of the present invention can be a portable compact disc read-only memory (CD-ROM) and includes program code, and can run on an electronic device, such as a personal computer. However, the program product of the present invention is not limited thereto. In this document, the readable storage medium can be any tangible medium that contains or stores a program, and the program can be used by or in combination with an instruction execution system, apparatus, or device.

[0154] The program product may employ any combination of one or more readable media. The readable media may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples of the readable storage medium (a non-exhaustive list) include: an electrical connection having one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0155] A computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, in which the readable program code is carried. Such a propagated data signal may take many forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the foregoing. The readable signal medium may also be any readable medium other than the readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device.

[0156] The program code contained on the readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0157] The program code for performing the operations of the present invention may be written in any combination of one or more programming languages, including object-oriented programming languages such as Java, C++, etc., and also including conventional procedural programming languages such as the "C" language or similar programming languages. The program code may be executed entirely on the user's computing device, partially on the user's device, executed as a stand-alone software package, partially on the user's computing device and partially on a remote computing device, or entirely on the remote computing device or server. In the case of a remote computing device, the remote computing device may be connected to the user's computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., through the Internet using an Internet service provider).

[0158] It should be noted that although several modules or units of devices for action execution are mentioned in the foregoing detailed description, such a division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more of the above-described modules or units may be embodied in one module or unit. Conversely, the features and functions of one module or unit described above may be further divided and embodied by a plurality of modules or units.

[0159] In addition, although the steps of the methods in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step for execution, and / or one step may be decomposed into multiple steps for execution, etc.

[0160] From the description of the above embodiments, those skilled in the art can easily understand that the exemplary embodiments described herein can be implemented by software or by a combination of software and necessary hardware. Therefore, the technical solutions according to the embodiments of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, mobile hard disk, etc.) or on a network, and includes several instructions to enable a computing device (such as a personal computer, server, mobile terminal, or network device, etc.) to execute the methods according to the embodiments of the present disclosure.

[0161] After considering the specification and practicing the invention disclosed herein, those skilled in the art will readily conceive of other embodiments of the present disclosure. This application is intended to cover any variations, uses, or adaptations of the present disclosure, which follow the general principles of the present disclosure and include known common knowledge or conventional technical means in the technical field not disclosed herein. The specification and examples are only regarded as exemplary, and the true scope and spirit of the present disclosure are pointed out by the appended claims.

Claims

1. An optimization method for a memory cell layout, characterized in that, Including: Constructing an initial population based on multiple size variables in the layout and the size range of each said size variable; Configuring a required evaluation model based on the performance optimization requirements for the said layout; Calculating the evaluation values of the initial population based on the said evaluation model; Performing a preferential iterative evolution on the initial population based on the evaluation values of the initial population until the target values of each said size variable are obtained based on the iterative evolution results.

2. The optimization method of the storage cell layout according to claim 1, wherein The said layout includes multiple transistors. Constructing an initial population based on multiple size variables in the layout and the size range of each said size variable includes: For a single said transistor, sorting the multiple size variables in a specified order to obtain a variable sequence; For the multiple said transistors, configuring multiple variable sequences with the said specified order into a variable matrix; Generating the initial population based on the variable matrix and the size range.

3. The optimization method of the memory cell layout according to claim 2, wherein Generating the initial population based on the variable matrix and the size range includes: Determining the size range corresponding to each said size variable; Randomly assigning values to each said size variable in the variable matrix within the corresponding size range to obtain encoded genes, and the number of times of the random assignment corresponds to a preset quantity; Generating the initial population based on the encoded genes of the preset quantity.

4. The optimization method of the memory cell layout according to claim 1, wherein, Configuring a required evaluation model based on the performance optimization requirements for the said layout includes: Selecting a target index associated with the performance optimization requirements from multiple candidate performance indicators; Configuring a corresponding weight coefficient for each said target index based on the performance optimization requirements; Obtaining the evaluation model based on the target index and the corresponding weight coefficient.

5. The optimization method of the memory cell layout according to claim 4, wherein The said candidate performance indicators include: The gate delay, dynamic power consumption, static power consumption, transistor saturation current, and parasitic capacitance of the memory cell.

6. The optimization method for the layout of a storage cell according to claim 1, wherein Calculating the evaluation values of the initial population based on the said evaluation model includes: The initial population includes a preset quantity of encoded genes, and each said encoded gene corresponds to an evaluated layout to be evaluated. Detecting whether the layout to be evaluated meets the design rules; For the layout to be evaluated that does not meet the design rules, the obtained evaluation value is 0; For the layout to be evaluated that meets the design rules, evaluating the evaluation value of the layout to be evaluated based on the said evaluation model.

7. The optimization method of the storage cell layout according to claim 6, wherein Evaluating the evaluation value of the layout to be evaluated based on the said evaluation model includes: Performing a performance simulation on the layout to be evaluated to obtain the index value of the target index associated with the performance optimization requirements; Inputting the index value into the evaluation model to obtain the evaluation value.

8. The optimization method of the memory cell layout according to claim 1, wherein Performing a preferential iterative evolution on the initial population based on the evaluation values of the initial population until the target values of each said size variable are obtained based on the iterative evolution results includes: Performing a preferential selection on a preset quantity of encoded genes based on a preferential strategy to obtain preferred genes; Performing an iterative evolution based on the preferred genes so that after each iterative evolution, a preset quantity of evolved genes are obtained as the iterative evolution results; Detecting that the iterative evolution operation meets the termination condition, and selecting target genes from the evolved genes to determine the target values of each said size variable based on the target genes.

9. The optimization method of the memory cell layout according to claim 8, wherein Before constructing an initial population based on the size variables of multiple transistors in a layout and the size range of each of the size variables, it further includes: Configuring the evolutionary parameters of the preset quantity, the selection strategy, the termination condition, and the iterative evolution based on the performance optimization objective of the layout.

10. The optimization method of the storage cell layout according to claim 8, characterized in that, Selecting superior genes from a preset quantity of encoded genes based on a selection strategy, including: Sorting the preset quantity of encoded genes based on the corresponding evaluation values; The selection strategy includes a survival probability, and the superior genes are selected from the sorting result based on the survival probability.

11. The optimization method for a memory cell layout according to claim 8, wherein: The selection strategy includes one of a roulette wheel strategy, a tournament strategy, and an elitist retention strategy.

12. The optimization method of the storage cell layout according to claim 9, wherein Performing iterative evolution based on the superior genes, so as to obtain the preset quantity of evolved genes after each iterative evolution, including: Performing a hybridization operation based on the superior genes until the preset quantity of hybrid genes is obtained; Performing a mutation operation on the preset quantity of hybrid genes based on the evolutionary parameters, completing one iterative evolution, and obtaining the preset quantity of evolved genes.

13. The optimization method of the storage cell layout according to claim 8, wherein When it is detected that the iterative evolution operation meets the termination condition, selecting target genes from the evolved genes, including: The termination condition includes the number of generations of inheritance. When it is detected that the number of times of iterative evolution reaches the number of generations of inheritance, multiple generations of the evolved genes are obtained; Determining the evolved gene with the maximum evaluation value as the target gene.

14. The optimization method of the memory cell layout according to claim 8, characterized in that When it is detected that the iterative evolution operation meets the termination condition, selecting target genes from the evolved genes, including: The termination condition includes an evaluation threshold. When it is detected that the evaluation value of the evolved genes obtained based on the iterative evolution operation reaches the evaluation threshold, the evolved gene with the evaluation threshold is determined as the target gene.

15. The optimization method of the memory cell layout according to any one of claims 1 to 14, characterized in that, The layout is provided with polysilicon, connection regions, and active regions of transistors, and the multiple size variables include: The distances in a first direction between the polysilicon and the connection regions on both sides respectively; The distance in the first direction between two adjacent polysilicons; The distance in a second direction perpendicular to the first direction between two adjacent active regions; and The extension length in the second direction of one side edge of the polysilicon relative to the intersecting active region.

16. An optimization device for a memory cell layout, characterized in that It includes: A construction module for constructing an initial population based on multiple size variables in a layout and the size range of each of the size variables; A configuration module for configuring a required evaluation model based on the performance optimization requirements of the layout; A calculation module for calculating the evaluation values of the initial population based on the evaluation model; An evolution module for performing a selective iterative evolution on the initial population based on the evaluation values of the initial population until target values of each of the size variables are obtained based on the iterative evolution result.

17. An electronic device, characterized in that, It includes: A processor; And A memory for storing executable instructions of the processor; Wherein, the processor is configured to execute the optimization method for the memory cell layout according to any one of claims 1 to 15 by executing the executable instructions.

18. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the optimization method of the storage cell layout described in any one of claims 1 to 15.

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