Module structure of integrated circuit and integrated circuit chip
Through the physical isomorphic module and internal feedthrough path set with mirror symmetrical settings, the problem of high difficulty in converging module connections in large-scale chip design is solved, and the effect of saving chip resources and shortening iteration cycles is achieved.
Patent Information
- Application Number
- CN202510370385.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-27
- Publication Date
- 2025-07-11
AI Technical Summary
In large-scale chip design, the connection between modules is difficult to converge due to too many top-level registers and logic, and the mirror symmetric design requires a long trace distance, and some symmetric design increases the cost of back-end implementation.
The physical isomorphic module with mirror symmetrical settings is designed through internal feedthrough paths and redundant interfaces to realize signal transmission between modules, reduce trace distance and save chip area.
The mirror symmetry and module physical isomorphism are realized, which reduces chip resources and area, shortens the iterative convergence cycle, and reduces the back-end implementation workload.
Smart Images
Figure CN120297219A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of chip technology, and particularly to a module structure of an integrated circuit and an integrated circuit chip. Background Art
[0002] In traditional chip design, after the physical implementation of modules is completed, when doing top-level implementation, the connections between modules will be realized through channels reserved at the top level. As the chip scale becomes larger and larger, there are more and more registers and logics at the top level, which often become the bottleneck of the physical implementation of the entire chip, with high convergence difficulty and long cycle. Therefore, many current chips adopt "channel-less", that is, channel-less design, or channel-less design between some modules, such as the feedthrough design method (feedthrough).
[0003] In addition, during the use of the chip, there is often a situation where one module needs to be used in multiple copies. In the floorplan design of the entire chip, according to the business and module characteristics of the chip, for example, some network switching chips, etc., symmetric design or partial symmetric design can be done. However, a chip that only considers interface symmetric design still requires a long routing distance, and adopting partial symmetric design will also cause costs in the back-end implementation.
[0004] Therefore, a module structure design scheme is needed that can save routing distance and chip area, and at the same time meet module physical isomorphism and achieve mirror symmetry design. Summary of the Invention
[0005] The present invention aims to provide a module structure of an integrated circuit and an integrated circuit chip that can achieve mirror symmetry and maximum module physical isomorphism.
[0006] According to one aspect of the present invention, a module structure of an integrated circuit is provided, which at least includes a first physically isomorphic module and a second physically isomorphic module that are mirror-symmetrically arranged. Each physically isomorphic module at least includes a first input interface, a first output interface, a first feedthrough input interface, and a logic processing module.
[0007] The first input interface of the first physically isomorphic module is connected to the first output interface of the first physically isomorphic module through an internal feedthrough path.
[0008] The first output interface of the first physically isomorphic module is also connected to the first feedthrough input interface of the second physically isomorphic module through a channel.
[0009] The first input interface of the first physically isomorphic module is used to receive a signal to be fed through to the second physically isomorphic module.
[0010] The logic processing module of the second physical isomorphism module processes the signals of the first feedthrough input interface of the second physical isomorphism module.
[0011] According to some embodiments, the first input interface of the second physical isomorphism module is a redundant interface, the first output interface of the second physical isomorphism module is a redundant interface, and the first feedthrough input interface of the first physical isomorphism module is a redundant interface.
[0012] According to some embodiments, each physical isomorphism module further includes a first direct input interface,
[0013] The first direct input interface is used to receive the signal to be processed input to the physical isomorphism module; the logic processing module of the physical isomorphism module is further used to process the signals of the first direct input interface.
[0014] According to some embodiments, in the first physical isomorphism module and the second physical isomorphism module, when the first direct input interface of one of the physical isomorphism modules is connected to the destination port, the first direct input interface of the other physical isomorphism module is a redundant interface.
[0015] According to some embodiments, the logic processing module includes a selector and a processing unit, and the selector includes a first selection input interface, a second selection input interface, and a control interface:
[0016] The first selection input interface of the selector is connected to the first direct input interface, the second selection input interface of the selector is connected to the first feedthrough input interface, and the control interface of the selector is used to receive control information;
[0017] The selector outputs the signal received by the first selection input interface or the signal received by the second selection input interface according to the control information;
[0018] The processing unit is used to receive and process the signal output by the selector.
[0019] According to some embodiments, each physical isomorphism module further includes a beat register provided in the internal feedthrough path.
[0020] According to some embodiments, each physical isomorphism module includes at least a second output interface, a second input interface, and a second feedthrough output interface,
[0021] The second feedthrough output interface of the second physical isomorphism module is connected to the output end of the logic processing module of the second physical isomorphism module;
[0022] The second feedthrough output interface of the second physical isomorphism module is connected to the second input interface of the first physical isomorphism module through a channel;
[0023] The second input interface of the first physical isomorphism module is connected to the second output interface of the first physical isomorphism module through an internal feedthrough path.
[0024] According to some embodiments, the second input interface and the second output interface of the second physical isomorphism module are redundant interfaces, and the second feedthrough output interface of the first physical isomorphism module is a redundant interface.
[0025] According to some embodiments, the physical isomorphism module further includes a second direct output interface, and the second direct output interface is connected to the output port of the corresponding logic processing module;
[0026] In the first physical isomorphism module and the second physical isomorphism module, when the second direct output interface of one of the physical isomorphism modules is connected to the destination port, the second direct output interface of the other physical isomorphism module is a redundant interface.
[0027] According to another aspect of the present invention, there is provided an integrated circuit chip, including the module structure of the integrated circuit according to any one of the above claims.
[0028] According to an exemplary embodiment of the present invention, the module structure of the integrated circuit at least includes a first physical isomorphism module and a second physical isomorphism module that are mirror-symmetrically arranged. The mirror-symmetric design reduces complexity and facilitates layout planning and wiring optimization. Each physical isomorphism module at least includes a first signal input interface, a first signal output interface, and a first feedthrough input interface. The setting of multiple interfaces enhances the flexibility of signal transmission between modules, and the logic processing unit processes data, improving the stability of the system.
[0029] By setting a feedthrough path and redundant interfaces in the integrated circuit module, physical isomorphism and mirror-symmetric setting of the integrated circuit module can be achieved, which can ensure a short wiring distance, save the overall resources and area of the chip. For the back-end implementation, it can save human resources and greatly reduce the workload of the back-end implementation, shortening the iteration convergence cycle.
[0030] In the prior art, if a mirror-symmetric structure is to be maintained, the feedthrough scheme may need to be abandoned, and the wiring is routed from the top layer channel or other surrounding modules, bypassing the large module in the middle. In this way, the wiring distance will be greatly increased, and the register and buffer resources will also increase. Through the technical solution of the present invention, feedthrough can be realized on the mirror-symmetric structure, so as to make full use of the area and wiring resources of the middle module to realize feedthrough, saving the overall resources and area of the chip.
[0031] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly introduced below.
[0033] Figure 1A Show a layout design diagram of an existing integrated circuit chip module.
[0034] Figure 1B Show another layout design diagram of an existing integrated circuit chip module.
[0035] Figure 2 Show a layout schematic diagram of a physically isomorphic integrated circuit chip module.
[0036] Figure 3A Show a schematic diagram of the conventional layout and wire connection of an integrated circuit chip module.
[0037] Figure 3B Show a schematic diagram of the conventional feed-through wire connection and layout of an integrated circuit chip module.
[0038] Figure 4 Show a schematic diagram of the module structure layout and feed-through connection of an integrated circuit according to an exemplary embodiment.
[0039] Figure 5 Show a schematic diagram of a logic processing module in an integrated circuit module structure according to an exemplary embodiment.
[0040] Figure 6 Show a schematic diagram of the module structure components and feed-through connection of an integrated circuit according to another exemplary embodiment.
[0041] Figure 7 Show a layout schematic diagram of a physically isomorphic module in an integrated circuit chip according to an exemplary embodiment.
[0042] Figure 8 Show a method flowchart for the feed-through path design for an integrated circuit module structure according to an exemplary embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0043] The exemplary embodiments will now be described more fully with reference to the drawings. However, the exemplary embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this invention will be thorough and complete, and the concept of the exemplary embodiments will be fully conveyed to those skilled in the art. Identical reference numerals in the figures denote identical or similar parts, and thus their repeated description will be omitted.
[0044] In addition, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of the embodiments of the present invention. However, those skilled in the art will realize that the technical solutions of the present invention can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, well-known methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the present invention.
[0045] The block diagrams shown in the drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.
[0046] The flowcharts shown in the drawings are only exemplary illustrations and do not necessarily include all the content and operations / steps, nor are they necessarily executed in the described order. For example, some operations / steps can be decomposed, while some operations / steps can be combined or partially combined, so the actual execution order may change according to the actual situation.
[0047] It should be understood that although terms such as first, second, and third may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another. Therefore, the first component discussed below can be referred to as the second component without departing from the teachings of the concept of the present invention. As used herein, the term "and / or" includes any one of the associated listed items and all combinations of one or more of them.
[0048] Those skilled in the art can understand that the drawings are only schematic diagrams of exemplary embodiments, and the modules or processes in the drawings are not necessarily essential for implementing the present invention, so they cannot be used to limit the protection scope of the present invention.
[0049] In traditional chip design, after the physical implementation of the modules is completed, when doing the top-level implementation, the connections between the modules will be realized through the channels reserved at the top level. As Figure 1A shown, the integrated circuit chip is divided into 4 modules, namely module A, module B, module C, and module D. And when doing the top-level (TOP) design, a channel is reserved in the middle. The interface connection between module A and module D will be placed in this channel at the top level to be realized. Correspondingly, the flop registers required for the interfaces between the modules are also placed in the top-level channel.
[0050] As the chip scale becomes larger and larger, there are more and more registers and logics at the top level, and the convergence difficulty is high. See Figure 1B, showing a schematic layout diagram of an integrated circuit chip module adopting a channel-less design. For the connection between module A and module D, since there is no top-level channel, a feedthrough design is adopted, and the trace penetrates through the inside of module B or module C. Adopting this feedthrough method greatly compresses the area of the top-level channel, and the area utilization rate of the chip will be higher.
[0051] In chip design, especially for the backend physical implementation (Physical Design, PD), when a module needs to be used multiple times, a symmetric design can be made to simplify the design process. However, for a chip that only considers the symmetric design of the interface, there is still a long trace distance, and adopting a partially symmetric design will also cause costs in the backend implementation.
[0052] Before describing the embodiments of the present application, some terms or concepts related to the embodiments of the present application are explained.
[0053] Physical Isomorphism, in chip design, refers to that multiple modules or instances are completely the same in physical implementation. That is, the modules are not only consistent in function and logical design, but also all their physical characteristics such as layout, wiring, clock tree synthesis, and power network are completely the same, although they may perform different signal processing functions. This design method is usually used to create scalable and reusable modules to reduce the impact of process variations, improve test coverage, and reduce development costs.
[0054] Figure 2 Showing a schematic layout diagram of an integrated circuit chip module with physical isomorphism.
[0055] See Figure 2 , in the integrated circuit chip, module A and module F are packaged into an upper-level physical module (TOP_AF). In physical implementation, only one separate TOP_AF is made and instantiated 4 times on the final chip top-level design layout (TOPfloorplan), so that the four areas of module A_0 and module F_0, module A_1 and module F_1, module A_2 and module F_2, and module A_3 and module F_3 are mirror-symmetrically designed, which can greatly reduce the scale of the top-level design. Module F may involve external interfaces. After mirror flipping, the interfaces can be led out from the top and bottom of the TOP respectively, making the data flow smoother.
[0056] In this case, for data routing between modules, see Figure 3A, assuming that there is an interface between module C and module A, since module A has 4 copies, there are a total of 4 groups of interfaces between module C and the 4 parts of module A. Module C can be connected to the interfaces of module A_0 and module A_1 from the top channel. If the interface routing between module C and module A_2 and module A_3 is directly connected, since module A_2 and module A_3 are mirror images of module A_0 and module A_1, this group of interfaces must enter from the bottom of module A_2 and module A_3. However, the routing distance using this form is very long. The long routing increases the length of the interconnection line, thereby introducing more parasitic capacitance and resistance, which will also increase the delay of signal transmission and reduce the overall performance of the system.
[0057] See also Figure 3B For the interface between module A_2 and module A_3, if the following Figure 3B The routing form is to first connect module C to module A_0 and module A_1 respectively, and then pass through module A_0 and module A_1 to module A_2 and module A_3, that is, feedthrough is performed in module A_0 and module A_1. According to the example embodiment, for the path from module C to module A_2, position P1 of module A_0 serves as the output port of module A_0. After output from module A_0, it enters module A_2 from position P2 of module A_2. For module A_2, position P2 serves as the input interface of module A_2, which is inconsistent with the mirror-symmetric design. If module A_0 and module A_2 are mirror images of each other, then the functional logic of position P1 of module A_0 and position P2 of module A_2 should be exactly the same.
[0058] Therefore, if you want to reduce the length of the wiring, if you choose to do feedthrough from module A_0 and module A_1, you can only give up the mirror symmetric design. However, if module A_2 and module A_0 are not mirrored, then the interface output by module A_2 to module F_2 will no longer be located at the position P4 in the figure, which will bring the cost of long wiring. Alternatively, module A needs to be implemented in two different physical copies and treated as two modules at the back end. Module A_0 and module A_1 use the same copy for replication, and module A_2 and module A_3 use another copy for replication, which will cause costs in the back end implementation.
[0059] In the existing technology, for the top-level floorplan design of the mirror-symmetric structure, either feedthrough is abandoned, which will increase the top-level channels, increase the chip area, and increase the difficulty of back-end convergence; or feedthrough technology is used, but it will destroy the symmetric design and physical isomorphic design of some modules. It cannot guarantee that the functional logic of the four regions of module A is exactly the same, which will also increase the cost of convergence difficulty.
[0060] Therefore, the present invention proposes a module structure for an integrated circuit chip. By adding redundant interfaces, mirror symmetry and feedthrough design can be achieved simultaneously, reducing the workload of backend implementation and shortening the cycle of iterative convergence.
[0061] The exemplary embodiments of the present invention will be described below with reference to the accompanying drawings.
[0062] Figure 4 A schematic diagram of the module structure layout and feedthrough connection of an integrated circuit according to an exemplary embodiment is shown.
[0063] According to an exemplary embodiment, referring to Figure 4 , the module structure of the integrated circuit includes at least a first physically isomorphic module 101 and a second physically isomorphic module 201 that are mirror-symmetrically arranged. Each physically isomorphic module includes a first input interface 012, a first output interface 013, a first feedthrough input interface 014, and a logic processing module. Each physically isomorphic module further includes a first direct input interface 011.
[0064] According to some embodiments, the first direct input interface 011 is used to receive the signal to be processed input to the physically isomorphic module. The first direct input interface 011 is used to directly receive the signal transmitted from an external module to the integrated circuit. The first direct input interface 011 provides a dedicated input path for external signals, ensuring that the signal can directly enter the module for processing without going through any intermediate steps or feedthrough processes.
[0065] The first input interface 012 of the first physically isomorphic module 101 is connected to the first output interface 013 of the first physically isomorphic module 101 through an internal feedthrough path. The first output interface 013 of the first physically isomorphic module 101 is also connected to the first feedthrough input interface 014 of the second physically isomorphic module 201 through a channel. The first input interface 012 of the first physically isomorphic module 101 is used to receive the signal to be feedthrough to the second physically isomorphic module 201. The logic processing module of the second physically isomorphic module 201 processes the signal of the first feedthrough input interface 014 of the second physically isomorphic module 201. The logic processing module of the physically isomorphic module is also used to process the signal of the first direct input interface 011.
[0066] According to some embodiments, the first input interface 011 of the second physical isomorphism module 201 is a redundant interface, the first output interface 013 of the second physical isomorphism module 201 is a redundant interface, and the first feedthrough input interface 014 of the first physical isomorphism module 101 is a redundant interface. If an interface is a redundant interface, it will not be connected to other ports, that is, the input redundant interface is connected to 0, and the output redundant interface is left floating and not used.
[0067] In the first physical isomorphism module 101 and the second physical isomorphism module 201, when the first direct input interface 011 of one of the physical isomorphism modules is connected to the destination port, the first direct input interface 011 of the other physical isomorphism module is a redundant interface. The destination port is the connection port between the external module and the physical isomorphism module. For example Figure 4 if the first input interface 011 of the first physical isomorphism module 101 in [example] is connected to the destination port, then the first direct input interface 011 of the second physical isomorphism module 201 is a redundant interface.
[0068] Each physical isomorphism module further includes a beat register disposed on the internal feedthrough path. For example, the beat register is disposed inside the first physical isomorphism module 101, that is, in the path from the first input interface 012 to the first output interface 013.
[0069] When the source external module wants to transmit information to the second physical isomorphism module 201, it enters the first physical isomorphism module 101 through the first input interface 012 of the first physical isomorphism module 101, passes through the beat register inside the first physical isomorphism module 101, and then is transmitted to the first output interface 013 of the first physical isomorphism module 101, and then is transmitted to the inside of the second physical isomorphism module 201 through the first feedthrough input interface 014 of the second physical isomorphism module 201.
[0070] When the external module interacts with the interface of the integrated circuit chip, the external module first connects to the first physical isomorphism module 101, and then makes a routing connection to the second physical isomorphism module 201 through the first physical isomorphism module 101, through the feedthrough routing of the first physical isomorphism module 101 and the second physical isomorphism module 201. The first direct input interface 011 of the first physical isomorphism module 101 is the self-use input interface of the first physical isomorphism module 101, and the first input interface 012 of the first physical isomorphism module 101 is the input interface for the use of the second physical isomorphism module 201. The first output interface 013 of the first physical isomorphism module 101 is the output interface of the first physical isomorphism module 101, and the first feedthrough input interface 014 of the first physical isomorphism module 101 is a redundant interface.
[0071] For the internal logic of the first physical isomorphic module 101, the first direct input interface 011 is actually used to process the information brought by the external module. For the second physical isomorphic module 201, the information transmitted by the external module to the second physical isomorphic module is input from the first feedthrough input interface 014. Therefore, for the internal logic of the second physical isomorphic module, the first feedthrough input interface 014 needs to be used to process the information brought by the external module. From this, it can be seen that the interfaces required for the internal processing logic are different. To make the first physical isomorphic module 101 and the second physical isomorphic module 201 completely isomorphic, according to the exemplary embodiment, a logic processing module is added inside each physical isomorphic module.
[0072] Figure 5 A schematic diagram showing a logic processing module in an integrated circuit module structure according to an exemplary embodiment.
[0073] According to some embodiments, the logic processing module includes a selector and a processing unit, and the selector can be a multiplexer (MUX).
[0074] Refer to Figure 5 , the logic processing module includes a selector 601 and a processing unit 705. The selector 601 includes a first selection input interface 701, a second selection input interface 704, and a control interface 703. The first selection input interface 701 of the selector 601 is connected to the first direct input interface 011, the second selection input interface 704 of the selector 601 is connected to the first feedthrough input interface 014, the control interface 703 of the selector is used to receive control information, and the selector outputs the signal received by the first direct input interface 011 or the signal received by the first feedthrough input interface 014 according to the control information. The processing unit 705 is used to receive and process the signal output by the selector 601.
[0075] Through the logic processing module, the first physical isomorphic module 101 processes the information input from the first direct input interface 011 of the first physical isomorphic module 101, and the second physical isomorphic module 201 processes the information input from the first feedthrough input interface 014 of the second physical isomorphic module 201.
[0076] Figure 6 A schematic diagram showing the module structure components and feedthrough connections of an integrated circuit according to another exemplary embodiment.
[0077] According to some other embodiments, each physical isomorphic module includes a second output interface 022, a second input interface 023, and a second feedthrough output interface 024. The second feedthrough output interface 024 of the second physical isomorphic module 201 is connected to the output end of the logic processing module of the second physical isomorphic module 201. The physical isomorphic module further includes a second direct-through output interface 021, and the second direct-through output interface 021 is connected to the output port of the corresponding logic processing module.
[0078] Output from the first physical isomorphic module 101 to an external module. Refer to Figure 6 , the second feedthrough output interface 024 of the second physical isomorphic module 201 is connected to the second input interface 023 of the first physical isomorphic module 101 through a channel, and the second input interface 023 of the first physical isomorphic module 101 is connected to the second output interface 022 of the first physical isomorphic module 101 through an internal feedthrough path. The second input interface 023 and the second output interface 022 of the second physical isomorphic module 201 are redundant interfaces, and the second feedthrough output interface 024 of the first physical isomorphic module 101 is a redundant interface.
[0079] In the first physical isomorphic module 101 and the second physical isomorphic module 201, when the second direct-through output interface 021 of one of the physical isomorphic modules is connected to a destination port, the second direct-through output interface 021 of the other physical isomorphic module is a redundant interface. As Figure 6 shown, if the first input interface 021 of the first physical isomorphic module 101 is connected to a destination port, then the first direct-through input interface 021 of the second physical isomorphic module 201 is a redundant interface.
[0080] Entering from the first input interface 023 of the first physical isomorphic module 101 and then outputting from the first output interface 022 of the first physical isomorphic module 101 to an external module, the data actually transmitted by the first output interface 022 of the first physical isomorphic module 101 is the output data from the second physical isomorphic module 201 to the external module.
[0081] Figure 7 Shows a layout schematic diagram of physical isomorphic modules in an integrated circuit chip according to an exemplary embodiment.
[0082] According to some embodiments, adopting the integrated circuit chip design of this exemplary embodiment, the module structure of the integrated circuit chip may further include a third physical isomorphic module and a fourth physical isomorphic module. As Figure 7As shown, the same module is instantiated four times, namely the first physically isomorphic module (A_A1 and F_F1), the second physically isomorphic module (A_A2 and F_F2), the third physically isomorphic module (A_A3 and F_F3), and the fourth physically isomorphic module (A_A4 and F_F4). The third physically isomorphic module is arranged symmetrically with respect to the first physically isomorphic module in a mirror image, the fourth physically isomorphic module is arranged symmetrically with respect to the second physically isomorphic module in a mirror image, and the third physically isomorphic module is arranged symmetrically with respect to the fourth physically isomorphic module in a mirror image.
[0083] Based on the integrated circuit chip feedthrough technology, this embodiment realizes the transmission between the upper and lower parts of the module. However, considering the connection between the first output interface and the first feedthrough input interface of the two modules, there will be crossovers. Therefore, in the implementation of the top-level floorplan, it is impossible to achieve an absolutely channel-free situation, and a narrow channel needs to be reserved to realize the crossover routing.
[0084] The narrow channel provides a dedicated space for placing these crossover traces when the connection between modules needs to cross other signal lines, avoiding wiring congestion and signal interference. By pre-planning the position and width of the narrow channel, complex interconnection requirements can be more flexibly handled without affecting the overall layout. The specific value of the width of the narrow channel depends on factors such as the process node, the number of metal layers, and the expected wiring density, etc. It can accommodate the necessary traces sufficiently, but is as small as possible to reduce the impact on other wiring resources. Generally speaking, the width may range from a few micrometers to dozens of micrometers, and it is considered in the early design stage and optimized through detailed simulation and analysis tools to ensure that its position and size can maximize the wiring efficiency.
[0085] The integrated circuit chip proposed by the present invention can maximize the physical isomorphism of the module while realizing mirror symmetry and feedthrough by increasing redundant interfaces and some narrow channels. Only one detailed physical design is required, and then the module is replicated to meet the needs of multiple application scenarios, reducing repetitive labor. Through the feedthrough technology and narrow channels, complex top-level wiring can be avoided, reducing the risk of wiring congestion.
[0086] In an actual chip, some large modules will be placed inside, such as modules where multiple data streams converge, shared caches, etc. Through the technical solution of the present invention, a feedthrough design can be realized on the mirror-symmetric structure, making full use of the area and wiring resources of the intermediate module to achieve feedthrough, so as to save the overall resources and area of the chip. This not only improves the design efficiency, reduces the consumption of human resources, but also greatly shortens the iterative convergence cycle of the backend implementation.
[0087] Since all the modules are physically isomorphic, the input signals need to be selected through the logic processing module. According to some embodiments, when instantiating the first physically isomorphic module at the top layer of the integrated circuit chip, the control interface of the first physically isomorphic module can be connected to the constant 0, the control interface of the second physically isomorphic module can be connected to the constant 1, and the control interfaces of the third physically isomorphic module and the fourth physically isomorphic module can be connected to the constants 2 and 3 respectively.
[0088] The input interface is selected through the control interface 703 of the logic processing module. When the control information (ID) input through the control interface 703 is 0, it means that the first physically isomorphic module is selected, and the first direct input interface of the first physically isomorphic module is used as the input. When the control interface ID is 1, it means that the second physically isomorphic module is selected, and the first feedthrough input interface of the second physically isomorphic module is used as the input. The relationship between the third physically isomorphic module and the fourth physically isomorphic module is the same as that between the first physically isomorphic module and the second physically isomorphic module. Therefore, when looking at the four modules as a whole, when the control interface ID is 0 and 2, the first direct input interface is selected; when the control interface is 1 and 3, the first feedthrough input interface is selected. In this way, a completely mirror-symmetric design of the four modules is achieved, which can greatly reduce the scale of the top-level design and improve the convergence efficiency of physical implementation.
[0089] Figure 8 A method flowchart for the feedthrough path design of an integrated circuit module structure according to an exemplary embodiment is shown.
[0090] See Figure 8 , in order to achieve the mirror symmetry of the integrated circuit chip and meet the physical isomorphism of the modules, a method for the feedthrough path design of an integrated circuit module structure is proposed.
[0091] In S801, the first interface, the second interface, the third interface, and the fourth interface of the integrated circuit module are set, and a feedthrough path is formed between the second interface and the third interface.
[0092] According to the exemplary embodiment, the first interface of the integrated circuit module is set, and the first interface is used to be electrically connected to an external module or as a redundant interface. When the external module needs to transmit information to the integrated circuit module, the first interface of the first module is electrically connected to the external module as an input interface. When the integrated circuit module needs to transmit information to the external module, the first interface of the first module is electrically connected to the external module as an output interface.
[0093] A second interface of the integrated circuit module is provided. The second interface is used for electrically connecting to the external module or as a redundant interface. When the external module needs to transmit information to the integrated circuit module, the second interface of the first module is electrically connected to the external module as an input interface. When the integrated circuit module needs to transmit information to the external module, the second interface of the first module is electrically connected to the external module as an output interface.
[0094] A third interface of the integrated circuit module is provided. The third interface is used as a feed-through signal interface or as a redundant interface. When the external module needs to transmit information to the integrated circuit module, the third interface of the first module serves as a feed-through signal interface.
[0095] A fourth interface of the integrated circuit module is provided. The fourth interface is used as a feed-through signal interface or as a redundant interface. When the external module needs to transmit information to the integrated circuit module, the fourth interface of the first module serves as a redundant interface.
[0096] A feed-through path is formed between the second interface and the third interface to facilitate the transmission of information from the external module through the inside of the first module to the second module. This can ensure a shorter routing distance and save the overall chip resources and area.
[0097] In S803, the integrated circuit module as the first module and the integrated circuit module as the second module are arranged in a mirror-symmetrical manner.
[0098] According to the exemplary embodiment, the first module and the second module of the integrated circuit chip are arranged in a mirror-symmetrical manner. The first interface of the first module is electrically connected to the external module. Correspondingly, the first interface of the second module serves as a redundant interface. The second interface of the first module is electrically connected to the external module. The second interface of the second module serves as a redundant interface. The third interface of the first module is connected to the fourth interface of the second module. The fourth interface of the first module and the third interface of the second module serve as redundant interfaces; the fourth interface of the second module and the third interface of the second module are used as feed-through signal interfaces.
[0099] When the interface that is mirror-symmetrical to the redundant interface is an input interface, the corresponding redundant interface is fixedly connected to zero for positioning. When the interface that is mirror-symmetrical to the redundant interface is an output interface, the corresponding redundant interface is floating.
[0100] The integrated circuit chip design of this exemplary embodiment adopts a mirror-symmetrical first module and second module. Through the mirror-symmetrical design, it is ensured that the two modules are completely identical in physical characteristics, which can not only simplify the layout and routing process and reduce complexity. The feedthrough signal interface and feedthrough path allow signals to directly pass through the inside of the module, reducing the need for long traces, optimizing the routing resources, and achieving necessary cross-traces without disrupting the overall layout, providing a path for signals that need to cross between modules. Through the feedthrough path and redundant interfaces set by the present invention, both a short trace path is guaranteed and the physical isomorphism of the chip is satisfied. For the backend implementation, it can save human resources and greatly reduce the workload of the backend implementation, shortening the iteration convergence cycle.
[0101] It should be noted that in the specific implementation process, those skilled in the art can understand that the above device may also only include the components necessary to implement the solution of the embodiments of this specification, and does not necessarily include all the components shown in the figure.
[0102] Those skilled in the art can clearly understand that the technical solution of the present invention can be implemented by means of software and / or hardware. The "units" and "modules" in this specification refer to software and / or hardware that can independently complete or cooperate with other components to complete specific functions, where the hardware can be, for example, a field programmable gate array, an integrated circuit, etc.
[0103] It should be noted that for the foregoing method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should know that the present invention is not limited by the described action sequence, because according to the present invention, certain steps can be in other sequences or performed simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to the present invention.
[0104] In the above embodiments, the descriptions of the various embodiments have their own emphases. For the parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.
[0105] In several embodiments provided by the present invention, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of units is only a logical function division. In actual implementation, there can be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed mutual coupling or direct coupling or communication connection can be through some service interfaces. The indirect coupling or communication connection of the device or unit can be in an electrical or other form.
[0106] The unit described as a separate component may or may not be physically separated. The component displayed as a unit may or may not be a physical unit, that is, it may be located in one place or may be distributed across multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
[0107] In addition, each functional unit in various embodiments of the present invention may be integrated in a processing unit, may exist separately as individual physical units, or two or more units may be integrated in one unit. The above integrated units can be implemented in the form of hardware or in the form of software functional units.
[0108] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods in various embodiments of the present invention.
[0109] In the above embodiments, the descriptions of each embodiment have their own focuses. For the parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.
[0110] The exemplary embodiments of the present invention have been specifically shown and described above. It should be understood that the present invention is not limited to the detailed structures, setting methods, or implementation methods described herein; on the contrary, the present invention is intended to cover various modifications and equivalent settings included within the spirit and scope of the appended claims.
Claims
1. A module structure of an integrated circuit, characterized in that At least including a first physically isomorphic module and a second physically isomorphic module which are mirror-symmetrically arranged. Each physically isomorphic module at least includes a first input interface, a first output interface, a first feedthrough input interface, and a logic processing module. The first input interface of the first physically isomorphic module is connected to the first output interface of the first physically isomorphic module through an internal feedthrough path. The first output interface of the first physically isomorphic module is also connected to the first feedthrough input interface of the second physically isomorphic module through a channel. The first input interface of the first physically isomorphic module is used to receive a signal to be fed through to the second physically isomorphic module. The logic processing module of the second physically isomorphic module processes the signal of the first feedthrough input interface of the second physically isomorphic module.
2. The module structure according to claim 1, wherein: The first input interface of the second physically isomorphic module is a redundant interface, the first output interface of the second physically isomorphic module is a redundant interface, and the first feedthrough input interface of the first physically isomorphic module is a redundant interface.
3. The module structure according to claim 1, wherein Each physically isomorphic module further includes a first direct input interface. The first direct input interface is used to receive a signal to be processed input to the physically isomorphic module. The logic processing module of the physically isomorphic module is also used to process the signal of the first direct input interface.
4. The module structure according to claim 3, wherein: In the first physically isomorphic module and the second physically isomorphic module, when the first direct input interface of one of the physically isomorphic modules is connected to a destination port, the first direct input interface of the other physically isomorphic module is a redundant interface.
5. The module structure according to claim 1, wherein The logic processing module includes a selector and a processing unit. The selector includes a first selection input interface, a second selection input interface, and a control interface: The first selection input interface of the selector is connected to the first direct input interface, the second selection input interface of the selector is connected to the first feedthrough input interface, and the control interface of the selector is used to receive control information. The selector outputs the signal received by the first selection input interface or the signal received by the second selection input interface according to the control information. The processing unit is used to receive and process the signal output by the selector.
6. The module structure according to claim 1, wherein Each physically isomorphic module further includes a beat register arranged on the internal feedthrough path.
7. The module structure according to claim 1, wherein Each physically isomorphic module at least includes a second output interface, a second input interface, and a second feedthrough output interface. The second feedthrough output interface of the second physically isomorphic module is connected to the output end of the logic processing module of the second physically isomorphic module. The second feedthrough output interface of the second physically isomorphic module is connected to the second input interface of the first physically isomorphic module through a channel. The second input interface of the first physically isomorphic module is connected to the second output interface of the first physically isomorphic module through an internal feedthrough path.
8. The module structure according to claim 7, characterized in that: The second input interface and the second output interface of the second physical isomorphism module are redundant interfaces, and the second feedthrough output interface of the first physical isomorphism module is a redundant interface.
9. The module structure according to claim 8, characterized in that, The physical isomorphism module further includes a second direct output interface. The second direct output interface is connected to the output port of the corresponding logic processing module. In the first physical isomorphism module and the second physical isomorphism module, when the second direct output interface of one of the physical isomorphism modules is connected to the destination port, the second direct output interface of the other physical isomorphism module is a redundant interface.
10. An integrated circuit chip, characterized in that, It includes the module structure according to any one of claims 1-9.