Design parameter processing method of printed circuit board, electronic equipment and storage medium

Abstract

The invention provides a design parameter processing method of a printed circuit board, electronic equipment and a storage medium, and relates to the technical field of printed circuit boards. The method comprises the following steps: in response to a selection operation for a signal interconnection object in a layout and wiring diagram, determining an associated node belonging to the same signal channel with the signal interconnection object in nodes of the layout and wiring diagram; the associated node is determined based on the relation information of the node and the signal interconnection object; and outputting a parameter table based on the connection relationship between the signal interconnection object and the associated node and the design parameter. The method is used for achieving the effect of improving the efficiency of the design parameters of each node on the output signal channel.

Description

Technical Field

[0001] This application relates to the technical field of printed circuit boards, and in particular, to a method for processing design parameters of a printed circuit board, an electronic device, and a storage medium. Background Art

[0002] The design parameters of a printed circuit board have a significant impact on the working state of the printed circuit board.

[0003] In the related art, after the layout and wiring diagram of the printed circuit board is designed, the design parameters of the nodes in the layout and wiring diagram can only be queried one by one, and then the design parameters are manually recorded, and this process is inefficient. Summary of the Invention

[0004] Embodiments of this application provide a method for processing design parameters of a printed circuit board, an electronic device, and a storage medium, so as to achieve the effect of improving the efficiency of the design parameters of each node on the output signal channel.

[0005] In a first aspect, an embodiment of this application provides a method for processing design parameters of a printed circuit board, including: in response to a selection operation on a signal interconnection object in a layout and wiring diagram, determining, among the nodes of the layout and wiring diagram, associated nodes that belong to the same signal channel as the signal interconnection object; the associated nodes are determined based on the relationship information of the nodes and the signal interconnection object; and outputting a parameter table based on the connection relationship and design parameters of the signal interconnection object and the associated nodes.

[0006] In a second aspect, an embodiment of this application provides a device for processing design parameters of a printed circuit board, including:

[0007] a node selection module, configured to, in response to a selection operation on a signal interconnection object in a layout and wiring diagram, determine, among the nodes of the layout and wiring diagram, associated nodes that belong to the same signal channel as the signal interconnection object; the associated nodes are determined based on the relationship information of the nodes and the signal interconnection object;

[0008] a parameter table output module, configured to output a parameter table based on the connection relationship and design parameters of the signal interconnection object and the associated nodes.

[0009] In a third aspect, an embodiment of this application provides an electronic device, including: a memory, a processor; the memory stores computer-executable instructions; the processor executes the computer-executable instructions stored in the memory, so that the processor executes the first aspect and / or various possible implementation manners of the first aspect as described above.

[0010] In a fourth aspect, an embodiment of this application provides a computer-readable storage medium, in which computer-executable instructions are stored, and when the computer-executable instructions are executed by a processor, they are used to implement the first aspect and / or various possible implementation manners of the first aspect as described above.

[0011] In a fifth aspect, an embodiment of the present application provides a computer program product, including a computer program which, when executed by a processor, implements the above first aspect and / or various possible implementation manners of the first aspect.

[0012] The method for processing design parameters of a printed circuit board, an electronic device, a storage medium, and a program product provided by the embodiments of the present application, in response to a selection operation on a signal interconnection object in a layout and routing diagram, determine associated nodes belonging to the same signal channel as the signal interconnection object, and output a parameter table based on the connection relationship and design parameters of the signal interconnection object and the associated nodes, that is, the parameter table includes the design parameters of the interconnection object and the associated nodes sorted according to the connection relationship; in the related art, the user manually queries the design parameters of the nodes one by one based on the layout and routing diagram, and then records the design parameters. Compared with the related art, in the embodiments of the present application, the user only needs to select the signal interconnection object, and then can automatically output the parameter table of each node on the signal channel corresponding to the signal interconnection object, avoiding the situation of introducing errors due to manual participation, greatly simplifying the operation, and effectively improving the efficiency and accuracy of outputting the design parameters of each node on the signal channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application.

[0014] Figure 1 It is a schematic diagram of the scenario of the method for processing design parameters of a printed circuit board provided by the present application;

[0015] Figure 2 It is a flowchart of the method for processing design parameters of a printed circuit board provided by the present application Figure 1 ;

[0016] Figure 3 It is a schematic diagram of each node of a signal channel in a layout and routing diagram provided by the present application;

[0017] Figure 4 It is a schematic diagram of the generated signal channel diagram provided by the present application;

[0018] Figure 5 It is a flowchart of the method for processing design parameters of a printed circuit board provided by the present application Figure 2 ;

[0019] Figure 6 It is a schematic diagram of the structure of the device for processing design parameters of a printed circuit board provided by the present application;

[0020] Figure 7 It is a schematic diagram of the structure of the electronic device provided by the present application.

[0021] Through the above-mentioned drawings, specific embodiments of the present application have been shown, and will be described in more detail hereinafter. These drawings and the written description are not intended to limit the scope of the concept of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by reference to specific embodiments. Detailed Description of the Embodiments

[0022] Here, exemplary embodiments will be described in detail, and examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0023] The method for processing design parameters of a printed circuit board provided by an embodiment of the present application can be applied to an application environment as Figure 1 shown. Among them, the terminal 102 communicates with the server 104 through a network. The data storage system can store the data that the server 104 needs to process. The data storage system can be integrated on the server 104, or can be placed in the cloud or on other network servers.

[0024] For example, the terminal 102 can design a printed circuit board through a relevant application program to obtain a layout and wiring diagram of the printed circuit board. The terminal 102 can also obtain the layout and wiring diagram of the printed circuit board from the server 104. The terminal 102 determines, among the nodes of the layout and wiring diagram, the associated nodes that belong to the same signal channel as the signal interconnection object in response to a selection operation on the signal interconnection object in the layout and wiring diagram. The terminal 102 outputs a parameter table based on the connection relationship and design parameters of the signal interconnection object and the associated nodes.

[0025] Among them, the terminal 102 can be, but is not limited to, various personal computers, laptop computers, smart phones, tablet computers, Internet of Things devices, and portable wearable devices. The Internet of Things devices can be smart speakers, smart TVs, smart air conditioners, smart vehicle-mounted devices, etc. The portable wearable devices can be smart watches, smart bracelets, head-mounted devices, etc. The server 104 can be implemented by an independent server or a server cluster composed of multiple servers.

[0026] Next, specific embodiments will be used to describe in detail the technical solution of the present application and how the technical solution of the present application solves the above technical problems. The following several specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. Next, embodiments of the present application will be described with reference to the drawings.

[0027] Figure 2Flow schematic of the method for processing design parameters of a printed circuit board provided in this application Figure 1 , the method for processing the design parameters of a printed circuit board is executed by the terminal in Figure 1 , or can be executed in cooperation with the terminal and the server in Figure 1 . Taking the execution of the method for processing the design parameters of a printed circuit board by the terminal as an example for illustration; as Figure 2 shown, the method for processing the design parameters of a printed circuit board includes:

[0028] S201. In response to a selection operation on a signal interconnection object in the layout and routing diagram, determine, among the nodes in the layout and routing diagram, the associated nodes that belong to the same signal channel as the signal interconnection object; the associated nodes are determined based on the relationship information of the nodes and the signal interconnection object.

[0029] Among them, a printed circuit board (PCB) is a physical carrier of surface-mounted electronic devices.

[0030] The layout and routing diagram is obtained through PCB design and is often called layout; the layout and routing diagram is a graphical representation obtained through PCB design and can display the positions of surface-mounted devices, transmission lines, vias, PCB layers, etc.

[0031] The signal interconnection object includes a target signal network and an initial node; the target signal network is one of multiple signal networks of the PCB; the signal network can represent the signals transmitted by surface-mounted devices in the PCB and can thus also be used to determine the connection relationship between surface-mounted devices; the signal networks of the PCB can include power supply type signals net, ground signals net, control signals net, analog signals net, etc.; the initial node can include at least one of surface-mounted devices, transmission lines, and vias.

[0032] The signal channel can represent the transmission link of signals in the PCB. The transmission link is composed of surface-mounted devices, transmission lines, and vias, and each node in the transmission link belongs to the same signal network.

[0033] The associated nodes and the initial nodes belong to the signal channel corresponding to the target signal network, and the associated nodes are directly or indirectly connected to the initial nodes.

[0034] In practical applications, the layout and routing diagram is displayed through the relevant application program of the PCB, and then the layout and routing diagram can be displayed in the relevant application program of the PCB, and a selection operation is performed on the signal interconnection object in the layout and routing diagram.

[0035] Among them, the relationship information of the nodes can represent the connection relationship of the nodes; based on the relationship information of the nodes, other nodes connected to this node can be determined.

[0036] Specifically, the user performs a selection operation on the signal interconnection object in the layout and wiring diagram. In response to this selection operation, the terminal obtains the relationship information of the nodes in the layout and wiring diagram, and determines the associated nodes belonging to the same signal channel as the initial node according to the relationship information of the nodes and the target signal network.

[0037] Among them, the user can click on the signal interconnection object, or select the signal interconnection object by drawing a box around it, or enter the identifier of the signal interconnection object in the selection command line to perform the selection operation on the signal interconnection object.

[0038] Optionally, obtain the relationship information of the initial node, determine the nodes that are connected to the initial node and whose signal network is the target signal network according to the relationship information, and then continue to select the nodes whose signal network is the target signal network according to the relationship information of the selected nodes until the end selection condition is reached, and take the selected nodes as the associated nodes.

[0039] When the initial node includes a first node and a second node, it can start from the first node, determine the nodes that are connected to the first node and whose signal network is the target signal network according to the relationship information of the first node, and then continue to select the nodes whose signal network is the target signal network according to the relationship information of the selected nodes until the selected node is the second node, that is, the end selection condition is reached. It can be understood that the initial node includes the first node and the second node, that is, the user wants to know the design parameter situation of the signal channel between the first node and the second node.

[0040] When the initial node includes a third node, start from the third node, determine the nodes that are directly or indirectly connected to the third node and whose signal network is the target signal network until the unselected nodes cannot be determined according to the relationship information of the selected nodes, that is, the end selection condition is reached. It can be understood that the initial node includes the third node, that is, the user wants to know the design parameter situation of the signal channel where the third node is located.

[0041] Optionally, before S201, the design parameter processing method of the printed circuit board further includes: when the layout and wiring diagram of the printed circuit board is displayed on the current interface, in response to the script running instruction, activate the parameter processing script; correspondingly, among the nodes of the layout and wiring diagram, determining the associated nodes belonging to the same signal channel as the signal interconnection object includes: determining the associated nodes belonging to the same signal channel as the signal interconnection object through the parameter processing script among the nodes of the layout and wiring diagram.

[0042] Among them, the current interface is an interface of a relevant application program of the PCB, which can be a design interface or a simulation interface; the design interface is the interface for PCB design in the relevant application program of the PCB. Correspondingly, the relevant application program can be an application program for PCB design; the simulation interface is the interface for simulating and testing the PCB in the relevant application program of the PCB. Correspondingly, the relevant application program can be an application program for simulating and testing the PCB; the relevant application program can also integrate design and simulation functions, which is an application program for designing the PCB and simulating and testing the PCB; the embodiments of the present application do not specifically limit the relevant application program of the PCB.

[0043] The parameter processing script is a custom script; the custom script can expand the functions of the relevant application program, perform customized operations, and achieve complex tasks that cannot be completed by the native application program; in the embodiments of the present application, the parameter processing script is used to output the design parameters of the nodes in the signal channels of the PCB. It should be noted that the parameter processing script of the embodiments of the present application has been installed in the relevant application program of the PCB, and the parameter processing script can be directly called when using the relevant application program of the PCB.

[0044] The script running instruction is used to call the parameter processing script; in actual applications, the script running instruction can be initiated by a predefined shortcut key. For example, a mapping relationship between the shortcut key "F12" and the script running instruction is pre-established, and when it is detected that the shortcut key "F12" is triggered, the script running instruction is initiated; the script running instruction can also be initiated by a custom menu item. For example, a custom menu item is added to the parameter processing script in advance, and when it is detected that the menu control corresponding to the custom menu item is triggered, the script running instruction is initiated.

[0045] Specifically, when the layout and wiring diagram of the PCB is displayed on the current interface, the user triggers the shortcut key or the menu control, and the terminal initiates the script running instruction in response to the trigger operation. In response to the script running instruction, the parameter processing script is activated; it should be noted that activating the parameter processing script makes the objects in the layout and wiring diagram in a selectable state, so as to facilitate subsequent selection operations.

[0046] Specifically, after the parameter processing script is activated, the signal interconnection objects in the layout and wiring diagram of the printed circuit board displayed on the current interface are in a selectable state; the user performs a selection operation on the signal interconnection objects in the layout and wiring diagram, and the terminal, in response to the selection operation, determines, among the nodes in the layout and wiring diagram, the associated nodes that belong to the same signal channel as the signal interconnection objects through the parameter processing script.

[0047] Optionally, after activating the parameter processing script, a parameter processing window is displayed in the current interface by the activated parameter processing script. In response to a selection operation on a signal interconnection object in the layout wiring diagram, the selected signal interconnection object is displayed in the parameter processing window. After determining the associated nodes through the parameter processing script, the signal interconnection object and the associated nodes are displayed in the parameter processing window.

[0048] S202, output a parameter table based on the connection relationship and design parameters of the signal interconnection object and the associated nodes.

[0049] Among them, the design parameters may include but are not limited to: the pin pitch of surface mount devices, the aperture of vias, the pad diameter, the anti-pad diameter, the line width, line length, and copper thickness of transmission lines.

[0050] Among them, the parameter table includes the design parameters of the signal interconnection object and the associated nodes, and the order of the design parameters in the parameter table is determined according to the connection relationship between the signal interconnection object and the associated nodes.

[0051] Specifically, determine the connection relationship between the initial node and the associated node in the signal interconnection object, determine the respective serial numbers of the initial node and the associated node according to the connection relationship, sequentially obtain the design parameters of the initial node and the associated node based on the serial numbers, and each time a design parameter is obtained, write the design parameter into the parameter table. In this way, the design parameters of the initial node and the associated node can be written into the parameter table in the order of the serial numbers. After writing the design parameters of the initial node and the associated node into the parameter table, output the parameter table.

[0052] In practical applications, a parameter table can be output based on the connection relationship and design parameters of the signal interconnection object and the associated nodes through the parameter processing script.

[0053] The design parameter processing method for a printed circuit board provided by an embodiment of the present application, in response to a selection operation on a signal interconnection object in the layout wiring diagram, determines the associated nodes belonging to the same signal channel as the signal interconnection object, and outputs a parameter table based on the connection relationship and design parameters of the signal interconnection object and the associated nodes, that is, the parameter table includes the design parameters of the interconnection object and the associated nodes sorted according to the connection relationship; in the related art, the user manually queries the design parameters of the nodes one by one based on the layout wiring diagram and then records the design parameters. Compared with the related art, in the embodiment of the present application, the user only needs to select the signal interconnection object, and then the parameter table of each node on the signal channel corresponding to the signal interconnection object can be automatically output, avoiding the situation of introducing errors by manual participation, greatly simplifying the operation, and effectively improving the efficiency and accuracy of outputting the design parameters of each node on the signal channel.

[0054] In a possible implementation, the signal interconnection object includes a target signal network and an initial node; among the nodes of the layout and routing diagram, determining an associated node that belongs to the same signal channel as the signal interconnection object includes: when the initial node belongs to the target signal network, based on the relationship information of the nodes in the layout and routing diagram, determining at least one node link to which the initial node belongs; based on the target signal network, determining an associated node that belongs to the same signal channel as the initial node in the node link.

[0055] Among them, the relationship information of the nodes includes the relationship information of each node in the layout and routing diagram; the relationship information of the nodes includes a first connection identifier and a second connection identifier, respectively representing both ends of the node; when the first connection identifier of one node is the same as the second connection identifier of another node, it can be determined that the two nodes are connected, and the two nodes belong to one node link; for example, the relationship information of node a1 is (L3, L4), the relationship information of node a2 is (L4, L5), and node a1 and node a2 are connected and belong to one node link.

[0056] Specifically, the signal interconnection object includes a target signal network and an initial node. For the selection operation of the signal interconnection object, the user can click on the target signal network and the initial node in sequence to obtain the signal network of the initial node. If the signal network is the target signal network, it is determined that the initial node belongs to the target signal network; if the signal network is not the target signal network, it is determined that the initial node does not belong to the target signal network.

[0057] Optionally, when the initial node does not belong to the target signal network, an error prompt is displayed on the current page. The error prompt is used to indicate that the initial node does not belong to the target signal network and prompts the user to select again.

[0058] When the initial node belongs to the target signal network, obtain the relationship information of each node in the layout and routing diagram, and determine at least one node link to which the initial node belongs according to the relationship information of each node.

[0059] Specifically, take the initial node as the starting node, obtain the relationship information of the starting node, based on the relationship information of the starting node and the relationship information of other nodes, select candidate nodes connected to the starting node among other nodes, take the candidate nodes as the starting node, and return to continue executing the step of obtaining the relationship information of the starting node until no candidate nodes connected to the starting node can be obtained. According to the starting node and the obtained candidate nodes, determine at least one node link to which the initial node belongs; determine an associated node that belongs to the same signal channel as the initial node in the at least one node link.

[0060] In practical applications, it is possible to determine whether the initial node belongs to the target signal network through a parameter processing script, determine at least one node link to which the initial node belongs according to the relationship information of the nodes in the layout and wiring diagram, and determine the associated nodes that belong to the same signal channel as the initial node in the node link based on the target signal network.

[0061] Optionally, the initial node includes a first initial node and a second initial node; determining the associated nodes that belong to the same signal channel as the initial node in the node link based on the target signal network includes: selecting a target link in the node link according to the target signal network; taking the nodes between the first initial node and the second initial node in the target link as the associated nodes that belong to the same signal channel as the initial node.

[0062] It should be noted that the initial node includes a first initial node and a second initial node, that is, the user selects the first initial node and the second initial node in the layout and wiring diagram. The user's intention is to output the design parameters of each node on the signal path from the first initial node to the second initial node and belonging to the target signal network; the associated nodes are the nodes between the first initial node and the second initial node in the target link.

[0063] Specifically, for each node link, if each node in the node link belongs to the target signal network, then take this node link as the target link, and take the nodes between the first initial node and the second initial node in the target link as the associated nodes.

[0064] Optionally, the initial node includes a third initial node; determining the associated nodes that belong to the same signal channel as the initial node in the node link based on the target signal network includes: selecting a target link in the node link according to the target signal network; taking the nodes other than the third initial node in the target link as the associated nodes.

[0065] It should be noted that the user selects the third initial node in the layout and wiring diagram. The user's intention is to output the design parameters of each node on the signal path where the third initial node is located and belongs to the target signal network; the associated nodes are the nodes other than the third initial node in the target link.

[0066] In the above embodiments, according to the target signal network and the initial node, the associated nodes that are in the same signal channel as the initial node can be quickly determined. This process does not require manual participation, improving the processing efficiency of the design parameters.

[0067] In a possible implementation, the signal interconnection object includes an initial node; a parameter table is output based on the connection relationship and design parameters of the signal interconnection object and the associated nodes, including: determining the sequence identifiers of the initial node and the associated nodes based on the relationship information between the initial node and the associated nodes; traversing the initial node and the associated nodes to obtain the nodes to be processed based on the sequence identifiers; obtaining the design parameters of the nodes to be processed, and writing the design parameters of the nodes to be processed and the corresponding sequence identifiers into the parameter table; and outputting the parameter table when the traversal of the initial node and the associated nodes is completed.

[0068] Wherein, the relationship information includes the first connection identifier and the second connection identifier of the nodes; when two nodes are connected, the first connection identifier of the first node among the two nodes is the same as the second connection identifier of the second node among the two nodes.

[0069] The sequence identifier is used to represent the position of the node in the signal channel.

[0070] Optionally, when the initial node includes a first initial node and a second initial node, the first initial node selected by the user for the first time is used as the starting node, and the second initial node selected by the user for the second time is used as the ending node. Furthermore, the sequence identifier of the first initial node is the first one, and the sequence identifier of the second initial node is the last one.

[0071] Exemplarily, if the user first selects device A as the first initial node and then selects device Z as the second initial node, the signal channel is in the order from device A to device Z.

[0072] Optionally, when the initial node includes a third initial node, the sequence identifier of the signal channel can be determined according to the default order, and the default order can be the order in which the signal flows in the signal channel.

[0073] Specifically, the first connection identifier and the second connection identifier of the initial node and the associated nodes are obtained, and the sequence identifiers of the initial node and the associated nodes in the signal channel are determined according to the first connection identifier and the second connection identifier of the initial node and the associated nodes respectively.

[0074] Exemplarily, the initial node and the associated nodes include: node x1, node x2, node x3, and node x4. The relationship information of node x1 is: (TOP, L1), the relationship information of node x2 is: (L3, L9), the relationship information of node x3 is (L1, L4), and the relationship information of node x4 is (L4, L3). It can be determined that the sequence identifier of node x1 is 1, the sequence identifier of node x3 is 2, the sequence identifier of node x4 is 3, and the sequence identifier of node x2 is 4.

[0075] After determining the sequence identifiers of the initial node and the associated nodes, in ascending order of the sequence identifiers, traverse the initial node and the associated nodes to obtain the nodes to be processed, acquire the design parameters of the nodes to be processed, and write the design parameters and the sequence identifiers of the nodes to be processed into the parameter table.

[0076] The parameter table includes multiple rows of cells. The row number corresponding to the node to be processed can be determined according to the sequence identifier, and the design parameters and the sequence identifier are written into the cells of the row corresponding to the row number.

[0077] After writing the design parameters and the sequence identifier of the node to be processed obtained from the current traversal into the parameter table, mark the node to be processed obtained from the current traversal as the processed state; continue to traverse the nodes to be processed in the initial nodes and associated nodes that are not marked as the processed state in ascending order of the sequence identifier until all the initial nodes and associated nodes are marked as the processed state, that is, the design parameters of the initial nodes and associated nodes are completed, and then output the parameter table; the output parameter table includes the design parameters of the associated nodes of the initial node, and the initial node and the associated nodes are arranged according to the sequence identifier.

[0078] In practical applications, a parameter processing script can be used to determine the sequence identifiers of the initial node and the associated nodes based on the relationship information between the initial node and the associated nodes, traverse the initial node and the associated nodes based on the sequence identifiers to obtain the nodes to be processed, acquire the design parameters of the nodes to be processed, and write the design parameters and the corresponding sequence identifiers of the nodes to be processed into the parameter table; when the traversal of the initial node and the associated nodes is completed, output the parameter table.

[0079] In the above embodiment, according to the relationship information between the initial node and the associated nodes, determine the sequence identifier, obtain the design parameters according to the sequence identifier, write the design parameters and the sequence identifier into the parameter table, and then the sequence of the initial node and the associated nodes in the signal channel can be determined through the parameter table, improving the quality of the parameter table.

[0080] In a possible implementation manner, acquiring the design parameters of the node to be processed includes: when the node to be processed is a surface mount device, acquiring the layer information, width, and thickness of the surface mount device; when the node to be processed is a transmission line, acquiring the layer information, width, length, and thickness of the transmission line to obtain the design parameters of the node to be processed; when the node to be processed is a via, acquiring the layer information, thickness, aperture diameter, and pad diameter of the via to obtain the design parameters of the node to be processed.

[0081] Among them, the layer information of the surface mount device represents the PCB layer where the surface mount device is located; the layer information of the node can also represent the connection relationship of the node; the width of the surface mount device is the width of the surface mount device body or the pin, and the thickness of the surface mount device is the height of the surface mount device in the vertical direction.

[0082] The layer information of the transmission line represents the PCB layer where the transmission line is located, the width of the transmission line is the line width, the length of the transmission line is the line length, and the thickness of the transmission line is the line thickness.

[0083] The layer information of the via represents the PCB layer where the via is located, the thickness of the via is the dimension in the vertical direction of the via, the aperture of the via is the diameter of the via, and the pad diameter is the outer diameter of the circular pad around the via.

[0084] Optionally, the design parameters of the surface mount device further include type; the design parameters of the transmission line further include type, and the design parameters of the via further include type.

[0085] The above-mentioned nodes to be processed and the corresponding design parameters are only examples. In actual applications, the nodes to be processed can also be of other types, and the design parameters can also have other parameters. For example, the design parameters of the via can also include the anti-pad diameter.

[0086] Exemplarily, the signal channel is as follows: from the pad of the surface mount device A on the TOP layer, drill a blind via B from the first layer to the third layer, lay a section of strip transmission line C on the third layer, pass through the buried via D to the fourth layer, lay a section of strip transmission line E on the fourth layer, pass through the buried via F to the ninth layer, lay a section of strip transmission line G on the ninth layer, and then connect to the pad Z of the surface mount connector on the BOTTOM layer through the blind via H.

[0087] The initial nodes include the surface mount device A and the surface mount device Z. Furthermore, the signal channel from the surface mount device A to the surface mount device Z includes the nodes: surface mount device A, via B, transmission line C, via D, transmission line E, via F, transmission line G, via H, surface mount device Z. The nodes of the signal channel in the layout and routing diagram are as Figure 3 shown; obtain the design parameters of each node in the signal channel from the surface mount device A to the surface mount device Z, determine the sequence identifier of each node, write the design parameters and sequence identifier of each node into the parameter table, and obtain the parameter table as shown in Table 1.

[0088] Table 1

[0089]

[0090] In the above embodiment, the design parameters of the surface mount device, the transmission line, and the via can be quickly obtained, improving the processing efficiency of the design parameters.

[0091] In a possible implementation manner, the design parameter processing method of the printed circuit board further includes: in response to a display instruction for the parameter table, generate a signal channel diagram according to the parameter table, and display the signal channel diagram on the display sub-page.

[0092] Optionally, a layout and routing diagram is displayed in the current interface (design interface or simulation interface). The current interface includes a signal channel display control. When the user triggers the signal channel display control, the terminal responds to the trigger operation for the signal channel display control, displays a data selection window, selects a parameter table through the data selection window, initiates a display instruction for the parameter table in response to the confirmation operation triggered in the data selection window, obtains the sequence identifiers and design parameters of each node in the parameter table through a parameter processing script, compiles the sequence identifiers and design parameters of each node into a simulation language, and runs the simulation language through an electronic design plugin to display a signal channel diagram on a display sub-page; the display sub-page can be displayed on top of the current interface.

[0093] Exemplarily, the signal channel from surface mount device A to surface mount device Z includes nodes: surface mount device A, via B, transmission line C, via D, transmission line E, via F, transmission line G, via H, surface mount device Z. According to the parameter table corresponding to the signal channel from surface mount device A to surface mount device Z, the generated signal channel diagram is as Figure 4 shown; the generated signal channel diagram may further include the design parameters of each node ( Figure 4 not shown). In this way, the design parameter situation of each node can be intuitively understood through the signal channel diagram.

[0094] In the above embodiment, the signal channel diagram is displayed through the parameter table, and the design parameter situation of each node in the signal channel diagram can be intuitively understood, improving the convenience of design parameter processing.

[0095] In a possible implementation manner, the method for processing design parameters of a printed circuit board further includes: responding to a modification operation on the parameter table to determine a target parameter table; the target parameter table includes target nodes and target design parameters of the target nodes; responding to an import operation on the target parameter table, constructing a target signal channel based on the target nodes and target design parameters; selecting a signal channel to be processed corresponding to the target nodes in the layout and routing diagram, and replacing the signal channel to be processed with the target signal channel to obtain a modified layout and routing diagram; responding to a simulation test instruction, performing a simulation test on the modified layout and routing diagram.

[0096] Among them, the modification operation on the parameter table includes, but is not limited to: deletion operation, addition operation, and replacement operation; exemplarily, the user can change the aperture of a certain via in the parameter table, modify the line width of a certain transmission line, add a via in a certain cross-layer transmission line, etc.

[0097] The target nodes included in the target parameter table include at least part of the initial nodes and associated nodes; the target design parameters are the design parameters of the target nodes.

[0098] The signal channel to be processed is the signal channel to which the interconnection object and the associated node belong.

[0099] Specifically, after the user modifies the parameter table, a target parameter table is obtained, and the target parameter table can be saved at the file path specified by the user.

[0100] Optionally, a layout wiring diagram is displayed in the simulation interface. The simulation interface includes a synchronous modification control. The user can trigger the synchronous modification control. The terminal responds to the trigger operation for the synchronous modification control and displays an import sub-page in the simulation interface. The target parameter table is selected through the import sub-page. The user triggers the confirmation control in the import sub-page, and then the import operation for the target parameter table is executed. In response to the import operation, the terminal constructs a target signal channel based on the target nodes and target design parameters included in the target parameter table through a parameter processing script, selects the signal channel to be processed corresponding to the target node in the layout wiring diagram, and replaces the signal channel to be processed with the constructed target signal channel to obtain a modified layout wiring diagram.

[0101] After obtaining the modified layout wiring diagram, a simulation test is performed on the modified layout wiring diagram in the simulation interface to obtain a simulation test result.

[0102] In one example, based on the layout wiring diagram in the design interface, according to the selected signal interconnection object, a parameter table of the selected signal channel is output, and the target parameter table is obtained by modifying the parameter table. The layout wiring diagram is displayed in the simulation interface, and the obtained target parameter table after modification is imported, so that the layout wiring diagram can be synchronously modified, and the modified layout wiring diagram is subjected to a simulation test in the simulation interface. Among them, the design interface and the simulation interface can belong to the relevant application programs of the same PCB, or the design interface belongs to the application program for designing the PCB, and the simulation interface belongs to the application program for performing simulation tests on the PCB.

[0103] In another example, based on the layout wiring diagram in the simulation interface, according to the selected signal interconnection object, a parameter table of the selected signal channel is output, and the target parameter table is obtained by modifying the parameter table. The obtained target parameter table after modification is imported, so that the layout wiring diagram can be synchronously modified, and the modified layout wiring diagram is subjected to a simulation test in the simulation interface. Among them, the simulation interface can belong to the application program that integrates the design of the PCB and performs simulation tests on the PCB, or belongs to the application program dedicated to performing simulation tests on the PCB.

[0104] It should be noted that by selecting the signal interconnection object in the layout wiring diagram, outputting the parameter table of the selected signal channel, and importing the obtained target parameter table after modifying the parameter table to synchronously modify the layout wiring diagram. After realizing the synchronous modification of the layout wiring diagram, the modified layout wiring diagram can be directly subjected to a simulation test, which improves the efficiency of PCB design and modification.

[0105] In the related art, when performing a simulation test on a layout wiring diagram to obtain test results such as S-parameters, if the test results are not good, it is difficult to determine the nodes that cause the poor test results. It is necessary to modify the design parameters of the nodes one by one according to experience and then perform a simulation test to determine whether the modified nodes are the nodes that affect the test results. In this way, a large number of modifications and simulations are required, resulting in low efficiency. In this embodiment, through a parameter table, the design parameters of a signal channel in the layout wiring diagram can be synchronously modified, and then a simulation test can be performed. It can be determined whether the modified signal channel is the signal channel that affects the test results, and the range of nodes that affect the test results can be quickly narrowed, effectively improving the simulation efficiency.

[0106] In the above embodiment, the design parameters of each node in the signal channel can be modified together to obtain a target parameter table, and the synchronous modification of the layout wiring diagram can also be realized through the target parameter table. Furthermore, the simulation test can be directly performed on the modified layout wiring diagram. In the case of batch modification of design parameters, the modification efficiency is greatly improved, and the simulation test efficiency is also improved.

[0107] Exemplarily, as Figure 5 shown, the method for processing the design parameters of a printed circuit board includes:

[0108] When the layout wiring diagram of the printed circuit board is displayed in the simulation interface of the related application program of the PCB, the terminal activates the parameter processing script in response to the script running instruction, so that the nodes in the layout wiring diagram are in a selectable state.

[0109] In response to the selection operation on the target signal network, the first initial node, and the second initial node in the layout wiring diagram, it is determined whether the first initial node and the second initial node belong to the target signal network.

[0110] When the first initial node and the second initial node do not belong to the target signal network, an error prompt is displayed.

[0111] When the first initial node and the second initial node belong to the target signal network, the terminal determines the node link to which the first initial node and the second initial node belong based on the relationship information of the nodes through the parameter processing script, and determines the target link belonging to the target signal network in the node link.

[0112] The nodes in the target link that are between the first initial node and the second initial node are used as the associated nodes belonging to the same signal channel as the first initial node and the second initial node.

[0113] According to the relationship information of the first initial node, the second initial node, and the associated nodes, the sequence identifiers of the first initial node, the second initial node, and the associated nodes are determined.

[0114] Traverse the nodes to be processed among the first initial node, the second initial node, and the associated node based on the sequential identifier.

[0115] When the node to be processed is a surface mount device, obtain the layer information, width, and thickness of the surface mount device to obtain the design parameters of the surface mount device; when the node to be processed is a transmission line, obtain the layer information, width, length, and thickness of the transmission line to obtain the design parameters of the transmission line; when the node to be processed is a via, obtain the layer information, thickness, aperture diameter, and pad diameter of the via to obtain the design parameters of the via.

[0116] According to the sequential identifier of the node to be processed, write the design parameters of the node to be processed into the parameter table, and output the parameter table when the traversal of the first initial node, the second initial node, and the associated node is completed.

[0117] Modify the parameter table to obtain a target parameter table; the target parameter table includes target nodes and target design parameters of the target nodes.

[0118] In response to an import operation for the target parameter table, construct a target signal channel according to the target nodes and target design parameters, select the signal channel to be processed corresponding to the target node in the layout and wiring diagram displayed on the simulation interface, and replace the signal channel to be processed with the target signal channel to obtain a modified layout and wiring diagram.

[0119] In response to a simulation test instruction, perform a simulation test on the modified layout and wiring diagram.

[0120] The method for processing the design parameters of a printed circuit board provided by the embodiments of the present application, in response to a selection operation for a signal interconnection object in the layout and wiring diagram, determines an associated node that belongs to the same signal channel as the signal interconnection object, and outputs a parameter table based on the connection relationship and design parameters of the signal interconnection object and the associated node, that is, the parameter table includes the design parameters of the interconnection object and the associated node sorted according to the connection relationship; in the related art, the user manually queries the design parameters of the nodes one by one based on the layout and wiring diagram, and then records the design parameters. Compared with the related art, in the embodiments of the present application, the user only needs to select the signal interconnection object, and the parameter table of each node on the signal channel corresponding to the signal interconnection object can be automatically output, avoiding the situation of introducing errors by manual participation, greatly simplifying the operation, and effectively improving the efficiency and accuracy of outputting the design parameters of each node on the signal channel.

[0121] It should be understood that although the steps in the flowcharts involved in the above embodiments are shown in sequence according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear indication in this article, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same moment, but can be executed at different moments. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.

[0122] Figure 6 FIG. is a schematic structural diagram of a printed circuit board design parameter processing device provided by the present application. As Figure 6 shown, the printed circuit board design parameter processing device 60 provided in this embodiment includes:

[0123] A node selection module 601, configured to, in response to a selection operation on a signal interconnection object in a layout and routing diagram, determine, among the nodes in the layout and routing diagram, an associated node that belongs to the same signal channel as the signal interconnection object; the associated node is determined based on the relationship information of the nodes and the signal interconnection object;

[0124] A parameter table output module 602, configured to output a parameter table based on the connection relationship and design parameters of the signal interconnection object and the associated node.

[0125] In a possible implementation manner, the signal interconnection object includes a target signal network and an initial node; the node selection module 601 is further configured to, when the initial node belongs to the target signal network, determine at least one node link to which the initial node belongs based on the relationship information of the nodes in the layout and routing diagram; and determine, based on the target signal network, an associated node that belongs to the same signal channel as the initial node in the node link.

[0126] In a possible implementation manner, the initial node includes a first initial node and a second initial node; the node selection module 601 is further configured to select a target link in the node link according to the target signal network; and use the nodes between the first initial node and the second initial node in the target link as the associated nodes that belong to the same signal channel as the initial node.

[0127] In a possible implementation, the signal interconnection object includes an initial node; the parameter table output module 602 is further configured to determine the sequence identifiers of the initial node and the associated node based on the relationship information between the initial node and the associated node; traverse the initial node and the associated node based on the sequence identifiers to obtain the nodes to be processed; obtain the design parameters of the nodes to be processed, and write the design parameters of the nodes to be processed and the corresponding sequence identifiers into the parameter table; and output the parameter table when the traversal of the initial node and the associated node is completed.

[0128] In a possible implementation, the parameter table output module 602 is further configured to, when the node to be processed is a surface mount device, obtain the layer information, width, and thickness of the surface mount device; when the node to be processed is a transmission line, obtain the layer information, width, length, and thickness of the transmission line to obtain the design parameters of the node to be processed; and when the node to be processed is a via, obtain the layer information, thickness, aperture, and pad diameter of the via to obtain the design parameters of the node to be processed.

[0129] In a possible implementation, the design parameter processing device for a printed circuit board further includes:

[0130] A parameter modification module, configured to determine a target parameter table in response to a modification operation on the parameter table; the target parameter table includes target nodes and target design parameters of the target nodes;

[0131] A parameter import module, configured to construct a target signal channel based on the target nodes and the target design parameters in response to an import operation on the target parameter table;

[0132] A synchronization modification module, configured to select a to-be-processed signal channel corresponding to the target node in the layout and routing diagram, and replace the to-be-processed signal channel with the target signal channel to obtain a modified layout and routing diagram;

[0133] A simulation module, configured to perform a simulation test on the modified layout and routing diagram in response to a simulation test instruction.

[0134] The design parameter processing device for a printed circuit board provided in this embodiment can execute the design parameter processing method for a printed circuit board provided in the above method embodiment, and its implementation principle and technical effects are similar, which will not be elaborated here in this embodiment.

[0135] Figure 7 This is a schematic structural diagram of an electronic device provided in the present application. As Figure 7 shown, the electronic device 70 provided in this embodiment includes: at least one processor 701 and a memory 702. Optionally, the device 70 further includes a communication component 703. Among them, the processor 701, the memory 702, and the communication component 703 are connected through a bus.

[0136] In a specific implementation process, at least one processor 701 executes computer-executable instructions stored in a memory 702, so that at least one processor 701 executes the above-mentioned method.

[0137] For the specific implementation process of the processor 701, reference may be made to the above method embodiments. Their implementation principles and technical effects are similar, and will not be elaborated here in this embodiment.

[0138] In the above embodiments, it should be understood that the processor may be a central processing unit (Central Processing Unit, CPU for short), or may also be other general-purpose processors, digital signal processors (Digital Signal Processor, DSP for short), application specific integrated circuits (Application Specific Integrated Circuit, ASIC for short), etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The steps of the method disclosed in combination with the invention can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules in the processor.

[0139] The memory may include a high-speed memory (Random Access Memory, RAM), and may also include a non-volatile memory (Non-volatile Memory, NVM), such as at least one disk memory.

[0140] The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, the bus in the drawings of this application is not limited to only one bus or one type of bus.

[0141] This application also provides a computer program product, including a computer program, which implements the above-mentioned method when executed by a processor.

[0142] This application also provides a computer-readable storage medium, in which computer-executable instructions are stored. When the processor executes the computer-executable instructions, the above-mentioned method is implemented.

[0143] The above-readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, a magnetic disk, or an optical disk. The readable storage medium can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0144] An exemplary readable storage medium is coupled to the processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can be located in an application specific integrated circuit (ASIC). Of course, the processor and the readable storage medium can also exist as discrete components in a device.

[0145] The division of units is only a logical function division. In actual implementation, there can be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be indirect couplings or communication connections through some interfaces, devices, or units, and can be in electrical, mechanical, or other forms.

[0146] The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0147] In addition, the functional units in each embodiment of the present invention can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit.

[0148] If a function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods of the various embodiments of the present invention. The aforementioned storage medium includes: USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs, etc., all kinds of media that can store program codes.

[0149] Those of ordinary skill in the art can understand that all or part of the steps of implementing the above method embodiments can be completed by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When this program is executed, it executes the steps including the above method embodiments; and the aforementioned storage medium includes: ROMs, RAMs, magnetic disks, or optical discs, etc., all kinds of media that can store program codes.

[0150] Finally, it should be noted that: After considering the specification and practicing the invention disclosed herein, those skilled in the art will easily think of other implementation manners of the present invention. The present invention is intended to cover any variations, uses, or adaptive changes of the present invention. These variations, uses, or adaptive changes follow the general principles of the present invention and include the common general knowledge or conventional technical means in the technical field of the present invention that are not disclosed in the present invention. It is not limited to the exact structure described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present invention is only limited by the appended claims.

Claims

1. A method for processing design parameters of a printed circuit board, characterized in that, Including: In response to a selection operation on a signal interconnection object in a layout wiring diagram, among the nodes of the layout wiring diagram, determining associated nodes that belong to the same signal channel as the signal interconnection object; The associated nodes are determined based on the relationship information of the nodes and the signal interconnection object; Outputting a parameter table based on the connection relationship and design parameters of the signal interconnection object and the associated nodes.

2. The method according to claim 1, wherein The signal interconnection object includes a target signal network and an initial node; The determining, among the nodes of the layout wiring diagram, associated nodes that belong to the same signal channel as the signal interconnection object includes: When the initial node belongs to the target signal network, based on the relationship information of the nodes in the layout wiring diagram, determining at least one node link to which the initial node belongs; Based on the target signal network, determining, in the node link, associated nodes that belong to the same signal channel as the initial node.

3. The method according to claim 2, wherein The initial node includes a first initial node and a second initial node; The determining, based on the target signal network, in the node link, associated nodes that belong to the same signal channel as the initial node includes: Selecting a target link in the node link according to the target signal network; Taking the nodes between the first initial node and the second initial node in the target link as associated nodes that belong to the same signal channel as the initial node.

4. The method according to claim 1, characterized in that, The signal interconnection object includes an initial node; The outputting a parameter table based on the connection relationship and design parameters of the signal interconnection object and the associated nodes includes: Based on the relationship information of the initial node and the associated nodes, determining the sequence identifiers of the initial node and the associated nodes; Traversing the initial node and the associated nodes based on the sequence identifiers to obtain nodes to be processed; Obtaining the design parameters of the nodes to be processed, and writing the design parameters of the nodes to be processed and the corresponding sequence identifiers into the parameter table; When the traversal of the initial node and the associated nodes is completed, outputting the parameter table.

5. The method according to claim 4, wherein The obtaining the design parameters of the nodes to be processed includes: When the node to be processed is a surface mount device, obtaining the layer information, width and thickness of the surface mount device; When the node to be processed is a transmission line, obtaining the layer information, width, length and thickness of the transmission line to obtain the design parameters of the node to be processed; When the node to be processed is a via, obtaining the layer information, thickness, aperture diameter and pad diameter of the via to obtain the design parameters of the node to be processed.

6. The method according to any one of claims 1 to 5, characterized in that, The method further includes: In response to a modification operation on the parameter table, determining a target parameter table; the target parameter table includes target nodes and the target design parameters of the target nodes; In response to an import operation on the target parameter table, constructing a target signal channel based on the target nodes and the target design parameters; Selecting, in the layout wiring diagram, the to-be-processed signal channel corresponding to the target node, and replacing the to-be-processed signal channel with the target signal channel to obtain a modified layout wiring diagram; In response to a simulation test instruction, performing a simulation test on the modified layout wiring diagram.

7. A design parameter processing device for a printed circuit board, characterized in that, The device includes: a node selection module, configured to determine, in the nodes of the layout wiring diagram, associated nodes that belong to the same signal channel as the signal interconnection object in response to a selection operation on the signal interconnection object in the layout wiring diagram; the associated nodes are determined based on the relationship information of the nodes and the signal interconnection object; a parameter table output module, configured to output a parameter table based on the connection relationship and design parameters of the signal interconnection object and the associated nodes.

8. An electronic device, characterized in that, Comprising: a processor, and a memory communicatively connected to the processor; the memory stores computer-executable instructions; the processor executes the computer-executable instructions stored in the memory to implement the method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, Computer-executable instructions are stored in the computer-readable storage medium, and when the computer-executable instructions are executed by a processor, they are used to implement the method according to any one of claims 1 to 6.

10. A computer program product, characterized in that, Comprising computer-executable instructions, and when the computer-executable instructions are executed by a processor, they implement the method according to any one of claims 1 to 6.

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