Memory device and method of operating memory device

Abstract

A memory device and a method of operating the memory device are disclosed. The memory device includes: a memory array including N + 1 resistive memory cells for each of a plurality of word lines, the N + 1 resistive memory cells having a resistance value representing a bit sequence of N bits, the resistance value being determined based on a stagnation resistance value of an error memory cell of the N + 1 resistive memory cells, the resistance values are respectively set; and a write encoder configured to generate N + 1 write signals indicating resistance values to be set for the N + 1 resistive memory cells, respectively, and N is an integer greater than or equal to 1.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2024-0003449, filed with the Korean Intellectual Property Office on January 9, 2024, and Korean Patent Application No. 10-2024-0046050, filed with the Korean Intellectual Property Office on April 4, 2024, the entire disclosures of which are hereby incorporated by reference for all purposes. Technical Field

[0002] The present disclosure relates to a memory device and a method of operating the memory device. Background Art

[0003] Semiconductor memory devices can be classified into volatile memory devices and non-volatile memory devices. Volatile memory devices lose stored data when power is interrupted, while non-volatile memory devices do not lose stored data even when power is interrupted. Volatile semiconductor memory devices can read and write quickly, but may lose stored data when the external power is turned off. In contrast, non-volatile memory devices can read and write relatively more slowly than volatile memory devices, but can retain corresponding data even when the external power is turned off. Summary of the Invention

[0004] The present invention is provided in a simplified form to introduce a selection of concepts that are further described in the detailed description below. The present invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to assist in determining the scope of the claimed subject matter.

[0005] In one general aspect, there is provided an apparatus including: a memory array including N + 1 resistive memory cells, the N + 1 resistive memory cells including resistance values representing an N-bit sequence, the resistance values being determined based on a stagnation resistance value of an error memory cell on a word line including the error memory cell, the resistance values being respectively set; and a write encoder configured to generate N + 1 write signals respectively indicating the resistance values to be set for the N + 1 resistive memory cells, and N is an integer greater than or equal to 1.

[0006] When a bit value at a bit position in the bit sequence is a first bit value, resistance values of adjacent memory elements corresponding to the bit position among the N + 1 resistive memory cells may be the same value, and when the bit value at the bit position is a second bit value, resistance values of adjacent memory elements corresponding to the bit position among the N + 1 resistive memory cells may be different values.

[0007] The write encoder may include: a plurality of exclusive OR (XOR) elements configured to generate the N+1 write signals based on the stuck resistance value and an N-bit signal respectively indicating the bit values of the bit sequence.

[0008] The write encoder may be configured to: generate, for N+1 selected resistive memory cells of a word line selected for writing, write signals for setting a resistance value combination that matches the stuck resistance value of an error memory cell among two available resistance value combinations representing the bit sequence.

[0009] The write encoder may be configured to: calculate, based on the magnitude of the stuck resistance value and the position of the error memory cell in the word line, the resistance value combination to be set for the N+1 resistive memory cells.

[0010] The write encoder may include: a first XOR element and a second XOR element, the first XOR element being configured to generate a write signal based on the stuck resistance value and the bit sequence, and the second XOR element being configured to generate an inverted write signal in response to the value of the write signal corresponding to the error memory cell among the write signals being a value different from the stuck resistance value, the inverted write signal being inverted from the write signal.

[0011] The second XOR element may be configured to: pass the write signal in response to the value of the write signal corresponding to the error memory cell among the write signals being a value the same as the stuck resistance value.

[0012] The device may include: a reference write circuit configured to set, for resistive memory cells of a memory array, a resistance value of a first resistance state corresponding to a first bit value; determine, as error memory cells, resistive memory cells among the resistive memory cells corresponding to a part of the resistive memory cells from which a second bit value is read; and manage the error memory cells as having a resistance value of a second resistance state.

[0013] The write encoder may further be configured to: record, in an error message, the value of the word line indicating the location of the error memory cell, the value of the column line indicating the location of the error memory cell, and the stuck resistance value of the error memory cell.

[0014] The write encoder may further be configured to: periodically update the error message for a plurality of resistive memory cells of the memory array using a first result of setting and reading a resistance value of a first resistance state and a second result of setting and reading a resistance value of a second resistance state.

[0015] The device may include a plurality of word lines including the word lines, and the column lines where the first error memory cells of the first word line among the plurality of word lines are located and the column lines where the second error memory cells of the second word line among the plurality of word lines are located are at different positions.

[0016] The device may include: a read circuit configured to generate a bit read signal based on a result of an XOR performed on resistance values, the resistance values being set for the N + 1 resistive memory cells arranged along the word line selected for reading.

[0017] The read circuit may include: an XOR element connected to two adjacent resistive memory cells among the N + 1 resistive memory cells.

[0018] The read circuit may be configured to: output, as a bit value for the two adjacent resistive memory cells, a result of comparing the delays occurring in the two adjacent resistive memory cells based on the resistance values and parasitic capacitances set for the two adjacent resistive memory cells among the N + 1 resistive memory cells.

[0019] In one general aspect, there is provided a processor-implemented method, the method including: generating N + 1 write signals respectively indicating N + 1 resistance values representing an N-bit sequence, the N + 1 resistance values being determined based on the stagnant resistance values of error memory cells on a word line of a memory array including error memory cells; and setting the resistance values respectively according to the N + 1 write signals for the N + 1 resistive memory cells.

[0020] The step of generating the N + 1 write signals may include: generating the N + 1 write signals based on N-bit signals respectively indicating the bit values of the bit sequence and the stagnant resistance values, and N may be an integer greater than or equal to 1.

[0021] The step of generating the N + 1 write signals may include: generating a write signal indicating a resistance value combination that matches the stagnant resistance value of an error memory cell among two available resistance value combinations representing the bit sequence.

[0022] The step of generating the N + 1 write signals may include: inverting the write signal in response to a value of an error write signal corresponding to an error memory cell among the write signals being a different value from the stagnant resistance value.

[0023] The method may include: setting a resistance value of a first resistance state corresponding to a first bit value for a resistive memory cell of a memory array; determining, as error memory cells, resistive memory cells corresponding to a part of the resistive memory cells from which a second bit value is read; and managing the error memory cells as having a resistance value of a second resistance state.

[0024] The method may include: generating an N-bit read signal based on a result of an exclusive OR (XOR) operation performed on resistance values, the resistance values being set for the N + 1 resistive memory cells arranged along a selected word line for reading.

[0025] In one general aspect, there is provided a processor-implemented method, the method including: selecting, from among N + 1 memory cells connected to a word line, one memory cell having a reference resistance value among the N + 1 memory cells; in response to a bit value at a position represented by resistance values of the selected one memory cell and an adjacent memory cell among the N bits being a first value, setting the resistance value of the adjacent memory cell to the reference resistance value; and in response to the bit value at the position represented by the resistance values of the selected one memory cell and the adjacent memory cell among the N bits being a second value different from the first value, setting the resistance value of the adjacent memory cell to a value different from the reference resistance value.

[0026] The exclusive OR (XOR) operation may be performed in response to the first value being zero (0) and the second value being 1.

[0027] The exclusive NOR (XNOR) operation may be performed in response to the first value being 1 and the second value being 0.

[0028] N may be an integer greater than or equal to 2, and when the bit value at the position is 0, the resistance values of two adjacent memory cells representing the bit value at the position are the same value, and when the bit value at the position is 1, the resistance values of two adjacent memory cells representing the bit value at the position are different values.

[0029] N may be an integer greater than or equal to 2, and when the bit value at the position is 0, the resistance values of two adjacent memory cells representing the bit value at the position are different values, and when the bit value at the position is 1, the resistance values of two adjacent memory cells representing the bit value at the position are the same value.

[0030] The selected one memory cell may be an error memory cell, the reference resistance value may be a stagnant resistance value of the error memory cell, and N may be an integer greater than or equal to 1.

[0031] In a memory device including a plurality of word lines, the column positions of the defective memory cells of at least two word lines may be different.

[0032] Other features and aspects will be apparent from the following detailed description, the drawings, and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 Illustrates an example memory device in accordance with one or more embodiments.

[0034] Figure 2 Illustrates a memory device in accordance with one or more embodiments.

[0035] Figure 3 Illustrates an example method of operating a memory device in accordance with one or more embodiments.

[0036] Figure 4 Illustrates an example method of a read operation of a memory device in accordance with one or more embodiments.

[0037] Figure 5 Illustrates an example bit sequence using combinations of resistance values in a memory device in accordance with one or more embodiments.

[0038] Figure 6 Illustrates an example read operation method in accordance with one or more embodiments.

[0039] Figure 7A and Figure 7B Illustrates an example read operation performed by a read circuit in a memory device in accordance with one or more embodiments.

[0040] Figure 8 Illustrates an example method of setting a resistance value in accordance with one or more embodiments.

[0041] Figure 9 and Figure 10 Illustrates an example setting operation based on the resistance values of defective memory cells performed by a memory device in accordance with one or more embodiments.

[0042] Figure 11 、 Figure 12A and Figure 12B Illustrates an example circuit of a write encoder referring to defective memory cells in a memory device in accordance with one or more embodiments.

[0043] Figure 13 Illustrates an example method of generating error information in accordance with one or more embodiments.

[0044] Figures 14 to 16 Illustrates an example of generating error information in accordance with one or more embodiments.

[0045] Throughout the drawings and the detailed description, unless otherwise described or provided, the same reference numerals can be understood to refer to the same or similar elements, features, and structures. The drawings may not be to scale, and for clarity, illustration, and convenience, the relative sizes, proportions, and depictions of elements in the drawings may be exaggerated. Detailed Description

[0046] The following detailed description is provided to assist the reader in obtaining a comprehensive understanding of the methods, devices, and / or systems described herein. However, various changes, modifications, and equivalents of the methods, devices, and / or systems described herein will be apparent after understanding the disclosure of this application. For example, the sequences of operations within the operations described herein and / or the sequences of operations are merely examples and are not limited to those set forth herein, but rather can be changed as will be apparent after understanding the disclosure of this application, except for the sequences of operations within the operations and / or the sequences of operations that must occur in a particular order. As another example, the sequences of operations and / or the sequences of operations within the operations can be performed in parallel, except for at least a portion of the sequences of operations within the operations and / or the sequences of operations that must occur in a sequence (e.g., a particular order). Additionally, for greater clarity and conciseness, descriptions of features known after understanding the disclosure of this application may be omitted.

[0047] The features described herein can be implemented in different forms and should not be construed as limited to the examples described herein. Instead, the examples described herein are provided only to illustrate some of the many possible ways of implementing the methods, devices, and / or systems described herein that will be apparent after understanding the disclosure of this application.

[0048] Throughout the specification, when a component or element is described as being "on", "connected to", "coupled to", or "joined to" another component, element, or layer, it can be directly (e.g., in contact with another component or element) "on" another component, element, or layer, directly (e.g., in contact with another component or element) "connected to", "coupled to", or "joined to" another component, element, or layer, or one or more other components, elements, layers may reasonably be present therebetween. When a component or element is described as being "directly on" another component or element, "directly connected to", "directly coupled to", or "directly joined to" another component or element, no other components or elements may be present therebetween. Similarly, expressions such as "between" and "immediately between" and "adjacent to" and "immediately adjacent to" can be interpreted as previously described.

[0049] Although terms such as "first", "second", and "third" or A, B, (a), (b), etc. may be used herein to describe various components, elements, regions, layers, or parts, these components, elements, regions, layers, or parts are not limited by these terms. For example, each of these terms is not used to define, for example, the nature, order, or sequence of the corresponding component, element, region, layer, or part, but is only used to distinguish the corresponding component, element, region, layer, or part from other components, elements, regions, layers, or parts. Thus, a first component, first element, first region, first layer, or first part as referred to in the examples described herein may also be referred to as a second component, second element, second region, second layer, or second part without departing from the teachings of the examples.

[0050] The terms used herein are for the purpose of describing various examples only and are not intended to limit the disclosure. Unless the context clearly indicates otherwise, the singular forms are intended to include the plural forms as well. As a non-limiting example, the terms "comprising", "including", and "having" indicate the presence of the stated features, quantities, operations, components, elements, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, quantities, operations, components, elements, and / or combinations thereof, or alternatively the presence of alternative stated features, quantities, operations, components, elements, and / or combinations thereof. Additionally, while one embodiment may state that the terms "comprising", "including", and "having" indicate the presence of the stated features, quantities, operations, components, elements, and / or combinations thereof, there may be other embodiments in which one or more of the stated features, quantities, operations, components, elements, and / or combinations thereof are absent.

[0051] As used herein, the term "and / or" includes any one of the related listed items and any combination of any two or more thereof. Unless the corresponding description and examples require such a list (e.g., "at least one of A, B, and C") to be interpreted as having a conjunctive meaning, the phrases "at least one of A, B, and C", "at least one of A, B, or C", etc. are intended to have a disjunctive meaning, and these phrases "at least one of A, B, and C", "at least one of A, B, or C", etc. also include examples in which there may be one or more of each of A, B, and / or C (e.g., any combination of one or more of each of A, B, and C).

[0052] Due to manufacturing techniques and / or tolerances, variations in the shapes shown in the figures may occur. Thus, the examples described herein are not limited to the specific shapes shown in the figures but include shape changes that occur during manufacturing.

[0053] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains and based on the understanding of the disclosure of this application. Unless explicitly defined as such herein, terms (such as those defined in common dictionaries) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the disclosure of this application, and shall not be interpreted in an idealized or overly formal sense. The use of the term "may" herein with respect to an example or embodiment (e.g., with respect to what an example or embodiment may include or implement) indicates that there is at least one example or embodiment that includes or implements such a feature, and all examples are not limited thereto.

[0054] Figure 1 Illustrates an example memory device according to one or more embodiments.

[0055] Referring to Figure 1 , in a non-limiting example, the non-volatile memory device 100 may include a memory array 110. Here, an electronic device (such as the non-volatile memory device 100) represents one or more processors, or one or more processors and a memory storing instructions, the instructions being configured to implement one or more or any combination of the operations or methods described herein. The one or more processors may be corresponding dedicated hardware-based computers or other dedicated hardware. The one or more processors may be configured to execute such instructions. The one or more memories may store instructions that, when executed by the one or more processors, configure the one or more processors to execute one or more or any combination of the operations of the methods described herein.

[0056] In one example, the memory array 110 may include a plurality of resistive memory cells. The plurality of resistive memory cells may be arranged along lines. For example, the plurality of resistive memory cells may be arranged along a plurality of word lines and a plurality of column lines. Here, the word lines may also be referred to as row lines.

[0057] The memory array 110 may have N + 1 resistive memory cells 111 representing an N-bit sequence for each word line. Here, N may be an integer greater than or equal to 2, and the bit sequence may represent a sequence of multiple bit values. In this disclosure, a bit sequence including N bit values (i.e., an N-bit sequence) is described as an example. The combination of N + 1 resistance values respectively set for the N + 1 resistive memory cells 111 corresponding to one of the word lines may correspond to the N-bit sequence. Here, for simplicity, the combination of resistance values may also be referred to as a resistance value combination. As Figure 1As shown, the first to the N+1 resistive memory cells may be arranged along the same word line. The N+1 resistance values may be based on the result of encoding an N-bit sequence. The encoding may be, for example, XOR-based encoding. The mapping relationship between the resistance value combinations and the bit sequences will be described in more detail with reference to Figure 5 The resistance value combinations may refer to the combinations of the resistance values set for the N+1 resistive memory cells 111 corresponding to the respective word lines, which may also be referred to as resistance value sequences.

[0058] In one example, the resistive memory cell may include a resistive memory element. The resistive memory element may have a set resistance value and may have one of a plurality of resistance values. For example, the resistive memory element may have one of a first resistance value and a second resistance value. In this case, the first resistance value may be less than the second resistance value. The first resistance value may be the resistance value of the low resistance state (LRS) (e.g., R P ), and the second resistance value may be the resistance value of the high resistance state (HRS) (e.g., R AP ). As will be described in more detail with reference to Figure 2 The resistive memory element of the resistive memory cell may be, for example, a magnetoresistive random access memory (MRAM).

[0059] In one example, the resistance states (e.g., resistance values) of multiple resistive memory elements may represent a single bit value. For example, a single bit value may be determined based on the two resistance states of two adjacent resistive memory elements. In this case, two identical resistance states may represent the first bit value (e.g., bit value 0), and two different resistance states may represent the second bit value (e.g., bit value 1). For example, when the bit value at a specific bit position in the bit sequence is the first bit value, the resistance values of the adjacent memory elements corresponding to that bit position among the N+1 resistive memory cells 111 may be the same. When the bit value at the bit position is the second bit value, the resistance values of the adjacent memory elements corresponding to that bit position among the N+1 resistive memory cells 111 may be different.

[0060] In one example, a method of operating a memory device 100, such as a memory encoding method, may be a method of encoding bit values using two adjacent resistive memory cells. For example, as described above, when the bit value is a first value, the memory encoding method may set the resistance values of two adjacent resistive memory cells to be the same. As described above, when the bit value is a second value different from the first value, the memory encoding method may also set the resistance values of two adjacent resistive memory cells to be different. The memory encoding method may encode N bit values using N + 1 resistive memory cells. The N + 1 resistive memory cells may be connected to a common word line, and N may be an integer greater than or equal to 2.

[0061] As a reference, an example in which the first bit value is zero (0) and the second bit value is 1 is described herein as an example. The memory encoding method described above may be based on an XOR where the first value is 0 and the second value is 1. Here, the encoding performed by mapping the bit value 0 to the same resistance value of two resistive memory elements and mapping the bit value 1 to different resistance values of two resistive memory elements may be referred to as XOR encoding. This is because, as described below, the resistance values set by the above mapping can be converted into bit values through an XOR operation. However, the example is not limited thereto. The memory encoding method may also be based on an exclusive NOR (XNOR) where the first value is 1 and the second value is 0, which may also be referred to as XNOR encoding. Hereinafter, operations related to XOR encoding will be described in more detail with reference to Figure 7A and Figure 12A and operations related to XNOR encoding will be described in more detail with reference to Figure 7B and Figure 12B

[0062] In one example, the memory device 100 may set resistance values encoded based on an XOR of a bit sequence for the resistive memory cells in a memory macro structure having the resistive memory cells. In one example, the memory macro structure of the memory device 100 may have a reduced area overhead and an increased read margin. Therefore, the memory device 100 can perform a read operation with reduced power consumption.

[0063] Figure 2 A memory device according to one or more embodiments is shown.

[0064] Referring to Figure 2 , in a non-limiting example, the memory device 100 may include a memory array (e.g., an XOR memory array) 110, a line selection circuit 230, a read circuit 250, and a write circuit 270.

[0065] As referred to above with reference to Figure 1As described, the memory array 110 may include N + 1 resistive memory cells representing an N-bit sequence for each line (e.g., word line). In Figure 2 In the example shown in FIG. Figure 2 , the memory array 110 may have M + 1 word lines and N + 1 column lines. The N + 1 column lines may include N data column lines and one reference column line. In this case, M may represent an integer greater than or equal to 1, and N may represent an integer greater than or equal to 2. The memory array 110 may include a total of (M + 1)×(N + 1) resistive memory cells.

[0066] In one example, the resistive memory cell may be a 1T1R (e.g., one transistor / one resistor) structure including one transistor and one resistive element. One transistor may operate as a switching element that allows access to the corresponding resistive element among a plurality of resistive elements arranged along the line. As described below, the switching element (e.g., transistor) of the resistive memory cell may be turned on by the word line driver 231. For example, the resistive memory cell may include an MRAM element as the resistive memory element.

[0067] The MRAM element may have a magnetic tunnel junction (MTJ) element. In Figure 2 In the example shown in FIG. Figure 2 , the MTJ i,j may be an MTJ element located on the i-th word line among a plurality of word lines and the j-th data column line among a plurality of data column lines, and REF i may be an MTJ element located on the i-th word line and the reference line (e.g., reference column line). In this case, i may represent an integer greater than or equal to 0 and less than or equal to M, and j may represent an integer greater than or equal to 0 and less than or equal to N - 1. The MTJ element may be a memory element whose resistance value changes according to the spin state of internal electrons. For example, depending on the configuration, the MRAM element may have a resistance value corresponding to one of a high resistance state (e.g., R AP ) and a low resistance state (e.g., R P ). Even when the power supply voltage is removed, the MRAM element may have non-volatile characteristics by maintaining the spin state of internal electrons. Therefore, in one example, the MRAM element may have a small size and low leakage current. Although the MRAM element is mainly described herein as an example of the resistive memory element, the examples of the resistive memory element are not limited thereto. The resistive memory element may be, for example, one of a ferroelectric random access memory (FRAM) device, a phase change memory (PCM) device, a three-dimensional (3D) XPoint device, a spin transfer torque MRAM (STT-MRAM) device, a nanoRAM (NRAM) device, a resistive RAM (ReRAM) device, and a conductive bridge RAM (CBRAM) device.

[0068] The line selection circuit 230 can select at least one word line from multiple word lines for a read operation or a write operation. The line selection circuit 230 can include an address decoder 232 and a word line driver 231.

[0069] The address decoder 232 can identify the word line corresponding to the given address information among multiple word lines. For example, the memory device 100 can receive an access request for accessing a memory (e.g., the memory array 110) from an external device (e.g., a host). The access request for a read operation or a write operation can include information (e.g., a memory address) indicating the memory location in the memory (e.g., the memory array 110) to which access is to be made. The address decoder 232 can decode the memory address to generate information indicating the word line corresponding to the requested memory location among multiple word lines.

[0070] The word line driver 231 can activate (or enable) the word line corresponding to the access request among multiple word lines. For example, the word line driver 231 can apply a signal (e.g., a word line selection signal) to the selected word line among multiple word lines. The word line driver 231 can apply an enable signal to the word line indicated by the result of decoding the access request by the address decoder 232. The switching element (e.g., a transistor) of the resistive memory cell connected to the selected word line can be turned on by the signal applied to the selected word line, and the resistive memory elements arranged on the selected word line can be respectively connected to the column lines. The memory device 100 can set (e.g., write) a resistance value for the resistive memory elements of the activated (or enabled) word line, or read the already set resistance value. Here, one resistive memory element can store data.

[0071] The read circuit 250 can read the data (e.g., a bit sequence) recorded (or written) in N + 1 resistive memory cells of the memory array 110. For example, the read circuit 250 can generate a bit read signal based on the XOR result of the resistance values "set for N + 1 resistive memory cells arranged along the word line selected for reading". As described in more detail below, Figure 5 the resistance value combinations and the bit sequences can be mapped to each other based on XOR coding. The read circuit 250 can include N read units (e.g., a first read unit to an Nth read unit) configured to generate N-bit read signals respectively. In one example, since each read unit includes logic elements and / or logic circuits (e.g., an XOR circuit), it can have a relatively simplified structure and reduced power consumption. In addition, each read unit can compare the resistive memory cells along adjacent column lines, and thus can ensure a read margin and allow the read operation to be performed more efficiently.

[0072] The write circuit 270 may write a resistance value according to a bit sequence corresponding to a resistive memory cell of the memory array 110. When the memory access request is a write request for writing, the memory access request may include a memory address and a value (e.g., a bit sequence) to be written to the memory address. The write circuit 270 may set a resistance value for the resistive memory cells of the word line activated (or enabled) in response to the memory access request, and the resistance value corresponds to the result of the XOR encoding performed on the bit sequence of the memory access request. In one example, the write circuit 270 may include a reference write circuit 271, a write encoder 273, and a write driver 275.

[0073] The reference write circuit 271 may set the resistance values of the resistive memory elements arranged along the reference column lines. For example, the reference write circuit 271 may set a resistance value determined according to the XOR encoding for the resistive memory element corresponding to the reference column line in the selected word line. Although the reference write circuit 271 is shown as being separated from the write encoder 273 and the write driver 275 in Figure 2 , the example is not limited thereto. The structure and / or function of the reference write circuit 271 may be integrated into the write encoder 273 and / or the write driver 275.

[0074] The write encoder 273 may generate N + 1 write signals respectively indicating the resistance values to be set for N + 1 resistive memory cells based on a reference signal and N bit signals respectively indicating the bit values of the bit sequence. The reference signal may be a signal indicating the bit value corresponding to "the resistance value (e.g., the reference resistance value) set for the resistive memory element arranged on the reference column line in the word line". The N bit signals may be signals respectively indicating the bit values corresponding to the bit positions in the N bit sequence. Each of the N + 1 write signals may indicate the resistance value to be set for the corresponding resistive memory cell.

[0075] The write driver 275 may set the resistance values for the resistive memory cells arranged along the word line selected for writing according to the XOR-based encoding result of the bit sequence. Each of the N + 1 write signals may indicate the resistance value to be set for the resistive memory element at a specific position among the N + 1 resistive memory elements in the selected word line. The write driver 275 may set the resistance value indicated by the specific write signal for the corresponding resistive memory cell. The write driver 275 may use the N + 1 write signals to set the resistance values of the N + 1 resistive memory cells. For example, when the bit value of a specific write signal is 0, the write driver 275 may set the resistance value (e.g., R) of the first resistance state (e.g., the low resistance state LRS) for the corresponding resistive memory cell. P). For another example, when the bit value of a specific write signal is 1, the write driver 275 can set the resistance value (e.g., high resistance state HRS) of the second resistance state for the corresponding resistive memory cell (e.g., R AP ). The write driver 275 can set the resistance value determined based on the XOR encoding for the corresponding resistive memory cell by applying a setting signal (e.g., voltage and / or current) corresponding to the corresponding write signal to each resistive memory cell in the enabled word line.

[0076] In a memory device according to an example (e.g., memory device 100), the two resistance values set for two adjacent resistive memory cells that are adjacent to each other and arranged along the same word line can represent a single bit value. The memory device can read the bit value independently of the resistance offset according to the position of the resistive memory elements in the memory array (e.g., memory array 110) caused by the wiring resistance.

[0077] In one example, the reference resistance for reading the resistance value of a specific resistive memory cell can be the resistance value of an adjacent resistive memory cell arranged adjacent to the corresponding resistive memory cell. In a comparative example, a comparison is performed between the reference threshold resistance (R REF ) of the reference column or reference row and the resistance of each resistive memory cell (e.g., R LRS , R HRS ), so there may be problems related to the dependence on the column position and / or row position. In contrast, in the memory device according to the example, a comparison can be performed between the resistance value of each resistive memory cell and the resistance value of the adjacent resistive memory cell, so that read offset can be suppressed even at different column positions.

[0078] The memory device can read the bit value with an increased read margin based on the resistance value and / or combination of resistance values of each resistive memory element, regardless of the change in the resistance value of the resistive memory element (e.g., MTJ). A comparison can be performed between adjacent resistive memory elements adjacent to each other. In this case, the resistive memory elements are implemented using the same material, so the process, voltage, temperature (PVT) variations 211 can move in the same direction, which can provide more robust read characteristics.

[0079] Further, in the comparative example, the low resistance state can be a state where the resistance is lower than the reference resistance, and the high resistance state can be a state where the resistance is higher than the reference resistance. In contrast, according to the example, the low resistance state can be a state where the resistance is lower than the resistance of the high resistance state, and the high resistance state can be a state where the resistance is higher than the resistance of the low resistance state. Thus, it can be understood that, compared with the comparative example, in the memory device according to the example, the read margin considered for determining the resistance state is substantially doubled. This is because adjacent MTJ elements having a symmetric layout and positioned adjacent to each other can be used as a reference. Therefore, the memory device can ensure a larger noise margin and thus can provide a read result (or a readout result) that is more robust to PVT variations 211.

[0080] Two MTJ elements can reference each other and can be implemented in a small area. As described above, the memory array 110 can be implemented using N + 1 resistive memory cells (e.g., N + 1 resistive memory elements) for an N-bit sequence, and thus only one column line needs to be added in the entire macro structure. Therefore, the area overhead can be negligible.

[0081] In one example, a non-volatile memory device (e.g., memory device 100) can effectively reduce power consumption and prevent leakage current by retaining data even when power is off. The memory device can be used in various hardware including, for example, low-power neuromorphic processors, mobile devices, and edge devices. The memory device can provide reduced power consumption and reduced area in read operations and write operations.

[0082] Figure 3 An example method of operating a memory device according to one or more embodiments is shown.

[0083] Referring to Figure 3 , in one non-limiting example, in operation 310, a non-volatile memory device (e.g., memory device 100) can set resistance values representing an N-bit sequence for N + 1 resistive memory cells arranged on a word line selected from the memory array for writing. Here, N can be an integer greater than or equal to 2. For example, the word line driver of the memory device can select a word line corresponding to a memory write request. The write circuit can set the resistance values for the resistive memory cells arranged along the selected word line, and the set resistance values are determined based on XOR coding according to the bit sequence corresponding to the memory write request. When the bit value at a bit position in the bit sequence is a first bit value, the memory device can set the same resistance value for the adjacent memory element corresponding to that bit position. When the bit value at the bit position is a second bit value, the memory device can set a different resistance value for the adjacent memory element corresponding to that bit position. An example of such a write operation of the memory device will be described in more detail below with reference to Figures 8 to 16 a more detailed description of an example of such a write operation of the memory device.

[0084] In operation 330, a non-volatile memory device (e.g., memory device 100) may output N-bit read signals from N + 1 resistive memory cells arranged on a word line selected for reading from a memory array. For example, a word line driver of the memory device may select a word line corresponding to a memory read request. A read circuit may determine bit read signals based on an XOR operation according to resistance values set for resistive memory cells of the word line corresponding to the memory read request. Examples of such a read operation of the memory device will be described in more detail below with reference to Figures 4 to 7A and Figure 7B Examples of such a read operation of the memory device will be described in more detail below with reference to

[0085] Figure 4 FIG. shows an example method of a read operation of a memory device according to one or more embodiments.

[0086] Referring to Figure 4 , in a non-limiting example, in operation 431, a memory device (e.g., memory device 100) may activate (or enable) a word line corresponding to a memory read request. For example, the memory device may identify a word line indicated by a memory address of the memory read request. The memory device may activate resistive memory cells by connecting resistive memory elements of the identified word line to their respective column lines.

[0087] In operation 433, a memory device (e.g., memory device 100) may output bit read signals based on a combination of resistance values stored in two adjacent resistive memory cells. The memory device may determine bit read signals indicating bit values of each of two adjacent resistive memory cells among resistive memory elements arranged along the word line. In one example, the memory device may determine bit values corresponding to resistance values of two adjacent resistive memory cells according to a mapping based on XOR encoding. The mapping based on XOR encoding will be described below with reference to Tables 1 and 2 below. Table 1 is a truth table of XOR elements presented for reference.

[0088] Table 1:

[0089] As shown in Table 1, XOR may have an output Q of 0 when inputs A and B (A, B) are the same, and an output Q of 1 when inputs A and B (A, B) are different. The resistance value (e.g., R P ) of the first resistance state (e.g., low resistance state LRS) itself or a signal (e.g., voltage signal or current signal) corresponding to the resistance value of the first resistance state may represent a first logic value (e.g., L or 0). The resistance value (e.g., RAP The signal corresponding to the resistance value of the second resistance state (e.g., a voltage signal or a current signal) can represent the second logic value (e.g., H or 1). Referring to the truth table in Table 1 above, the two inputs A and B of the XOR operation can be the logic values corresponding to the resistance values set for adjacent resistive memory elements, and the output Q can be a bit value. Therefore, the mapping between each bit value and the resistance value combination according to XOR encoding can be represented as presented in Table 2 below.

[0090] Table 2:

[0091] As shown in Table 2 above, the bit value 0 can be written and read as indicating a state (R AP , R AP ) or (R P , R P ) in which two resistive memory cells have the same resistance value. The bit value 1 can be written and read as indicating a state (R AP, R P ) or (R P , R AP ) in which two resistive memory cells have different resistance values. The result of the XOR operation between the logic values corresponding to the resistance values stored in the two resistive memory cells can be the bit value at the corresponding bit position. Therefore, the result of the XOR encoding of the corresponding bit value can be the resistance values stored in two adjacent resistive memory cells corresponding to that bit position.

[0092] In operation 435, the memory device (e.g., memory device 100) can output a read result based on the bit read signal. As described above, the resistive memory cells arranged along each word line of the memory array can have resistance values corresponding to the result of encoding the bit sequence based on the XOR operation. In one example, the memory device can determine the bit sequence by decoding the resistance value combination based on the XOR operation. For example, the memory device can generate a bit read signal by simultaneously performing the above operations (e.g., in operation 433) for every two adjacent resistive memory cells. As a reference, there can be N adjacent pairs for N + 1 resistive memory cells, and the operations in operation 433 can be performed on the N adjacent pairs simultaneously and / or in parallel. The memory device can generate a bit sequence corresponding to the resistance value combination (e.g., resistance value sequence) as the read result by combining the bit values respectively indicated by the generated bit read signals.

[0093] Figure 5 Illustrates an example bit sequence using the resistance value combination in a memory device according to one or more embodiments.

[0094] Referring toFigure 5 , in a non - limiting example, to assist in understanding the decoding based on the XOR operation, an example 510 is shown where a 4 - bit sequence 530 is represented by four data column lines (COL[3:0]) and a reference column line (REF). The 4 - bit sequence 530 is represented by RDATA[3:0], which can be given, for example, as 4'b1011. In the 4 - bit sequence 530, RDATA[3] which is 1 (e.g., the most significant bit (MSB)) can be represented as (R AP , R P ). Then, RDATA[2] which is 0 (e.g., MSB - 1) can be represented as (R P , R P ). Similarly, RDATA[1] (e.g., least significant bit (LSB)+1) and RDATA[0] (e.g., LSB) can be represented as (R P , R AP ) and (R AP , R P ) respectively. Thus, by combining these resistance values, a first resistance value combination 511 of (R AP , R P , R P , R AP , R P ) can be obtained. In the first resistance value combination 511, the reference resistance value can be R AP . In contrast, when the reference resistance value is R P , the second resistance value combination 512 can be (R P , R AP , R AP , R P , R AP ). The reference resistance value can be the resistance value on which the resistance value combination (or resistance value sequence) is based, which can be the first resistance value. In an example, a memory device (e.g., memory device 100) can select a resistance value combination by determining the value of a write signal indicating the reference resistance value. For example, the memory device can select the first resistance value combination 511 by determining the value of the write signal indicating the reference resistance value as 1 (corresponding to R AP ). The memory device can select the second resistance value combination 512 by determining the value of the write signal indicating the reference resistance value as 0 (corresponding to R P ).

[0095] As described above, according to the XOR encoding, there may always be two resistance value combinations that can represent a single bit sequence. For example, a memory device (e.g., memory device 100) can set (e.g., write) one of the available resistance value combinations representing the bit sequence for N + 1 resistive memory cells of a word line selected for writing. AsFigure 5 As shown in Figure 5 , by XOR encoding, the resistance value combinations representing a bit sequence can be in a complementary relationship with each other. That is, in the corresponding column lines, the resistance value of one resistance value combination in the resistance value combinations can have a logic value opposite to that of the resistance value of the other resistance value combination. As described above, since the two resistance value combinations correspond to the same bit sequence, the memory device can output the same bit sequence as the result of reading the two resistance value combinations.

[0096] Although only one example of a 4-bit sequence is shown in Figure 5 , Tables 3 and 4 below can show the two resistance value combinations that can be used for all 4-bit sequences. In Tables 3 and 4 below, COL[4] can be a reference column line, and COL[3:0] can be data column lines. Table 3 provides the resistance value combinations corresponding to 4-bit sequences when the low resistance value (R Figure 5 ) is set as the reference resistance value of the resistive memory cell of the reference column line COL[4]. Table 4 provides the resistance value combinations corresponding to 4-bit sequences when the high resistance value (R P ) is set as the reference resistance value of the resistive memory cell of the reference column line COL[4]. AP ) is set as the reference resistance value of the resistive memory cell of the reference column line COL[4].

[0097] Table 3:

[0098] Table 4:

[0099] Although the 4-bit sequence has been described above, other bit sequences of N bits or more can also use the two available resistance value combinations. Table 5 below provides the resistance value combinations to which the 8-bit sequence 8'b10010101 is mapped.

[0100] Table 5:

[0101] Therefore, even when the number N of bits forming the bit sequence increases, the memory device can represent N bits (e.g., 8 bits) with N + 1 (e.g., 9) resistive memory elements.

[0102] Figure 6 shows an example read operation method according to one or more embodiments. Referring to Figure 6 , in one non-limiting example, in operation 631, the memory device (e.g., memory device 100) can be in an idle state waiting for a memory access request. In response to receiving a memory read request, the memory device can initiate an operation to read the memory. Figure 6 ), in one non-limiting example, in operation 631, the memory device (e.g., memory device 100) can be in an idle state waiting for a memory access request. In response to receiving a memory read request, the memory device can initiate an operation to read the memory.

[0103] In operation 632, a memory device (e.g., memory device 100) may activate (or enable) a word line 720 based on decoding an address in a read request.

[0104] Figure 7A and Figure 7B illustrates an example read operation performed by a read circuit in a memory device according to one or more embodiments. In Figure 7A and Figure 7B , A represents a voltage corresponding to a first resistive memory element A during charge and discharge, B represents a voltage corresponding to a second resistive memory element B during charge and discharge, XOR represents an output pulse generated by an XOR element, R represents a signal input to a reset port (e.g., the R node) of an SR latch, RN represents a signal input to a reset port (e.g., the RN node) of the SR latch, and Q represents a signal output from the Q node of the SR latch. Referring to Figure 7A , in one non-limiting example, an address decoder 232 may receive an address ADDR of a memory read request. The address decoder 232 may provide information indicating a word line 720 corresponding to a result of decoding the address ADDR. For example, a word line driver may activate (or enable) the word line 720 corresponding to the address ADDR. By applying a signal 1 along the word line 720 selected from the memory array, the word line driver may allow a read pulse to be transmitted to the resistive memory elements located on the selected word line 720.

[0105] Referring to Figure 6 , in operation 633, a memory device (e.g., memory device 100) may generate an edge of a strobe signal STRB. For example, a strobe signal generation circuit (not shown) of the memory device may generate the strobe signal STRB. The strobe signal STRB may be provided to Figure 7A the read pulse generator 710 and the reset generator 731 shown in

[0106] In operation 634, a memory device (e.g., memory device 100) may generate a reset signal in response to the edge. For example, referring to Figure 7A , a reset generator 731 may generate a reset signal (Reset) in response to the strobe signal STRB. The reset generator 731 may detect each rising edge and each falling edge of the strobe signal STRB. The reset generator 731 may transmit a pulse (e.g., a short pulse) to a reset port (e.g., the R node) of an SR latch of the read circuit 250 for each rising edge and falling edge of the strobe signal STRB. Thus, at each edge of the strobe signal STRB, data stored in the Q node of the SR latch may be initialized to zero (0).

[0107] Referring toFigure 6 , in operation 635, the memory device may propagate the edge to the memory array. Refer to Figure 7A , the read pulse generator 710 of the memory device may include buffers (BUF) connected to each column line (e.g., bit line), and may supply a strobe signal STRB to the corresponding column line through the buffers to drive the bit line.

[0108] Refer to Figure 6 , in operation 636, the memory device (e.g., memory device 100) may set the latch circuit according to the result of the XOR operation based on the delay difference. In one example, the read circuit 250 may include an XOR element connected to two adjacent resistive memory cells among N + 1 resistive memory cells. Refer to Figure 7A , the first read unit 751 and the second read unit 752 may each include an XOR element. In the first read unit 751, the XOR element may output the result of comparing the resistance value of the first resistive memory element A with the resistance value of the second resistive memory element B. For example, the first read unit 751 may output a value 0 when the resistance values of the first resistive memory element A and the second resistive memory element B are the same, and may output a value 1 when the resistance values are different.

[0109] In one example, a voltage may be provided to the input terminal of the XOR element by the power driven to the bit line. The time for the voltage to be charged or discharged may vary according to the resistance value set for the resistive memory cell and the parasitic capacitance formed along the bit line. As described above, the XOR element may output the result of the comparison between the resistance values set for the two resistive memory elements (e.g., 0 if equal, 1 if different) through a delay (e.g., charge delay or discharge delay) that varies according to the resistance value set for each resistive memory element. For example, the read circuit 250 may provide an output based on the result of the comparison between the delays occurring in two adjacent resistive memory cells (depending on the resistance values and parasitic capacitances set for the two adjacent resistive memory cells) as the bit values for the two adjacent resistive memory cells. Each XOR circuit of the read circuit 250 may output the "XOR output" as "1" when the difference in delays exceeds the threshold, and may output the "XOR output" as "0" when the difference in delays is less than or equal to the threshold.

[0110] For example, the resistance values stored in the first resistive memory element A and the second resistive memory element B at the first address A0 among multiple word lines may be (R P , R AP ). Until it is set to the first resistance value R PWhen the voltage of the node to which the first resistive memory element A and the XOR element are connected reaches the threshold voltage, the first time t can be used P . Until it is set to the second resistance value R AP When the voltage of the node to which the second resistive memory element B and the XOR element are connected reaches the threshold voltage, the second time t can be used AP . The first time t P can be shorter than the second time t AP . Therefore, from the rising edge of the strobe signal STRB until the voltages of the resistive memory element A and the resistive memory element B reach the threshold voltage respectively, a delay corresponding to (t P , t AP ) can occur. Therefore, the voltages at the two input terminals of the XOR element can be different during the delay difference (i.e., t AP - t P ). The XOR element can generate an output pulse corresponding to "1" (or logical value H) during the delay difference t AP - t P . This output pulse can be transmitted to the set port (e.g., S node) of the SR latch in the corresponding read unit. The Q node of the SR latch can output a signal corresponding to "1" (or logical value H).

[0111] In one example, the resistance values stored in the first resistive memory element A and the second resistive memory element B of the second address A1 among multiple word lines can be (R AP , R P ). Similarly, from the falling edge of the strobe signal STRB until the voltages of the resistive memory element A and the resistive memory element B reach the threshold voltage respectively, a delay corresponding to (t AP , t P ) can occur. As a reference, the charging time of the voltage can be considered in the rising edge, and the discharging time of the voltage can be considered in the falling edge. The XOR element can generate an output pulse corresponding to the logical value H during the delay difference t AP - t P . The Q node of the SR latch can output a signal corresponding to "1" (or logical value H).

[0112] In one example, the resistance values stored in the first resistive memory element A and the second resistive memory element B of the third address A2 can be (R P , R P ). In this case, the same delay (e.g., t P). Therefore, the XOR element can provide a signal corresponding to "0" (or logic value L). Therefore, the output of the SR latch can hold the value 0 (e.g., a signal corresponding to logic value L) initialized by the reset signal. At the fourth address A3, since the delay is the same as t AP the output of the SR latch can also be held at 0.

[0113] As a reference, although an example including only the first resistive memory element A and the second resistive memory element B in the word line 720 corresponding to the first address A0 has been described above, the same or similar description can also be applied to N + 1 resistive memory cells including resistive memory elements of a reference column line and resistive memory elements of a data column line. Figure 7A

[0114] In addition, the resistance values of the resistive memory elements may not be ideal and may not be exactly the same, so errors may exist therefrom. Therefore, even when the same resistance value is set, there may be a delay difference. Therefore, the XOR element (or XOR circuit) can be designed to output a pulse signal corresponding to "1" (or logic value H) only when the delay difference at the two input terminals exceeds a threshold value. The XOR element can also be designed such that the threshold value is variable and adjustable.

[0115] Although Figure 7A an example of reading using a delay difference is shown, the example is not limited thereto. The memory device can also apply a current to the resistive memory element and output the result of sensing a voltage difference. The memory device can also apply a voltage to the resistive memory element and output the result of sensing a current difference. The memory device can be implemented in various structures that "can compare the resistance values set for two adjacent resistive memory elements".

[0116] Referring to Figure 6 , in operation 637, the memory device (e.g., memory device 100) can read the output of the latch circuit using an edge-synchronous clock. For example, the memory device can read the bit value set for the Q node of the SR latch through input-output logic (IO logic) using a clock synchronized with the rising edge and falling edge of the strobe signal STRB. As described above with reference to Figure 7A the bit values of the resistive memory cells located on the same word line 720 can be read together at one time.

[0117] Once the memory device has completed the output of the bit read signal, it can return to Figure 6 operation 631 in

[0118] Although it has been described above with reference to Figure 7APrimarily describes XOR encoding, but the examples are not limited thereto. The memory device may also have resistance values set based on exclusive NOR (XNOR) encoding rather than XOR encoding. Refer to Figure 7B , in a non-limiting example, an operation of reading a resistance value based on XNOR encoding is shown, and XNOR encoding will be described in more detail below with reference to Figure 12B .

[0119] In one example, a memory device (e.g., memory device 100) may read a bit sequence from resistance values set based on XNOR encoding. For example, different from the example where the reading units 751 and 752 shown in Figure 7A include XOR elements, Figure 7B the reading circuit 250b shown in Figure 7A may include reading units 751b and 752b having XNOR elements. The output waveform of the XNOR element and the output waveform QB of the SR latch in the reading circuit 250b may be inverted waveforms that are inverted from the output waveform of the XOR element and the output waveform Q of the SR latch in the reading circuit 250 described above with reference to Figure 7A . Other operations of the reading circuit 250b may be similar to those of the reading circuit 250 described above with reference to Figure 7A , and thus will not be described again. For example, operations 631, 632, 633, 634, and 635 are the same as those described above with reference to Figure 7A , and will not be described again.

[0120] Refer to Figure 6 , in operation 636, the memory device (e.g., memory device 100) may set a latch circuit according to the result of an XNOR operation based on a delay difference. In one example, the reading circuit 250b may include an XNOR element connected to two adjacent resistive memory cells among N + 1 resistive memory cells. Figure 7B shows an example where the first reading unit 751b and the second reading unit 752b each include an XNOR element. For example, the first reading unit 751b may output 1 when the resistance values of the first resistive memory element A and the second resistive memory element B are the same, and output 0 when they are different.

[0121] Refer to Figure 7B, a voltage can be supplied to the input terminal of the XNOR element by driving the power to the bit line. The time for which the voltage is charged or discharged can vary according to the resistance value set for the resistive memory cell and the parasitic capacitance formed along the bit line. As described above, the XNOR element can output the result of comparing the resistance values set for two resistive memory elements (e.g., 1 if equal, 0 if different) through a delay (e.g., charge delay or discharge delay) that varies according to the resistance value set for each resistive memory element. For example, each XNOR circuit of the read circuit 250b can output the "XNOR output" as "0" when the delay difference exceeds the threshold, and output the "XNOR output" as "1" when the delay difference is less than or equal to the threshold.

[0122] For example, when the resistance values stored in the first resistive memory element A and the second resistive memory element B at the first address A0 among multiple word lines are (R P , R AP ), the XNOR element can generate an output pulse corresponding to "0" (or logical value L) during the delay difference (i.e., t AP - t P ). This output pulse can be transmitted to the set port (e.g., SN node) of the SR latch in the corresponding read unit. QB of the SR latch can output a signal corresponding to "0" (or logical value L). For reference, Figure 7A shows a NOR-gate-based SR latch operating in a high-active state (high active), while Figure 7B shows an XNOR-gate-based SR latch operating in a low-active state (low active). The output pulse generated by the XNOR element can be input to the SN node of the SR latch, and the SR latch of Figure 7B can generate an output at the QB node.

[0123] In one example, when the resistance values stored in the first resistive memory element A and the second resistive memory element B at the second address A1 among multiple word lines are (R AP , R P ), the XNOR element can generate an output pulse corresponding to the logical value L during the delay difference (i.e., t AP - t P ). The QB node of the SR latch can output a signal corresponding to "0" (or logical value L).

[0124] In one example, when the resistance values stored in the first resistive memory element A and the second resistive memory element B at the third address A2 are (R P , R PWhen (), the XNOR element can provide a signal corresponding to "1" (or logical value H). Therefore, the SR latch can hold the value 1 (e.g., a signal corresponding to the logical value H) initialized to the reset signal (RN in Figure 7B at the QB node. At the fourth address A3, since the delay is the same as t AP , the QB output of the SR latch can also be held at 1.

[0125] Referring to Figure 6 , in operation 637, the memory device can read the output of the latch circuit using an edge-synchronous clock. For example, the memory device can read the bit value set for the QB node of the SR latch using a clock synchronized with the rising edge and falling edge of the strobe signal STRB through input-output logic (IO logic).

[0126] Figure 8 shows an example method of setting a resistance value according to one or more embodiments. Referring to Figure 8 , in a non-limiting example, a method of operating a memory device (e.g., memory device 100) (e.g., a memory encoding method) can be a method of encoding N bits using N + 1 memory cells connected to a word line. For example, the memory encoding method can select one memory cell having a reference resistance value from among the N + 1 memory cells. In this example, when the bit value at the position represented by the resistance values of the selected memory cell and its adjacent memory cell among the N bits is a first value, the memory encoding method can set the resistance value of the adjacent memory cell to the reference resistance value. When the bit value at the position represented by the resistance values of the selected memory cell and its adjacent memory cell among the N bits is a second value different from the first value, the memory encoding method can set the resistance value of the adjacent memory cell to a value different from the reference resistance value. Here, N can be an integer greater than or equal to 1.

[0127] For example, XOR can have a first value of 0 and a second value of 1. When N is an integer greater than or equal to 2, and the bit value at a specific position is 0, the resistance values of the two adjacent memory cells representing the bit value at the specific position can be the same. When the bit value at a specific position is 1, the resistance values of the two adjacent memory cells representing the bit value at the specific position can be different.

[0128] In one example, XNOR can have a first value of 1 and a second value of 0. When N is an integer greater than or equal to 2, and the bit value at a specific position is 0, the resistance values of the two adjacent memory cells representing the bit value at the specific position can be different. When the bit value at a specific position is 1, the resistance values of the two adjacent memory cells representing the bit value at the specific position can be the same.

[0129] The selected memory cells described above may be error memory cells (i.e., cells including defective resistive memory elements). The reference resistance value may be the fixed resistance value of the error memory cells (or the stuck resistance value here). In a memory device including multiple word lines, the column positions of the error memory cells of at least two word lines may be different. Hereinafter, error repair of a memory device with dynamically selected memory cells using the above reference memory cells will be described.

[0130] In one example, in operation 811, a memory device (e.g., write encoder 273) may generate N + 1 write signals respectively indicating N + 1 resistance values, where the N + 1 resistance values represent an N-bit sequence (data) determined based on the stuck resistance value of the error memory cells in the word lines including the error memory cells. The error memory cells may be cells including defective resistive memory elements, and due to the fault condition, the resistance of the resistive memory elements of the error memory cells may not change (or not flip). The resistance value of the error memory cells may have a resistance value R stuck in a first resistance state (e.g., low resistance state LRS) P and a resistance value R in a second resistance state (e.g., high resistance state HRS). AP of one of them.

[0131] Figure 9 and 10 illustrate an example setting operation based on the resistance values of error memory cells performed by a memory device according to one or more embodiments.

[0132] Referring to Figure 9 , in a non-limiting example, a memory device (e.g., memory device 100) may include a memory array 110 having error memory cells 913, a line selection circuit 230, a read circuit 250, a write encoder 273, a write driver 275, and an error information provider 977. As a reference, in the example shown in Figure 9 , Figure 2 parts of the reference write circuit 271 in

[0133] The N + 1 resistive memory cells of the memory array 110 may respectively have resistance values determined based on the stuck resistance value of the error memory cells in the word lines including the error memory cells. The normal resistance values may be recorded or written into the memory array 110 by the write encoder 273 with reference to the error information (REFCELL, or denoted as Refcell). The read circuit 250 may read the resistance value combination based on an XOR operation. Therefore, the presence or absence of errors does not need to be considered when designing the read circuit 250. For example, as Figure 9As shown, the memory array 110 may include error memory cells 913 located at different positions on each word line. Among the word lines that may include memory cells as error memory cells 913, the stuck resistance value and the error occurrence position of the error memory cells 913 may be used for XOR encoding.

[0134] The error information provider 977 may provide information about the error memory cells (e.g., error information REFCELL). The error information provider 977 may be implemented as, for example, a lookup table (LUT) circuit that provides the error information REFCELL to the write encoder 273.

[0135] The write encoder 273 may generate multiple write signals for multiple resistive memory elements for each word line by referring to the error information REFCELL. In one example, the write encoder 273 may include multiple XOR elements that generate N + 1 write signals based on the stuck resistance value and an N-bit signal respectively indicating the bit values of the bit sequence DATA.

[0136] In one example, the write encoder 273 may generate a write signal for setting a resistance value combination that "matches the stuck resistance value of the error memory cell among the two available resistance value combinations representing the bit sequence DATA" for the N + 1 resistive memory cells of the word line selected for writing. The write encoder 273 may determine the resistance value combination to be set for the N + 1 resistive memory cells based on the magnitude of the stuck resistance value (e.g., R P or R AP ) and the position of the error memory cell in the word line. Referring to Figure 10 , in a non-limiting example, the bit sequence DATA of 4'b1011 may be represented by a first resistance value combination 1011 of R P R AP R AP R P R AP and a second resistance value combination 1012 of R AP R P R P R AP R P R P The 4-bit sequence DATA may be represented by five resistive memory cells. An example where the resistance value of one of the five resistive memory cells is stuck to the first resistance value R P is shown. In one example, in a first case 1021 where the first of the five resistive memory cells is the R PIn the fourth case 1024 of the error memory cell (e.g., REF = 4), the first resistance value combination 1011 can be representative (i.e., the first resistance value combination 1011 can represent the first case 1021 and the fourth case 1024). Similarly, in the second unit being R P In the second case 1022 of the error memory cell (e.g., REF = 2), in the third unit being R P In the third case 1023 of the error memory cell (e.g., REF = 3) and in the fifth unit being R P In the fifth case 1025 of the error memory cell (e.g., REF = 5), the second resistance value combination 1012 can be representative (i.e., the second case 1022, the third case 1023, and the fifth case 1025 are represented by the second resistance value combination 1012).

[0137] Although only the example of the bit sequence DATA of 4'b1011 has been described above, the resistance value combination referring to the error memory cell can also be selected for any bit sequence DATA. For example, in the word line, the third memory cell (e.g., the resistive memory cell corresponding to COL[2]) can be an error memory cell having a stalled first resistance value R P For the word line in which the resistive memory cell corresponding to COL[2] has a stalled first resistance value R P Table 6 below provides an example resistance value combination mapped for each bit sequence DATA.

[0138] Table 6:

[0139] Therefore, through a flexible mapping based on XOR coding, a resistance value combination can be selected based on the stalled resistance value of any one of the multiple resistive memory cells in the word line. In one example, the memory device can record the error information REFCELL of the error memory cell and provide the error information REFCELL to the write encoder 273 to allow the write encoder 273 to use this information of the error memory cell. As described above, even when the error memory cell stalls to the first resistance value or the second resistance value, the memory device can always be able to determine the correct resistance value combination for any bit sequence DATA.

[0140] Referring to Figure 8 , in operation 813, the write driver 275 can set the resistance values according to N + 1 write signals for N + 1 resistive memory cells. For example, the write driver 275 can set the resistance values according to the N + 1 write signals for the word line that is "activated (or enabled) in response to the address of the memory write request".

[0141] As described above, in one example, using the information of the error memory cells, the memory device can implement the memory repair function without the need for a separate spare memory cell. In contrast, in one example, when a specific memory cell fails and malfunctions, the memory may require a memory repair circuit. In this case, according to the example, the memory device can consider and use the value of the faulty memory cell without additional area, and thus can increase its yield. In addition, even if an error occurs in the memory cells during operation, the memory device can update the error information REFCELL through monitoring as described in more detail below Figures 13 to 16 to dynamically provide the memory repair function.

[0142] Figure 11 、 Figure 12A and Figure 12B FIG. shows an example circuit of a write encoder for error memory cells in a reference memory device according to one or more embodiments.

[0143] Referring to Figure 11 , in a non-limiting example, the memory device 1100 may include an error information provider 977, a write encoder 273, a line selection circuit 230, a write driver 275, and a memory array 110.

[0144] The error information provider 977 may store the error information to be provided to the write encoder 273. The error information may be implemented as a LUT. The error information provider 977 may store the stall value SV (e.g., a value indicating the stall resistance magnitude) and the error location value CS for each address (ADDR[3:0]) (e.g., the address corresponding to an arbitrary word line). The stall value SV may be a value indicating the stall resistance magnitude of the error memory cell (e.g., R P or R APThe value of ) can be an error value. The error position value CS (e.g., column selection value) can be a value indicating the position (e.g., column position) of the resistive memory cell where the resistive switching is not available and an error has occurred in the corresponding word line. As an example, the default reference value DRV can be input from the user as a reference value for XOR encoding (or XNOR encoding), but is not limited thereto. The default reference value DRV can be 0 or 1. Based on the comparison result between the stall value SV and the XOR encoded value (or XNOR encoded value) of the error occurrence position in the encoded result (e.g., encoded value EV), the encoded result based on the default reference value DRV and the bit sequence (Data[N-1:0]) can be used as it is or can be inverted. For example, when the stall value SV and the encoded value EV of the error occurrence position are the same, the memory device 1100 can use the write signal corresponding to the encoded result. On the contrary, when the stall value SV and the encoded value EV of the error occurrence position are different, the memory device 1100 can use the inverted write signal obtained by inverting the write signal corresponding to the encoded result. The error information provider 977 can receive the address of the memory write request as an input and output the stall value SV and the error position value CS corresponding to the address. Figure 11 The example error information shown in can represent information about the error memory cells in the word lines corresponding to the addresses "0000", "0001", "0010", "0100", and "1000". As a reference, when an address other than the register address is received as an input, the error information provider 977 can output the stall value SV as 0 and the error position value CS as "000" as default information. This will be described in more detail with reference to Figures 13 to 16 the construction of the error information.

[0145] The write encoder 273 can determine a write signal corresponding to one of the two resistance value combinations based on the stall value SV and the error position (e.g., a value indicating the position of the error memory cell in the word line).

[0146] Referring to Figure 12A , in one non-limiting example, the write encoder 273 can include a first XOR element 1271 and a second XOR element 1273.

[0147] The first XOR element 1271 may generate a write signal based on the stalling resistance value and the bit sequence. The XOR gates of the first XOR element 1271 may output 0 when their inputs are the same and output 1 when the inputs are different. The output of at least one XOR gate in the first XOR element 1271 may be connected to the input of another XOR gate in the first XOR element 1271. The XOR gates in the first XOR element 1271 may be connected sequentially. In one example, except for the XOR gate corresponding to the least significant bit (LSB) of the bit sequence (Data[N-1:0]) in the first XOR element 1271, the output of each of the remaining XOR gates in the first XOR element 1271 may be connected to the input of the next XOR gate in the first XOR element 1271. The XOR gate corresponding to the most significant bit (MSB) of the bit sequence in the first XOR element 1271 may generate the XOR result between the default reference value DRV and the MSB value of the bit sequence (e.g., Data[N-1]). Except for the XOR gate corresponding to the MSB of the bit sequence in the first XOR element 1271, each of the remaining XOR gates in the first XOR element 1271 may generate the XOR result between the output of the previous XOR gate in the first XOR element 1271 and the bit value at the corresponding bit position in the bit sequence. The first XOR element 1271 may generate N write signals. In this case, the N+1 write signals obtained when the N write signals generated by the first XOR element 1271 are combined with a given default reference value DRV may be the result of XOR encoding performed on the N-bit sequence (or the bit sequence of N bits). However, as described below, the write signal corresponding to the result of XOR encoding may be inverted by the second XOR element 1273.

[0148] In one example, as described above with reference to Figure 5 the same bit sequence may be represented by a combination of two resistance values. The write encoder 273 may use the write signal generated by the first XOR element 1271 as it is, or invert the write signal through the second XOR element 1273. For example, when the value of the write signal corresponding to the faulty memory cell among the stalling resistance value and the write signal is different, the second XOR element 1273 may generate an inverted write signal obtained by inverting the write signal. In another example, when the value of the write signal corresponding to the faulty memory cell among the stalling resistance value and the write signal is the same, the second XOR element 1273 may pass the write signal generated by the first XOR element 1271 without inverting it.

[0149] In one example, the write encoder 273 may include a selection circuit 1272 that controls a second XOR element 1273. The selection circuit 1272 may operate the second XOR element 1273 as an inverter 1283 or an element 1281 based on a comparison between a stagnation value SV corresponding to a selected word line and a coded value EV corresponding to a corresponding error position (e.g., the position of a cell in the word line where an error has occurred).

[0150] As a reference, in the case where the second XOR element 1273 can operate as an inverter, when a value 1 is given to one of the two inputs of the XOR gate in the second XOR element 1273, the XOR gate inverts the value of the other input. In the case where the second XOR element 1273 can operate as an element 1281, when a value 0 is given to one of the two inputs of the XOR gate in the second XOR element 1273, the XOR gate passes the value of the other input as it is. Therefore, the selection circuit 1272 can provide a signal corresponding to 1 to the second XOR element 1273 when the stagnation value SV and the coded value EV of the corresponding error position are different, and provide a signal corresponding to 0 to the second XOR element 1273 when the stagnation value SV and the coded value EV are the same.

[0151] In one example, the selection circuit 1272 may include a comparator XOR gate (comp) and a multiplexer (MUX). The MUX may be an (N + 1)-to-1 MUX, and the (N + 1)-to-1 MUX may provide a coded value EV corresponding to an error position value CS indicated by error information to the comparator XOR gate comp. The output Flip of the comparator XOR gate comp may be 0 when the coded value EV and the stagnation value SV are the same, and may be 1 when the coded value EV and the stagnation value SV are different. One of the two input terminals of the XOR gate in the second XOR element 1273 may receive the output Flip of the comparator XOR gate comp. The other of the two input terminals of the XOR gate in the second XOR element 1273 may receive the corresponding write signal generated by the first XOR element 1271 described above.

[0152] In Figure 12A the example shown, Data[N - 1:0] may represent the bit sequence of the data targeted by the write request. The first XOR element 1271 may generate a write signal corresponding to the result of XOR encoding the bit sequence Data[N - 1:0] based on a default reference value DRV. The stagnation value SV may be the fixed resistance value of the error memory cell as described above. As described above, the default reference value DRV may be the value based on which the first XOR element 1271 performs XOR encoding. Hereinafter, the operation of the write encoder (e.g., the write encoder 273) using error information will be described.

[0153] As described above, the write encoder may generate a write signal indicating a combination of resistance values based on a comparison between a stagnation value SV and an encoded value EV. The encoded value EV may be the value of the write signal for a resistive memory cell in which an error has occurred at an error location value CS. The error location value CS may indicate the location of the resistive memory cell in which the error has occurred. For example, when the stagnation value SV and the encoded value EV are the same (e.g., both are 0 or both are 1), the write signal generated by the first XOR element 1271 may be used without inversion. In this case, as Figure 12A shown, the second XOR element 1273 of the write encoder may be interpreted as an element 1281 that passes the default reference value DRV and the output of the XOR gate in the first XOR element 1271 as they are. In one example, when the stagnation value SV and the encoded value EV are different, the second XOR element 1273 may transmit an inverted write signal obtained by inverting the write signal from the first XOR element 1271 and an inverted write signal obtained by inverting the default reference value DRV to the write driver. In this case, as Figure 12A shown, the second XOR element 1273 of the write encoder may be interpreted as an inverter 1283 that inverts the default reference value DRV and the output of the XOR gate in the first XOR element 1271.

[0154] In one example, the final write signal (COL[N:0]) may be the write signal from the first XOR element 1271 or the inverted write signal from the second XOR element 1273. The final write signal (COL[N:0]) may be a value indicating the resistance magnitude to be set for the resistive memory elements of the word lines for each column. For example, when the value of the write signal is 0, the resistance magnitude to be set may be R P , and when the value of the write signal is 1, the resistance magnitude to be set may be R AP . However, the examples are not limited thereto, and they may be mapped conversely according to the design.

[0155] Although Figure 12A shows an example of XOR encoding, the examples are not limited thereto. The memory device (e.g., memory device 100 and / or write encoder 273) may also determine the resistance value of the resistive memory element based on XNOR encoding. Referring to Figure 12B , in one non-limiting example, the write encoder 273 may include a first XNOR element 1271b and a second XNOR element 1273b.

[0156] The first XNOR element 1271b may generate a write signal based on the stagnant resistance value and the bit sequence. The XNOR gate of the first XNOR element 1271b may output 1 when the inputs are the same and output 0 when the inputs are different. The output of at least one XNOR gate in the first XNOR element 1271b may be connected to the input of another XNOR gate in the first XNOR element 1271b. The XNOR gates in the first XNOR element 1271b may be connected sequentially. In one example, except for the XNOR gate corresponding to the LSB of the bit sequence in the first XNOR element 1271b, the output of each of the remaining XNOR gates in the first XNOR element 1271b may be connected to the input of the next XNOR gate in the first XNOR element 1271b. The XNOR element corresponding to the MSB of the bit sequence in the first XNOR element 1271b may generate an XNOR result between the default reference value DRV and the MSB value of the bit sequence. Except for the XNOR gate corresponding to the MSB of the bit sequence in the first XNOR element 1271b, each of the remaining XNOR gates in the first XNOR element 1271b may generate an XNOR result between the output of the previous XNOR gate in the first XNOR element 1271b and the bit value at the corresponding bit position in the bit sequence. The first XNOR element 1271b may generate N write signals. The N + 1 write signals obtained when the N write signals generated by the first XNOR element 1271b are combined with a given default reference value DRV may be the result of XNOR encoding performed on an N-bit sequence (or a bit sequence of N bits). However, as described below, the write signal corresponding to the result of XNOR encoding may be inverted by the second XNOR element 1273b.

[0157] In one example, as referred to above Figure 5 as described, the same bit sequence may be represented by a combination of two resistance values. The write encoder 273 may use the write signal generated by the first XNOR element 1271b as it is, or invert the write signal through the second XNOR element 1273b. For example, when the value of the write signal corresponding to the faulty memory cell among the stagnant resistance value and the write signal is different, the second XNOR element 1273b may generate an inverted write signal obtained by inverting the write signal. In another example, when the value of the write signal corresponding to the faulty memory cell among the stagnant resistance value and the write signal is the same, the second XNOR element 1273b may pass the write signal generated by the first XNOR element 1271b without inversion.

[0158] In one example, the write encoder 273 may include a selection circuit 1272b that controls a second XNOR element 1273b. The selection circuit 1272b may operate the second XNOR element 1273b as an inverter 1283b or an element 1281b based on a comparison between a stalling value SV corresponding to a selected word line and a coded value EV corresponding to a corresponding error location (e.g., the location of a cell in the word line in which an error has occurred).

[0159] As a reference, in the case where the second XNOR element 1273b operates as an inverter, when 0 is given to one of the two inputs of the XORN gate in the second XNOR element 1273b, the XNOR gate inverts the value of the other input. In the case where the second XNOR element 1273b operates as an element 1281b, when 1 is given to one of the two inputs of the XORN gate in the second XNOR element 1273b, the XNOR gate passes the value of the other input as it is. Accordingly, the selection circuit 1272b may provide a signal corresponding to 0 to the second XNOR element 1273b when the stalling value SV and the coded value EV of the corresponding error location are different, and provide a signal corresponding to 1 to the second XNOR element 1273b when the stalling value SV and the coded value EV are the same.

[0160] In one example, the selection circuit 1272b may include a comparator XNOR gate (compb) and a MUX. The MUX may be an (N + 1)-to-1 MUX, and the (N + 1)-to-1 MUX may provide a coded value EV corresponding to an error location value CS indicated by error information to the comparator XNOR gate compb. The output Flip of the comparator XNOR gate compb may be 1 when the coded value EV and the stalling value SV are the same, and may be 0 when the coded value EV and the stalling value SV are different. One input terminal of the two input terminals of the XNOR gate in the second XNOR element 1273b may receive the output Flip of the comparator XNOR gate compb. The other input terminal of the two input terminals of the XNOR gate in the second XNOR element 1273b may receive a corresponding write signal generated by the first XNOR element 1271b described above.

[0161] In Figure 12BIn the example shown, Data[N-1:0] may represent the bit sequence of the data targeted by the write request. The first XNOR element 1271b may generate a write signal corresponding to the result of XNOR encoding performed on the bit sequence Data[N-1:0] based on the default reference value DRV. The stagnation value SV may be the fixed resistance value of the error memory cell as described above. As described above, the default reference value DRV may be the value based on which the first XNOR element 1271b performs XNOR encoding. Hereinafter, the operation of a write encoder (e.g., write encoder 273) using error information will be described.

[0162] As described above, the write encoder may generate a write signal indicating a combination of resistance values based on a comparison between the stagnation value SV and the encoded value EV. The encoded value EV may be the value of the write signal for a resistive memory cell in which an error has occurred at the error location value CS. The error location value CS may indicate the location of the resistive memory cell in which an error has occurred. For example, when the stagnation value SV and the encoded value EV are the same (e.g., both are 0 or both are 1), the write signal generated by the first XNOR element 1271b may be used without inversion. In this case, as Figure 12B shown, the second XNOR element 1273b of the write encoder may be interpreted as an element 1281b that passes the default reference value DRV and the output of the XNOR gate in the second XNOR element 1273b. In another example, when the stagnation value SV and the encoded value EV are different, the second XNOR element 1273b may transmit an inverted write signal obtained by inverting the write signal from the first XNOR element 1271b and an inverted write signal obtained by inverting the default reference value DRV to the write driver. In this case, as Figure 12B shown, the second XNOR element 1273b of the write encoder may be interpreted as an inverter 1283b that inverts the default reference value DRV and the output of the XNOR gate in the second XNOR element 1273b.

[0163] The final write signal (COL[N:0]) may be the write signal from the first XNOR element 1271b or the inverted write signal from the second XNOR element 1273b. The final write signal (COL[N:0]) may be a value indicating the resistance magnitude to be set for the resistive memory elements of the word lines for each column. For example, when the value of the write signal is 0, the resistance magnitude to be set may be R P and when the value of the write signal is 1, the resistance magnitude to be set may be R AP . However, the examples are not limited thereto, and they may be mapped conversely according to the design.

[0164] Figure 13Illustrate an example method of generating error information according to one or more embodiments.

[0165] In one example, a memory device (e.g., memory device 100) may manage error information. The error information may be prepared during the manufacturing and processing steps of the memory device. During the manufacturing and processing steps, the memory array may be subjected to tests described in more detail below to detect faulty memory cells. However, the example is not limited thereto. The memory device may also collect and update error information while monitoring the memory array. For example, the memory device may use the results of setting and reading the resistance values of the first resistance state of a plurality of resistive memory cells in the memory array and the results of setting and reading the resistance values of the second resistance state of a plurality of resistive memory cells in the memory array to periodically update the error information. Example error detection operations will be described in more detail below with reference to Figures 13 to 16 In one non-limiting example, in operation 1310, a memory device (e.g., memory device 100) may set the same resistance value for all resistive memory cells. The memory device may set the resistance value corresponding to the first bit value (e.g., bit value 0) for the resistive memory cells of the memory array. Figures 13 to 16 More detailed description of the example error detection operations.

[0166] Refer to Figure 13 In one non-limiting example, in operation 1310, a memory device (e.g., memory device 100) may set the same resistance value for all resistive memory cells. The memory device may set the resistance value corresponding to the first bit value (e.g., bit value 0) for the resistive memory cells of the memory array.

[0167] For example, in operation 1311, a memory device (e.g., memory device 100) may perform R P write and read on all cells.

[0168] Figures 14 to 16 Illustrate an example of generating error information according to one or more embodiments.

[0169] Refer to Figure 14 In one non-limiting example, a memory device (e.g., memory device 100) may generate a write signal (e.g., the write signal WDATA[3:0] for each row (e.g., any one of row0 to row9) is "0000") with R P as the reference resistance value from a bit sequence indicating 0. As indicated by reference numeral 1411, the memory device may attempt to set the resistance value corresponding to the generated write signal for all resistive memory cells (e.g., R P ). In the example shown in Figure 14 , the resistance value of the first resistance state may be R P . As indicated by reference numeral 1412, the memory device may perform XOR-encoding-based reading on the resistive memory cells with the resistance value set (e.g., as described above with reference to Figures 4 to 7B(read as described). Since the original bit sequence is "0000", the read result (RDATA[3:0]) can all be "0000", but when there are faulty memory cells, a "1" can be read from one or two adjacent bit positions relative to the faulty memory cell.

[0170] In one example, in operation 1312, the memory device can perform R AP write and read on all resistive memory cells. Referring to Figure 15 , in a non-limiting example, the memory device (e.g., memory device 100) can generate a write signal (e.g., "0000") with R AP as the reference resistance value from a bit sequence indicating 0. As indicated by reference numeral 1531, the memory device can attempt to set the resistance values corresponding to the generated write signal for all resistive memory cells (e.g., R AP ). In the example shown in Figure 15 , the resistance value of the first resistance state can be R AP . As indicated by reference numeral 1532, the memory device can perform XOR-encoding-based read on the resistive memory cells with the resistance values set (e.g., the read described above with reference to Figures 4 to 7B ). Since the original bit sequence is "0000", the read result can all be "0000", but when there are faulty memory cells, a "1" can be read from one or two adjacent bit positions relative to the faulty memory cell.

[0171] Referring to Figure 13 , in operation 1330, the memory device can determine error information based on the read error. For example, the memory device (e.g., write encoder 273) can determine the resistive memory cells corresponding to the part among the resistive memory cells from which the second bit value (e.g., bit value "1") is read as faulty memory cells.

[0172] In operation 1331, the memory device (e.g., memory device 100) can identify R AP errors. For example, referring to Figure 14 , as indicated by reference numeral 1413, the memory device can determine the position of the faulty memory cell corresponding to the bit position where a bit error has occurred. In the example shown in Figure 14 , the result of RDATA[3]='1' for which R P write has been attempted can indicate that the resistance value of REF (or COL[4]) is R AP . The result of RDATA[2:1]='11' can indicate that the resistance value of COL[2] is R APThe result of RDATA[0] = '1' can indicate that the resistance value of COL[0] is R AP .

[0173] In operation 1332, a memory device (e.g., memory device 100) can identify R P errors. For example, referring to Figure 15 , as indicated by reference numeral 1533, the memory device can determine the location of an error memory cell corresponding to the bit position where a bit error has occurred. In the example shown in Figure 15 , the result of RDATA[3] = '1' can indicate that the resistance value of REF (or COL[4]) is R P . The result of RDATA[1:0] = '11' can indicate that the resistance value of COL[1] is R P .

[0174] The memory device (e.g., memory device 100) can manage the error memory cell as having a resistance value of a second resistance state. The resistance value of the second resistance state can be R in the example shown in Figure 14 , and the resistance value of the second resistance state can be R in the example shown in AP , and the resistance value of the second resistance state can be R in the example shown in Figure 15 . The memory device can record (or write) in the error information the value of the word line indicating where the error memory cell is located (e.g., the address corresponding to that word line), the value of the column line indicating where the error memory cell is located (e.g., the error location value), and the stagnant resistance value of the error memory cell. As described above, the memory device can have multiple word lines including that word line. The column line where the error memory cell of the first word line among the multiple word lines is located can be different from the column line where the error memory cell of the second word line among the multiple word lines is located. The memory device can manage the error information separately for each word line where an error has occurred. The memory device can selectively determine the memory cells where an error has occurred for each word line. Referring to Figure 16 , in one non-limiting example, as a result of the error detection described above with reference to Figure 14 and Figure 15 , the memory device (e.g., memory device 100) can identify the locations where R P errors have occurred and the locations where R AP errors have occurred. The memory device can update and manage the error information 1610 (such as by writing to encoder 273), and the error information 1610 includes the address, stagnant value SV, and error location value CS for each error. The error information 1610 can be used by the above-described error information provider.

[0175] Figure 16 For example, in Figure 16In the example shown, in the error location value CS, "100", "011", "010", "001", and "000" may respectively indicate a resistive memory cell on the first column line (as a default reference memory cell), a resistive memory cell on the second column line, a resistive memory cell on the third column line, a resistive memory cell on the fourth column line, and a resistive memory cell on the fifth column line. However, the error location value CS is not limited to the foregoing example.

[0176] In one example, when an error that prevents a resistive memory cell from being programmed (e.g., a non-flip resistance error) occurs, the memory device (e.g., memory device 100 and / or write encoder 273) may record (or write) the stagnant resistance value of the resistive memory cell on the corresponding word line. Based on the stagnant resistance value, the memory device may determine the combination of resistance values set for the resistive memory cells arranged on the corresponding word line, and thus may implement an automatic memory repair function. Therefore, in one example, the problem of a fault with a stagnant resistance value can be solved without the need for additional components, devices, and / or area overhead.

[0177] As described herein and with respect to Figures 1 to 16The electronic devices, memory devices, circuits, XNOR elements, XOR elements, memories, processors, non-volatile memory device 100, memory array 111, write circuit 270, reference write circuit 271, write encoder 273, write driver 275, line selection circuit 230, word line driver 231, address decoder 232, read circuit 250, read circuit 250b, read pulse generator 710, reset generator 731, read units 751, 752, 751b and 752b, error information provider 977, memory device 1100, first XOR elements 1271 and 1271b, second XOR elements 1273 and 1273b, inverters 1283 and 1283b, elements 1281 and 1281b, selection circuits 1272 and 1272b, electronic device 1900, memory 1910 and processor 1920 described herein are implemented by or represent hardware components. As described above, or in addition to the above description, examples of hardware components that can be used to perform the operations described in the present application include, where appropriate: controllers, sensors, generators, drivers, memories, comparators, arithmetic logic units, adders, subtractors, multipliers, dividers, integrators, and any other electronic components configured to perform the operations described in the present application. In other examples, one or more of the hardware components that perform the operations described in the present application are implemented by computing hardware (e.g., by one or more processors or computers). A processor or computer can be implemented by one or more processing elements (such as logic gate arrays, controllers and arithmetic logic units, digital signal processors, microcomputers, programmable logic controllers, field programmable gate arrays, programmable logic arrays, microprocessors, or any other device or combination of devices configured to respond and execute instructions in a defined manner to achieve the desired result). In one example, a processor or computer includes or is connected to one or more memories that store instructions or software executed by the processor or computer. The hardware components implemented by the processor or computer can execute instructions or software (such as an operating system (OS) and one or more software applications running on the OS) to perform the operations described in the present application. The hardware components can also access, manipulate, process, create, and store data in response to the execution of the instructions or software. For simplicity, the singular terms "processor" or "computer" may be used in the description of the examples described in the present application, but in other examples, multiple processors or computers may be used, or a processor or computer may include multiple processing elements, or multiple types of processing elements, or both. For example, a single hardware component or two or more hardware components can be implemented by a single processor, or two or more processors, or a processor and a controller.One or more hardware components can be implemented by one or more processors, or processors and controllers, and one or more other hardware components can be implemented by one or more other processors, or additional processors and additional controllers. One or more processors or processors and controllers can implement a single hardware component, or two or more hardware components. As described above, or in addition to the above description, example hardware components can have any one or more of different processing configurations, examples of different processing configurations including single processors, independent processors, parallel processors, single instruction single data (SISD) multiprocessing, single instruction multiple data (SIMD) multiprocessing, multiple instruction single data (MISD) multiprocessing, and multiple instruction multiple data (MIMD) multiprocessing.

[0178] Figures 1 to 16 The method for performing the operations described in this application shown in through Figures 1 to 16 is performed by computing hardware (e.g., by one or more processors or a computer), which is implemented to execute instructions or software as described above to perform the operations performed by the method described in this application. For example, a single operation or two or more operations can be performed by a single processor, or two or more processors, or processors and controllers. One or more operations can be performed by one or more processors, or processors and controllers, and one or more other operations can be performed by one or more other processors, or additional processors and additional controllers. One or more processors or processors and controllers can perform a single operation, or two or more operations.

[0179] Instructions or software for controlling computing hardware (e.g., one or more processors or a computer) to implement the hardware components and perform the methods described above can be written as a computer program, code segment, instruction, or any combination thereof to individually or jointly direct or configure one or more processors or a computer to operate as a machine or special-purpose computer for performing the operations performed by the hardware components and the methods described above. In one example, the instructions or software include machine code (such as machine code generated by a compiler) directly executable by one or more processors or a computer. In another example, the instructions or software include high-level code executable by one or more processors or a computer using an interpreter. The instructions or software can be written in any programming language based on the block diagrams and flowcharts shown in the figures and the corresponding descriptions herein, which disclose algorithms for performing the operations performed by the hardware components and the methods described above.

[0180] Instructions or software for controlling computing hardware (e.g., one or more processors or computers) to implement the hardware components and execute the methods as described above, as well as any associated data, data files, and data structures, can be recorded, stored, or fixed in one or more non-transitory computer-readable storage media, or recorded, stored, or fixed on one or more non-transitory computer-readable storage media, and thus are not signals themselves. As described above, or in addition to the above description, examples of non-transitory computer-readable storage media include: read-only memory (ROM), random access programmable read-only memory (PROM), electrically erasable programmable read-only memory (EEPROM), random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, non-volatile memory, CD-ROM, CD-R, CD+R, CD-RW, CD+RW, DVD-ROM, DVD-R, DVD+R, DVD-RW, DVD+RW, DVD-RAM, BD-ROM, BD-R, BD-R LTH, BD-RE, Blu-ray or optical disc storage devices, hard disk drives (HDD), solid state drives (SSD), flash memory, card-type memories (such as, multimedia cards or micro-cards (e.g., Secure Digital (SD) or Extreme Digital (XD))), magnetic tapes, floppy disks, magneto-optical data storage devices, optical data storage devices, hard disks, solid state disks, and / or any one or more of any other devices, any other device being configured to store instructions or software and any associated data, data files, and data structures in a non-transitory manner and provide the instructions or software and any associated data, data files, and data structures to one or more processors or computers such that the one or more processors or computers can execute the instructions. In one example, the instructions or software and any associated data, data files, and data structures are distributed across a networked computer system such that the instructions and software and any associated data, data files, and data structures are stored, accessed, and executed by one or more processors or computers in a distributed manner.

[0181] Although this disclosure includes specific examples, it will be apparent after understanding the disclosure of this application that various changes in form and detail can be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein are considered to be merely descriptive and not for purposes of limitation. The description of a feature or aspect in each example will be considered applicable to similar features or aspects in other examples. Appropriate results can be achieved if the described techniques are performed in a different order, and / or if the components in the described system, architecture, device, or circuit are combined in a different manner, and / or replaced or supplemented by other components or their equivalents.

[0182] Accordingly, in addition to what is disclosed above and in all of the appended drawings, the scope of the disclosure also includes the claims and their equivalents (i.e., all variations within the scope of the claims and their equivalents will be construed as being included in the disclosure).

Claims

1. A memory device, comprising: A memory array including, for each of a plurality of word lines, N + 1 resistive memory cells, the N + 1 resistive memory cells having resistance values representing a bit sequence of N bits, the resistance values being determined based on the stuck resistance values of the error memory cells among the N + 1 resistive memory cells, and the resistance values being set respectively; and A write encoder configured to generate N + 1 write signals respectively indicating the resistance values to be set for the N + 1 resistive memory cells, wherein N is an integer greater than or equal to 1.

2. The memory device according to claim 1, wherein, When the bit value at the bit position in the bit sequence is the first bit value, the resistance values of the adjacent memory elements corresponding to the bit position among the N + 1 resistive memory cells are the same value, and wherein, when the bit value at the bit position is a second bit value different from the first bit value, the resistance values of the adjacent memory elements corresponding to the bit position among the N + 1 resistive memory cells are different values.

3. The memory device according to claim 1, wherein, The write encoder includes: A plurality of exclusive - OR elements configured to generate the N + 1 write signals based on the stuck resistance value and N - bit signals respectively indicating the bit values of the bit sequence.

4. The memory device according to claim 1, wherein, The write encoder is configured to: Generate write signals for setting a resistance value combination that matches the stuck resistance value of the error memory cell among two available resistance value combinations representing the bit sequence for the N + 1 resistive memory cells of the selected word line for writing.

5. The memory device according to claim 1, wherein, The write encoder is configured to: Determine the resistance value combination to be set for the N + 1 resistive memory cells based on the magnitude of the stuck resistance value and the position of the error memory cell in the word line.

6. The memory device according to claim 1, wherein, The write encoder includes: A first exclusive - OR element configured to generate a plurality of write signals based on the stuck resistance value and the bit sequence; and A second exclusive - OR element configured to generate an inverted write signal in response to the value of the write signal corresponding to the error memory cell among the plurality of write signals being a value different from the stuck resistance value, the inverted write signal being inverted from the write signal.

7. The memory device according to claim 6, wherein, The second exclusive - OR element is configured to: Transmit the plurality of write signals in response to the value of the write signal corresponding to the error memory cell among the plurality of write signals being a value the same as the stuck resistance value.

8. The memory device according to claim 1, the memory device being configured to: Set resistance values of a first resistance state corresponding to the first bit value for a plurality of resistive memory cells of the memory array; Determine, as error memory cells, the resistive memory cells corresponding to a part of the resistive memory cells from which the second bit value is read; And Manage the error memory cells as having resistance values of a second resistance state.

9. The memory device according to claim 1, wherein, The write encoder is further configured to: Record, in the error information, the value of the word line indicating the location of the error memory cell, the value of the column line indicating the location of the error memory cell, and the stuck resistance value of the error memory cell.

10. The memory device according to claim 9, wherein, The write encoder is further configured to: For multiple resistive memory cells of a memory array, error information is periodically updated using a first result of setting and reading a resistance value of a first resistance state and a second result of setting and reading a resistance value of a second resistance state.

11. The memory device according to any one of claims 1 to 10, Among them, a column line where a first error memory cell of a first word line among the plurality of word lines is located is different from a column line where a second error memory cell of a second word line among the plurality of word lines is located.

12. The memory device according to any one of claims 1 to 10, further comprising: a reading circuit configured to generate a bit read signal based on a result of performing an exclusive OR on resistance values set for N + 1 resistive memory cells arranged along a word line selected for reading.

13. The memory device according to claim 12, wherein, The reading circuit includes: an exclusive OR element connected to two adjacent resistive memory cells among the N + 1 resistive memory cells arranged along the word line selected for reading.

14. The memory device according to claim 13, wherein, The reading circuit is configured to: output, as a bit value for the two adjacent resistive memory cells, a result of comparing delays occurring in the two adjacent resistive memory cells based on the resistance values and parasitic capacitances set for the two adjacent resistive memory cells.

15. A method of operating a memory device, the method comprising: generating N + 1 write signals respectively indicating N + 1 resistance values representing a bit sequence of N bits, the N + 1 resistance values being determined based on a stagnant resistance value of an error memory cell among N + 1 resistive memory cells arranged on a word line of a memory array including the error memory cell; and respectively setting the N + 1 resistance values according to the N + 1 write signals for the N + 1 resistive memory cells, where N is an integer greater than or equal to 1.

16. The method according to claim 15, wherein The step of generating the N + 1 write signals includes: generating the N + 1 write signals based on N bit signals respectively indicating bit values of the bit sequence and the stagnant resistance value.

17. The method according to claim 15, wherein, The step of generating the N + 1 write signals includes: generating the N + 1 write signals indicating a resistance value combination that matches the stagnant resistance value of the error memory cell among two available resistance value combinations representing the bit sequence.

18. The method according to claim 15, wherein, The step of generating the N + 1 write signals includes: in response to a value of an error write signal corresponding to the error memory cell among the N + 1 write signals being a different value from the stagnant resistance value, inverting the N + 1 write signals.

19. The method according to any one of claims 15 to 18, further comprising: setting a resistance value of a first resistance state corresponding to a first bit value for multiple resistive memory cells of a memory array; determining, as error memory cells, resistive memory cells corresponding to a part of the resistive memory cells from which a second bit value is read among the multiple resistive memory cells; and managing the error memory cells as having a resistance value of a second resistance state.

20. The method according to any one of claims 15 to 18, further comprising: Generating an N-bit read signal based on the result of an exclusive-OR operation performed on resistance values, the resistance values being set for N+1 resistive memory cells arranged along a selected word line for reading.

21. A method of operating a memory device, the method comprising: Selecting, from among N+1 memory cells connected to a word line, one memory cell having a reference resistance value among the N+1 memory cells; In response to a bit value represented by the resistance values of the selected one memory cell and an adjacent memory cell among an N-bit bit sequence being a first value, setting the resistance value of the adjacent memory cell to the reference resistance value; and In response to the bit value represented by the resistance values of the selected one memory cell and the adjacent memory cell among the N-bit bit sequence being a second value different from the first value, setting the resistance value of the adjacent memory cell to a value different from the reference resistance value, where N is an integer greater than or equal to 1.

22. The method according to claim 21, wherein Performing an exclusive-OR operation in response to the first value being 0 and the second value being 1.

23. The method according to claim 21, wherein, Performing a NAND operation in response to the first value being 1 and the second value being 0.

24. The method according to claim 21, wherein, N is an integer greater than or equal to 2, where, when the bit value is 0, the resistance values of two adjacent memory cells representing the bit value are the same value, and where, when the bit value is 1, the resistance values of two adjacent memory cells representing the bit value are different values.

25. The method according to claim 21, wherein N is an integer greater than or equal to 2, where, when the bit value is 0, the resistance values of two adjacent memory cells representing the bit value are different values, and where, when the bit value is 1, the resistance values of two adjacent memory cells representing the bit value are the same value.

26. The method according to any one of claims 21 to 25, wherein, The selected one memory cell is an error memory cell, where the reference resistance value is the stagnant resistance value of the error memory cell.

27. The method according to claim 26, wherein, In a memory device including multiple word lines, the column positions of the error memory cells of at least two word lines are different.

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