Memory device and operating method thereof

Abstract

The invention provides a memory device and an operating method thereof. The memory device includes a first cell string disposed between a first bit line and a common source line and a second cell string disposed between the first bit line and the common source line. At least two first ground selection transistors among the first ground selection transistors of the first cell string have a first program state, and the remaining first ground selection transistors have an erase state. At least two of the second ground selection transistors of the second cell string have a first program state, and the remaining second ground selection transistors have an erase state.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices, and more particularly, to a memory device and an operation method thereof. Background Art

[0002] Semiconductor memories are classified as volatile memories or non-volatile memories. Volatile memories lose data stored therein when power is turned off, such as static random access memories (SRAMs) or dynamic random access memories (DRAMs). Non-volatile memories retain data stored therein even when power is turned off, such as flash memories, phase change RAMs (PRAMs), magnetic RAMs (MRAMs), resistive RAMs (RRAMs), or ferroelectric RAMs (FRAMs).

[0003] Flash memory devices are widely used as high-capacity storage media. Generally, a flash memory device stores data or reads stored data by controlling levels of various lines (e.g., a string selection line, word lines, and a ground selection line) connected to a plurality of memory cells. When controlling various lines individually in units of cell strings, reliability and performance of the flash memory device can be improved. However, due to an increase in complexity of a process of manufacturing the flash memory device, it is difficult to form lines individually. Summary of the Invention

[0004] Embodiments of the present disclosure provide a memory device and an operation method thereof having improved performance and improved reliability.

[0005] According to an embodiment, a memory device includes a first cell string and a second cell string. The first cell string is disposed between a first bit line and a common source line and includes a first string selection transistor connected to a first string selection line and first ground selection transistors respectively connected to a plurality of ground selection lines. The second cell string is disposed between the first bit line and the common source line and includes a second string selection transistor connected to a second string selection line and second ground selection transistors respectively connected to the plurality of ground selection lines. At least two of the first ground selection transistors are configured to have a first programming state, and remaining ones of the first ground selection transistors are configured to have an erased state. At least two of the second ground selection transistors are configured to have the first programming state, and remaining ones of the second ground selection transistors are configured to have the erased state.

[0006] According to an embodiment, a memory device includes: a first cell string connected to a first bit line, a first string selection line, and a plurality of ground selection lines; a second cell string connected to the first bit line, a second string selection line, and the plurality of ground selection lines; a third cell string connected to the first bit line, a third string selection line, and the plurality of ground selection lines; and a fourth cell string connected to the first bit line, a fourth string selection line, and the plurality of ground selection lines. When the first cell string is selected, a first turn-on voltage is applied to a first ground selection line and a second ground selection line among the plurality of ground selection lines, and a second turn-on voltage lower than the first turn-on voltage is applied to the remaining ground selection lines among the plurality of ground selection lines except the first ground selection line and the second ground selection line. When the second cell string is selected, the first turn-on voltage is applied to the second ground selection line and a third ground selection line among the plurality of ground selection lines, and the second turn-on voltage is applied to the remaining ground selection lines among the plurality of ground selection lines except the second ground selection line and the third ground selection line.

[0007] According to an embodiment, an operation method of a memory device, the memory device including a plurality of cell strings disposed between a bit line and a common source line, the plurality of cell strings being respectively connected to a plurality of string selection lines, and each of the plurality of cell strings being connected to a plurality of word lines and a plurality of ground selection lines, the operation method including: selecting at least two ground selection lines among the plurality of ground selection lines; simultaneously applying a programming voltage to the at least two ground selection lines; and simultaneously applying a verification voltage to the at least two ground selection lines.

[0008] According to an embodiment, a memory device includes a plurality of first cell transistors connected in series between a first bit line and a common source line. The plurality of first cell transistors include a plurality of first string selection transistors, a plurality of first memory cells, and a plurality of first ground selection transistors. At least two of the plurality of ground selection transistors are configured to have a first programming state, and the remaining ground selection transistors among the plurality of ground selection transistors except the at least two ground selection transistors are configured to have an erased state. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other objects and features of the present disclosure will become readily apparent by referring to the embodiments of the present disclosure described in detail with reference to the accompanying drawings.

[0010] Figure 1 is a block diagram showing a memory device according to an embodiment of the present disclosure.

[0011] Figure 2 is shown in Figure 1The circuit diagram of the first memory block included in the memory cell array.

[0012] Figure 3 is Figure 2 The top view of the first memory block.

[0013] Figure 4A and Figure 4B is a diagram for describing a method of controlling Figure 2 and Figure 3 the first memory block.

[0014] Figure 5 is a flowchart showing Figure 1 the operation method of the memory device.

[0015] Figure 6 is a flowchart showing Figure 5 the operation S120.

[0016] Figure 7 is for describing the operation according to Figure 6 the flowchart.

[0017] Figure 8 is a flowchart showing Figure 5 the operation S130.

[0018] Figure 9 is for describing the operation according to Figure 8 the flowchart.

[0019] Figure 10 is for describing the operation of programming the 3a ground selection transistor and the 4a ground selection transistor of the first memory block simultaneously. Figure 9 The diagram of the threshold voltage distribution of the ground selection transistor programmed according to the embodiment.

[0020] Figure 11 shows according to Figure 10 the embodiment.

[0021] Figure 12A and Figure 12B is a diagram for describing the GSL coding mode according to an embodiment of the present disclosure.

[0022] Figure 13 is a diagram for describing the GSL coding mode according to an embodiment of the present disclosure.

[0023] Figure 14A and Figure 14B is a diagram for describing the GSL coding mode according to an embodiment of the present disclosure.

[0024] Figure 15A and Figure 15BIt is a diagram for describing the GSL coding mode according to an embodiment of the present disclosure.

[0025] Figure 16A and Figure 16B It is a diagram for describing the GSL coding mode according to an embodiment of the present disclosure.

[0026] Figure 17A and Figure 17B It is a diagram for describing the GSL coding mode according to an embodiment of the present disclosure.

[0027] Figure 18 It is a diagram for describing the GSL coding mode according to an embodiment of the present disclosure.

[0028] Figure 19 It is a diagram for describing the GSL coding mode according to an embodiment of the present disclosure.

[0029] Figure 20 It is a diagram for describing the GSL coding mode according to an embodiment of the present disclosure.

[0030] Figure 21 It is a diagram for describing the GSL coding mode according to an embodiment of the present disclosure.

[0031] Figure 22 and Figure 23 It is a diagram for describing the GSL coding mode according to an embodiment of the present disclosure.

[0032] Figure 24 It is a diagram for describing a memory device according to an embodiment of the present disclosure.

[0033] Figure 25 It is a block diagram showing a memory system according to an embodiment of the present disclosure. Detailed Embodiments

[0034] Hereinafter, embodiments of the present disclosure will be described in detail and clearly to the extent that an ordinary person skilled in the art can easily implement the present disclosure.

[0035] Figure 1 It is a block diagram showing a memory device according to an embodiment of the present disclosure. Referring to Figure 1 , the memory device 100 may include a storage cell array 110, a row decoder circuit 120, a page buffer circuit 130, a data input / output circuit 140, a buffer circuit 150, a control logic circuit 160, and a voltage generation circuit 170. In an embodiment, the memory device 100 may include a NAND flash memory device, but the present disclosure is not limited thereto.

[0036] The memory cell array 110 may include a plurality of memory blocks. Each of the plurality of memory blocks may include a plurality of cell strings. Each of the plurality of cell strings may include a plurality of cell transistors stacked in a direction perpendicular to the substrate. The plurality of cell transistors may be connected in series between a bit line BL and a common source line. The plurality of cell transistors may be connected to a string select line SSL, a word line WL, and a ground select line GSL. A detailed description of the plurality of memory blocks will be made with reference to Figure 2 Describe the plurality of memory blocks in detail.

[0037] The row decoder circuit 120 may be connected to the memory cell array 110 through the string select line SSL, the word line WL, and the ground select line GSL. The row decoder circuit 120 may operate under the control of the control logic circuit 160. For example, under the control of the control logic circuit 160, the row decoder circuit 120 may decode the row address RA received from the buffer circuit 150; based on the decoding result, the row decoder circuit 120 may control or drive the string select line SSL, the word line WL, and the ground select line GSL, or may control the voltage to be applied to the string select line SSL, the word line WL, and the ground select line GSL.

[0038] The page buffer circuit 130 may be connected to the memory cell array 110 through the bit line BL. The page buffer circuit 130 may be connected to the data input / output circuit 140 through a plurality of data lines DL. The page buffer circuit 130 may operate under the control of the control logic circuit 160. For example, in the programming operation of the memory device 100, the page buffer circuit 130 may store the data to be programmed in the memory cell array 110 under the control of the control logic circuit 160. In the read operation of the memory device 100, the page buffer circuit 130 may sense the voltage of the bit line BL and may store the sensed voltage as read data.

[0039] The data input / output circuit 140 may be connected to the page buffer circuit 130 through a plurality of data lines DL. The data input / output circuit 140 may receive a column address CA from the buffer circuit 150. The data input / output circuit 140 may send the data read by the page buffer circuit 130 to the buffer circuit 150 according to the column address CA. The data input / output circuit 140 may send the data received from the buffer circuit 150 to the page buffer circuit 130 based on the column address CA.

[0040] The buffer circuit 150 may receive a command CMD and an address ADDR from an external device (e.g., a controller) through a first signal line SIGL1, and may exchange data "DATA" with the external device (e.g., a controller) through the first signal line SIGL1. In an embodiment, the first signal line SIGL1 may include a data signal line (e.g., a DQ line) and a data strobe signal line (e.g., a DQS line).

[0041] The buffer circuit 150 can operate under the control of the control logic circuit 160. For example, the control logic circuit 160 can exchange control signals CTRL with an external device (e.g., a controller) via a second signal line SIGL2. The control logic circuit 160 can control the buffer circuit 150 based on the control signal CTRL such that the buffer circuit 150 routes a command CMD, an address ADDR, and data "DATA". Under the control of the control logic circuit 160, the buffer circuit 150 can classify the signals received via a first signal line SIGL1 as either a command CMD or an address ADDR. The buffer circuit 150 can transmit the command CMD to the control logic circuit 160. The buffer circuit 150 can transmit a row address RA of the address ADDR to the row decoding circuit 120 and can transmit a column address CA of the address ADDR to the data input / output circuit 140. The buffer circuit 150 can exchange data "DATA" with the data input / output circuit 140.

[0042] The control logic circuit 160 can decode the command CMD received from the buffer circuit 150 and can control the memory device 100 or various components of the memory device 100 based on the decoding result.

[0043] Under the control of the control logic circuit 160, the voltage generation circuit 170 can generate various operating voltages VOP used in the memory device 100. In an embodiment, the operating voltages VOP can include various voltages such as a programming voltage, a pass voltage, a selected read voltage, a non-selected read voltage, an erase voltage, and a verify voltage. Hereinafter, the various voltages used to describe embodiments of the present disclosure can be included in the operating voltages VOP generated by the voltage generation circuit 170.

[0044] Figure 2 is a circuit diagram of a first memory block included in the Figure 1 memory cell array to be described. The structure of the first memory block BLK1 will be described with reference to Figure 2 However, the present disclosure is not limited thereto. For example, the memory cell array 110 can include a plurality of memory blocks, each of which is structurally similar to Figure 2 the first memory block BLK1.

[0045] In an embodiment, the first memory block BLK1 to be described with reference to Figure 2 can correspond to a physical erase unit of the memory device 100. However, the present disclosure is not limited thereto. For example, the memory device 100 can perform an erase operation in units of pages, word lines, sub-blocks, or planes.

[0046] In an embodiment, the first memory block BLK1 to be described with reference to Figure 2The described first memory block BLK1 is provided only as an example. The number of cell strings can be increased or decreased, and the number of rows and the number of columns of the cell strings can be increased or decreased depending on the number of cell strings. In addition, the number of cell transistors GST, MC, dMC, SST, and ECT in the first memory block BLK1 can be increased or decreased, and the height of the first memory block BLK1 can be increased or decreased according to the number of cell transistors. Additionally, the number of lines GSL, WL, dWL, and SSL connected to the cell transistors can be increased or decreased depending on the number of cell transistors.

[0047] Reference Figure 1 and Figure 2 , the first memory block BLK1 may include a plurality of cell strings CS1a, CS1b, CS1c, CS1d, CS2a, CS2b, CS2c, and CS2d. The plurality of cell strings CS1a to CS2d may be arranged along a first direction DR1 and a second direction DR2 to form rows and columns.

[0048] The plurality of cell strings CS1a to CS2d may be connected to bit lines BL1 and BL2. For example, each of the bit lines BL1 and BL2 may extend along the second direction DR2. The cell strings CS1a, CS1b, CS1c, and CS1d among the plurality of cell strings CS1a to CS2d that are located in the same column (i.e., the first column) may be connected to the first bit line BL1, and the cell strings CS2a, CS2b, CS2c, and CS2d among the plurality of cell strings CS1a to CS2d that are located in the same column (i.e., the second column) may be connected to the second bit line BL2.

[0049] The 1a cell string CS1a may include a plurality of cell transistors connected in series between the first bit line BL1 and the common source line CSL. The plurality of cell transistors of the 1a cell string CS1a located in the first column and the first row may include a first erase control transistor ECT1, a plurality of ground select transistors GST1 to GSTk, dummy memory cells dMC1 and dMC2, a plurality of memory cells MC1 to MCn, a string select transistor SST, and a second erase control transistor ECT2. In an embodiment, each of the plurality of cell transistors may be implemented using a charge trap flash (CTF) memory cell.

[0050] Multiple unit transistors of the 1a unit string CS1a can be connected in series and can be stacked in a third direction DR3 (or height direction), which is perpendicular to the plane defined by the first direction DR1 and the second direction DR2 or the substrate. For example, multiple memory cells MC1 to MCn can be connected in series and can be stacked in a third direction DR3 (or height direction) that is perpendicular to the substrate. A string selection transistor SST can be disposed between the multiple memory cells MC1 to MCn and the first bit line BL1. Multiple ground selection transistors GST1 to GSTk can be connected in series and can be stacked in a third direction DR3 (or height direction) that is perpendicular to the substrate. The serially connected multiple ground selection transistors GST1 to GSTk can be disposed between the serially connected multiple memory cells MC1 to MCn and the common source line CSL.

[0051] In an embodiment, a first dummy memory cell dMC1 can be disposed between the multiple memory cells MC1 to MCn and the multiple ground selection transistors GST1 to GSTk. In an embodiment, a second dummy memory cell dMC2 can be disposed between the multiple memory cells MC1 to MCn and the string selection transistor SST.

[0052] In an embodiment, a first erase control transistor ECT1 can be disposed between the multiple ground selection transistors GST1 to GSTk and the common source line CSL. A second erase control transistor ECT2 can be disposed between the string selection transistor SST and the first bit line BL1. The first erase control transistor ECT1 and the second erase control transistor ECT2 can be used to charge or erase the channel of the 1a unit string CS1a with an erase voltage based on the gate-induced drain leakage (GIDL) phenomenon to erase the first memory block BLK1.

[0053] For ease of description, the structure of the 1a unit string CS1a is described, but the present disclosure is not limited thereto. For example, each of the remaining unit strings CS1b to CS1d and CS2a to CS2d can be structurally similar to the 1a unit string CS1a.

[0054] The first erase control transistors ECT1 of the multiple unit strings CS1a to CS2d can be commonly connected to a first erase control line ECL1. The second erase control transistors ECT2 of the multiple unit strings CS1a to CS2d can be commonly connected to a second erase control line ECL2.

[0055] Among the multiple memory cells MC1 to MCn, the memory cells located at the same height from the substrate can be commonly connected to the same word line, and the memory cells among the multiple memory cells MC1 to MCn located at another height can be commonly connected to another word line. For example, the first memory cell MC1 of the multiple cell strings CS1a to CS2d can be located at the same height from the substrate and can be commonly connected to the first word line WL1. The nth memory cell MCn of the multiple cell strings CS1a to CS2d can be located at the same height from the substrate and can be commonly connected to the nth word line WLn.

[0056] In an embodiment, the first dummy memory cell dMC1 among the multiple cell strings CS1a to CS2d can be located at the same height from the substrate and can be commonly connected to the first dummy word line dWL1. The second dummy memory cell dMC2 among the multiple cell strings CS1a to CS2d can be located at the same height from the substrate and can be commonly connected to the second dummy word line dWL2.

[0057] The string selection transistors SST of the multiple cell strings CS1a to CS2d can be connected to multiple string selection lines SSLa to SSLd. For example, the string selection transistors located in the same row can be connected to the same string selection line, and the string selection transistors located in different rows can be connected to different string selection lines. Specifically, the string selection transistors SST of the cell strings CS1a and CS2a located in the first row can be connected to the a-th string selection line SSLa; the string selection transistors SST of the cell strings CS1b and CS2b located in the second row can be connected to the b-th string selection line SSLb; the string selection transistors SST of the cell strings CS1c and CS2c located in the third row can be connected to the c-th string selection line SSLc; and the string selection transistors SST of the cell strings CS1d and CS2d located in the fourth row can be connected to the d-th string selection line SSLd.

[0058] For the sake of simplicity of the drawings and convenience of description, the description is given as each of the multiple cell strings CS1a to CS2d includes one string selection transistor SST, but the present disclosure is not limited thereto. Each of the multiple cell strings CS1a to CS2d can include multiple string selection transistors, and the string selection transistors located in the same row among the string selection transistors located at the same height from the substrate can be connected to the same string selection line; in this case, the string selection transistors located in different rows can be connected to different string selection lines.

[0059] Ground selection transistors located at the same height from the substrate may be connected to the same ground selection line. For example, the first ground selection transistor GST1 among the plurality of cell strings CS1a to CS2d may be located at the same height from the substrate and may be commonly connected to the first ground selection line GSL1. The k-th ground selection transistor GSTk among the plurality of cell strings CS1a to CS2d may be located at the same height from the substrate and may be commonly connected to the k-th ground selection line GSLk.

[0060] As Figure 2 shown, the plurality of cell strings CS1a to CS2d may be commonly connected to the ground selection lines GSL1 to GSLk, or may share the ground selection lines GSL1 to GSLk. In this case, since the plurality of cell strings CS1a to CS2d are controlled by the same ground selection line, the ground selection transistors of the unselected cell strings may be turned on during a read operation, a verify operation, or a channel recovery operation, resulting in problems such as reduced reliability, reduced performance, and increased power consumption.

[0061] To solve the above problems, the ground selection transistors GST1 to GSTk of the plurality of cell strings CS1a to CS2d may be connected to the ground selection lines in units of rows such that the plurality of cell strings CS1a to CS2d are individually controlled or controlled in units of rows. In this case, the ground selection transistors of the unselected cell strings may be turned off during a read operation, a verify operation, or a channel recovery operation, and thus, problems such as reduced reliability, reduced performance, and increased power consumption may be solved.

[0062] However, physical limitations of the first memory block BLK1 may make it difficult to implement a structure in which the ground selection transistors GST1 to GSTk of the plurality of cell strings CS1a to CS2d are connected to the ground selection lines in units of rows. In this case, each of the ground selection transistors GST1 to GSTk of the plurality of cell strings CS1a to CS2d may be separately set with a threshold voltage, and the voltages of the plurality of ground selection lines GSL1 to GSLk may be controlled to individually control the plurality of cell strings CS1a to CS2d.

[0063] Figure 3 is Figure 2 a top view of the first memory block. For ease of description, some components of the first memory block BLK1 are omitted. However, the present disclosure is not limited thereto. Refer to Figure 2 and Figure 3, a first memory block BLK1 may be formed on a substrate. The first memory block BLK1 may include a ground selection structure GSS, a word line structure WLS, and a plurality of string selection structures SSSa, SSSb, SSSc, and SSSd. The ground selection structure GSS, the word line structure WLS, and the plurality of string selection structures SSSa, SSSb, SSSc, and SSSd may be disposed between word line cuts WL_CUT and may be stacked along a direction (e.g., a third direction DR3) perpendicular to the substrate defined by a first direction DR1 and a second direction DR2.

[0064] The plurality of string selection structures SSSa, SSSb, SSSc, and SSSd may extend along the first direction DR1 and may be electrically separated from each other by string selection cuts SSS_CUT. The first memory block BLK1 may include a plurality of vertical structures VS1 to VS16. The plurality of vertical structures VS1 to VS16 may penetrate the ground selection structure GSS, the word line structure WLS, and the plurality of string selection structures SSSa, SSSb, SSSc, and SSSd. For example, the first vertical structure VS1 to the fourth vertical structure VS4 may penetrate the ground selection structure GSS, the word line structure WLS, and the a-th string selection structure SSSa; the fifth vertical structure VS5 to the eighth vertical structure VS8 may penetrate the ground selection structure GSS, the word line structure WLS, and the b-th string selection structure SSSb; the ninth vertical structure VS9 to the twelfth vertical structure VS12 may penetrate the ground selection structure GSS, the word line structure WLS, and the c-th string selection structure SSSc; and the thirteenth vertical structure VS13 to the sixteenth vertical structure VS16 may penetrate the ground selection structure GSS, the word line structure WLS, and the d-th string selection structure SSSd.

[0065] The plurality of vertical structures VS1 to VS16 may be connected to a plurality of bit lines BL1, BL2, BL3, and BL4 extending along the second direction DR2. For example, the first vertical structure VS1, the fifth vertical structure VS5, the ninth vertical structure VS9, and the thirteenth vertical structure VS13 may be connected to the first bit line BL1, the second vertical structure VS2, the sixth vertical structure VS6, the tenth vertical structure VS10, and the fourteenth vertical structure VS14 may be connected to the second bit line BL2, the third vertical structure VS3, the seventh vertical structure VS7, the eleventh vertical structure VS11, and the fifteenth vertical structure VS15 may be connected to the third bit line BL3, and the fourth vertical structure VS4, the eighth vertical structure VS8, the twelfth vertical structure VS12, and the sixteenth vertical structure VS16 may be connected to the fourth bit line BL4.

[0066] In an embodiment, each of the plurality of vertical structures VS1 to VS16 may form a cell string. For example, Figure 3 the first vertical structure VS1 and the second vertical structure VS2 may respectively correspond toFigure 2 The first unit string CS1a and the second unit string CS2a of Figure 3 The fifth vertical structure VS5 and the sixth vertical structure VS6 of Figure 2 The first unit string CS1b and the second unit string CS2b of Figure 3 The ninth vertical structure VS9 and the tenth vertical structure VS10 of Figure 2 The first unit string CS1c and the second unit string CS2c of Figure 3 The thirteenth vertical structure VS13 and the fourteenth vertical structure VS14 of Figure 2 The first unit string CS1d and the second unit string CS2d of

[0067] In Figure 3 In the structure of the first memory block BLK1 described in Figure 2 The four string selection structures SSSa to SSSd of Figure 3 That is, in the first memory block BLK1 described in Figure 2 and Figure 3 The SSL - GSL structure of the first memory block BLK1 described in

[0068] Figure 4A and Figure 4B are diagrams for describing a method of controlling Figure 2 and Figure 3 the first memory block. Hereinafter, for ease of description, embodiments of the present disclosure will be described based on a plurality of unit strings CSa, CSb, CSc, and CSd connected to the first bit line BL1. In addition, some unit transistors (e.g., dummy memory cells and erase control transistors) included in each of the plurality of unit strings CSa, CSb, CSc, and CSd are omitted. However, the present disclosure is not limited thereto.

[0069] Hereinafter, for the sake of simplicity of the drawings and convenience of description, some ground selection lines GSL and some ground selection transistors GST are shown in the drawings, but the present disclosure is not limited thereto. For example, in the following drawings, the ground selection transistor or the dummy ground selection transistor is shown as being directly connected to the common source line CSL. However, additional ground selection transistors may further exist between the ground selection transistor or the dummy ground selection transistor and the common source line CSL.

[0070] Referring to Figures 1 to 4B, the first memory block BLK1 may include cell strings CSa to CSd. Each of the cell strings CSa to CSd may be connected between a first bit line BL1 and a common source line CSL. The cell string CSa may include a plurality of ground selection transistors GST1a to GST4a, a plurality of memory cells MC1a to MCna, and the a-th string selection transistor SSTa. The cell string CSb may include a plurality of ground selection transistors GST1b to GST4b, a plurality of memory cells MC1b to MCnb, and the b-th string selection transistor SSTb. The cell string CSc may include a plurality of ground selection transistors GST1c to GST4c, a plurality of memory cells MC1c to MCnc, and the c-th string selection transistor SSTc. The cell string CSd may include a plurality of ground selection transistors GST1d to GST4d, a plurality of memory cells MC1d to MCnd, and the d-th string selection transistor SSTd.

[0071] The string selection transistor SSTa of the cell string CSa may be connected to the a-th string selection line SSLa; the string selection transistor SSTb of the cell string CSb may be connected to the b-th string selection line SSLb; the string selection transistor SSTc of the cell string CSc may be connected to the c-th string selection line SSLc; and the string selection transistor SSTd of the cell string CSd may be connected to the d-th string selection line SSLd.

[0072] The ground selection transistors GST1a to GST4a, GST1b to GST4b, GST1c to GST4c, and GST1d to GST4d of the cell strings CSa to CSd and the memory cells MC1a to MCna, MC1b to MCnb, MC1c to MCnc, and MC1d to MCnd may be connected to a plurality of ground selection lines GSL1 to GSL4 and a plurality of word lines WL1 to WLn. For example, the first memory cells MC1a, MC1b, MC1c, and MC1d of the cell strings CSa to CSd may be connected to the first word line WL1, and the n-th memory cells MCna, MCnb, MCnc, and MCnd of the cell strings CSa to CSd may be connected to the n-th word line WLn.

[0073] The ground selection transistors GST1a, GST1b, GST1c, and GST1d of the a-th unit string CSa to the d-th unit string CSd can be connected to the first ground selection line GSL1; the ground selection transistors GST2a, GST2b, GST2c, and GST2d of the a-th unit string CSa to the d-th unit string CSd can be connected to the second ground selection line GSL2; the ground selection transistors GST3a, GST3b, GST3c, and GST3d of the a-th unit string CSa to the d-th unit string CSd can be connected to the third ground selection line GSL3; and the ground selection transistors GST4a, GST4b, GST4c, and GST4d of the a-th unit string CSa to the d-th unit string CSd can be connected to the fourth ground selection line GSL4.

[0074] In an embodiment, when the memory device 100 operates, one of the multiple unit strings CSa to CSd can be selected, and the remaining unit strings can be unselected. In this case, the threshold voltage of each of the multiple ground selection transistors GST1a to GST4d can be set such that the remaining unselected unit strings among the multiple unit strings CSa to CSd are not electrically connected to the common source line CSL.

[0075] For example, as Figure 4B shown, the threshold voltage or threshold voltage distribution of the a-th programming state Pa can be higher than the threshold voltage or threshold voltage distribution of the erase state "E". In this case, the ground selection transistor having the a-th programming state Pa can be turned off by the first turn-on voltage VON1 and can be turned on by the second turn-on voltage VON2. In an embodiment, the erase state "E" can indicate a threshold voltage distribution different from the threshold voltage distribution of the a-th programming state Pa. In an embodiment, the erase state "E" can indicate a threshold voltage distribution lower than the threshold voltage distribution of the a-th programming state Pa. For example, the threshold voltage of the ground selection transistor corresponding to the erase state "E" can be lower than the threshold voltage of the ground selection transistor corresponding to the a-th programming state Pa. In an embodiment, the threshold voltage of the ground selection transistor corresponding to the erase state "E" can be different from the threshold voltage of the memory cell MC corresponding to the erase state "E".

[0076] The threshold voltages of the fourth local selection transistor GST4a, the third local selection transistor GST3b, the second local selection transistor GST2c, and the first local selection transistor GST1d among the plurality of local selection transistors GST1a to GST4a can be set to the a-th programming state Pa. In this case, since the first turn-on voltage VON1 or the second turn-on voltage VON2 is applied to each of the plurality of local selection lines GSL1 to GSL4, the remaining unselected cell strings among the plurality of cell strings CSa to CSd except the selected cell string may not be electrically connected to the common source line CSL.

[0077] Specifically, assume that the a-th cell string CSa is the selected cell string. In this case, the first turn-on voltage VON1 can be applied to the first local selection line GSL1 to the third local selection line GSL3, and the second turn-on voltage VON2 can be applied to the fourth local selection line GSL4. When the first turn-on voltage VON1 is applied to the first local selection line GSL1, the first local selection transistor GST1a, the first local selection transistor GST1b, and the first local selection transistor GST1c can be turned on, and the local selection transistor GST1d can be turned off. When the first turn-on voltage VON1 is applied to the second local selection line GSL2, the second local selection transistor GST2a, the second local selection transistor GST2b, and the second local selection transistor GST2d can be turned on, and the local selection transistor GST2c can be turned off. When the first turn-on voltage VON1 is applied to the third local selection line GSL3, the third local selection transistor GST3a, the third local selection transistor GST3c, and the third local selection transistor GST3d can be turned on, and the local selection transistor GST3b can be turned off. When the second turn-on voltage VON2 is applied to the fourth local selection line GSL4, the local selection transistors GST4a, GST4b, GST4c, and GST4d connected to the fourth local selection line GSL4 can be turned on.

[0078] That is, according to the above bias conditions associated with the local selection lines GSL1 to GSL4, since all the local selection transistors GST1a to GST4a of the a-th cell string CSa as the selected cell string are turned on, the a-th cell string CSa can be electrically connected to the common source line CSL. On the contrary, since the third local selection transistor GST3b, the second local selection transistor GST2c, and the first local selection transistor GST1d are turned off, the b-th cell string CSb, the c-th cell string CSc, and the d-th cell string CSd as the unselected cell strings can be electrically separated from the common source line CSL. Therefore, problems that may occur during the operation of the memory device 100, such as reduced reliability, reduced performance, and increased power consumption, can be prevented.

[0079] In an embodiment, programming operations associated with the ground selection lines GSL1 to GSL4 may be performed to set the threshold voltages of the ground selection transistors GST4a, GST3b, GST2c, and GST1d to the threshold voltage of the a-th programming state Pa. For example, by applying a programming voltage to the fourth ground selection line GSL4 and a pass voltage to the remaining lines (e.g., GSL1 to GSL3 and WL1 to WLn), the threshold voltage of the 4a-th ground selection transistor GST4a can be set to the a-th programming state Pa. By applying a programming voltage to the third ground selection line GSL3 and a pass voltage to the remaining lines (e.g., GSL1, GSL2, GSL4, and WL1 to WLn), the threshold voltage of the 3b-th ground selection transistor GST3b can be set to the a-th programming state Pa. By applying a programming voltage to the second ground selection line GSL2 and a pass voltage to the remaining lines (e.g., GSL1, GSL3, GSL4, and WL1 to WLn), the threshold voltage of the 2c-th ground selection transistor GST2c can be set to the a-th programming state Pa. By applying a programming voltage to the first ground selection line GSL1 and a pass voltage to the remaining lines (e.g., GSL2, GSL3, GSL4, and WL1 to WLn), the threshold voltage of the 1d-th ground selection transistor GST1d can be set to the a-th programming state Pa.

[0080] In an embodiment, the threshold voltages of the ground selection transistors GST1a to GST4d may change due to various factors. For example, when the memory device 100 operates, the threshold voltages of the ground selection transistors GST1a to GST4d may decrease depending on the retention characteristics of the ground selection transistors GST1a to GST4d. Alternatively, when the memory device 100 operates, read interference may occur in the ground selection transistors GST1a to GST4d, resulting in an increase in the threshold voltages of the ground selection transistors GST1a to GST4d. Alternatively, when the memory device 100 operates, hot electron injection phenomena may occur in the ground selection transistors GST1a to GST4d, resulting in an increase in the threshold voltages of the ground selection transistors GST1a to GST4d.

[0081] As described above, when the threshold voltages of the ground selection transistors GST1a to GST4d change, the memory device 100 may not operate properly, resulting in a decrease in performance and reliability in the memory device 100.

[0082] Figure 5 is a flowchart showing Figure 1 the operation method of the memory device. Hereinafter, for ease of description, embodiments of the present disclosure will be described based on the operation method of the memory device 100. However, the present disclosure is not limited thereto. For example, it may be performed according to Figure 5The operations of the flowchart. That is, during the process of manufacturing or testing the memory device 100, the setting of the threshold voltages of multiple select transistors of the memory device 100 can be performed. Alternatively, during the operation of the memory device 100, the memory device 100 can perform operations according to Figure 5 the flowchart.

[0083] Refer to Figure 1 and Figure 5 , in operation S110, the memory device 100 can determine the SSL-GSL structure of the memory device 100. For example, the memory device 100 can include multiple memory blocks formed based on one of various structures. As an example, as described in reference Figure 2 and Figure 3 , each of the multiple memory blocks of the memory device 100 can be formed based on a 4SSL-1GSL structure. References Figure 2 and Figure 3 describe the structure of the 4SSL-1GSL structure, and thus, additional descriptions will be omitted to avoid redundancy.

[0084] In operation S120, the memory device 100 can generate a GSL coding pattern for programming select transistors based on the SSL-GSL structure. For example, as described in reference Figure 4A and Figure 4B , in the first memory block BLK1 having a 4SSL-1GSL structure, some select transistors GST4a, GST3b, GST2c, and GST1d can be programmed to the a-th programming state so that the unselected cell strings are not electrically connected to the common source line CSL. In this case, the cell strings CSa, CSb, CSc, and CSd can be individually controlled by controlling the levels of multiple select lines GSL1 to GSL4. However, as described in reference Figure 4A and Figure 4B , the threshold voltages of the select transistors can change due to various factors; in this case, the reliability and performance of the operations of the memory device 100 may decrease.

[0085] The GSL coding pattern according to an embodiment of the present disclosure can be set such that at least two select transistors have the same threshold voltage state. In this case, the change in the threshold voltages of the select transistors can be prevented or minimized, and thus, the decrease in the reliability and performance of the operations of the memory device 100 can be prevented. In an embodiment, that the select transistors are adjacent to each other can mean that the select transistors are directly connected. Or, that the select transistors are adjacent to each other can mean that no other dummy select transistors exist between the adjacent select transistors.

[0086] The GSL coding mode according to embodiments of the present disclosure will be described in detail with reference to the following drawings.

[0087] In operation S130, the memory device 100 may perform a multi-GSL programming operation based on the GSL coding mode. For example, the memory device 100 may simultaneously program at least two adjacent ground selection transistors by simultaneously applying a programming voltage to at least two adjacent ground selection lines based on the GSL coding mode. The multi-GSL programming operation in operation S130 will be described in detail with reference to the following drawings.

[0088] As described above, according to embodiments of the present disclosure, since at least two adjacent ground selection transistors have the same threshold voltage state, a change in the threshold voltage of the ground selection transistors can be prevented or minimized. That is, a reduction in the reliability and operating performance of the memory device 100 can be prevented.

[0089] Figure 6 is a flowchart showing Figure 5 operation S120. Figure 7 is a diagram for describing the operations of the flowchart according to Figure 6 the flowchart.

[0090] Hereinafter, for ease of description, embodiments of the present disclosure will be described based on cell strings CSa, CSb, CSc, and CSd connected to the first bit line BL1, but the present disclosure is not limited thereto. For example, it can be understood that embodiments of the present disclosure are applicable to a plurality of cell strings respectively connected to a plurality of bit lines BLs. As an example, the a-th cell string CSa may indicate a cell string connected to the first bit line BL1 and connected to the a-th string selection line SSLa, but it can be understood that the a-th cell string CSa indicates any other cell string connected to the a-th string selection line SSLa and any other bit line, or can be replaced therewith.

[0091] Refer to Figure 1 , Figure 6 and Figure 7 , in operation S121, the memory device 100 may determine a first number of strings to be electrically separated. For example, as described with reference to Figure 2 and Figure 3 , the first memory block BLK1 may have a 4SSL-1GSL structure. In this case, electrical separation of four cell strings of the first memory block BLK1 may be required. In this case, the first number may be "4".

[0092] In operation S122, the memory device 100 may generate a GSL preset pattern based on the first number. Hereinafter, for ease of description, it is assumed that when a ground selection transistor is set to one of an erase state "E" or a first a programming state Pa, a bit pattern "0" indicates that the ground selection transistor corresponding to the bit pattern "0" is in the erase state "E", and a bit pattern "1" indicates that the ground selection transistor corresponding to the bit pattern "1" is in the first a programming state Pa. That is, when the pattern corresponding to the ground selection transistors GST1a, GST2a, GST3a, and GST4a connected to the first ground selection line is

[0011] , it means that the first a ground selection transistor GST1a is in the erase state "E", the second a ground selection transistor GST2a is in the erase state "E", the third a ground selection transistor GST3a is in the first a programming state Pa, and the fourth a ground selection transistor GST4a is in the first a programming state Pa. This example is provided to easily and briefly describe the embodiments of the present disclosure, however, the present disclosure is not limited thereto.

[0093] In an embodiment, as described above, electrical separation of four cell strings of the first memory block BLK1 may be required. In this case, a GSL preset pattern for four ground selection lines may be generated. In this case, a GSL preset pattern may be generated such that at least two adjacent ground selection transistors have the same threshold voltage state.

[0094] The expression "adjacent ground selection transistors" or ground selection transistors being adjacent to each other may refer to ground selection transistors that are physically adjacent to each other and connected in series among the ground selection transistors included in the same cell string. For example, the first a cell string CSa may include ground selection transistors GST1a, GST2a, GST3a, and GST4a connected in series. In this case, the first a ground selection transistor GST1a and the second a ground selection transistor GST2a may be adjacent ground selection transistors to each other. Alternatively, the third a ground selection transistor GST3a and the fourth a ground selection transistor GST4a may be adjacent ground selection transistors to each other. However, the present disclosure is not limited thereto.

[0095] In an embodiment, as Figure 7 shown, when the first a cell string CSa, the second b cell string CSb, the third c cell string CSc, and the fourth d cell string CSd sharing the ground selection line are electrically separated from each other, the GSL preset patterns for the first ground selection line GSL1 to the fourth ground selection line GSL4 may be determined as

[0011] ,

[0110] ,

[1100] , and

[1001] , respectively.

[0096] As an example, the GSL preset mode of the first select line GSL1 being

[0011] can mean that, through multi-GSL programming operations, the first select transistor GST1a of the first area is programmed to have an erase state "E", the first select transistor GST1b of the first area is programmed to have an erase state "E", the first select transistor GST1c of the first area is programmed to have the a programming state Pa, and the first select transistor GST1d of the first area is programmed to have the a programming state Pa. The GSL preset mode of the second select line GSL2 being

[0110] can mean that, through multi-GSL programming operations, the second select transistor GST2a of the second area is programmed to have an erase state "E", the second select transistor GST2b of the second area is programmed to have the a programming state Pa, the second select transistor GST2c of the second area is programmed to have the a programming state Pa, and the second select transistor GST2d of the second area is programmed to have an erase state "E". The GSL preset mode of the third select line GSL3 being

[1100] can mean that, through multi-GSL programming operations, the third select transistor GST3a of the third area is programmed to have the a programming state Pa, the third select transistor GST3b of the third area is programmed to have the a programming state Pa, the third select transistor GST3c of the third area is programmed to have an erase state "E", and the third select transistor GST3d of the third area is programmed to have an erase state "E". The GSL preset mode of the fourth select line GSL4 being

[1001] can mean that, through multi-GSL programming operations, the fourth select transistor GST4a of the fourth area is programmed to have the a programming state Pa, the fourth select transistor GST4b of the fourth area is programmed to have an erase state "E", the fourth select transistor GST4c of the fourth area is programmed to have an erase state "E", and the fourth select transistor GST4d of the fourth area is programmed to have the a programming state Pa.

[0097] In operation S123, the memory device 100 can execute a GSL encoding mode based on the GSL preset mode. For example, as Figure 7 shown, the GSL preset modes of the first select line GSL1 to the fourth select line GSL4 can be determined to be

[0011] ,

[0110] ,

[1100] , and

[1001] , respectively.

[0098] In this case, a first dummy ground selection line dGSL1 can be provided between the first ground selection line GSL1 and the substrate. The GSL preset mode of the first dummy ground selection line dGSL1 can correspond to the GSL preset mode of the first ground selection line GSL1. That is, the first dummy ground selection line dGSL1 can correspond to the mode of

[0011] . As described above, the second dummy ground selection line dGSL2 can be disposed between the fourth ground selection line GSL4 and the word lines (e.g., WL1 to WLn). The GSL preset mode of the second dummy ground selection line dGSL2 can correspond to the GSL preset mode of the fourth ground selection line GSL4. That is, the second dummy ground selection line dGSL2 can correspond to the mode of

[1001] .

[0099] In this case, the GSL coding mode can include the modes

[0011] ,

[0011] ,

[0110] ,

[1100] ,

[1001] , and

[1001] , which respectively correspond to the first dummy ground selection line dGSL1, the first ground selection line GSL1 to the fourth ground selection line GSL4, and the second dummy ground selection line dGSL2.

[0100] When the GSL coding mode is generated as Figure 7 shown, in each of the cell strings CSa to CSd, at least two adjacent ground selection transistors can have the same state. For example, in the a-th cell string CSa, the 3a-th ground selection transistor GST3a, the 4a-th ground selection transistor GST4a, and the 2a-th dummy ground selection transistor dGST2a can be adjacent ground selection transistors and can have the same programming state, i.e., the a-th programming state Pa. In the b-th cell string CSb, the 2b-th ground selection transistor GST2b and the 3b-th ground selection transistor GST3b can be adjacent ground selection transistors and can have the same programming state, i.e., the a-th programming state Pa. In the c-th cell string CSc, the 1c-th ground selection transistor GST1c, the 2c-th ground selection transistor GST2c, and the 1c-th dummy ground selection transistor dGST1c can be adjacent ground selection transistors and can have the same programming state, i.e., the a-th programming state Pa. In the d-th cell string CSd, the 1d-th ground selection transistor GST1d and the 1d-th dummy ground selection transistor dGST1d can be adjacent ground selection transistors and can have the same programming state, i.e., the a-th programming state Pa, and the 4d-th ground selection transistor GST4d and the 2d-th dummy ground selection transistor dGST2d can be adjacent ground selection transistors and can have the same programming state, i.e., the a-th programming state Pa. That is, through the above GSL coding mode, in each cell string, at least two adjacent ground selection transistors can have the same state.

[0101] Figure 8 is a flowchart showing Figure 5 operation S130. Figure 9 is a diagram for describing the operations of the flowchart according to Figure 8 . For ease of description, additional descriptions associated with the above components will be omitted to avoid redundancy.

[0102] Referring to Figure 1 , Figure 8 and Figure 9 , in operation S131, the memory device 100 may select "n" ground selection lines (n is a natural number of 2 or greater) based on the GSL coding pattern. In an embodiment, the "n" ground selection lines may be adjacent ground selection lines to each other.

[0103] For example, assume that the GSL coding pattern is the pattern described with reference to Figure 7 . That is, the GSL coding pattern may include patterns

[0011] ,

[0011] ,

[0110] ,

[1100] ,

[1001] , and

[1001] , which respectively correspond to a first dummy ground selection line dGSL1, a first ground selection line GSL1 to a fourth ground selection line GSL4, and a second dummy ground selection line dGSL2.

[0104] The memory device 100 may perform a multi-GSL programming operation on the ground selection transistors GST1a, GST2a, GST3a, and GST4a and the dummy ground selection transistors dGST1a and dGST2a of the a-th unit string CSa. According to the GSL coding pattern, the 3a-th ground selection transistor GST3a and the 4a-th ground selection transistor GST4a of the a-th unit string CSa and the 2a-th dummy ground selection transistor dGST2a may be programmed to the a-th programming state Pa. In this case, the third ground selection line GSL3 and the fourth ground selection line GSL4 connected to the ground selection transistors (e.g., GST3a and GST4a) to be programmed to the a-th programming state Pa may be selected.

[0105] In an embodiment, when generating a GSL preset pattern based on two adjacent ground selection transistors, two ground selection lines connected to the adjacent ground selection transistors corresponding to the same state may be selected. In an embodiment, when a dummy ground selection line is included in the ground selection lines connected to the adjacent ground selection transistors corresponding to the same state, two ground selection lines other than the dummy ground selection line may be selected. However, the present disclosure is not limited thereto. For example, the number of ground selection lines to be selected for the multi-GSL programming operation may be changed and modified differently, which will be described in detail by the following embodiments.

[0106] In operation S132, the memory device 100 may simultaneously apply a programming voltage to the selected "n" ground selection lines such that the ground selection transistors connected to the selected "n" ground selection lines are programmed simultaneously. For example, as Figure 9 shown, the third ground selection line GSL3 and the fourth ground selection line GSL4 may be selected to program the ground selection transistors GST3a and GST4a of the a-th cell string CSa to the a-th programming state Pa. The memory device 100 may simultaneously apply a programming voltage to the third ground selection line GSL3 and the fourth ground selection line GSL4, and may apply a voltage to the remaining lines (e.g., dGSL1, GSL1, GSL2, dGSL2, and WL1 to WLn). In addition, a power supply voltage (e.g., VCC) may be applied to the a-th string selection line SSLa connected to the a-th string selection transistor SSTa of the a-th cell string CSa which is the selected cell string, and a turn-off voltage (e.g., ground voltage) may be applied to the remaining string selection lines SSLb, SSLc, and SSLd. In this case, the 3a-th ground selection transistor GST3a and the 4a-th ground selection transistor GST4a of the a-th cell string CSa may be programmed simultaneously.

[0107] In an embodiment, the multi-GSL programming operation of simultaneously programming the 3a-th ground selection transistor GST3a and the 4a-th ground selection transistor GST4a may be performed based on an incremental step pulse programming (ISPP) scheme. For example, after applying a programming voltage to the third ground selection line GSL3 and the fourth ground selection line GSL4, the 3a-th ground selection transistor GST3a and the 4a-th ground selection transistor GST4a may be verified by applying a verification voltage to the third ground selection line GSL3 and the fourth ground selection line GSL4. When the result of verifying the programming states of the 3a-th ground selection transistor GST3a and the 4a-th ground selection transistor GST4a indicates a failure, a higher programming voltage may be applied to the third ground selection line GSL3 and the fourth ground selection line GSL4, and then the verification voltage may be applied to the third ground selection line GSL3 and the fourth ground selection line GSL4.

[0108] In an embodiment, the memory device 100 may set the threshold voltages of the ground selection transistors of the first memory block BLK1 by repeatedly performing operation S131 and operation S132 based on a GSL coding pattern.

[0109] For example, as Figure 9As shown, the memory device 100 may program the 3a-th ground selection transistor GST3a and the 4a-th ground selection transistor GST4a of the a-th cell string CSa simultaneously. The memory device 100 may program the 2a-th dummy ground selection transistor dGST2a of the a-th cell string CSa. The memory device 100 may program the 2b-th ground selection transistor GST2b and the 3b-th ground selection transistor GST3b of the b-th cell string CSb simultaneously. The memory device 100 may program the 1c-th ground selection transistor GST1c and the 2c-th ground selection transistor GST2c of the c-th cell string CSc simultaneously. The memory device 100 may program the 1c-th dummy ground selection transistor dGST1c. The memory device 100 may program the 1d-th dummy ground selection transistor dGST1d and the 1d-th ground selection transistor GST1d of the d-th cell string CSd simultaneously. The memory device 100 may program the 4d-th ground selection transistor GST4d and the 2d-th dummy ground selection transistor dGST2d simultaneously. In an embodiment, the above programming sequence is provided as an example, and the present disclosure is not limited thereto.

[0110] As described above, a GSL coding pattern may be generated such that adjacent ground selection transistors have the same state (e.g., the a-th programming state). The memory device 100 may program at least two adjacent ground selection transistors simultaneously based on the GSL coding pattern.

[0111] In an embodiment, at least two adjacent ground selection transistors may include dummy ground selection transistors. In this case, when the number of the remaining ground selection transistors other than the dummy ground selection transistors among at least two adjacent ground selection transistors is a multiple of a given number (e.g., two or more), the memory device 100 may program the remaining ground selection transistors simultaneously and may program the dummy ground selection transistors individually. Alternatively, when the number of at least two adjacent ground selection transistors including dummy ground selection transistors is a multiple of a given number (e.g., two or more), the memory device 100 may program at least two adjacent ground selection transistors including dummy ground selection transistors simultaneously.

[0112] According to the above embodiments, together with an adjacent ground selection transistor or an adjacent dummy ground selection transistor, the ground selection transistors (e.g., GST1a to GST4a, GST1b to GST4b, GST1c to GST4c, and GST1d to GST4d) that will be used to individually control cell strings are programmed simultaneously with respect to the ground selection transistors targeted at the a-th programming state Pa. For example, the 3a-th ground selection transistor GST3a and the 4a-th ground selection transistor GST4a of the a-th cell string CSa are programmed simultaneously; the 2b-th ground selection transistor GST2b and the 3b-th ground selection transistor GST3b of the b-th cell string CSb are programmed simultaneously; the 1c-th ground selection transistor GST1c and the 2c-th ground selection transistor GST2c of the c-th cell string CSc are programmed simultaneously. In addition, in the d-th cell string CSd, the 1d-th ground selection transistor GST1d is programmed simultaneously with the 1d-th dummy ground selection transistor dGST1d, and the 4d-th ground selection transistor GST4d is programmed simultaneously with the 2d-th dummy ground selection transistor dGST2d. In this case, the cell characteristics of the ground selection transistors (e.g., GST1a to GST4a, GST1b to GST4b, GST1c to GST4c, and GST1d to GST4d) that will be used to individually control cell strings can be improved. For example, the holding characteristics of the ground selection transistors can be improved, the ground selection transistors can be strengthened against read interference, and hot electron injection in the ground selection transistors can be reduced. Therefore, the reliability and performance of the memory device 100 can be improved.

[0113] In an embodiment, in order to select a specific cell string during the operation of the memory device 100, the same bias can be provided to at least two adjacent ground selection lines based on the GSL coding pattern.

[0114] For example, when selecting the a-th cell string CSa, the second turn-on voltage VON2 can be applied to the third ground selection line GSL3 and the fourth ground selection line GSL4, the first turn-on voltage VON1 can be applied to the first ground selection line GSL1 and the second ground selection line GSL2, and the second turn-on voltage VON2 can be applied to the first dummy ground selection line dGSL1 and the second dummy ground selection line dGSL2. In this case, the ground selection transistors GST1a to GST4a of the a-th cell string CSa are turned on, the 2b-th ground selection transistor GST2b of the b-th cell string CSb is turned off, the 1c-th ground selection transistor GST1c and the 2c-th ground selection transistor GST2c of the c-th cell string CSc are turned off, and the 1d-th ground selection transistor GST1d of the d-th cell string CSd is turned off. Therefore, the remaining cell strings CSb, CSc, and CSd except for the a-th cell string CSa can be electrically separated from the common source line CSL.

[0115] As described above, when selecting the b-th cell string CSb, the second turn-on voltage VON2 can be applied to the second ground selection line GSL2 and the third ground selection line GSL3, the first turn-on voltage VON1 can be applied to the first ground selection line GSL1 and the fourth ground selection line GLS4, and the second turn-on voltage VON2 can be applied to the first dummy ground selection line dGSL1 and the second dummy ground selection line dGSL2. In this case, the ground selection transistors GST1b to GST4b of the b-th cell string CSb are turned on, the 4a-th ground selection transistor GST4a of the a-th cell string CSa is turned off, the 1c-th ground selection transistor GST1c of the c-th cell string CSc is turned off, and the 1d-th to 4d-th ground selection transistors GST1d to GST4d of the d-th cell string CSd are turned off. Therefore, the remaining cell strings CSa, CSc, and CSd except for the b-th cell string CSb can be electrically separated from the common source line CSL.

[0116] Figure 10 is for describing the operation of programming the 3a-th and 4a-th ground selection transistors of the first memory block simultaneously Figure 9 is a diagram. Figure 11 shows according to Figure 10 the threshold voltage distributions of the ground selection transistors programmed according to the embodiments of

[0117] In an embodiment, Figure 10 is a vertical cross-sectional view showing the a-th cell string CSa and the b-th cell string CSb. For ease of description, some components are omitted. However, the present disclosure is not limited thereto.

[0118] Referring to Figure 1 , Figure 8 , Figure 9 , Figure 10 and Figure 11 , the first dummy ground selection line dGSL1, the first to fourth ground selection lines GSL1 to GSL4, the word lines WL1 to WLn, and the string selection lines SSLa and SSLb can be stacked on the substrate SUB.

[0119] The horizontal insulating pattern HL may be formed to extend along the upper surfaces, lower surfaces, and sidewalls (or lateral surfaces) of each of the first dummy ground selection line dGSL1, the first ground selection line GSL1 to the fourth ground selection line GSL4, the word lines WL1 to WLn, and the string selection lines SSLa and SSLb. In an embodiment, the horizontal insulating pattern HL may form part of a data storage layer for storing data. The horizontal insulating pattern HL may be implemented with one of high-k dielectric layers such as a silicon oxide layer and a hafnium oxide layer, and may be formed of a material having a dielectric constant less than that of the blocking insulating layer BIL. The a-th string selection line SSLa and the b-th string selection line SSLb may be electrically separated from each other by a separation insulating pattern SPR.

[0120] A plurality of vertical structures (e.g., VS (refer to Figure 3 )) may be formed to extend in a direction perpendicular to the substrate SUB through the first dummy ground selection line dGSL1, the first ground selection line GSL1 to the fourth ground selection line GSL4, the word lines WL1 to WLn, and the string selection lines SSLa and SSLb. Each of the plurality of vertical structures (e.g., VS (refer to Figure 3 )) may include a vertical pattern VP and a data storage pattern DS.

[0121] The vertical pattern VP may include a semiconductor material and may serve as the channel of the unit transistors (e.g., GST, MC, and SST) included in each of the a-th unit string CSa and the b-th unit string CSb.

[0122] The data storage pattern DS may be disposed to surround the vertical pattern VP and may include a charge storage layer configured to store data. For example, the data storage pattern DS may include a tunnel insulating layer TIL, a charge storage layer CIL, and a blocking insulating layer BIL. The charge storage layer CIL may be one of an insulating layer having many trap sites and an insulating layer including nanoparticles. For example, the charge storage layer CIL may include one of a trap insulating layer, a floating gate electrode, and an insulating layer including conductive nanodots.

[0123] In an embodiment, the data storage pattern DS may extend in a direction perpendicular to the substrate SUB while intersecting the sidewalls of the first dummy ground selection line dGSL1, the first ground selection line GSL1 to the fourth ground selection line GSL4, the second dummy ground selection line dGSL2, the word lines WL1 to WLn, and the string selection lines SSLa and SSLb. The bit line BL may be formed on the vertical structure and may be electrically connected to the vertical structure through a contact plug PLG.

[0124] The above cross-sectional structure of the first memory block BLK1 is provided as an example, and the present disclosure is not limited thereto.

[0125] In an embodiment, the vertical structure that runs through the a-th string selection line SSLa is the a-th unit string CSa. In this case, the first dummy ground selection line dGSL1, and the data storage pattern DS and the vertical pattern VS adjacent thereto can form the 1a-th dummy ground selection transistor dGST1a; the first ground selection line GSL1 to the fourth ground selection line GSL4, and the data storage pattern DS and the vertical pattern VS adjacent thereto can respectively form the 1a-th ground selection transistor GST1a to the 4a-th ground selection transistor GST4a; the second dummy ground selection line dGSL2, and the data storage pattern DS and the vertical pattern VS adjacent thereto can form the 2a-th dummy ground selection transistor dGST2a; the first word line WL1 to the n-th word line WLn, and the data storage pattern DS and the vertical pattern VS adjacent thereto can respectively form the first memory cell MC1 to the n-th memory cell MCn; and the a-th string selection line SSLa, and the data storage pattern DS and the vertical pattern VS adjacent thereto can form the a-th string selection transistor SSTa.

[0126] In this case, charges can be trapped in the data storage pattern DS corresponding to each cell transistor due to the voltage applied to each line. This can mean that the threshold voltage of each cell transistor is changed.

[0127] According to an embodiment of the present disclosure, at least two adjacent ground selection transistors are programmed simultaneously. For example, as Figure 10 shown, the 3a-th ground selection transistor GST3a and the 4a-th ground selection transistor GST4a of the a-th unit string CSa can be programmed simultaneously. In this case, the power supply voltage VCC can be applied to the a-th string selection line SSLa; the turn-off voltage VOFF (e.g., ground voltage or negative voltage) can be applied to the b-th string selection line SSLb; the pass voltage VPASS can be applied to the plurality of word lines WL1 to WLn, the first dummy ground selection line dGSL1 and the second dummy ground selection line dGSL2, and the first ground selection line GSL1 and the second ground selection line GSL2; and the programming voltage VPGM can be applied to the third ground selection line GSL3 and the fourth ground selection line GSL4. According to the above bias conditions, charges can be trapped in the data storage pattern DS adjacent to the third ground selection line GSL3 and the fourth ground selection line GSL4. That is to say, the 3a-th ground selection transistor GST3a and the 4a-th ground selection transistor GST4a can be programmed. Or, the threshold voltages of the 3a-th ground selection transistor GST3a and the 4a-th ground selection transistor GST4a can be increased.

[0128] In this case, the cell characteristics of the third selected transistor GST3a and the fourth selected transistor GST4a can be improved. For example, the threshold voltage of a cell transistor can be determined by the charge trapped in the data storage pattern corresponding to the cell transistor. The charge trapped in the data storage pattern can diffuse over time to any other adjacent region. In this case, the threshold voltage of the corresponding cell transistor can decrease. In contrast, the threshold voltages of the third selected transistor GST3a and the fourth selected transistor GST4a are determined by the charge trapped in the data storage pattern DS (e.g., region A) adjacent to the third ground selection line GSL3 and the fourth ground selection line GSL4. In this case, since the region where the charge is trapped is relatively wide, the charge diffusion phenomenon may occur relatively less frequently. In other words, when programming the third selected transistor GST3a and the fourth selected transistor GST4a simultaneously, the retention characteristics can be improved.

[0129] Alternatively, when the memory device 100 operates, read interference may occur in the ground selection transistors. In this case, the threshold voltages of the ground selection transistors may increase. However, according to an embodiment of the present disclosure, since at least two adjacent ground selection lines are biased identically, at least two adjacent ground selection transistors connected to the at least two adjacent ground selection lines operate like a single cell transistor. In this case, since there is an effect of increasing the cell size, read interference in the ground selection transistors can be prevented or reduced.

[0130] Alternatively, when the memory device 100 operates, a potential difference may be generated in the cell string channel under specific biasing conditions. In this case, hot carrier injection (HCI) may occur. This may mean that the threshold voltage of the cell transistor increases due to hot carrier injection. However, according to an embodiment of the present disclosure, at least two adjacent ground selection transistors can be programmed simultaneously, and thus hot carrier injection can be prevented or mitigated.

[0131] For example, as Figure 11 shown, at least two adjacent ground selection transistors can be programmed simultaneously to have the a-th programming state Pa. In this case, the a-th programming state Pa of the at least two adjacent ground selection transistors can be verified by using the verification voltage VVFY.

[0132] In an embodiment, the threshold voltages of at least two adjacent ground selection transistors may be distributed as the b-th programming state Pb. In this case, the lower limit value of the b-th programming state Pb may be a first level VL1, and the first level VL1 may be lower than the verification voltage VVFY. That is, even if at least two adjacent ground selection transistors are simultaneously programmed to have the a-th programming state Pa, each of the at least two adjacent ground selection transistors may have the b-th programming state Pb with a level lower than the a-th programming state Pa, and thus, the potential difference in the cell string channel under a specific bias condition can be reduced. Therefore, hot electron injection can be prevented or alleviated.

[0133] As described above, according to an embodiment of the present disclosure, a plurality of cell strings may be separately connected to a plurality of string selection lines, respectively, and may share the same ground selection line. In this case, the threshold voltages of the plurality of ground selection transistors may be separately set to separately control the plurality of cell strings, and the GSL coding pattern may be determined such that at least two adjacent ground selection transistors have the same state. The memory device 100 may program at least two adjacent ground selection transistors simultaneously based on the GSL coding pattern. Therefore, the change in the threshold voltage of the ground selection transistors due to various factors can be prevented or minimized. This may mean that the reliability and performance of the memory device 100 are improved.

[0134] The GSL coding pattern according to various structures of the memory block will be described with reference to the following drawings. For ease of description, additional descriptions associated with the above components will be omitted to avoid redundancy.

[0135] Figure 12A and Figure 12B are diagrams for describing the GSL coding pattern according to an embodiment of the present disclosure. Referring to Figure 1 、 Figure 12A and Figure 12B , the memory block included in the memory device 100 may have a 4SSL-1GSL structure. It may be necessary to electrically distinguish four cell strings. In this case, the GSL preset pattern may be generated as shown in Figure 12A . For example, the GSL preset pattern may include patterns

[0011] ,

[0110] ,

[1100] , and

[1001] for the first ground selection line GSL1 to the fourth ground selection line GSL4. Referring to Figure 7 to describe Figure 12A 's GSL preset pattern, and thus, additional descriptions will be omitted to avoid redundancy.

[0136] In an embodiment, a first dummy ground selection line dGSL1 to a fifth dummy ground selection line dGSL5 may be provided. The first dummy ground selection line dGSL1 may be disposed between a substrate (or a common source line CSL) and a first ground selection line GSL1, the second dummy ground selection line dGSL2 may be disposed between the first ground selection line GSL1 and a second ground selection line GSL2, the third dummy ground selection line dGSL3 may be disposed between the second ground selection line GSL2 and a third ground selection line GSL3, the fourth dummy ground selection line dGSL4 may be disposed between the third ground selection line GSL3 and a fourth ground selection line GSL4, and the fifth dummy ground selection line dGSL5 may be disposed between the fourth ground selection line GSL4 and word lines WL1 to WLn.

[0137] In this case, a GSL coding pattern may be generated based on a GSL preset pattern such that at least “i” adjacent ground selection transistors have the same state (i is a multiple of a given number).

[0138] For example, the first dummy ground selection line dGSL1 may be set to the same pattern as the first ground selection line GSL1 (i.e.,

[0011] ). Associated with the second dummy ground selection line dGSL2, since the first ground selection transistor GST1c and the second ground selection transistor GST2c of the c-th cell string CSc are programmed to the a-th programming state Pa, the second dummy ground selection line dGSL2 may be set to the pattern

[0110] . Associated with the third dummy ground selection line dGSL3, since the second ground selection transistor GST2b and the third ground selection transistor GST3b of the b-th cell string CSb are programmed to the a-th programming state Pa, the third dummy ground selection line dGSL3 may be set to the pattern

[0100] . Associated with the fourth dummy ground selection line dGSL4, since the third ground selection transistor GST3a and the fourth ground selection transistor GST4a of the a-th cell string CSa are programmed to the a-th programming state Pa, and the number of adjacent ground selection transistors dGST2b, GST2b, dGST3b, and GST3b having the same state in the b-th cell string CSb is “4”, the fourth dummy ground selection line dGSL4 may be set to the pattern

[1000] . The fifth dummy ground selection line dGSL5 may be set to the same pattern as the fourth ground selection line GSL4 (i.e.,

[1001] ).

[0139] When the patterns for the dummy ground selection lines dGSL1 to dGSL5 are set as described above, the number of adjacent ground selection transistors having the same state in each cell string may be “i” (i is a multiple of a given number (e.g., a multiple of 2)).

[0140] The memory device 100 may perform a multi-GSL programming operation based on the generated GSL coding pattern. For example, asFigure 12B As shown, associated with the a-th unit string CSa, the memory device 100 can program the 3a-th ground selection transistor GST3a and the 4a-th dummy ground selection transistor dGST4a simultaneously, and can program the 4a-th ground selection transistor GST4a and the 5a-th dummy ground selection transistor dGST5a simultaneously. Associated with the b-th unit string CSb, the memory device 100 can program the 2b-th dummy ground selection transistor dGST2b and the 2b-th ground selection transistor GST2b simultaneously, and can program the 3b-th dummy ground selection transistor dGST3b and the 3b-th ground selection transistor GST3b simultaneously. Associated with the c-th unit string CSc, the memory device 100 can program the 1c-th dummy ground selection transistor dGST1c and the 1c-th ground selection transistor GST1c simultaneously, and can program the 2c-th dummy ground selection transistor dGST2c and the 2c-th ground selection transistor GST2c simultaneously. Associated with the d-th unit string CSd, the memory device 100 can program the 1d-th dummy ground selection transistor dGST1d and the 1d-th ground selection transistor GST1d simultaneously, and can program the 4d-th ground selection transistor GST4d and the 5d-th dummy ground selection transistor dGST5d simultaneously.

[0141] In an embodiment, when the a-th unit string CSa is selected, the second turn-on voltage VON2 can be applied to the third ground selection line GSL3 and the fourth ground selection line GSL4, the second turn-on voltage VON2 can be applied to the dummy ground selection lines dGSL1 to dGSL5, and the first turn-on voltage VON1 can be applied to the first ground selection line GSL1 and the second ground selection line GSL2. In this case, all the ground selection transistors of the a-th unit string CSa are turned on, the 2b-th ground selection transistor GST2b of the b-th unit string CSb is turned off, the 1c-th ground selection transistor GST1c of the c-th unit string CSc is turned off, and the 1d-th ground selection transistor GST1d of the d-th unit string CSd is turned off. Thus, the remaining unit strings CSb, CSc, and CSd except for the a-th unit string CSa which is the selected unit string can be electrically separated from the common source line CSL.

[0142] Figure 13 is a diagram for describing the GSL coding pattern according to an embodiment of the present disclosure. Refer to Figure 1 and Figure 13 , the memory blocks included in the memory device 100 can have a 4SSL-1GSL structure. It may be necessary to electrically distinguish four unit strings. In this case, as Figure 13The GSL preset patterns shown are generated. For example, the GSL preset patterns may include the patterns

[0001] ,

[0010] ,

[0100] , and

[1000] for the first ground selection line GSL1 to the fourth ground selection line GSL4.

[0143] In an embodiment, a first dummy ground selection line dGSL1, a third dummy ground selection line dGSL3, and a fifth dummy ground selection line dGSL5 may be provided. The first dummy ground selection line dGSL1 may be provided between the substrate (or common source line CSL) and the first ground selection line GSL1, the third dummy ground selection line dGSL3 may be provided between the second ground selection line GSL2 and the third ground selection line GSL3, and the fifth dummy ground selection line dGSL5 may be provided between the fourth ground selection line GSL4 and the word lines WL1 to WLn.

[0144] In this case, a GSL encoding pattern may be generated based on the GSL preset pattern such that at least “i” adjacent ground selection transistors have the same state (i is a multiple of a given number).

[0145] For example, the first dummy ground selection line dGSL1 may be set to the same pattern as the first ground selection line GSL1 (i.e.,

[0001] ). The third dummy ground selection line dGSL3 may be set to

[0110] based on the patterns of the second ground selection line GSL2 and the third ground selection line GSL3. The fifth dummy ground selection line dGSL5 may be set to the same pattern as the fourth ground selection line GSL4 (i.e.,

[1000] ).

[0146] When the patterns for the dummy ground selection lines dGSL1, dGSL3, and dGSL5 are set as described above, the number of adjacent ground selection transistors having the same state in each cell string may be “2”. That is, a GSL encoding pattern may be generated such that at least two adjacent ground selection transistors have the same state.

[0147] Figure 14A and Figure 14B are diagrams for describing the GSL encoding pattern according to an embodiment of the present disclosure. Refer to Figure 1 , Figure 14A and Figure 14B , the memory blocks included in the memory device 100 may have an 8SSL-1GSL structure. That is, eight cell strings may be respectively connected to eight string selection lines and may have the same ground selection line. In this case, it may be necessary to electrically distinguish the eight cell strings. In this case, the GSL preset patterns may be generated as Figure 14A shown.

[0148] For example, the first ground selection line GSL1 can be set to the pattern [00000011], the second ground selection line GSL2 can be set to the pattern [00000110], the third ground selection line GSL3 can be set to the pattern [00001100], the fourth ground selection line GSL4 can be set to the pattern [00011000], the fifth ground selection line GSL5 can be set to the pattern [00110000], the sixth ground selection line GSL6 can be set to the pattern [01100000], the seventh ground selection line GSL7 can be set to the pattern [11000000], and the eighth ground selection line GSL8 can be set to the pattern [10000001].

[0149] In an embodiment, a first dummy ground selection line dGSL1 and a second dummy ground selection line dGSL2 can be provided. The first dummy ground selection line dGSL1 can be provided between the substrate (or common source line CSL) and the first ground selection line GSL1, and the second dummy ground selection line dGSL2 can be provided between the eighth ground selection line GSL8 and the plurality of word lines WL1 to WLn.

[0150] In this case, a GSL coding pattern can be generated based on the GSL preset pattern. For example, the first dummy ground selection line dGSL1 can be set to the same pattern as the first ground selection line GSL1 (i.e., [00000011]). The second dummy ground selection line dGSL2 can be set to the same pattern as the eighth ground selection line GSL8 (i.e., [10000001]).

[0151] When the patterns for the dummy ground selection lines dGSL1 and dGSL2 are set as described above, the number of adjacent ground selection transistors having the same state in each cell string can be "at least 2 or more".

[0152] The memory device 100 can perform a multi-GSL programming operation based on the GSL coding pattern. For example, as Figure 14BAs shown, associated with the a-th unit string CSa, the memory device 100 can program the 7a-th ground selection transistor GST7a and the 8a-th ground selection transistor GST8a simultaneously, and can program the 2a-th dummy ground selection transistor dGST2a. Associated with the b-th unit string CSb, the memory device 100 can program the 6b-th ground selection transistor GST6b and the 7b-th ground selection transistor GST7b simultaneously. Associated with the c-th unit string CSc, the memory device 100 can program the 5c-th ground selection transistor GST5c and the 6c-th ground selection transistor GST6c simultaneously. Associated with the d-th unit string CSd, the memory device 100 can program the 4d-th ground selection transistor GST4d and the 5d-th ground selection transistor GST5d simultaneously. Associated with the e-th unit string CSe, the memory device 100 can program the 3e-th ground selection transistor GST3e and the 4e-th ground selection transistor GST4e simultaneously. Associated with the f-th unit string CSf, the memory device 100 can program the 2f-th ground selection transistor GST2f and the 3f-th ground selection transistor GST3f simultaneously. Associated with the g-th unit string CSg, the memory device 100 can program the 1g-th ground selection transistor GST1g and the 2g-th ground selection transistor GST2g simultaneously, and can program the 1g-th dummy ground selection transistor dGST1g. Associated with the h-th unit string CSh, the memory device 100 can program the 1h-th dummy ground selection transistor dGST1h and the 1h-th ground selection transistor GST1h simultaneously, and can program the 8h-th ground selection transistor GST8h and the 2h-th dummy ground selection transistor dGST2h simultaneously.

[0153] As described above, since at least two adjacent ground selection transistors are programmed simultaneously for each of the multiple unit strings CSa to CSh, the reliability and performance of the memory device 100 can be improved.

[0154] Figure 15A and Figure 15B are diagrams for describing the GSL coding pattern according to an embodiment of the present disclosure. Refer to Figure 1 、 Figure 15A and Figure 15B , the memory blocks included in the memory device 100 may have an 8SSL-1GSL structure. That is, eight unit strings can be respectively connected to eight string selection lines and can have the same ground selection line. In this case, it may be necessary to electrically distinguish the eight unit strings. In this case, the GSL preset pattern can be generated as shown in Figure 15A .

[0155] The first ground selection line GSL1 can be set to the pattern [00001111], the second ground selection line GSL2 can be set to the pattern [00011110], the third ground selection line GSL3 can be set to the pattern [00111100], the fourth ground selection line GSL4 can be set to the pattern [01111000], the fifth ground selection line GSL5 can be set to the pattern [11110000], the sixth ground selection line GSL6 can be set to the pattern [11100001], the seventh ground selection line GSL7 can be set to the pattern [11000011], and the eighth ground selection line GSL8 can be set to the pattern [10000111].

[0156] As described above, the first dummy ground selection line dGSL1 can be disposed between the substrate (or common source line CSL) and the first ground selection line GSL1, and the second dummy ground selection line dGSL2 can be disposed between the eighth ground selection line GSL8 and the plurality of word lines WL1 to WLn.

[0157] In this case, a GSL encoding pattern can be generated based on the GSL preset pattern. For example, the first dummy ground selection line dGSL1 can be set to the same pattern as the first ground selection line GSL1 (i.e., [00001111]). The second dummy ground selection line dGSL2 can be set to the same pattern as the eighth ground selection line GSL8 (i.e., [10000111]).

[0158] When the patterns for the dummy ground selection lines dGSL1 and dGSL2 are set as described above, the number of adjacent ground selection transistors having the same state in each cell string can be "at least 2 or more".

[0159] The memory device 100 can perform a multi-GSL programming operation based on the GSL encoding pattern. For example, as Figure 15BAs shown, associated with the a-th unit string CSa, the memory device 100 can program the 5a-th ground selection transistor GST5a and the 6a-th ground selection transistor GST6a simultaneously, can program the 7a-th ground selection transistor GST7a and the 8a-th ground selection transistor GST8a simultaneously, and can program the 2a-th dummy ground selection transistor dGST2a. Associated with the b-th unit string CSb, the memory device 100 can program the 4b-th ground selection transistor GST4b and the 5b-th ground selection transistor GST5b simultaneously, and can program the 6b-th ground selection transistor GST6b and the 7b-th ground selection transistor GST7b simultaneously. Associated with the c-th unit string CSc, the memory device 100 can program the 3c-th ground selection transistor GST3c and the 4c-th ground selection transistor GST4c simultaneously, and can program the 5c-th ground selection transistor GST5c and the 6c-th ground selection transistor GST6c simultaneously. Associated with the d-th unit string CSd, the memory device 100 can program the 2d-th ground selection transistor GST2d and the 3d-th ground selection transistor GST3d simultaneously, and can program the 4d-th ground selection transistor GST4d and the 5d-th ground selection transistor GST5d simultaneously. Associated with the e-th unit string CSe, the memory device 100 can program the 1e-th ground selection transistor GST1e and the 2e-th ground selection transistor GST2e simultaneously, can program the 3e-th ground selection transistor GST3e and the 4e-th ground selection transistor GST4e simultaneously, and can program the 1e-th dummy ground selection transistor dGST1e. Associated with the f-th unit string CSf, the memory device 100 can program the 1f-th dummy ground selection transistor dGST1f and the 1f-th ground selection transistor GST1f simultaneously, and can program the 2f-th ground selection transistor GST2f and the 3f-th ground selection transistor GST3f simultaneously. In some embodiments, the memory device 100 can also program the 8f-th ground selection transistor GST8f and the 2f-th dummy ground selection transistor dGST2f simultaneously. Associated with the g-th unit string CSg, the memory device 100 can program the 1g-th ground selection transistor GST1g and the 2g-th ground selection transistor GST2g simultaneously, can program the 7g-th ground selection transistor GST7g and the 8g-th ground selection transistor GST8g simultaneously, can program the 1g-th dummy ground selection transistor dGST1g, and can program the 2g-th dummy ground selection transistor dGST2g.Associated with the h-th unit string CSh, the memory device 100 can program the 1h-th dummy ground selection transistor dGST1h and the 1h-th ground selection transistor GST1h simultaneously, can program the 6h-th ground selection transistor GST6h and the 7h-th ground selection transistor GST7h simultaneously, and can program the 8h-th ground selection transistor GST8h and the 2h-th dummy ground selection transistor dGST2h simultaneously.

[0160] As described above, since at least two adjacent ground selection transistors are programmed simultaneously for each of the multiple unit strings CSa to CSh, the reliability and performance of the memory device 100 can be improved.

[0161] Figure 16A and Figure 16B are diagrams for describing the GSL coding pattern according to an embodiment of the present disclosure. Refer to Figure 1 、 Figure 16A and Figure 16B , the memory blocks included in the memory device 100 can have an 8SSL-1GSL structure. That is, eight unit strings can be respectively connected to eight string selection lines and can have the same ground selection line. In this case, it may be necessary to electrically distinguish the eight unit strings. In this case, the GSL preset pattern can be generated as shown in Figure 16A .

[0162] In the above embodiment, the GSL preset pattern is generated based on multiples of 2. That is, similar to [00000011], [00001111], etc., in the pattern corresponding to one ground selection line, the GSL preset pattern is generated such that two or four ground selection transistors have the a-th programming state. However, the present disclosure is not limited thereto, and the GSL preset pattern can be generated based on 2 or a larger natural number.

[0163] For example, as shown in Figure 16A , the GSL preset pattern can be generated based on "3". For example, the first ground selection line GSL1 can be set to the pattern [00000111], the second ground selection line GSL2 can be set to the pattern [000001110], the third ground selection line GSL3 can be set to the pattern [00011100], the fourth ground selection line GSL4 can be set to the pattern [00111000], the fifth ground selection line GSL5 can be set to the pattern [01110000], the sixth ground selection line GSL6 can be set to the pattern [11100000], the seventh ground selection line GSL7 can be set to the pattern [11000001], and the eighth ground selection line GSL8 can be set to the pattern [10000011].

[0164] As described above, the first dummy ground selection line dGSL1 can be disposed between the substrate (or the common source line CSL) and the first ground selection line GSL1, and the second dummy ground selection line dGSL2 can be disposed between the eighth ground selection line GSL8 and the plurality of word lines WL1 to WLn.

[0165] In this case, the GSL coding pattern can be generated based on the GSL preset pattern. For example, the first dummy ground selection line dGSL1 can be set to the same pattern as the first ground selection line GSL1 (i.e., [00000111]). The second dummy ground selection line dGSL2 can be set to the same pattern as the eighth ground selection line GSL8 (i.e., [10000011]).

[0166] When the patterns for the dummy ground selection lines dGSL1 and dGSL2 are set as described above, the number of adjacent ground selection transistors having the same state in each cell string can be "at least 2 or more".

[0167] The memory device 100 can perform a multi-GSL programming operation based on the GSL coding pattern. In the above embodiment, the memory device 100 can program two adjacent ground selection transistors simultaneously, but the present disclosure is not limited thereto. For example, the memory device 100 can program "n" adjacent ground selection transistors simultaneously (n is a natural number of 2 or greater).

[0168] For example, as Figure 16BAs shown, associated with the a-th cell string CSa, the memory device 100 can program the 6a-th ground selection transistor GST6a and the 7a-th ground selection transistor GST7a simultaneously, and can program the 8a-th ground selection transistor GST8a and the 2a-th dummy ground selection transistor dGST2a simultaneously. Associated with the b-th cell string CSb, the memory device 100 can program the 5b-th ground selection transistor GST5b, the 6b-th ground selection transistor GST6b, and the 7b-th ground selection transistor GST7b simultaneously. Associated with the c-th cell string CSc, the memory device 100 can program the 4c-th ground selection transistor GST4c, the 5c-th ground selection transistor GST5c, and the 6c-th ground selection transistor GST6c simultaneously. Associated with the d-th cell string CSd, the memory device 100 can program the 3d-th ground selection transistor GST3d, the 4d-th ground selection transistor GST4d, and the 5d-th ground selection transistor GST5d simultaneously. Associated with the e-th cell string CSe, the memory device 100 can program the 2e-th ground selection transistor GST2e, the 3e-th ground selection transistor GST3e, and the 4e-th ground selection transistor GST4e simultaneously. Associated with the f-th cell string CSf, the memory device 100 can program the 1f-th dummy ground selection transistor dGST1f and the 1f-th ground selection transistor GST1f simultaneously, and can program the 2f-th ground selection transistor GST2f and the 3f-th ground selection transistor GST3f simultaneously. Associated with the g-th cell string CSg, the memory device 100 can program the 1g-th dummy ground selection transistor dGST1g, the 1g-th ground selection transistor GST1g, and the 2g-th ground selection transistor GST2g simultaneously, and can program the 8g-th ground selection transistor GST8g and the 2g-th dummy ground selection transistor dGST2g simultaneously. Associated with the h-th cell string CSh, the memory device 100 can program the 1h-th dummy ground selection transistor dGST1h and the 1h-th ground selection transistor GST1h simultaneously, and can program the 7h-th ground selection transistor GST7h, the 8h-th ground selection transistor GST8h, and the 2h-th dummy ground selection transistor dGST2h simultaneously.

[0169] As described above, the memory device 100 may perform a multi-GSL programming operation based on a GSL coding pattern such that at least two adjacent ground selection transistors are programmed simultaneously. In this case, the number of adjacent ground selection transistors to be programmed simultaneously may be a natural number of 2 or greater. In the above embodiment, when adjacent ground selection transistors having the same state include dummy ground selection transistors and the number of adjacent ground selection transistors is a multiple of a given number, the dummy ground selection transistors may be programmed individually. However, the present disclosure is not limited thereto. For example, the number of adjacent ground selection transistors to be programmed simultaneously may be changed or modified differently such that the dummy ground selection transistors are programmed simultaneously with any other ground selection transistors. For example, as Figure 15B shown, the 5a-th ground selection transistor GST5a, the 6a-th ground selection transistor GST6a, the 7a-th ground selection transistor GST7a, and the 8a-th ground selection transistor GST8a of the a-th cell string CSa and the 2a-th dummy ground selection transistor dGST2a may be programmed to the a-th programming state Pa. In this case, the memory device 100 may program the 5a-th ground selection transistor GST5a and the 6a-th ground selection transistor GST6a simultaneously, and may program the 7a-th ground selection transistor GST7a, the 8a-th ground selection transistor GST8, and the 2a-th dummy ground selection transistor dGST2a simultaneously. That is, on the dummy ground selection line, when the number of ground selection transistors to be programmed is 5, the memory device 100 may program two ground selection transistors simultaneously and may program the remaining three ground selection transistors simultaneously.

[0170] The above order of the multi-GSL programming operation and the number of ground selection transistors to be programmed simultaneously may be changed and modified differently, and the present disclosure is not limited thereto.

[0171] Figure 17A and Figure 17B are diagrams for describing a GSL coding pattern according to an embodiment of the present disclosure. Referring to Figure 1 、 Figure 17A and Figure 17B , a memory block included in the memory device 100 may have an 8SSL-1GSL structure. That is, eight cell strings may be respectively connected to eight string selection lines and may have the same ground selection line. In this case, it may be necessary to electrically distinguish the eight cell strings. In this case, a GSL preset pattern may be generated as Figure 17A shown.

[0172] For example, the first ground selection line GSL1 can be set to the pattern [11111100], the second ground selection line GSL2 can be set to the pattern [11111001], the third ground selection line GSL3 can be set to the pattern [11110011], the fourth ground selection line GSL4 can be set to the pattern [11100111], the fifth ground selection line GSL5 can be set to the pattern [11001111], the sixth ground selection line GSL6 can be set to the pattern [10011111], the seventh ground selection line GSL7 can be set to the pattern [00111111], and the eighth ground selection line GSL8 can be set to the pattern [01111110].

[0173] In an embodiment, a first dummy ground selection line dGSL1 and a second dummy ground selection line dGSL2 can be set. The first dummy ground selection line dGSL1 can be set between the substrate (or common source line CSL) and the first ground selection line GSL1, and the second dummy ground selection line dGSL2 can be set between the eighth ground selection line GSL8 and the plurality of word lines WL1 to WLn.

[0174] In this case, a GSL encoding pattern can be generated based on the GSL preset pattern. For example, the first dummy ground selection line dGSL1 can be set to the same pattern as the first ground selection line GSL1 (i.e., [11111100]). The second dummy ground selection line dGSL2 can be set to the same pattern as the eighth ground selection line GSL8 (i.e., [01111110]).

[0175] The memory device 100 can perform a multi-GSL programming operation based on the GSL encoding pattern. For example, as Figure 17B shown, the memory device 100 can program at least two adjacent ground selection transistors simultaneously based on the GSL encoding pattern. Figure 17B The multi-GSL programming operation of the ground selection transistors of the memory device 100 shown is similar to the method described above, and thus, additional description will be omitted to avoid redundancy.

[0176] Figure 18 is a diagram for describing a GSL encoding pattern according to an embodiment of the present disclosure. Referring to Figure 1 and Figure 18 , the memory blocks included in the memory device 100 can have an 8SSL-1GSL structure. That is, eight cell strings can be respectively connected to eight string selection lines and can have the same ground selection line. In this case, it may be necessary to electrically distinguish four cell string groups. In this case, a GSL preset pattern can be generated as Figure 18 shown.

[0177] For example, the number of unit strings (or the number of groups of unit strings) to be electrically separated may be 4. In this case, a GSL preset pattern can be generated for four ground selection lines GSL1 to GSL4. The first ground selection line GSL1 can be set to the pattern [00001111], the second ground selection line GSL2 can be set to the pattern [00111100], the third ground selection line GSL3 can be set to the pattern [11110000], and the fourth ground selection line GSL4 can be set to the pattern [11000011].

[0178] As described above, the first dummy ground selection line dGSL1 can be disposed between the substrate (or the common source line CSL) and the first ground selection line GSL1, and the second dummy ground selection line dGSL2 can be disposed between the fourth ground selection line GSL4 and the plurality of word lines WL1 to WLn.

[0179] In this case, a GSL coding pattern can be generated based on the GSL preset pattern. For example, the first dummy ground selection line dGSL1 can be set to the same pattern as the first ground selection line GSL1 (i.e., [00001111]). The second dummy ground selection line dGSL2 can be set to the same pattern as the eighth ground selection line GSL8 (i.e., [11000011]).

[0180] When the patterns for the dummy ground selection lines dGSL1 and dGSL2 are set as described above, the number of adjacent ground selection transistors having the same state in each unit string can be "at least 2 or more". The memory device 100 can perform a multi-GSL programming operation based on the GSL coding pattern.

[0181] Figure 19 is a diagram for describing a GSL coding pattern according to an embodiment of the present disclosure. Refer to Figure 1 and Figure 19 , the memory blocks included in the memory device 100 may have a 12SSL-1GSL structure. That is, 12 unit strings can be respectively connected to 12 string selection lines and can have the same ground selection line. In this case, it may be necessary to electrically separate the 12 unit strings. In this case, as Figure 19 shown, a GSL preset pattern can be generated for 12 ground selection lines GSL1 to GSL12.

[0182] For example, the first ground selection line GSL1 can be set to the pattern [000011110011], the second ground selection line GSL2 can be set to the pattern [000111100110], the third ground selection line GSL3 can be set to the pattern [001111001100], the fourth ground selection line GSL4 can be set to the pattern [011110011000], the fifth ground selection line GSL5 can be set to the pattern [111100110000], the sixth ground selection line GSL6 can be set to the pattern [111001100001], the seventh ground selection line GSL7 can be set to the pattern [110011000011], the eighth ground selection line GSL8 can be set to the pattern [100110000111], the ninth ground selection line GSL9 can be set to the pattern [001100001111], the tenth ground selection line GSL10 can be set to the pattern [011000011110], the eleventh ground selection line GSL11 can be set to the pattern [110000111100], and the twelfth ground selection line GSL12 can be set to the pattern [100001111001].

[0183] As described above, the first dummy ground selection line dGSL1 can be disposed between the substrate (or the common source line CSL) and the first ground selection line GSL1, and the second dummy ground selection line dGSL2 can be disposed between the twelfth ground selection line GSL12 and the plurality of word lines WL1 to WLn.

[0184] In this case, the GSL coding pattern can be generated based on the GSL preset pattern. For example, the first dummy ground selection line dGSL1 can be set to the same pattern as the first ground selection line GSL1 (i.e., [000011110011]). The second dummy ground selection line dGSL2 can be set to the same pattern as the twelfth ground selection line GSL12 (i.e., [100001111001]).

[0185] When the patterns for the dummy ground selection lines dGSL1 and dGSL2 are set as described above, the number of adjacent ground selection transistors having the same state in each cell string can be "at least 2 or more".

[0186] The memory device 100 can perform a multi-GSL programming operation based on the GSL coding pattern. The multi-GSL programming operation based on the GSL coding pattern is as described above, and thus, additional description will be omitted to avoid redundancy.

[0187] Figure 19 The embodiments are merely examples, and the present disclosure is not limited thereto. For example, it can be based on reference Figures 1 to 18At least one of the described methods generates a GSL preset pattern for 12 ground selection lines GSL1 to GSL12.

[0188] The GSL coding patterns described in the above embodiments are merely examples, and the present disclosure is not limited thereto. For example, the GSL coding pattern can be generated such that at least two adjacent ground selection transistors have the same state. In the GSL coding pattern described in the above embodiments, the inversion of the a-th programming state Pa and the erase state "E" is also feasible.

[0189] The above embodiments of the present disclosure are described based on a plurality of cell strings connected to one bit line (e.g., BL1). However, the present disclosure is not limited thereto. The above embodiments can be applied to cell strings respectively connected to a plurality of bit lines. For example, the ground selection transistors of the 1a-th cell string CS1a connected to the first bit line BL1 and the a-th string selection line SSLa and the ground selection transistors of the 2a-th cell string CS2a connected to the second bit line BL2 and the a-th string selection line SSLa can be programmed to the same pattern or the same state.

[0190] The above embodiments of the present disclosure are provided to easily describe the present disclosure, and the present disclosure is not limited thereto. For example, according to an embodiment of the present disclosure, a plurality of cell strings can be respectively connected to a plurality of string selection lines and can share the same ground selection line. In this case, in each of the plurality of cell strings, at least two ground selection transistors can have the same state (e.g., the erase state "E" or the a-th programming state Pa). As an example, at least two ground selection transistors can be programmed simultaneously. Therefore, the change in the threshold voltage of the ground selection transistors caused by various factors can be prevented or minimized. This can mean that the reliability and performance of the memory device 100 are improved.

[0191] Figure 20 and Figure 21 are diagrams for describing the GSL coding pattern according to an embodiment of the present disclosure. Refer to Figure 1 、 Figure 20 and Figure 21 , the memory blocks included in the memory device 100 can have a structure of 8SSL-1GSL. That is, eight cell strings can be respectively connected to eight string selection lines and can have the same ground selection line. In this case, it may be necessary to electrically distinguish the eight cell strings, and the GSL coding pattern is generated as shown in Figure 21 or Figure 22 . For example, in the above embodiments, the GSL preset pattern can be generated based on the structure of the memory block, and the GSL coding pattern can be generated based on the GSL preset pattern such that the dummy ground selection line has the same pattern as the adjacent ground selection line. In contrast, in Figure 21In the embodiments, it may not be necessary to fictitiously select lines.

[0192] For example, as Figure 21 shown, the first ground selection line GSL1 may be set to the pattern [00000001], the second ground selection line GSL2 may be set to the pattern [00000011], the third ground selection line GSL3 may be set to the pattern [00000110], the fourth ground selection line GSL4 may be set to the pattern [00001100], the fifth ground selection line GSL5 may be set to the pattern [00011000], the sixth ground selection line GSL6 may be set to the pattern [00110000], the seventh ground selection line GSL7 may be set to the pattern [01100000], the eighth ground selection line GSL8 may be set to the pattern [11000000], and the ninth ground selection line GSL9 may be set to the pattern [10000000].

[0193] In this case, at least two adjacent ground selection transistors may have the same programming state, and one of the cell strings CSa to CSh may be selected according to the turn-on voltages of the multiple ground selection lines GSL1 to GSL9.

[0194] Or, as Figure 21 shown, the first ground selection line GSL1 may be set to the pattern [00010010], the second ground selection line GSL2 may be set to the pattern [00010010], the third ground selection line GSL3 may be set to the pattern [00100101], the fourth ground selection line GSL4 may be set to the pattern [00100101], the fifth ground selection line GSL5 may be set to the pattern [01001001], the sixth ground selection line GSL6 may be set to the pattern [01001001], the seventh ground selection line GSL7 may be set to the pattern [10001110], the eighth ground selection line GSL8 may be set to the pattern [10001110], the ninth ground selection line GSL9 may be set to the pattern [11110000], and the tenth ground selection line GSL10 may be set to the pattern [11110000].

[0195] In this case, at least two adjacent ground selection transistors may have the same programming state, and one of the cell strings CSa to CSh may be selected according to the turn-on voltages of the multiple ground selection lines GSL1 to GSL10.

[0196] Figure 22 and Figure 23 are diagrams for describing the GSL coding patterns according to embodiments of the present disclosure. Refer to Figure 1 , Figure 22 , Figure 23, the memory blocks included in the memory device 100 may have a structure of 8SSL-1GSL. That is, eight cell strings may be connected to eight string selection lines and may have the same ground selection line.

[0197] In an embodiment, it is necessary to distinguish four cell string groups. In this case, as Figure 22 shown, the ground selection transistors GST1a to GST1h connected to the first ground selection line GSL1 may be programmed to have the pattern [00000011], the ground selection transistors GST2a to GST2h connected to the second ground selection line GSL2 may be programmed to have the pattern [00000011], the ground selection transistors GST3a to GST3h connected to the third ground selection line GSL3 may be programmed to have the pattern [00001100], the ground selection transistors GST4a to GST4h connected to the fourth ground selection line GSL4 may be programmed to have the pattern [00001100], the ground selection transistors GST5a to GST5h connected to the fifth ground selection line GSL5 may be programmed to have the pattern [00110000], the ground selection transistors GST6a to GST6h connected to the sixth ground selection line GSL6 may be programmed to have the pattern [00110000], the ground selection transistors GST7a to GST7h connected to the seventh ground selection line GSL7 may be programmed to have the pattern [11000000], and the ground selection transistors GST8a to GST8h connected to the eighth ground selection line GSL8 may be programmed to have the pattern [11000000].

[0198] Alternatively, as Figure 23 shown, the first ground selection line GSL1 may be programmed to have the pattern [11111100], the ground selection transistors GST2a to GST2h connected to the second ground selection line GSL2 may be programmed to have the pattern [11111100], the ground selection transistors GST3a to GST3h connected to the third ground selection line GSL3 may be programmed to have the pattern [11110011], the ground selection transistors GST4a to GST4h connected to the fourth ground selection line GSL4 may be programmed to have the pattern [11110011], the ground selection transistors GST5a to GST5h connected to the fifth ground selection line GSL5 may be programmed to have the pattern [11001111], the ground selection transistors GST6a to GST6h connected to the sixth ground selection line GSL6 may be programmed to have the pattern [11001111], the ground selection transistors GST7a to GST7h connected to the seventh ground selection line GSL7 may be programmed to have the pattern [00111111], and the ground selection transistors GST8a to GST8h connected to the eighth ground selection line GSL8 may be programmed to have the pattern [00111111].

[0199] In Figure 22 and Figure 23 In the embodiments, at least two adjacent ground selection transistors in each of the plurality of cell strings CSa to CSh may have the same program state or the same threshold state.

[0200] In Figure 22 and Figure 23 In the embodiments, an example of two cell strings being controlled together is described, but the scope of the present disclosure is not limited thereto. For example, each of the plurality of cell strings CSa to CSh may be controlled individually. Here, at least two adjacent ground selection transistors in each of the plurality of cell strings CSa to CSh may have the same program state or the same threshold state. In this case, the first ground selection line GSL1 may be programmed to have the pattern [00000001], the ground selection transistors GST2a to GST2h connected to the second ground selection line GSL2 may be programmed to have the pattern [00000001], the ground selection transistors GST3a to GST3h connected to the third ground selection line GSL3 may be programmed to have the pattern [00000010], and the ground selection transistors GST4a to GST4h connected to the fourth ground selection line GSL4 may be programmed to have the pattern [00000010]. Other ground transistors may have patterns similar to those described above, and thus additional description will be omitted to avoid redundancy.

[0201] Figure 24 FIG. shows a view for describing a memory device according to an embodiment of the present disclosure.

[0202] Referring Figure 24 , the memory device 500 may have a chip-to-chip (C2C) structure. Here, in the C2C structure, after manufacturing at least one upper chip including a cell region and at least one lower chip including a peripheral circuit region PERI separately, the upper chip and the lower chip may be joined to each other by a bonding method. As an example, the bonding method may refer to a method of electrically connecting or physically connecting a bonding metal pattern formed in the uppermost metal layer of the upper chip and a bonding metal pattern formed in the uppermost metal layer of the lower chip. For example, when the bonding metal pattern is formed of copper (Cu), the bonding method may be referred to as a "Cu-Cu bonding method". As another example, the bonding metal pattern may also be formed of aluminum (Al) or tungsten (W).

[0203] The memory device 500 may include at least one upper chip having a cell region. For example, as Figure 24As shown, the memory device 500 may be implemented to include two upper chips. However, this is exemplary, and the number of upper chips is not limited thereto. In the case where the memory device 500 is implemented to include two upper chips, the memory device 500 may be manufactured as follows: separately manufacture a first upper chip including a first cell region CELL1, a second upper chip including a second cell region CELL2, and a lower chip including a peripheral circuit region PERI, and then connect the first upper chip, the second upper chip, and the lower chip using a bonding method. The first upper chip may be flipped and connected to the lower chip using a bonding method, and the second upper chip may also be flipped and connected to the first upper chip using a bonding method. In the following description, the upper and lower portions of the first upper chip and the second upper chip are defined based on before the first upper chip and the second upper chip are flipped. That is, in Figure 24 , the upper portion of the lower chip refers to the upper portion defined based on the +Z axis direction, and the upper portions of the first upper chip and the second upper chip refer to the upper portions defined based on the -Z axis direction. However, this is exemplary, and only one of the first upper chip and the second upper chip may be flipped and connected using a bonding method.

[0204] Each of the peripheral circuit region PERI of the memory device 500 and the first cell region CELL1 and the second cell region CELL2 may include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0205] The peripheral circuit region PERI may include a first substrate 210 and a plurality of circuit elements 220a, 220b, and 220c formed on the first substrate 210. An interlayer insulating layer 215 including one or more insulating layers may be provided on the plurality of circuit elements 220a, 220b, and 220c, and a plurality of metal lines connecting the plurality of circuit elements 220a, 220b, and 220c may be provided in the interlayer insulating layer 215. For example, the plurality of metal lines may include first metal lines 230a, 230b, and 230c respectively connected to the plurality of circuit elements 220a, 220b, and 220c and second metal lines 240a, 240b, and 240c formed on the first metal lines 230a, 230b, and 230c. The plurality of metal lines may be formed of at least one of various conductive materials. For example, the first metal lines 230a, 230b, and 230c may be formed of tungsten having a relatively high resistivity, and the second metal lines 240a, 240b, and 240c may be formed of copper having a relatively low resistivity.

[0206] In this specification, only the first metal lines 230a, 230b, and 230c and the second metal lines 240a, 240b, and 240c are shown and described. However, it is not limited thereto, and one or more additional metal lines may be further formed on the second metal lines 240a, 240b, and 240c. In this case, the second metal lines 240a, 240b, and 240c may be formed of aluminum. At least some of the additional metal lines formed on the second metal lines 240a, 240b, and 240c may be formed of copper having a lower resistivity than that of the aluminum of the second metal lines 240a, 240b, and 240c.

[0207] The interlayer insulating layer 115 may be disposed on the first substrate 210 and may include an insulating material such as silicon oxide or silicon nitride.

[0208] Each of the first unit region CELL1 and the second unit region CELL2 may include at least one memory block. The first unit region CELL1 may include a second substrate 310 and a common source line 320. A plurality of word lines 330 (331 to 338) may be stacked on the second substrate 310 in a direction (Z-axis direction) perpendicular to the upper surface of the second substrate 310. A string selection line and a ground selection line may be disposed above and below the word lines 330, and a plurality of word lines 330 may be disposed between the string selection line and the ground selection line. Similarly, the second unit region CELL2 may include a third substrate 410 and a common source line 420, and a plurality of word lines 430 (431 to 438) may be stacked in a direction (Z-axis direction) perpendicular to the upper surface of the third substrate 410. The second substrate 310 and the third substrate 410 may be formed of various materials and may be, for example, a silicon substrate, a silicon germanium substrate, a germanium substrate, or a substrate having a single crystal epitaxial layer grown on a single crystal silicon substrate. A plurality of channel structures CH may be formed in the first unit region CELL1 and the second unit region CELL2.

[0209] In an embodiment, as shown in A1, the channel structure CH may be disposed in the bit line contact region BLBA and may extend in a direction perpendicular to the upper surface of the second substrate 310 to penetrate the word lines 330, the string selection line, and the ground selection line. The channel structure CH may include a data storage layer, a channel layer, and a buried insulating layer. The channel layer may be electrically connected to the first metal line 350c and the second metal line 360c in the bit line contact region BLBA. For example, the second metal line 360c may be a bit line and may be connected to the channel structure CH through the first metal line 350c. The bit line 360c may extend in a first direction (Y-axis direction) parallel to the upper surface of the second substrate 310.

[0210] In an embodiment, as shown in A2, the channel structure CH may include a lower channel LCH and an upper channel UCH connected to each other. For example, the channel structure CH may be formed by a process for the lower channel LCH and a process for the upper channel UCH. The lower channel LCH may extend in a direction perpendicular to the upper surface of the second substrate 310 and may penetrate the common source line 320 and the lower word lines 331 and 332. The lower channel LCH may include a data storage layer, a channel layer, and a buried insulating layer, and may be connected to the upper channel UCH. The upper channel UCH may penetrate the upper word lines 333 to 338. The upper channel UCH may include a data storage layer, a channel layer, and a buried insulating layer, and the channel layer of the upper channel UCH may be electrically connected to the first metal line 350c and the second metal line 360c. Since the length of the channel increases, it may be difficult to form a channel with a constant width due to process reasons. The memory device 500 according to an embodiment of the present disclosure may include a channel having improved width uniformity through the lower channel LCH and the upper channel UCH formed by sequential processes.

[0211] In the case where the channel structure CH includes the lower channel LCH and the upper channel UCH as shown in A2, the word lines near the boundary between the lower channel LCH and the upper channel UCH may be dummy word lines. For example, the word line 332 and the word line 333 forming the boundary between the lower channel LCH and the upper channel UCH may be dummy word lines. In this case, data may not be stored in the memory cells connected to the dummy word lines. Alternatively, the number of pages corresponding to the memory cells connected to the dummy word lines may be smaller than the number of pages corresponding to the memory cells connected to the normal word lines. The voltage level applied to the dummy word lines may be different from the voltage level applied to the normal word lines, and thus the influence of the non-uniform channel width between the lower channel LCH and the upper channel UCH on the operation of the memory device may be reduced.

[0212] Meanwhile, in A2, the number of the lower word lines 331 and 332 penetrated by the lower channel LCH is shown to be smaller than the number of the upper word lines 333 to 338 penetrated by the upper channel UCH. However, this is exemplary, and the present disclosure is not limited thereto. In another example, the number of the lower word lines penetrated by the lower channel LCH may be equal to or greater than the number of the upper word lines penetrated by the upper channel UCH. In addition, the above structure and connection relationship of the channel structure CH provided in the first unit region CELL1 may be applied to the channel structure CH provided in the second unit region CELL2 in the same manner.

[0213] In the bit line bonding region BLBA, a first through electrode THV1 may be provided in the first unit region CELL1, and a second through electrode THV2 may be provided in the second unit region CELL2. As Figure 24As shown, the first through electrode THV1 may penetrate the common source line 320 and the plurality of word lines 330. However, this is exemplary, and the first through electrode THV1 may alternatively penetrate the second substrate 310. The first through electrode THV1 may include a conductive material. Alternatively, the first through electrode THV1 may include a conductive material surrounded by an insulating material. The second through electrode THV2 may have the same shape and structure as the first through electrode THV1.

[0214] In an embodiment, the first through electrode THV1 and the second through electrode THV2 may be electrically connected through the first through metal pattern 372d and the second through metal pattern 472d. The first through metal pattern 372d may be formed on the lower side of the first upper chip including the first unit region CELL1, and the second through metal pattern 472d may be formed on the upper side of the second upper chip including the second unit region CELL2. The first through electrode THV1 may be electrically connected to the first metal line 350c and the second metal line 360c. The lower via 371d may be formed between the first through electrode THV1 and the first through metal pattern 372d, and the upper via 471d may be formed between the second through electrode THV2 and the second through metal pattern 472d. The first through metal pattern 372d and the second through metal pattern 472d may be connected by a bonding method.

[0215] In addition, in the bit line bonding region BLBA, the upper metal pattern 252 may be formed on the uppermost metal layer of the peripheral circuit region PERI, and the upper metal pattern 392 having the same shape as the upper metal pattern 252 may be formed on the uppermost metal layer of the first unit region CELL1. The upper metal pattern 392 of the first unit region CELL1 and the upper metal pattern 252 of the peripheral circuit region PERI may be electrically connected to each other by a bonding method. In the bit line bonding region BLBA, the bit line 360c may be electrically connected to the page buffer included in the peripheral circuit region PERI. For example, some circuit elements 220c of the peripheral circuit region PERI may provide a page buffer, and the bit line 360c may be electrically connected to the circuit element 220c providing the page buffer through the upper bonding metal 370c of the first unit region CELL1 and the upper bonding metal 270c of the peripheral circuit region PERI.

[0216] Continue to refer to Figure 24, in the word line bonding area WLBA, the word line 330 of the first cell area CELL1 can extend in a second direction (X-axis direction) parallel to the upper surface of the second substrate 310, and can be connected to a plurality of cell contact plugs 340 (341 to 347). The first metal line 350b and the second metal line 360b can be sequentially connected to the upper part of the cell contact plug 340 connected to the word line 330. In the word line bonding area WLBA, the cell contact plug 340 can be connected to the peripheral circuit area PERI through the upper bonding metal 370b of the first cell area CELL1 and the upper bonding metal 270b of the peripheral circuit area PERI.

[0217] The cell contact plug 340 can be electrically connected to a row decoder included in the peripheral circuit area PERI. For example, some circuit elements 220b in the peripheral circuit area PERI can provide a row decoder, and the cell contact plug 340 can be electrically connected to the circuit element 220b providing the row decoder through the upper bonding metal 370b of the first cell area CELL1 and the upper bonding metal 270b of the peripheral circuit area PERI. In an embodiment, the operating voltage of the circuit element 220b providing the row decoder can be different from the operating voltage of the circuit element 220c providing the page buffer. For example, the operating voltage of the circuit element 220c providing the page buffer can be greater than the operating voltage of the circuit element 220b providing the row decoder.

[0218] Similarly, in the word line bonding area WLBA, the word line 430 of the second cell area CELL2 can extend in a second direction (X-axis direction) parallel to the upper surface of the third substrate 410, and can be connected to a plurality of cell contact plugs 440 (441 to 447). The cell contact plug 440 can be connected to the peripheral circuit area PERI through the upper metal pattern of the second cell area CELL2, the lower metal pattern and the upper metal pattern of the first cell area CELL1, and the cell contact plug 348.

[0219] In the word line bonding area WLBA, the upper bonding metal 370b can be formed in the first cell area CELL1, and the upper bonding metal 270b can be formed in the peripheral circuit area PERI. The upper bonding metal 370b of the first cell area CELL1 and the upper bonding metal 270b of the peripheral circuit area PERI can be electrically connected to each other by a bonding method. The upper bonding metal 370b and the upper bonding metal 270b can be formed of aluminum, copper or tungsten.

[0220] In the external pad bonding region PA, the lower metal pattern 371e may be formed on the lower part of the first cell region CELL1, and the upper metal pattern 472a may be formed on the upper part of the second cell region CELL2. The lower metal pattern 371e of the first cell region CELL1 and the upper metal pattern 472a of the second cell region CELL2 may be connected in the external pad bonding region PA by a bonding method. Similarly, the upper metal pattern 372a may be formed on the upper part of the first cell region CELL1, and the upper metal pattern 272a may be formed on the upper part of the peripheral circuit region PERI. The upper metal pattern 372a of the first cell region CELL1 and the upper metal pattern 272a of the peripheral circuit region PERI may be connected to each other by a bonding method.

[0221] Common source line contact plugs 380 and 480 may be provided in the external pad bonding region PA. The common source line contact plugs 380 and 480 may be formed of a conductive material such as metal, metal compound, or doped polysilicon. The common source line contact plug 380 of the first cell region CELL1 may be electrically connected to the common source line 320, and the common source line contact plug 480 of the second cell region CELL2 may be electrically connected to the common source line 420. The first metal line 350a and the second metal line 360a may be sequentially stacked on the upper part of the common source line contact plug 380 of the first cell region CELL1, and the first metal line 450a and the second metal line 460a may be sequentially stacked on the upper part of the common source line contact plug 480 of the second cell region CELL2.

[0222] Input / output pads 205, 405, and 406 may be provided in the external pad bonding region PA. Refer to Figure 24 , the lower insulating layer 201 may cover the lower surface of the first substrate 210, and the first input / output pad 205 may be formed on the lower insulating layer 201. The first input / output pad 205 may be connected to at least one of the plurality of circuit elements 220a provided in the peripheral circuit region PERI through the first input / output contact plug 203, and may be separated from the first substrate 210 by the lower insulating layer 201. In addition, a side insulating layer may be provided between the first input / output contact plug 203 and the first substrate 210, and may electrically isolate the first input / output contact plug 203 from the first substrate 210.

[0223] An upper insulating layer 401 may be formed on the third substrate 410 to cover the upper surface of the third substrate 410. The second input / output pad 405 and / or the third input / output pad 406 may be disposed on the upper insulating layer 401. The second input / output pad 405 may be connected to at least one of the plurality of circuit elements 220a disposed in the peripheral circuit region PERI through the second input / output contact plug 403 and 303, and the third input / output pad 406 may be connected to at least one of the plurality of circuit elements 220a disposed in the peripheral circuit region PERI through the third input / output contact plug 404 and 304.

[0224] In an embodiment, the third substrate 410 may not be disposed in the region where the input / output contact plug is provided. For example, as shown in B, the third input / output contact plug 404 may be separated from the third substrate 410 in a direction parallel to the upper surface of the third substrate 410, may penetrate the interlayer insulating layer 415 of the second cell region CELL2, and may be connected to the third input / output pad 406. In this case, the third input / output contact plug 404 may be formed by various processes.

[0225] For example, as shown in B1, the third input / output contact plug 404 may extend in the third direction (Z-axis direction) and may have a diameter increasing toward the upper insulating layer 401. That is, while the channel structure CH described with reference to A1 has a diameter decreasing toward the upper insulating layer 401, the third input / output contact plug 404 may have a diameter increasing toward the upper insulating layer 401. For example, the third input / output contact plug 404 may be formed after the second cell region CELL2 and the first cell region CELL1 are coupled by a bonding method.

[0226] For example, as shown in B2, the third input / output contact plug 404 may extend in the third direction (Z-axis direction) and may have a diameter decreasing toward the upper insulating layer 401. That is, similarly to the channel structure CH, the third input / output contact plug 404 may have a diameter decreasing toward the upper insulating layer 401. For example, before the second cell region CELL2 and the first cell region CELL1 are coupled by a bonding method, the third input / output contact plug 404 may be formed together with the cell contact plug 440.

[0227] In an embodiment, the input / output contact plug may be arranged to overlap with the third substrate 410. For example, as shown in C, the second input / output contact plug 403 may be formed to penetrate the interlayer insulating layer 415 of the second cell region CELL2 in the third direction (Z-axis direction), and may be electrically connected to the second input / output pad 405 through the third substrate 410. In this case, the connection structure between the second input / output contact plug 403 and the second input / output pad 405 may be implemented in various ways.

[0228] For example, as shown in C1, an opening 408 may be formed through the third substrate 410, and the second input / output contact plug 403 may be directly connected to the second input / output pad 405 through the opening 408 formed in the third substrate 410. In this case, as shown in C1, the second input / output contact plug 403 may have a diameter that increases toward the second input / output pad 405. However, this is exemplary, and the second input / output contact plug 403 may have a diameter that decreases toward the second input / output pad 405.

[0229] For example, as shown in C2, the opening 408 may be formed through the third substrate 410, and a contact 407 may be formed in the opening 408. One end of the contact 407 may be connected to the second input / output pad 405, and the opposite end of the contact 407 may be connected to the second input / output contact plug 403. Thus, the second input / output contact plug 403 may be electrically connected to the second input / output pad 405 through the contact 407 in the opening 408. In this case, as shown in C2, the contact 407 may have a diameter that increases toward the second input / output pad 405, and the second input / output contact plug 403 may have a diameter that decreases toward the second input / output pad 405. For example, the third input / output contact plug 403 may be formed together with the cell contact plug 440 before the second cell region CELL2 and the first cell region CELL1 are coupled by a bonding method, and the contact 407 may be formed after the second cell region CELL2 and the first cell region CELL1 are coupled by a bonding method.

[0230] For example, as shown in C3, a blocking portion 409 may be additionally formed on the upper surface of the opening 408 of the third substrate 410. The blocking portion 409 may be a metal wire formed on the same layer as the common source line 420. However, this is exemplary, and the blocking portion 409 may be a metal wire formed on the same layer as at least one of the word lines 430. The second input / output contact plug 403 may be electrically connected to the second input / output pad 405 through the contact 407 and the blocking portion 409.

[0231] Meanwhile, similar to the second input / output contact plugs 403 and the third input / output contact plugs 404 of the second unit region CELL2, the second input / output contact plugs 303 and the third input / output contact plugs 304 of the first unit region CELL1 may have diameters that decrease toward the lower metal pattern 371e, or may have diameters that increase toward the lower metal pattern 371e.

[0232] Meanwhile, in some embodiments, a slit 411 may be formed in the third substrate 410. For example, the slit 411 may be formed at any position in the external pad bonding region PA. For example, as shown in D, when viewed in a plane, the slit 411 may be located between the second input / output pad 405 and the cell contact plug 440. However, this is exemplary, and the slit 411 may be formed such that when viewed in a plane, the second input / output pad 405 is located between the slit 411 and the cell contact plug 440.

[0233] For example, as shown in D1, the slit 411 may be formed through the third substrate 410. For example, the slit 411 may be used to prevent the third substrate 410 from cracking slightly when the opening 408 is formed. However, this is exemplary, and the slit 411 may be formed to have a depth ranging from about 60% to about 70% of the thickness of the third substrate 410.

[0234] For example, as shown in D2, a conductive material 412 may be formed in the slit 411. For example, the conductive material 412 may be used to release the leakage current generated when the circuit elements in the external pad bonding region PA are driven. In this case, the conductive material 412 may be connected to an external ground wire.

[0235] For example, as shown in D3, an insulating material 413 may be formed in the slit 411. For example, the insulating material 413 may be formed to electrically isolate the second input / output pad 405 and the second input / output contact plug 403 provided in the external pad bonding region PA from the word line bonding region WLBA. By forming the insulating material 413 in the slit 411, the influence of the voltage provided through the second input / output pad 405 on the metal layer provided on the third substrate 410 in the word line bonding region WLBA can be interrupted.

[0236] Meanwhile, in some embodiments, the first input / output pad 205, the second input / output pad 505, and the third input / output pad 406 may be selectively formed. For example, the memory device 500 may be implemented to include only the first input / output pad 205 provided on the first substrate 201, only the second input / output pad 405 provided on the third substrate 410, or only the third input / output pad 406 provided on the upper insulating layer 401.

[0237] Meanwhile, in some embodiments, at least one of the second substrate 310 of the first unit region CELL1 or the third substrate 410 of the second unit region CELL2 may be used as a sacrificial substrate and may be completely or partially removed before or after the bonding process. Additional layers may be stacked after removing the substrate. For example, the second substrate 310 of the first unit region CELL1 may be removed before or after the peripheral circuit region PERI and the first unit region CELL1 are bonded to each other, and an insulating layer for covering the upper surface of the common source line 320 or a conductive layer for connection may be formed. Similarly, the third substrate 410 of the second unit region CELL2 may be removed before or after the first unit region CELL1 and the second unit region CELL2 are bonded to each other, and an upper insulating layer 401 for covering the upper surface of the common source line 420 or a conductive layer for connection may be formed.

[0238] Figure 25 is a block diagram of a memory system according to an embodiment. Refer to Figure 25 , the memory system 2000 may include a memory device 2200 and a memory controller 2100.

[0239] The memory device 2200 may include first pins P11 to eighth pins P18, a memory interface circuit 2210, a control logic circuit 2220, and a memory cell array 2230.

[0240] The memory interface circuit 2210 may receive a chip enable signal nCE from the memory controller 2100 through the first pin P11. The memory interface circuit 2210 may transmit signals to and receive signals from the memory controller 2100 through the second pin P12 to the eighth pin P18 in response to the chip enable signal nCE. For example, when the chip enable signal nCE is in an enabled state (e.g., low level), the memory interface circuit 2210 may transmit signals to and receive signals from the memory controller 2100 through the second pin P12 to the eighth pin P18.

[0241] The memory interface circuit 2210 can receive a command latch enable signal CLE, an address latch enable signal ALE, and a write enable signal nWE from the memory controller 2100 via the second pin P12 to the fourth pin P14. The memory interface circuit 2210 can receive data signals DQ from the memory controller 2100 via the seventh pin P17 or transmit the data signals DQ to the memory controller 2100. A command CMD, an address ADDR, and data can be transmitted via the data signals DQ. For example, the data signals DQ can be transmitted through multiple data signal lines. In this case, the seventh pin P17 can include multiple pins corresponding to the multiple data signals DQ respectively.

[0242] The memory interface circuit 2210 can obtain the command CMD from the data signal DQ, and the command CMD is received in the enabled portion (e.g., high level state) of the command latch enable signal CLE based on the switching time point of the write enable signal nWE. The memory interface circuit 2210 can obtain the address ADDR from the data signal DQ, and the address ADDR is received in the enabled portion (e.g., high level state) of the address latch enable signal ALE based on the switching time point of the write enable signal nWE.

[0243] In an exemplary embodiment, the write enable signal nWE can be maintained in a static state (e.g., high level or low level) and switched between high level and low level. For example, the write enable signal nWE can be switched in the portion where the command CMD or the address ADDR is sent. Therefore, the memory interface circuit 2210 can obtain the command CMD or the address ADDR based on the switching time point of the write enable signal nWE.

[0244] The memory interface circuit 2210 can receive a read enable signal nRE from the memory controller 2100 via the fifth pin P15. The memory interface circuit 2210 can receive a data strobe signal DQS from the memory controller 2100 via the sixth pin P16 or transmit the data strobe signal DQS to the memory controller 2100.

[0245] In a data (DATA) output operation of the memory device 2200, the memory interface circuit 2210 may receive a switched read enable signal nRE through a fifth pin P15 before outputting the data DATA. The memory interface circuit 2210 may generate a data strobe signal DQS, which is switched based on the switching of the read enable signal nRE. For example, the memory interface circuit 2210 may generate the data strobe signal DQS based on the switching start time of the read enable signal nRE, and the data strobe signal DQS starts to switch after a predetermined delay (e.g., tDQSRE). The memory interface circuit 2210 may transmit a data signal DQ including the data DATA based on the switching time point of the data strobe signal DQS. Therefore, the data DATA may be aligned with the switching time point of the data strobe signal DQS and sent to the memory controller 2100.

[0246] In a data (DATA) input operation of the memory device 2200, when receiving the data signal DQ including the data DATA from the memory controller 2100, the memory interface circuit 2210 may receive the switched data strobe signal DQS from the memory controller 2100 together with the data DATA. The memory interface circuit 2210 may obtain the data DATA from the data signal DQ based on the switching time point of the data strobe signal DQS. For example, the memory interface circuit 2210 may sample the data signal DQ at the rising edge and the falling edge of the data strobe signal DQS and obtain the data DATA.

[0247] The memory interface circuit 2210 may send the ready / busy output signal nR / B to the memory controller 2100 through the eighth pin P18. The memory interface circuit 2210 may send the status information of the memory device 2200 to the memory controller 2100 through the ready / busy output signal nR / B. When the memory device 2200 is in the busy state (i.e., when an operation is being executed in the memory device 2200), the memory interface circuit 2210 may send the ready / busy output signal nR / B indicating the busy state to the memory controller 2100. When the memory device 2200 is in the ready state (i.e., when no operation is being executed or an operation is completed in the memory device 2200), the memory interface circuit 2210 may send the ready / busy output signal nR / B indicating the ready state to the memory controller 2100. For example, when the memory device 2200 is reading data DATA from the memory cell array 2230 in response to a page read command, the memory interface circuit 2210 may send the ready / busy output signal nR / B indicating the busy state (e.g., low level) to the memory controller 2100. For example, when the memory device 2200 is programming data DATA into the memory cell array 2230 in response to a programming command, the memory interface circuit 2210 may send the ready / busy output signal nR / B indicating the busy state to the memory controller 2100.

[0248] The control logic circuit 2220 may control all operations of the memory device 2200. The control logic circuit 2220 may receive the command / address CMD / ADDR obtained from the memory interface circuit 2210. The control logic circuit 2220 may generate control signals for controlling other components of the memory device 2200 in response to the received command / address CMD / ADDR. For example, the control logic circuit 2220 may generate various control signals for programming data DATA into the memory cell array 2230 or reading data DATA from the memory cell array 2230.

[0249] The memory cell array 2230 may store the data DATA obtained from the memory interface circuit 2210 under the control of the control logic circuit 2220. The memory cell array 2230 may output the stored data DATA to the memory interface circuit 2210 under the control of the control logic circuit 2220.

[0250] The memory cell array 2230 may include a plurality of memory cells. For example, the plurality of memory cells may be flash memory cells. However, the memory cells are not limited thereto, and the memory cells may be RRAM cells, FRAM cells, PRAM cells, thyristor RAM (TRAM) cells, or MRAM cells. Hereinafter, embodiments in which the memory cells are NAND flash memory cells will be mainly described.

[0251] The memory controller 2100 may include first pin P21 to eighth pin P28 and a controller interface circuit 2110. The first pin P21 to eighth pin P28 may respectively correspond to the first pin P11 to eighth pin P18 of the memory device 2200.

[0252] The controller interface circuit 2110 may send a chip enable signal nCE to the memory device 2200 through the first pin P21. The controller interface circuit 2110 may send the signals selected by the chip enable signal nCE to the memory device 2200 and receive the signals selected by the chip enable signal nCE from the memory device 2200 through the second pin P22 to eighth pin P28.

[0253] The controller interface circuit 2110 may send a command latch enable signal CLE, an address latch enable signal ALE, and a write enable signal nWE to the memory device 2200 through the second pin P22 to fourth pin P24. The controller interface circuit 2110 may send a data signal DQ to the memory device 2200 or receive a data signal DQ from the memory device 2200 through the seventh pin P27.

[0254] The controller interface circuit 2110 may send a data signal DQ including a command CMD or an address ADDR together with a switched write enable signal nWE to the memory device 2200. The controller interface circuit 2110 may send a data signal DQ including a command CMD to the memory device 2200 by sending a command latch enable signal CLE with an enabled state. In addition, the controller interface circuit 2110 may send a data signal DQ including an address ADDR to the memory device 2200 by sending an address latch enable signal ALE with an enabled state.

[0255] The controller interface circuit 2110 may send a read enable signal nRE to the memory device 2200 through the fifth pin P25. The controller interface circuit 2110 may receive a data strobe signal DQS from the memory device 2200 or send a data strobe signal DQS to the memory device 2200 through the sixth pin P26.

[0256] In a data (DATA) output operation of the memory device 2200, the controller interface circuit 2110 may generate a toggled read enable signal nRE and send the read enable signal nRE to the memory device 2200. For example, before outputting the data DATA, the controller interface circuit 2110 may generate a read enable signal nRE that changes from a static state (e.g., high level or low level) to a toggled state. Accordingly, the memory device 2200 may generate a toggled data strobe signal DQS based on the read enable signal nRE. The controller interface circuit 2110 may receive a data signal DQ including the data DATA from the memory device 2200 together with the toggled data strobe signal DQS. The controller interface circuit 2110 may obtain the data DATA from the data signal DQ based on the toggling time point of the data strobe signal DQS.

[0257] In a data (DATA) input operation of the memory device 2200, the controller interface circuit 2110 may generate a toggled data strobe signal DQS. For example, before sending the data DATA, the controller interface circuit 2110 may generate a data strobe signal DQS that changes from a static state (e.g., high level or low level) to a toggled state. The controller interface circuit 2110 may send a data signal DQ including the data DATA to the memory device 2200 based on the toggling time point of the data strobe signal DQS.

[0258] The controller interface circuit 2110 may receive a ready / busy output signal nR / B from the memory device 2200 through an eighth pin P28. The controller interface circuit 2110 may determine status information of the memory device 2200 based on the ready / busy output signal nR / B.

[0259] In an embodiment, the memory cell array 2230 of the memory device 2200 may include a plurality of memory blocks. The plurality of memory blocks may have one of the various structures described with reference to Figures 1 to 22 and may include a plurality of ground selection transistors programmed based on the GSL coding mode described with reference to Figures 1 to 22 The memory device 2200 may control a plurality of ground selection lines based on the method described with reference to Figures 1 to 22

[0260] ​In an embodiment, the ground selection transistors included in each of the plurality of memory blocks may be programmed based on a GSL coding pattern during the process of manufacturing the memory device 2200. Alternatively, under the control of the memory controller 2100, the memory device 2200 may program the ground selection transistors included in each of the plurality of memory blocks based on the GSL coding pattern. In an embodiment, when an erase operation on a memory block is performed, the memory device 2200 may perform a programming operation on the ground selection transistors based on the GSL coding pattern.

[0261] According to the present disclosure, a memory device may include a plurality of memory blocks, and each of the plurality of memory blocks may include a plurality of cell strings. The plurality of cell strings may be respectively connected to a plurality of string selection lines and may share the same ground selection line. In each of the plurality of cell strings, the memory device may program the ground selection transistors such that at least two adjacent ground selection transistors have the same programming state. In this case, since the cell characteristics of the ground selection transistors are improved, the reliability and performance of the memory device are improved.

[0262] Although the present disclosure includes many specific implementation details, these should not be construed as limitations on the scope of the claimed subject matter. Certain features described in the context of separate embodiments in the present disclosure may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented separately or in any suitable sub-combination in multiple embodiments. Additionally, although features may be described above as acting in certain combinations, one or more features from a combination may in some cases be stripped from the combination, and the combination may be directed to a sub-combination or variation of a sub-combination.

[0263] Although the present disclosure has been described with reference to embodiments of the present disclosure, it will be apparent to those of ordinary skill in the art that various changes and modifications can be made to the present disclosure without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A memory device, the memory device comprising: A first cell string, the first cell string being disposed between a first bit line and a common source line, and including a first string selection transistor connected to a first string selection line and first ground selection transistors respectively connected to a plurality of ground selection lines; And A second cell string, the second cell string being disposed between the first bit line and the common source line, and including a second string selection transistor connected to a second string selection line and second ground selection transistors respectively connected to the plurality of ground selection lines, Wherein, at least two of the first ground selection transistors are configured to have a first programming state, and one or more remaining first ground selection transistors among the first ground selection transistors are configured to have an erased state, and Wherein, at least two of the second ground selection transistors are configured to have the first programming state, and one or more remaining second ground selection transistors among the second ground selection transistors are configured to have the erased state.

2. The memory device according to claim 1, wherein, The at least two first ground selection transistors are adjacent to each other, and Wherein, the at least two second ground selection transistors are adjacent to each other.

3. The memory device according to claim 1, wherein, The first cell string further includes a first plurality of memory cells respectively connected to a plurality of word lines, and Wherein, the second cell string further includes a second plurality of memory cells respectively connected to the plurality of word lines.

4. The memory device according to claim 3, wherein, The first cell string further includes: A first dummy ground selection transistor, the first dummy ground selection transistor being disposed between the common source line and the first ground selection transistors, and connected to a first dummy ground selection line; and A second dummy ground selection transistor, the second dummy ground selection transistor being disposed between the first plurality of memory cells and the first ground selection transistors, and connected to a second dummy ground selection line, and Wherein, the second cell string further includes: A third dummy ground selection transistor, the third dummy ground selection transistor being disposed between the common source line and the second ground selection transistors, and connected to the first dummy ground selection line; and A fourth dummy ground selection transistor, the fourth dummy ground selection transistor being disposed between the second plurality of memory cells and the second ground selection transistors, and connected to the second dummy ground selection line.

5. The memory device according to claim 4, wherein, The first dummy ground selection transistor has the same state as the lowermost first ground selection transistor among the first ground selection transistors, Wherein, the second dummy ground selection transistor has the same state as the uppermost first ground selection transistor among the first ground selection transistors, Wherein, the third dummy ground selection transistor has the same state as the lowermost second ground selection transistor among the second ground selection transistors, Wherein, the fourth dummy ground selection transistor has the same state as the uppermost second ground selection transistor among the second ground selection transistors, Wherein, the lowermost first ground selection transistor indicates the ground selection transistor among the first ground selection transistors adjacent to the first dummy ground selection transistor, Among them, the top first ground selection transistor indicates the ground selection transistor among the first ground selection transistors that is adjacent to the second dummy ground selection transistor. Among them, the bottom second ground selection transistor is the ground selection transistor among the second ground selection transistors that is adjacent to the third dummy ground selection transistor, and Among them, the top second ground selection transistor indicates the ground selection transistor among the second ground selection transistors that is adjacent to the fourth dummy ground selection transistor.

6. The memory device according to claim 1, wherein, One of the at least two first ground selection transistors and one of the remaining second ground selection transistors are connected to the same ground selection line.

7. The memory device according to claim 1, the memory device further comprising: A third cell string, the third cell string being disposed between the first bit line and the common source line, and including a third string selection transistor connected to a third string selection line and third ground selection transistors respectively connected to the plurality of ground selection lines; And A fourth cell string, the fourth cell string being disposed between the first bit line and the common source line, and including a fourth string selection transistor connected to a fourth string selection line and fourth ground selection transistors respectively connected to the plurality of ground selection lines, Wherein, at least two of the third ground selection transistors are configured to have the first programming state, and one or more of the remaining third ground selection transistors are configured to have the erased state, and Wherein, at least two of the fourth ground selection transistors are configured to have the first programming state, and one or more of the remaining fourth ground selection transistors are configured to have the erased state.

8. The memory device according to claim 7, the memory device further comprising: A fifth cell string, the fifth cell string being disposed between the first bit line and the common source line, and including a fifth string selection transistor connected to a fifth string selection line and fifth ground selection transistors respectively connected to the plurality of ground selection lines; A sixth cell string, the sixth cell string being disposed between the first bit line and the common source line, and including a sixth string selection transistor connected to a sixth string selection line and sixth ground selection transistors respectively connected to the plurality of ground selection lines; A seventh cell string, the seventh cell string being disposed between the first bit line and the common source line, and including a seventh string selection transistor connected to a seventh string selection line and seventh ground selection transistors respectively connected to the plurality of ground selection lines; And An eighth cell string, the eighth cell string being disposed between the first bit line and the common source line, and including an eighth string selection transistor connected to an eighth string selection line and eighth ground selection transistors respectively connected to the plurality of ground selection lines.

9. The memory device according to claim 8, wherein, The number of the plurality of ground selection lines is 4 or 8.

10. The memory device according to claim 8, wherein, The number of the at least two first ground selection transistors is 2, 4 or 6.

11. The memory device according to claim 1, wherein, When the first cell string is selected, A first turn-on voltage is applied to at least two ground selection lines among the plurality of ground selection lines that are connected to the at least two first ground selection transistors, and a second turn-on voltage lower than the first turn-on voltage is applied to the remaining ground selection lines among the plurality of ground selection lines.

12. The memory device according to claim 1, wherein, A programming voltage is simultaneously applied to at least two first ground selection lines among the plurality of ground selection lines that are connected to the at least two first ground selection transistors, such that the at least two first ground selection transistors are programmed simultaneously, and wherein the programming voltage is simultaneously applied to at least two second ground selection lines among the plurality of ground selection lines that are connected to the at least two second ground selection transistors, such that the at least two second ground selection transistors are programmed simultaneously.

13. The memory device according to claim 1, the memory device further comprising: A third cell string, the third cell string being disposed between a second bit line and the common source line, and including a third string selection transistor connected to the first string selection line and third ground selection transistors respectively connected to the plurality of ground selection lines, wherein at least two of the third ground selection transistors are configured to have the first programming state, and one or more remaining third ground selection transistors among the third ground selection transistors are configured to have the erased state, and wherein the at least two first ground selection transistors and the at least two third ground selection transistors are respectively connected to the same ground selection line.

14. A memory device, the memory device comprising: A first cell string, the first cell string being connected to a first bit line, a first string selection line, and a plurality of ground selection lines; A second cell string, the second cell string being connected to the first bit line, a second string selection line, and the plurality of ground selection lines; A third cell string, the third cell string being connected to the first bit line, a third string selection line, and the plurality of ground selection lines; and A fourth cell string, the fourth cell string being connected to the first bit line, a fourth string selection line, and the plurality of ground selection lines, wherein when the first cell string is selected, a first turn-on voltage is applied to a first ground selection line and a second ground selection line among the plurality of ground selection lines, and a second turn-on voltage lower than the first turn-on voltage is applied to the remaining ground selection lines among the plurality of ground selection lines other than the first ground selection line and the second ground selection line, and wherein when the second cell string is selected, the first turn-on voltage is applied to the second ground selection line and a third ground selection line among the plurality of ground selection lines, and the second turn-on voltage is applied to the remaining ground selection lines among the plurality of ground selection lines other than the second ground selection line and the third ground selection line.

15. The memory device according to claim 14, wherein, The first ground selection line and the second ground selection line are adjacent to each other, and wherein the second ground selection line and the third ground selection line are adjacent to each other.

16. The memory device according to claim 15, wherein, When the third cell string is selected, the first turn-on voltage is applied to the third ground selection line and the fourth ground selection line among the plurality of ground selection lines, and the second turn-on voltage is applied to the remaining ground selection lines among the plurality of ground selection lines except the third ground selection line and the fourth ground selection line, and wherein the third ground selection line and the fourth ground selection line are adjacent to each other.

17. The memory device according to claim 14, the memory device further comprising: a fifth cell string connected to the first bit line, a fifth string selection line, and the plurality of ground selection lines; a sixth cell string connected to the first bit line, a sixth string selection line, and the plurality of ground selection lines; a seventh cell string connected to the first bit line, a seventh string selection line, and the plurality of ground selection lines; and an eighth cell string connected to the first bit line, an eighth string selection line, and the plurality of ground selection lines.

18. The memory device according to claim 17, wherein, The number of the plurality of ground selection lines is 8.

19. The memory device according to claim 17, wherein, Each of the first cell string to the eighth cell string is connected to a plurality of word lines, a first dummy ground selection line, and a second dummy ground selection line, wherein the first dummy ground selection line is disposed between the substrate and the plurality of ground selection lines, and wherein the second dummy ground selection line is disposed between the plurality of word lines and the plurality of ground selection lines.

20. A method of operating a memory device, the memory device including a plurality of cell strings disposed between a bit line and a common source line, the plurality of cell strings being respectively connected to a plurality of string selection lines, and each of the plurality of cell strings being connected to a plurality of word lines and a plurality of ground selection lines, the method comprising: selecting at least two ground selection lines among the plurality of ground selection lines; simultaneously applying a programming voltage to the at least two ground selection lines; and simultaneously applying a verification voltage to the at least two ground selection lines.

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