Memory controller, memory system, and method of operating memory controller

Abstract

A memory controller, a memory system, and a method of operating the memory controller are provided. The memory controller includes: a valley search manager configured to perform a valley search operation to search for a valley between threshold voltage distributions associated with the plurality of memory cells, and obtain a valley read level corresponding to the valley; and a read level generator. The read level generator is configured to: model a cumulative cell count function between the threshold voltage distributions based on a plurality of read levels; generating a cumulative read level between the threshold voltage distributions based on the cumulative cell count function; and generating an optimal read level based on the valley read level and the accumulated read level.

Description

Technical Field

[0001] The present disclosure relates to a memory controller and a memory system including the memory controller, and more particularly, to a memory controller that generates an optimal read level using a valley read level and an accumulated read level. Background Art

[0002] Flash memory is a non-volatile memory that can retain stored data even when power is turned off. Storage devices including flash memory, such as solid state drives (SSDs) and memory cards, are widely used, and storage devices are useful for storing or moving large amounts of data.

[0003] As the data storage capacity of flash memory increases and the number of bits stored per memory cell increases, the tolerance between multiple threshold voltage distributions may decrease. Therefore, in order to minimize errors during the data read process, it is necessary to calculate an optimal read level that can determine multiple threshold voltage distributions.

[0004] To calculate the optimal read level, a valley search operation may be performed on the threshold voltage distribution of the memory cells. Memory cells may deteriorate due to various reasons, such as repeated programming / erasing operations on the memory cells or long-term exposure to high temperatures. When deterioration occurs in the memory cells, errors may occur when a read operation is performed at the valley read level found through the valley search operation.

[0005] Therefore, techniques are needed to generate an optimal read level to minimize errors. Summary of the Invention

[0006] Embodiments provide a memory controller that generates an optimal read level by using a valley read level and an accumulated read level obtained by performing a valley search operation, thereby using the optimal read level to improve reliability when performing a data read operation.

[0007] According to an aspect of the present disclosure, a memory controller configured to control a memory device including a plurality of memory cells includes: a valley search manager configured to perform a valley search operation to search for a valley between threshold voltage distributions associated with the plurality of memory cells and obtain a valley read level corresponding to the valley; and a read level generator configured to: model an accumulated cell count function between the threshold voltage distributions based on a plurality of read levels; generate an accumulated read level between the threshold voltage distributions based on the accumulated cell count function; and generate an optimal read level based on the valley read level and the accumulated read level.

[0008] According to one aspect of the present disclosure, a method of operating a memory controller includes: performing a valley search operation that searches for valleys between threshold voltage distributions associated with a plurality of memory cells to obtain a plurality of read points including a plurality of read levels and cumulative cell count values respectively corresponding to the plurality of read levels; generating a valley read level corresponding to the valley based on the plurality of read points; modeling a cumulative cell count function between the threshold voltage distributions based on the plurality of read points, and generating a cumulative read level between the threshold voltage distributions based on the cumulative cell count function; and generating an optimal read level by applying a valley weight to the valley read level and applying a cumulative weight to the cumulative read level.

[0009] According to one aspect of the present disclosure, a memory system includes: a memory device; and a memory controller, wherein the memory device is configured to generate cumulative cell count values respectively corresponding to a plurality of read levels during a valley search operation that searches for valleys between threshold voltage distributions associated with a plurality of memory cells, and wherein the memory controller is configured to: receive the cumulative cell count values and generate a valley read level corresponding to the valley based on the cumulative cell count values; model a cumulative cell count function that takes the plurality of read levels as inputs and outputs the cumulative cell count values respectively corresponding to the plurality of read levels; generate a cumulative read level based on the cumulative cell count function; and generate an optimal read level based on the valley read level and the cumulative read level. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and / or other aspects will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 is a block diagram showing a host-memory system according to an embodiment; Figure 2 is a block diagram illustrating a memory controller according to an embodiment; Figure 3 is a diagram illustrating a memory device according to an embodiment; Figure 4 is a perspective view showing a memory block according to an embodiment; Figure 5 is a circuit diagram showing a memory block according to an embodiment; Figure 6 is a diagram for explaining the state of a memory cell according to an embodiment; Figure 7A is a diagram showing the distribution of threshold voltages of memory cells according to an embodiment; Figure 7B is a diagram showing the distribution of threshold voltages of memory cells according to an embodiment; Figure 8 It is a diagram for explaining the cumulative unit count value according to an embodiment; Figure 9 It is a diagram for explaining the method of generating a valley read level according to an embodiment; Figure 10 It is a diagram for explaining the method of generating a cumulative read level according to an embodiment; Figure 11 It is a diagram for explaining the method of generating an optimal read level according to an embodiment; Figure 12 It is a diagram for explaining the cumulative weight and valley weight according to an embodiment; Figure 13 It is a diagram showing the method of generating an optimal read voltage corresponding to multiple states on a threshold voltage distribution according to an embodiment; Figure 14A It is a diagram showing the error bits of the threshold voltage distribution of a memory cell according to an embodiment; Figure 14B It is a diagram showing the error bits of the threshold voltage distribution of a memory cell according to an embodiment; Figure 15 It is a diagram showing the method of generating an optimal read voltage corresponding to multiple states on a threshold voltage distribution according to an embodiment; Figure 16 It is a flowchart for explaining the method of operating a memory controller according to an embodiment; Figure 17 It shows a system to which a storage device according to an embodiment is applied. Detailed Description of the Invention

[0011] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and the description of the same components that has been given is omitted.

[0012] Figure 1 It is a block diagram showing a host-memory system according to an embodiment.

[0013] Refer to Figure 1 , the host-memory system 10 may include a host 200 and a memory system 100. Additionally, the memory system 100 may include a memory controller 110 and a memory device 120.

[0014] The host 200 may communicate with the memory system 100 through an interface. Here, the interface may be implemented using, for example, Non-Volatile Memory Express (NVMe), Non-Volatile Memory Management Interface (NVMe MI), or NVMe over Fabric (NVMeof).

[0015] The host 200 may provide a write request to the memory system 100 to request storing data in the memory system 100. Additionally, the host 200 may provide a logical address and data for identifying the data to the memory system 100. In one embodiment, the logical address may be included in the write request.

[0016] The host 200 may provide a read request to the memory system 100 to request the memory system 100 to provide data stored in the memory system 100. Additionally, the host 200 may provide a logical address for identifying the data to the memory system 100. In one embodiment, the logical address may be included in the read request.

[0017] The memory system 100 may include a memory controller 110 and a memory device 120. The memory controller 110 and the memory device 120 may be integrated into one semiconductor device. As an example, the memory controller 110 and the memory device 120 may be integrated into one semiconductor device. For example, the memory system 100 may be implemented as an internal memory built into an electronic device and may be an embedded universal flash storage (UFS) memory device, an embedded multimedia card (eMMC), or an SSD. In some embodiments, the memory system 100 may be implemented as an external memory removable from the electronic device, and may be, for example, a UFS memory card, a compact flash (CF) memory card, a secure digital (SD) memory card, a micro secure digital (micro-SD) memory card, a mini secure digital (Mini-SD) memory card, an extreme digital (xD) memory card, or a memory stick.

[0018] The memory controller 110 may control the memory device 120 to read data stored in the memory device 120 or write (or program) data to the memory device 120 in response to a request (e.g., a write request or a read request) provided from the host 200. Specifically, the memory controller 110 may control a write operation (or a program operation), a read operation, and an erase operation for the memory device 120 by providing a command / address CMD / ADD and a control signal CTRL to the memory device 120. Additionally, data DATA to be written and data DATA to be read may be transmitted and received between the memory controller 110 and the memory device 120.

[0019] The memory controller 110 can communicate with the host 200 through various standard interfaces. For example, the memory controller 110 can include interface circuits, and the interface circuits can provide various standard interfaces between the host 200 and the memory controller 110. The standard interfaces can include various interface methods, such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI Express (PCI-e), IEEE 1394, Universal Serial Bus (USB), SD card, Multimedia Card (MMC), Embedded Multimedia Card (eMMC), UFS, and CF card interfaces.

[0020] The memory controller 110 can include an Error Correction Code (ECC) circuit 111, a valley search manager 112, and a read level generator 113.

[0021] The ECC circuit 111 can be configured to detect errors in the data read from the memory device 120 and use error correction codes to correct the detected errors. The ECC circuit 111 can include any circuit, system, or device for error correction. When the ECC circuit 111 performs error correction, the error correction may fail when the number of error bits is greater than the correction threshold. In an embodiment, based on whether the ECC circuit 111 successfully corrects errors, the valley search manager 112 and / or the read level generator 113 can perform operations to generate an optimal read level. For example, the valley search manager 112 can generate a valley read level based on whether the ECC circuit 111 successfully corrects errors. Based on whether the ECC circuit 111 successfully corrects errors, the read level generator 113 can obtain an accumulated read level and generate an optimal read level based on the accumulated read level.

[0022] The valley search manager 112 can perform a valley search operation. Specifically, the valley search manager 112 can control the memory device 120 to perform a valley search operation on the memory device 120. The valley search operation can be an operation to search for a valley between the threshold voltage distributions of the memory cells included in the memory device 120. As an example, the valley search operation can be an operation to search for a valley formed at the intersection point of the threshold voltage distribution of the first state and the threshold voltage distribution of the second state among multiple states representing the values stored in the memory cells in the threshold voltage distribution. The second state can be adjacent to the first state and have a threshold voltage level higher than that of the first state.

[0023] The valley search manager 112 can obtain a valley read level corresponding to a valley through a valley search operation. The valley read level corresponding to a valley can represent the threshold voltage value of the valley in the threshold voltage distribution. The cell count value corresponding to a valley can represent the number of memory cells corresponding to the valley read level.

[0024] The valley search manager 112 can generate a valley read level based on multiple read points. The multiple read points can include multiple read levels and cumulative cell count values respectively corresponding to the multiple read levels. Specifically, the valley search manager 112 can model a cell count function based on the multiple read levels and the cumulative cell count values corresponding to the multiple read levels, search for a valley based on the modeled valley cell count function, and calculate the valley read level corresponding to the valley.

[0025] The cumulative cell count value can be a value obtained by sequentially accumulating the number of memory cells corresponding to each of the multiple read levels. The cumulative cell count value can be obtained by performing a counting operation (e.g., on-cell or off-cell counting) on the read data read using the multiple read levels through a valley search operation. For example, the first cumulative cell count value can be a value obtained by counting the on-cells (or off-cells) at the first read level, and the second cumulative cell count value can be a value obtained by counting the on-cells (or off-cells) at the second read level. As an example, the valley search manager 112 can obtain multiple read points from the memory device 120. However, the valley search manager 112 is not necessarily limited thereto, and the memory controller 110 can obtain multiple read points through a valley search operation.

[0026] The valley search manager 112 can perform a valley search operation for multiple states in the threshold voltage distribution and obtain a valley read voltage corresponding to each state. The valley search manager 112 can find the valleys of two adjacent states. The valley formed by one state among the multiple states and the state adjacent to the one state can be referred to as the valley corresponding to the one state. For example, the valley corresponding to the first state can mean the first valley formed by the first state and the second state adjacent to the first state, and the valley read voltage corresponding to the first state can mean the read voltage corresponding to the first valley. The valley search manager 112 can obtain the valley read level corresponding to each valley.

[0027] The read level generator 113 may manage or adjust the read level (or read voltage). The read level may be the voltage applied to a word line to read data stored in a programmed memory cell. For example, when the ECC circuit 111 fails to correct an error in the read data, the read level generator 113 may adjust the read level used in the memory device 120. The read level generator 113 may adjust the read level used in the memory device 120 to generate an optimal read level.

[0028] The read level generator 113 may be configured to determine an optimal read level. The optimal read level voltage may also be referred to as the optimal read level. The optimal read level may refer to the voltage level among the threshold voltage levels at which the lowest number of error bits occurs when a read operation is performed. By referring to the threshold voltage distribution corresponding to the memory cells included in the memory device 120, the threshold voltage distribution of ideal memory cells may form a symmetric distribution. However, the memory cells may deteriorate over time. The memory cells may deteriorate due to various factors. For example, the various factors may include charge leakage, read interference, program interference, coupling between adjacent memory cells, temperature variations, voltage variations, and deterioration of the memory cells due to repeated programming and erasing.

[0029] As the memory cells deteriorate, the threshold voltage distribution corresponding to the deteriorated memory cells may form an asymmetric distribution. Due to the asymmetry of the threshold voltage distribution, errors may occur even when a read operation is performed depending on the valley read level corresponding to the valley obtained through a valley search operation. Therefore, it is necessary to generate an optimal read level that causes fewer errors by using the valley read level calculated through the valley search operation.

[0030] The read level generator 113 may generate an optimal read level based on the valley read level and the cumulative read level. The read level generator 113 may receive the valley read level from the valley search manager 112. The read level generator 113 may generate the cumulative read level based on a plurality of read levels and the cumulative cell count values corresponding to the plurality of read levels. As an example, the read level may also be referred to as the read voltage level.

[0031] The read level generator 113 may model a cumulative cell count function between a plurality of read levels and the cumulative cell count values corresponding to the plurality of read levels with respect to the threshold voltage distribution. The cumulative cell count function may be a function representing the cumulative cell count values corresponding to a plurality of threshold voltages.

[0032] In one embodiment, the read level generator 113 may model the cumulative cell count function using a plurality of read points obtained through a valley search operation. As an example, the read level generator 113 may receive the plurality of read points from the memory device 120, or may receive the plurality of read points from another component of the memory controller 110 (e.g., the valley search manager 112 or the count logic). By modeling the cumulative cell count function using the plurality of read points obtained through the valley search operation, the cumulative cell count function can be modeled without additional components. Therefore, the production cost of the memory can be reduced and the degree of freedom in memory design can be increased.

[0033] The read level generator 113 may generate a cumulative read level based on the cumulative cell count function. The read level generator 113 may generate a cumulative read level corresponding to an ideal cell count value based on the cumulative cell count function. When the ideal cell count value is the output of the cumulative cell count function, the cumulative read level may be the input value of the cumulative cell count function.

[0034] In one embodiment, the ideal cell count value may be a value obtained by evenly dividing the number of memory cells included in the memory device 120 into a plurality of states in the threshold voltage distribution. The ideal cell count value may mean the number of memory cells included in one state when the plurality of memory cells are evenly divided into a plurality of states.

[0035] The read level generator 113 may generate an optimal read level based on the valley read level and the cumulative read level. The read level generator 113 may generate the optimal read level by applying a valley weight to the valley read level and applying a cumulative weight to the cumulative read level. In one embodiment, the valley weight and the cumulative weight are positive numbers, and the cumulative weight may be greater than the valley weight. As an example, the cumulative weight may be twice the valley weight. However, it is not necessarily limited thereto.

[0036] The read level generator 113 may generate optimal read levels corresponding to a plurality of states in the threshold voltage distribution. The read level generator 113 may generate an optimal read level between two adjacent states among the plurality of states. The optimal read level corresponding to a specific state may mean the optimal read level between the specific state and the state adjacent to the specific state. For example, in the threshold voltage distribution, when the first state and the second state correspond to adjacent states, the optimal read level corresponding to the first state may mean the optimal read level between the first state and the second state. When the second state and the third state correspond to adjacent states, the optimal read level corresponding to the second state may mean the optimal read level between the second state and the third state.

[0037] The memory controller 110 may control the memory device 120 such that the memory device 120 may perform a read operation according to an optimal read level. The memory controller 110 may provide information related to the optimal read level to the memory device 120 such that data may be read from the memory device 120. For example, the memory controller 110 may provide a control signal CTRL for controlling a read level based on the optimal read level to the memory device 120, or may provide information related to the optimal read level to the memory device 120. The memory device 120 may generate an internal control signal based on the control signal CTRL or the information related to the optimal read level to control a level of a read voltage.

[0038] The valley search manager 112 and / or the read level generator 113 may be implemented as hardware or software, or a combination of hardware and software. As an example, the valley search manager 112 and / or the read level generator 113 may be implemented as firmware or software for generating an optimal read level, or may be implemented as hardware capable of performing a series of operations. As an example, when the valley search manager 112 and / or the read level generator 113 are implemented as software including firmware, the memory controller 110 may include a memory storing the software, and the valley search manager 112 and / or the read level generator 113 may be loaded into the memory as software and executed by a processor.

[0039] The memory device 120 may include a non-volatile memory device, such as a flash memory. The flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. In one embodiment, the 3D memory array may include vertical NAND strings arranged in a vertical direction such that at least one memory cell is located on top of other memory cells. The at least one memory cell may include a charge trapping layer.

[0040] However, embodiments are not limited thereto, and the memory device 120 may include other types of memories. For example, the memory device 120 may include a non-volatile memory, and the non-volatile memory may be of various types, such as magnetic RAM (MRAM), spin transfer torque MRAM, conductive bridge RAM (CBRAM), ferroelectric RAM (FeRAM), phase RAM (PRAM), resistive RAM, nanotube RAM, polymer RAM (PoRAM), nano floating gate memory (NFGM), holographic memory, molecular electronic memory, or insulator resistance change memory. Hereinafter, embodiments will be described assuming that the memory device 120 is a flash memory device.

[0041] The memory device 120 may include a memory cell array 121 and control logic 122. The memory cell array 121 may include a plurality of memory blocks. Each memory block may include a plurality of memory cells arranged in a region where a plurality of word lines and a plurality of bit lines intersect. The plurality of memory cells may have a plurality of threshold voltage distributions depending on the programmed data. For example, when the memory cells are single-level cells (SLCs) that store one bit per memory cell, the memory cells may have two threshold voltage distributions depending on the programmed state. In another example, when the memory cells are multi-level cells (MLCs) that store two bits per memory cell, the memory cells may have four threshold voltage distributions depending on the programmed state. In another example, additionally, when the memory cells are triple-level cells (TLCs) that store three bits per memory cell, the memory cells may have eight threshold voltage distributions depending on the programmed state. Thus, when the memory cells store four or more bits per memory cell, the memory cells may have sixteen or more threshold voltage distributions depending on the programmed state. One threshold voltage distribution may correspond to a specific state of the memory cells.

[0042] The control logic 122 may control the overall operation of the memory device 120. As an example, the control logic 122 may generate a plurality of read points through a valley search operation. The control logic 122 may send the plurality of read points to the memory controller 110.

[0043] The memory controller 110 may model a cumulative cell count function using a cumulative cell count value, and generate an optimal read level by applying weights to each of the cumulative read level and the valley read level obtained based on the cumulative cell count function, thereby reducing errors in the read data. Thus, when performing a data read operation, the reliability can be improved.

[0044] Figure 2 is a block diagram for explaining a memory controller according to an embodiment. Because Figure 2 the memory controller 110, the valley search manager 112, and the read level generator 113 shown in Figure 1 correspond to the memory controller 110, the valley search manager 112, and the read level generator 113 shown in

[0045] the description of the memory controller 110, the valley search manager 112, and the read level generator 113 that has been given is omitted.

[0046] The CPU 114 can control the overall operation of the memory controller 110. Specifically, the CPU 114 can receive commands from a host (e.g., the host 200 in Figure 1 ) and control the memory controller 110 to perform operations according to the commands. The CPU 114 can perform garbage collection, address mapping, wear leveling, etc., to manage the memory device (e.g., the memory device 120 in Figure 1 ) by executing the firmware loaded in the ROM 115 of the memory controller 110.

[0047] The ROM 115 can be a ROM that stores programs executed by the CPU 114. The ROM 115 can store programs that implement the operation method of the memory controller 110 or firmware that records programs. The firmware can include a three-layer structure, e.g., a host interface layer (HIL), a flash translation layer (FTL), and a flash interface layer (FIL). In an embodiment, the firmware can be stored in the memory device.

[0048] In the buffer memory 116, software or firmware for operating the memory system 100 can be loaded from the ROM 115 or from the memory device. Additionally, the buffer memory 116 can temporarily store data sent from the host, data generated by the CPU 114, and data read from the memory device. The buffer memory 116 can include at least one dynamic random access memory (DRAM) or static random access memory (SRAM). In an embodiment, the buffer memory 116 can be provided within the memory controller 110, but can also be located outside the memory controller 110.

[0049] The ECC circuit 111 can perform error detection and correction functions on the read data read from the memory device. More specifically, the ECC circuit 111 can generate parity bits for the write data to be written to the memory device, and the parity bits generated in this way can be stored in the memory device together with the write data. When the data is the read data read from the memory device, the ECC circuit 111 can use the parity bits read from the memory device together with the read data to correct errors in the read data, and can output the error-corrected read data. In an embodiment, when the number of bits in error in the read data exceeds the limit that the ECC circuit 111 can correct, error correction may fail. In this case, the memory controller 110 can generate an optimal read level.

[0050] The read level generator 113 can determine whether to generate an optimal read level depending on whether error correction is successful in the ECC circuit 111. When error correction is successful, the read level generator 113 may not be as described above with reference to Figure 1The described optimal read level is generated based on the valley read level and the cumulative read level. The read level generator 113 may not model the cumulative cell count function based on multiple points and may not generate the cumulative read level. The read level generator 113 may control the memory device to perform a read operation at a pre-existing read level. As an example, the valley search manager 112 may also determine whether to generate the valley read level depending on whether error correction is successful in the ECC circuit 111. When ECC error correction is successful, the valley search manager 112 may not perform a valley search operation.

[0051] When error correction fails, the read level generator 113 may generate the optimal read level. Additionally, as an example, the valley search manager 112 may generate the valley read level through a valley search operation. The read level generator 113 may model the cumulative cell count function based on multiple read points generated through the valley search operation. The multiple read points may include multiple read levels and cumulative cell count values respectively corresponding to the multiple read levels. The read level generator 113 and the valley search manager 112 may be implemented using a hardware circuit and / or a processor that executes instructions stored in a memory.

[0052] The read level generator 113 may model the cumulative cell count function of a cubic function. As an example, the read level generator 113 may model the cumulative cell count function of a cubic function based on at least four read points. For example, the read level generator 113 may model the cumulative cell count function of a cubic function that takes four read levels as inputs and outputs four cumulative cell count values respectively corresponding to the four read levels.

[0053] The read level generator 113 may generate the cumulative read level based on the cumulative cell count function. The read level generator 113 may use the cumulative cell count function to obtain the cumulative read level corresponding to the ideal cell count value. The read level generator 113 may generate the optimal read level based on the valley read level and the cumulative read level obtained through the valley search operation.

[0054] When a read operation is performed, the voltage level at which the lowest number of error bits appears in the threshold voltage distribution may be between the cumulative read level and the valley read level. Accordingly, the read level generator 113 may calculate the threshold voltage value between the cumulative read level and the valley read level as the optimal read level. The optimal read level may be closer to the cumulative read level than the valley read level. The read level generator 113 may generate the optimal read level by applying different weights to each of the valley read level and the cumulative read level. As an example, the read level generator 113 may generate the optimal read level by applying a weight larger than the valley read level to the cumulative read level.

[0055] The host interface 117 can send data packets to the host and receive data packets from the host. The data packets sent from the host to the host interface 117 can include commands or data to be written to the memory device, and the data packets sent from the host interface 117 to the host can include responses to commands or data read from the memory.

[0056] The memory interface 118 can send data to be written to the memory device to the memory device or receive data read from the memory device. The memory interface 118 can be implemented to conform to a standard protocol, such as the Toggle or Open NAND Flash Interface (ONFI). In an embodiment, the components of the memory controller 110 can communicate with each other via the bus 119.

[0057] Figure 3 is a diagram illustrating a memory device according to an embodiment.

[0058] Reference Figure 3 , the memory device 120 can include a memory cell array 121, a control logic 122, a voltage generator 123, a row decoder 124, and a page buffer 125.

[0059] The memory cell array 121 can include a plurality of memory cells and can be connected to word lines WL, string select lines SSL, ground select lines GSL, and a plurality of bit lines BL. Specifically, the memory cell array 121 can be connected to the row decoder 124 via the word lines WL, string select lines SSL, and ground select lines GSL, and can be connected to the page buffer 125 via the plurality of bit lines BL.

[0060] The memory cell array 121 can include a plurality of memory blocks BLK1 to BLKz (z is a positive integer). For example, each of the memory blocks BLK1 to BLKz can include a plurality of memory cells. Each of the plurality of memory blocks BLK1 to BLKz can have a three-dimensional structure (or a vertical structure). The row decoder 124 can select the plurality of memory blocks BLK1 to BLKz. For example, the row decoder 124 can select a memory block corresponding to a block address from among the plurality of memory blocks BLK1 to BLKz.

[0061] Each memory cell included in the memory cell array 121 can store at least one bit. For example, the memory cell can be a single-level cell (SLC) that stores 1 bit of data. In another example, the memory cell can be a multi-level cell (MLC) that stores 2 bits of data. In another example, the memory cell can be a triple-level cell (TLC) that stores 3 bits of data. In another example, the memory cell can be a quad-level cell (or quadrupole-level cell QLC) that stores 4 bits of data. However, the embodiments are not limited thereto. For example, among the multiple memory blocks BLK1 to BLKz included in the memory cell array 121, some memory blocks can be SLC blocks. Other memory blocks can be MLC blocks or TLC blocks.

[0062] When an erase voltage is applied to the memory cell array 121, multiple memory cells can be in an erased state, and when a program voltage is applied to the memory cell array 121, multiple memory cells can be in a programmed state. In this case, each memory cell can have an erased state or at least one programmed state classified based on a threshold voltage. That is, the state of the memory cell can include an erased state and at least one programmed state, and a specific state of each memory cell can be an erased state or a specific programmed state.

[0063] The control logic 122 can generally control various operations of the memory device 120. For example, the control logic 122 can output various control signals for writing data to or reading data from the memory cell array 121 based on a command CMD, an address ADDR, and a control signal CTRL.

[0064] The various control signals output from the control logic 122 can be provided to the voltage generator 123, the row decoder 124, and the page buffer 125. The control logic 122 can provide a voltage control signal CTRL_vol to the voltage generator 123. The control logic 122 can output the voltage control signal CTRL_vol such that multiple read operations are performed at different read levels to calculate an optimal read level, and the voltage generator 123 can generate multiple read voltages based on the voltage control signal CTRL_vol.

[0065] As an example, the control logic 122 can output the voltage control signal CTRL_vol such that the read level changes according to a predetermined level interval, with one read level as the starting position. Additionally, the control logic 122 can receive information related to the optimal read level calculated according to the above embodiments, and can control the voltage generator 123 such that data is read according to the optimal read level. In an embodiment, the control logic 122 can output the voltage control signal CTRL_vol such that multiple read operations are performed at different read levels during a valley search operation.

[0066] In some embodiments, the control logic 122 may further include a unit counter 126. For example, the memory system may be implemented such that cumulative unit count values ccc corresponding to multiple read levels are generated in the memory device 120 and provided to the memory controller (e.g., Figure 1 memory controller 110). The unit counter 126 may count the number of memory cells corresponding to a specific threshold voltage range from the data sensed by the page buffer 125. The unit counter 126 may generate a cumulative unit count value ccc indicating the number of memory cells. In one embodiment, the memory cells being counted may be referred to as off cells. In another embodiment, the memory cells being counted may be referred to as on cells. As an example, the unit counter 126 may generate cumulative unit count values ccc corresponding to multiple read levels during a valley search operation. The unit counter may be implemented using hardware such as Boolean logic hardware and other hardware circuits such as flip - flops.

[0067] The voltage generator 123 may be connected to the memory cell array 121 through multiple word lines WL. The voltage generator 123 may generate various types of voltages based on a voltage control signal CTRL_vol to perform programming, reading, and erasing operations on the memory cell array 121. The voltage generator 123 may generate a word line voltage VWL, e.g., a programming voltage, a verification voltage, a reading voltage, an erasing voltage, etc. During a reading operation, the voltage generator 123 may generate a reading voltage under the control of the control logic 122 and provide the reading voltage to the row decoder 124.

[0068] The row decoder 124 may select a specific word line from among the word lines WL in response to a row address X - ADDR received from the control logic 122. Specifically, during a reading operation, the row decoder 124 may provide the reading voltage to the selected word line. Additionally, in response to a row address X - ADDR received from the control logic 122, the row decoder 124 may select some string selection lines from among the string selection lines SSL or some ground selection lines from among the ground selection lines GSL.

[0069] The page buffer 125 may be connected to the memory cell array 121 through multiple bit lines BL. The page buffer 125 may select some bit lines BL in response to a column address Y - ADDR received from the control logic 122. During a reading operation, the page buffer 125 operates as a sense amplifier and may sense the data stored in the selected memory cells through the selected bit lines.

[0070] The page buffer 125 may temporarily store the data DATA read from the memory cell array 121, or may temporarily store the data DATA to be stored in the memory cell array 121.

[0071] The page buffer 125 may include a plurality of page buffers respectively connected to a plurality of bit lines BL. The plurality of page buffers may be arranged to correspond to each bit line, and each page buffer may include a plurality of latches. Hereinafter, the page buffer 125 is defined as including the page buffers connected to each bit line. However, in an embodiment, the term may be defined differently, and as an example, one page buffer may be provided to correspond to a plurality of bit lines, and the structural unit provided to correspond to each bit line may be defined as a page buffer unit.

[0072] Figure 4 is a perspective view showing a memory block according to an embodiment.

[0073] Reference Figure 4 , the memory block BLKa may include a stack ST extending in the vertical direction VD on top of the substrate SUB. For example, the memory block BLKa may include a single stack ST between the substrate SUB and the bit lines BL1 to BL3. The common source line CSL may be provided on the substrate SUB, and in a region of the substrate SUB between two adjacent common source lines CSL, insulating films IL extending in the second horizontal direction HD2 are sequentially provided in the vertical direction VD, and the insulating films IL are spaced apart by a specific distance in the vertical direction VD. Columns P penetrating the insulating films IL in the vertical direction VD are provided in a region between two adjacent common source lines CSL of the substrate SUB. The columns P may be referred to as channel holes. The columns P may be formed in a cup shape (or closed-bottom cylindrical shape) extending in the vertical direction VD. The surface layer S of each column P may include a first type of silicon material and may be used as a channel region. In addition, the inner layer I of each column P may include an insulating material such as silicon oxide or air gap.

[0074] In a region between two adjacent common source lines CSL, a charge storage layer CS is provided along the exposed surfaces of the insulating films IL, the columns P, and the substrate SUB. The charge storage layer CS may include a gate insulating layer, a charge trapping layer, and a blocking insulating layer. For example, the charge storage layer CS may have an oxide-nitride-oxide (ONO) structure. In addition, in a region between two adjacent common source lines CSL, gate electrodes GE such as selection lines GSL and SSL and word lines WL1 to WL8 are provided on the exposed surface of the charge storage layer CS. A drain DR is provided on each of the plurality of columns P. On the drain DR, bit lines BL1 to BL3 extending in the first horizontal direction HD1 and spaced apart by a specific distance in the second horizontal direction HD2 are provided.

[0075] Figure 5 is a circuit diagram showing a memory block according to an embodiment.

[0076] Reference Figure 5, the memory block BLK may include NAND strings NS11 to NS33, and each NAND string (e.g., NS11) may include a string select transistor SST, a plurality of memory cells MC, and a ground select transistor GST connected in series. The string select transistor SST, the ground select transistor GST, and the memory cells MC included in each NAND string may form a structure stacked in a vertical direction on a substrate.

[0077] The bit lines BL1 to BL3 may extend in a first direction, and the word lines WL1 to WL8 may extend in a second direction. The NAND strings NS11, NS21, and NS31 may be located between the first bit line BL1 and the common source line CSL, the NAND strings NS12, NS22, and NS32 may be located between the second bit line BL2 and the common source line CSL, and the NAND strings NS13, NS23, and NS33 may be located between the third bit line BL3 and the common source line CSL.

[0078] The string select transistor SST may be connected to a corresponding one of the string select lines SSL1 to SSL3. The memory cells MC may be respectively connected to the corresponding word lines WL1 to WL8. The ground select transistor GST may be connected to a corresponding one of the ground select lines GSL1 to GSL3. The string select transistor SST may be connected to a corresponding bit line, and the ground select transistor GST may be connected to the common source line CSL. Here, the number of NAND strings, the number of word lines, the number of bit lines, the number of ground select lines, and the number of string select lines may vary depending on the embodiment.

[0079] Figure 6 is a diagram illustrating the states of memory cells according to an embodiment.

[0080] Reference Figure 6 , Figure 6 shows the states E and P1 to P7 of TLC. Figure 6 The illustrated embodiment is shown based on TLC, but the embodiment is not limited thereto. The embodiments described below can also be applied to SLC (which may have 2 states (e.g., E and P1)), MLC (which may have 4 states (e.g., E and P1 to P3)), and QLC (which may have 16 states (e.g., E and P1 to P15)). In the embodiments described below, it is assumed that the memory cells are TLC.

[0081] In Figure 6 , the horizontal axis represents the threshold voltage Vth of the memory cells, and the vertical axis represents the number of memory cells (cell count) corresponding to the threshold voltage Vth or the memory cell count value.

[0082] The TLC can have any one of eight states E and P1 to P7. For example, the TLC can have an erase state E. In another example, the TLC can have any one of the seven programming states P1 to P7.

[0083] In one embodiment, as Figure 6 shown, the TLC can be programmed such that the areas of the threshold voltage distributions corresponding to each of the states E and P1 to P7 of the TLC are the same. The areas of the threshold voltage distributions corresponding to each of the TLC states E and P1 to P7 can be the same and have a symmetric structure. The number of cells corresponding to each of the TLC states E and P1 to P7 can be equal to the ideal cell count value.

[0084] The first reference read level Vrd1 can have a voltage level between the erase state E and the first programming state P1. The second reference read level Vrd2 can have a voltage level between the first programming state P1 and the second programming state P2. In this way, the i-th read voltage (where i is an integer greater than or equal to 3) can have a voltage level between the (i - 1)-th programming state and the i-th programming state.

[0085] When the first reference read level Vrd1 is applied to the selected word line, the memory cells having the erase state E become ON cells, and the memory cells having one of the first programming state P1 to the seventh programming state P7 become OFF cells. When the second reference read level Vrd2 is applied to the selected word line, the memory cells having the erase state E or the first programming state P1 become ON cells, and the memory cells having one of the second programming state P2 to the seventh programming state P7 become OFF cells. In this way, when the i-th read voltage (where i is an integer greater than or equal to 3) is applied to the selected word line, the memory cells having the erase state E or the (i - 1)-th programming state become ON cells, and the memory cells having one of the i-th to the j-th programming states (where j is an integer greater than or equal to i) become OFF cells.

[0086] Figure 7A is a diagram showing the distribution of the threshold voltages of the memory cells according to an embodiment. Specifically, Figure 7A it can show the threshold voltage distribution before degradation occurs in the memory cells. In the Figure 7A shown threshold voltage distribution, the horizontal axis can represent the threshold voltage Vth of the memory cells, and the vertical axis can represent the number of memory cells (cell count) corresponding to the threshold voltage Vth or the memory cell count value.

[0087] Figure 7A The threshold voltage distribution shown in Figure 6 represents a part of the threshold voltage distribution inFigure 7A The threshold voltage distributions corresponding to the sixth programming state P6 and the seventh programming state P7 can be shown. In Figure 7A , for ease of explanation, the sixth programming state P6 and the seventh programming state P7 are shown, but this is merely an example. Descriptions similar to or the same as those of the sixth programming state P6 and the seventh programming state P7 can be applied to other states in the threshold voltage distribution.

[0088] In Figure 7A , since the memory cells are not deteriorated, the threshold voltage distribution can form a symmetric distribution. The sixth programming state P6 can be adjacent to the seventh programming state P7, and the seventh valley V7 can be formed. The threshold voltage distributions of the sixth programming state P6 and the seventh programming state P7 can be symmetric with respect to each other. The threshold voltage distributions of the sixth programming state P6 and the seventh programming state P7 can be symmetric with respect to the seventh valley V7. This can be applied equally or similarly to Figure 6 the other states E and P1 to P5 in

[0089] Referring to Figure 7A , the sum distribution SD can be the sum of the sixth programming state P6 and the seventh programming state P7. The sum distribution SD can be modeled as a probability density function, and the valley of the sum distribution SD can mean a part of the probability density function corresponding to the sum distribution SD. For example, the sixth programming state P6 can be adjacent to the seventh programming state P7, and the seventh valley V7 can be formed as the valley of the sum distribution SD. Therefore, when determining the threshold voltage distributions of the sixth programming state P6 and the seventh programming state P7, the valley is associated with the memory cells acted upon by the read voltage applied to the corresponding word line.

[0090] The threshold voltage corresponding to the valley of the sum distribution can be the valley read level. The valley read level of the seventh valley V7 of the sum distribution SD can be the seventh reference read level Vrd7. When the threshold voltage distribution of the memory cells forms a symmetric distribution as shown in Figure 7A , the threshold voltage level corresponding to the valley can be the optimal read level. That is, the seventh reference read level Vrd7 can match the optimal read level. However, when the threshold voltage distribution of the memory cells does not form a symmetric distribution, the threshold voltage level corresponding to the valley may not match the optimal read level. Hereinafter, the case where the threshold voltage distribution of the memory cells is asymmetric is described with reference to Figure 7B

[0091] Figure 7B is a diagram showing the distribution of the threshold voltage of the memory cells according to an embodiment. Specifically, Figure 7B the threshold voltage distribution when deterioration occurs in the memory cells can be shown. The description of the threshold voltage distribution of the memory cells in Figure 7B is omitted.

[0092] In Figure 7B , the threshold voltage distribution may form an asymmetric distribution due to the deterioration of the memory cells. The sixth programming state P6 may be adjacent to the seventh programming state P7, and the seventh valley V7 may be formed. The threshold voltage distributions of the sixth programming state P6 and the seventh programming state P7 may be asymmetric with respect to each other. This may be equivalently or similarly applied to Figure 6 the other states E, P1 to P5 in

[0093] Referring to Figure 7B , the sum distribution SD may be the sum of the sixth programming state P6 and the seventh programming state P7. The sum distribution SD may be modeled as a probability density function, and the valley of the sum distribution SD may mean a part of the probability density function corresponding to the sum distribution SD. The threshold voltage corresponding to the valley of the sum distribution SD may be the valley read level. The valley of the sum distribution SD may be the seventh valley V7, and the valley read level may be the seventh reference read level Vrd7.

[0094] When the threshold voltage distribution of the memory cells forms an asymmetric distribution as shown in Figure 7B , the threshold voltage level corresponding to the valley may not be the optimal read level. The valley read level may not be the optimal read level. That is, the seventh reference read level Vrd7 may not match the optimal read level Voc.

[0095] After data is written to the memory cells, disturbance degradation or retention degradation may occur in the memory cells. Disturbance degradation refers to the phenomenon in which the threshold voltage of the memory cells changes due to programming, reading, erasing, coupling, etc. that occur around the memory cells. Retention degradation refers to the phenomenon in which charges are trapped in the charge trapping layer of the memory cells and the trapped charges leak out over time after the memory cells are programmed and the threshold voltage of the memory cells changes. When degradation occurs in the memory cells, the threshold voltage of the memory cells changes, so when the data in the memory cells is read using the initially set read level, errors may be included in the read data.

[0096] When the memory cells deteriorate, the threshold voltage distribution may change to asymmetric as shown in Figure 7B . For example, the graphs representing the threshold voltage distributions of the sixth programming state P6 and the seventh programming state P7 may be asymmetric with respect to each other. The threshold voltage distribution region of the seventh programming state P7 may be wider than the threshold voltage distribution region of the sixth programming state P6.

[0097] When performing a read operation using a valley read level, errors may be included in the read data. For example, when performing a read operation using the seventh reference read level Vrd7, errors may be included in the read data. Therefore, when the threshold voltage distribution forms an asymmetric distribution, it is necessary to find the optimal read level Voc.

[0098] In Figure 7B , the optimal read level Voc can be the threshold voltage value between the seventh reference read level Vrd7 and the cumulative read level Vcc. That is, the optimal read level Voc can be the threshold voltage between the valley read level and the cumulative read level Vcc. Therefore, the valley read level and the cumulative read level Vcc can be used to calculate the optimal read level Voc. The following refers to Figure 10 to describe the cumulative read level Vcc.

[0099] Figure 8 is a diagram for explaining the cumulative cell count value according to an embodiment. The description of the cumulative cell count value in Figure 3 that has been given is omitted.

[0100] Referring to Figure 8 , the first curve graph ga can represent the sum distribution SD of two adjacent threshold voltage distributions in the threshold voltage distribution. The horizontal axis of the first curve graph ga can represent the threshold voltage Vth of the memory cell, and the vertical axis of the first curve graph ga can represent the number of memory cells (cell count) corresponding to the threshold voltage Vth. The second curve graph gb can represent the cumulative cell count value ccc of two adjacent threshold voltage distributions among the threshold voltage distributions. The horizontal axis of the second curve graph gb can represent the threshold voltage Vth of the memory cell, and the vertical axis of the second curve graph gb can represent the cumulative cell count value ccc corresponding to the threshold voltage Vth.

[0101] Figure 8 The threshold voltage distribution shown in Figure 6 represents a part of the threshold voltage distribution in Figure 8 and can represent the distribution of two adjacent threshold voltages. For example, Figure 8 can show the threshold voltage distributions corresponding to the first programming state P1 and the second programming state P2. In Figure 8 , for ease of explanation, the first programming state P1 and the second programming state P2 are shown, but this is only an example. The same or similar description as that of the first programming state P1 and the second programming state P2 can be applied to other states in the threshold voltage distribution. For example, Figure 8 's description can also be applied to Figure 6 the sixth programming state P6 and the seventh programming state P7 in the threshold voltage distribution of TLC. However, this is only an example and can represent two other adjacent states.

[0102] The sum distribution SD of the first curve graph ga can be the sum of the first programming state p1 and the second programming state p2. The sum distribution SD can be modeled as a probability density function and can form a valley value V of the sum distribution SD.

[0103] The second curve graph gb can represent the cumulative cell count value ccc corresponding to multiple read levels. The multiple read levels can mean any threshold voltage level in the threshold voltage distribution of the first programming state p1 and the second programming state p2. For example, the multiple read levels can be the threshold voltages close to the threshold voltage corresponding to the valley value V. The multiple read levels can be the threshold voltages close to the valley read level Vv corresponding to the valley value V. For example, the second curve graph gb can represent the cumulative cell count value ccc corresponding to the first read level RL1 to the fourth read level RL4.

[0104] The cumulative cell count value ccc can be a value that sequentially accumulates the number of memory cells corresponding to each of the multiple read levels. The cumulative cell count value ccc can be a value that sequentially accumulates the number of memory cells as the read level increases. As an example, the cumulative cell count value ccc corresponding to the first read level RL1 can be the first cumulative cell count value ccc1. The first cumulative cell count value ccc1 can be obtained by performing a counting operation (e.g., turned-on cell or turned-off cell counting) on the read data read using the first read level RL1. For example, the first cumulative cell count value ccc1 can be the number of turned-on cells counted using the first read level RL1. The second cumulative cell count value ccc2 can correspond to the second read level RL2 and can be obtained by performing a counting operation (e.g., turned-on cell or turned-off cell counting) on the read data read using the second read level RL2. For example, the second cumulative cell count value ccc2 can be the number of turned-on cells counted using the second read level RL2. The third cumulative cell count value ccc3 can correspond to the third read level RL3 and can be obtained by performing a counting operation (e.g., turned-on cell or turned-off cell counting) on the read data read using the third read level RL3. For example, the third cumulative cell count value ccc3 can be the number of turned-on cells counted using the third read level RL3. The fourth cumulative cell count value ccc4 can correspond to the fourth read level RL4 and can be obtained by performing a counting operation (e.g., turned-on cell or turned-off cell counting) on the read data read using the fourth read level RL4. For example, the fourth cumulative cell count value ccc4 can be the number of turned-on cells counted using the fourth read level RL4.

[0105] Figure 9 is a diagram for explaining a method of generating a valley read level according to an embodiment. In Figure 9Among them, the horizontal axis may represent the threshold voltage Vth of the memory cells, and the vertical axis may represent the number of memory cells (cell count) corresponding to the threshold voltage Vth. The description given in Figure 8 has been omitted.

[0106] In one embodiment, a plurality of read levels may be set through a valley search operation, and cumulative cell count values corresponding to the plurality of read levels may be obtained. As an example, the plurality of read levels may be preset and may be spaced apart from each other by a specific distance. In Figure 9 a plurality of read levels are shown as four read levels, including a first read level RL1 to a fourth read level RL4, but are not limited thereto. Hereinafter, the case where the plurality of read levels are the first read level RL1 to the fourth read level RL4 will be described.

[0107] Referring together to Figure 8 and Figure 9 , a memory controller (e.g., Figure 1 the memory controller 110 of Figure 1 ) may obtain cumulative cell count values ccc corresponding to the plurality of read levels through a valley search operation. Specifically, a valley search manager (e.g.,

[0108] the valley search manager 112 in Figure 1 ) may obtain a first cumulative cell count value ccc1 to a fourth cumulative cell count value ccc4 corresponding to the first read level RL1 to the fourth read level RL4.

[0108] The memory controller may generate a valley read level Vv based on the cumulative cell count value ccc. The memory controller may generate a valley cell count value VCNT based on the cumulative cell count value ccc, and generate a valley read level Vv based on the valley cell count value VCNT. In one embodiment, the valley cell count value VCNT may be the difference between the cumulative cell count value corresponding to a specific read level among the plurality of read levels and the cumulative cell count value corresponding to the read level adjacent to the specific read level.

[0109] For example, the first valley cell count value VCNT1 can be the difference between a first cumulative cell count value ccc1 corresponding to a first read level RL1 and a second cumulative cell count value ccc2 corresponding to a second read level RL2. The second read level RL2 can be adjacent to the first read level RL1, and the first valley cell count value VCNT1 can be a value obtained by subtracting the first cumulative cell count value ccc1 from the second cumulative cell count value ccc2. The second valley cell count value VCNT2 can be the difference between the second cumulative cell count value ccc2 corresponding to the second read level RL2 and a third cumulative cell count value ccc3 corresponding to a third read level RL3. The third read level RL3 can be adjacent to the second read level RL2, and the second valley cell count value VCNT2 can be a value obtained by subtracting the second cumulative cell count value ccc2 from the third cumulative cell count value ccc3. The third valley cell count value VCNT3 can be the difference between the third cumulative cell count value ccc3 corresponding to the third read level RL3 and a fourth cumulative cell count value ccc4 corresponding to a fourth read level RL4. The fourth read level RL4 can be adjacent to the third read level RL3, and the third valley cell count value VCNT3 can be a value obtained by subtracting the third cumulative cell count value ccc3 from the fourth cumulative cell count value ccc4.

[0110] The threshold voltage corresponding to each valley cell count value VCNT can be a value between two read levels used to generate the valley cell count value VCNT or one of the two read levels used to generate the valley cell count value VCNT. In one embodiment, the threshold voltage corresponding to each valley cell count value VCNT can be the intermediate value of the two read levels used to generate the valley cell count value VCNT. For example, the threshold voltage corresponding to the first valley cell count value VCNT1 can be the first sampled read level SRL1, the threshold voltage corresponding to the second valley cell count value VCNT2 is the second sampled read level SRL2, and the threshold voltage corresponding to the third valley cell count value VCNT3 can be the third sampled read level SRL3.

[0111] The memory controller may use read points including a sum distribution SD and cumulative cell count values respectively corresponding to multiple read levels to derive a valley cell count value VCNT and a sampled read level SRL corresponding to the valley cell count value VCNT. The memory controller may model a memory cell count function fv based on the valley cell count value VCNT and the sampled read level SRL corresponding to the valley cell count value VCNT, and may generate a valley read level Vv based on the memory cell count function fv. As an example, a memory cell count function fv of a quadratic function may be generated using a first sampled read level SRL1 to a third sampled read level SRL3 as inputs and a first valley cell count value VCNT1 to a third valley cell count value VCNT3 as outputs. For example, the lowest point of the memory cell count function fv may be a valley V, and a threshold voltage corresponding to the valley V may be the valley read level Vv. However, the memory cell count function fv is not necessarily limited thereto, and the valley read level Vv may be generated by various methods.

[0112] Figure 10 is a diagram for explaining a method of generating a cumulative read level according to an embodiment. In Figure 10 it, the horizontal axis may represent a threshold voltage Vth of a memory cell, and the vertical axis may represent a cumulative cell count value ccc corresponding to the threshold voltage Vth. The description of the method of generating a cumulative read level in Figure 10 which has already been given is omitted.

[0113] A cumulative read level Vc may be generated based on multiple read levels RL and cumulative cell count values ccc corresponding to the multiple read levels RL. Specifically, a read level generator (e.g., Figure 1 the read level generator 113 in

[0114] the memory controller may obtain a first cumulative cell count value ccc1 to a fourth cumulative cell count value ccc4 respectively corresponding to a first read level RL1 to a fourth read level RL4. That is, the memory controller may obtain multiple read points rpt. Since the cumulative read level Vc is generated using the cumulative cell count value ccc obtained through a valley search operation, the cumulative read level Vc may be calculated and the cost may be reduced even without an additional configuration for obtaining the cumulative cell count value ccc.

[0115] The read point rpt may include a read level and a cumulative cell count value ccc corresponding to the read level. The memory controller may obtain a first read point rpt1, a second read point rpt2, a third read point rpt3, and a fourth read point rpt4. The first read point rpt1 may include a first read level RL1 and a first cumulative cell count value ccc1, the second read point rpt2 may include a second read level RL2 and a second cumulative cell count value ccc2, the third read point rpt3 may include a third read level RL3 and a third cumulative cell count value ccc3, and the fourth read point rpt4 may include a fourth read level RL4 and a fourth cumulative cell count value ccc4.

[0116] The memory controller may model a cumulative cell count function fc between threshold voltage distributions based on multiple read points rpt, and may generate a cumulative read level Vc between threshold voltage distributions based on the modeled cumulative cell count function fc. The memory controller may model a cumulative cell count function fc that uses multiple read levels RL as inputs and uses cumulative cell count values ccc corresponding to the multiple read levels RL as outputs. The cumulative cell count function fc may refer to a function representing an ordered cumulative value of the number of memory cells corresponding to a threshold voltage.

[0117] The memory controller may model the cumulative cell count function fc based on at least four read levels and cumulative cell count values ccc corresponding to each of the at least four read levels. In one embodiment, the memory controller may model the cumulative cell count function fc based on four read points rpt including four read levels RL and four cumulative cell count values ccc corresponding to each of the four read levels RL. The memory controller may model the cumulative cell count function fc of a cubic function based on the first read point rpt1 to the fourth read point rpt4.

[0118] In one embodiment, the memory controller may generate a cumulative read level Vc corresponding to an ideal cell count value iccc based on a cumulative cell count function fc. The memory controller may obtain an output ideal cell count value iccc from the cumulative cell count function fc as an input corresponding to the cumulative read level Vc. The ideal cell count value iccc may be a value obtained by evenly dividing the number of memory cells included in the memory device into a plurality of states in a threshold voltage distribution. As an example, the ideal cell count value iccc may mean the number of memory cells included in one state when the plurality of memory cells included in a page are evenly divided into a plurality of states. Thus, the cumulative read level is a given read level configured to cause an ideal cell count value to be observed based on a plurality of memory cells holding data corresponding to a plurality of states associated with the threshold voltage distribution. For example, in TLC, the ideal cell count value iccc may mean the number of memory cells included in one state when the plurality of memory cells included in a page are evenly divided into eight states. The cumulative cell count function fc represents the effect of memory cells holding random data stored in the memory cells according to eight states.

[0119] Figure 11 is a diagram for explaining a method of generating an optimal read level according to an embodiment. Descriptions of the method of generating an optimal read level that have already been given are omitted. Figure 11 in the method of generating an optimal read level.

[0120] Reference Figure 11 , the first curve graph ga' may represent a sum distribution SD of two adjacent threshold voltage distributions among the threshold voltage distributions. The horizontal axis of the first curve graph ga' may represent the threshold voltage Vth of the memory cells, and the vertical axis of the first curve graph ga' may represent the number of memory cells (cell count) corresponding to the threshold voltage Vth. The first curve graph ga' represents a first programming state p1, a second programming state p2, and a sum distribution SD obtained by adding the first programming state p1 and the second programming state p2.

[0121] In Figure 11 , for ease of explanation, a first programming state P1 and a second programming state P2 are shown, but this is merely an example. Descriptions the same as or similar to the first programming state P1 and the second programming state P2 may be applied to other states in the threshold voltage distribution. For example, the first curve graph ga' may be two adjacent states among a plurality of states representing values stored in the memory cells in the threshold voltage distribution. For example, in TLC, the first state may be an erased state (e.g., Figure 6 the erased state E in Figure 6 ), and the second state may be one of the first to seventh programming states adjacent to the first state (e.g.,Figure 6 One of P1 to P7 in []. However, this is only an example and can also be applied to other level units (e.g., SLC, MLC, QLC, etc.).

[0122] The second curve graph gb' can represent the cumulative cell count function fc of two adjacent threshold voltage distributions among the threshold voltage distributions. The horizontal axis of the second curve graph gb' can represent the threshold voltage Vth of the memory cell, and the vertical axis of the second curve graph gb' can represent the cumulative cell count value ccc corresponding to the threshold voltage Vth.

[0123] A memory controller (e.g., Figure 1 the memory controller 110 of []) can generate an optimal read level Voc based on the cumulative read level Vc and the valley read level Vv. Specifically, a read level generator (e.g., Figure 1 the read level generator 113 in []) can generate the optimal read level Voc. The optimal read level Voc can refer to the voltage level at which the least number of error bits occur when performing a read operation at the threshold voltage level. As an example, the optimal read level Voc can be the threshold voltage corresponding to the intersection point of the first programming state p1 and the second programming state p2.

[0124] The memory controller can generate an optimal read level Voc for each state in the threshold voltage distribution. For example, the memory controller can generate 7 optimal read levels for each state in TLC. The memory controller can generate the optimal read level Voc between the erase state E and the first programming state P1, the optimal read level Voc between the first programming state P1 and the second programming state P2, the optimal read level Voc between the second programming state P2 and the third programming state P3, the optimal read level Voc between the third programming state P3 and the fourth programming state P4, the optimal read level Voc between the fourth programming state P4 and the fifth programming state P5, the optimal read level Voc between the fifth programming state P5 and the sixth programming state P6, and the optimal read level Voc between the sixth programming state P6 and the seventh programming state P7.

[0125] Refer to Figure 11 , the optimal read level Voc can be the threshold voltage value between the cumulative read level Vc and the valley read level Vv. When the threshold voltage distributions of the first programming state p1 and the second programming state p2 are asymmetric, the optimal read level Voc can be a voltage value closer to the valley read level Vv or the cumulative read level Vc. Therefore, the optimal read level Voc can be derived by applying different weights to each of the valley read level Vv and the cumulative read level Vc.

[0126] The memory controller may generate an optimal read level Voc by applying a valley weight to a valley read level Vv and applying an accumulation weight to an accumulation read level Vc. The accumulation weight and the valley weight may be positive numbers. When the threshold voltage distributions of a first programming state p1 and a second programming state p2 are asymmetric, the optimal read level Voc may be a voltage value closer to the accumulation read level Vc than the valley read level Vv. In one embodiment, the accumulation weight may be greater than the valley weight.

[0127] The memory controller may generate the optimal read level Voc based on Equation 1 below.

[0128] [Equation 1] Voc = Wv * Vv + Wc * Vc “*” indicates multiplication, Voc may be the optimal read level, Wv may be the valley weight, Vv may be the valley read level, Wc may be the accumulation weight, and Vc may be the accumulation read level. The accumulation weight Wc may be greater than the valley weight Wv. The optimal read level Voc may be generated as a value closer to the accumulation read level Vc than the valley read level Vv.

[0129] In an embodiment, when the threshold voltage distribution of the first programming state p1 is symmetric with the threshold voltage distribution of the second programming state p2, the valley read level Vv may be equal to the accumulation read level Vc, and the optimal read level Voc may be equal to the valley read level Vv.

[0130] By applying the valley weight Wv and the accumulation weight Wc greater than the valley weight Wv to the valley read level Vv and the accumulation read level Vc, respectively, the optimal read level Voc can be calculated to reduce errors in the read data even if two adjacent states are asymmetric in the threshold voltage distribution. Therefore, the optimal read level Voc for reducing errors during the read operation can be calculated more accurately.

[0131] Figure 12 is a diagram for explaining the accumulation weight and the valley weight according to an embodiment. In Figure 12 , the horizontal axis may represent the threshold voltage Vth of the memory cell. Figure 12 illustrates the case where the accumulation weight is twice the valley weight. Descriptions already given in Figure 11 are omitted.

[0132] Referring to Figure 12 , the optimal read level Voc may be a threshold voltage value between the accumulation read level Vc and the valley read level Vv. When a first state (e.g., Figure 11 the first programming state p1 in Figure 2When the threshold voltage distribution of the second programming state p2) in [ ] is asymmetric, the optimal read level Voc can be a voltage value closer to the cumulative read level Vc than the valley read level Vv. The difference between the cumulative read level Vc and the optimal read level Voc can be a first difference vd1. The difference between the valley read level Vv and the optimal read level Voc can be a second difference vd2. For example, the second difference vd2 can be twice the first difference vd1. The optimal read level Voc can correspond to a 1:2 division between the cumulative read level Vc and the valley read level Vv.

[0133] The memory controller can generate the optimal read level Voc by applying a valley weight to the valley read level Vv and applying a cumulative weight to the cumulative read level Vc. In one embodiment, the cumulative weight can be twice the valley weight. The memory controller can generate the optimal read level Voc based on Equation 2 below.

[0134] [Equation 2] Voc = × Vv + × Vc Here, Voc can be the optimal read level, Vv can be the valley read level, and Vc can be the cumulative read level. The cumulative weight can be 2 / 3, the valley weight can be 1 / 3, and the cumulative weight can be twice the valley weight. The optimal read level Voc can be generated as a value closer to the cumulative read level Vc than the valley read level Vv.

[0135] Figure 13 is a diagram showing a method of generating an optimal read voltage corresponding to multiple states on a threshold voltage distribution according to an embodiment. The description already given in [ ] is omitted. Figure 11 in [ ]

[0136] Referring to Figure 13 , Figure 13 the horizontal axis of [ ] can represent the threshold voltage Vth of the memory cell, and the vertical axis can represent the number of memory cells corresponding to the threshold voltage Vth (number of cells). The first sum distribution SD1 represents the sum distribution of the first state and the second state. The first state and the second state can be adjacent to each other. The second sum distribution SD2 represents the sum distribution of the third state and the fourth state. The third state and the fourth state can be adjacent to each other. The first to fourth states can represent some of the multiple states in the threshold voltage distribution. The third state is not adjacent to the first state and can have a higher threshold voltage level than the first state.

[0137] As an example, when the memory cell is TLC, the first state and the second state respectively correspond to the first programming state P1 and the second programming state P2, and the third state and the fourth state can respectively correspond to the third programming state P3 and the fourth programming state P4. However, the multiple states on the threshold voltage distribution are not necessarily limited to this, and the first state to the fourth state can correspond to other states (for example, Figure 6 the states E and P1 to P7 therein). Additionally, it can also correspond to the states at other memory cell levels. In Figure 13 for the sake of convenience of explanation, the first programming state p1 to the fourth programming state p4 are shown, but of course, Figure 13 the description can be applied to other states of the memory cell in the same or similar manner. Below, for the sake of convenience of explanation, the first programming state p1 to the fourth programming state p4 are described.

[0138] The memory controller (for example, Figure 1 the memory controller 110 therein) can generate a first optimal read level Voc1. The first optimal read level Voc1 can be the optimal read level corresponding to the first programming state p1. The optimal read level corresponding to the first programming state p1 can mean the optimal read level between the first programming state p1 and the second programming state p2. As an example, the optimal read level corresponding to the first programming state p1 can mean the optimal read level of the first sum distribution SD1 corresponding to the first programming state p1 and the second programming state p2. The memory controller can generate the first optimal read level Voc1 based on the first cumulative read level Vc1 and the first valley read level Vv1. The first valley read level Vv1 can be the valley read level corresponding to the first valley V1 in the first sum distribution SD1. The first cumulative read level Vc1 can be the cumulative read level derived based on the cumulative cell count function between the first programming state p1 and the second programming state p2.

[0139] The memory controller can generate a second optimal read level Voc2. The second optimal read level Voc2 can be the optimal read level corresponding to the third programming state p3. The memory controller can generate the second optimal read level Voc2 based on the second cumulative read level Vc2 and the second valley read level Vv2. The second valley read level Vv2 can be the valley read level corresponding to the second valley V2 in the second sum distribution SD2. The second cumulative read level Vc2 can be the cumulative read level obtained based on the cumulative cell count function between the third programming state p3 and the fourth programming state p4.

[0140] The memory controller can generate an optimal read level by applying a valley weight Wv and an accumulation weight Wc. The accumulation weight Wc can be greater than the valley weight Wv. In one embodiment, the memory controller can generate a first optimal read level Voc1 and a second optimal read level Voc2 by applying the same valley weight Wv and accumulation weight Wc. The memory controller can generate the first optimal read level Voc1 by applying the valley weight Wv to a first valley read level Vv1 and applying the accumulation weight Wc to a first accumulation read level Vc1. The memory controller can generate the second optimal read level Voc2 by applying the valley weight Wv to a second valley read level Vv2 and applying the accumulation weight Wc to a second accumulation read level Vc2. As an example, when the memory cell is TLC, the optimal read level for each state in the threshold voltage distribution can be generated by applying the same valley weight Wv and accumulation weight Wc.

[0141] Figure 14A is a diagram showing error bits of the threshold voltage distribution of a memory cell according to an embodiment. The threshold voltage distribution of the memory cell can be classified depending on a plurality of states as shown in Figure 6 and a state corresponding to a relatively high threshold voltage can have a high error bit. Hereinafter, referring together to Figure 14A and Figure 6 , and the description already given in Figure 6 can be omitted.

[0142] The horizontal axis of the first error curve graph EG1 can indicate the read level, and the vertical axis can indicate the error bit. For ease of explanation, in Figure 14A , it is assumed that the memory cell is TLC, and the threshold voltage of the memory cell can be programmed to one of eight states E and RP1 to RP7. For example, the first error curve graph EG1 can represent the third programming state P3.

[0143] The first error curve graph EG1 is a graph showing the error bits generated when a read voltage corresponding to the third programming state P3 is applied to read the third programming state P3 when the memory cell deteriorates. When the memory cell deteriorates, the optimal read level for reading the third programming state P3 can be the second voltage Vt2, and the valley read level found by the valley search operation can be the first voltage Vt1. That is, the optimal read level may not match the valley read level. In this case, the optimal read level can be calculated as the second voltage Vt2 or a value close to the second voltage Vt2 based on the first voltage Vt1.

[0144] Figure 14B is a diagram showing error bits of the threshold voltage distribution of a memory cell according to an embodiment. The description in Figure 14Athe description already given above. In the following, reference is made together to Figure 14A 、 Figure 14B and Figure 6 。

[0145] The horizontal axis of the second error curve graph EG2 may indicate a read level, and the vertical axis of the second error curve graph EG2 may indicate error bits. For example, the second error curve graph EG2 may represent a sixth programming state P6.

[0146] The second error curve graph EG2 is a curve graph showing error bits generated when a read voltage corresponding to the sixth programming state P6 is applied to read the sixth programming state P6 when the memory cell deteriorates. When the memory cell deteriorates, the optimal read level for reading the sixth programming state P6 may be a fourth voltage Vt4, and the valley read level found through a valley search operation may be a third voltage Vt3. That is, the optimal read level may not match the valley read level. In this case, the optimal read level may be calculated as the fourth voltage Vt4 or a value close to the fourth voltage Vt4 based on the third voltage Vt3.

[0147] When the memory cell deteriorates, the difference between the valley read level and the optimal read level corresponding to the third programming state P3 may be different from the difference between the valley read level and the optimal read level corresponding to the sixth programming state P6. The difference between the valley read level and the optimal read level corresponding to the sixth programming state P6 may be greater than the difference between the valley read level and the optimal read level corresponding to the third programming state P3. As an example, the difference between the third voltage Vt3 and the fourth voltage Vt4 may be greater than the difference between the first voltage Vt1 and the second voltage Vt2. That is, in a state of the threshold voltage distribution corresponding to a relatively high threshold voltage, the error between the valley read level and the optimal read level may be relatively large.

[0148] When generating the optimal read level, a cumulative weight and a valley weight corresponding to each state in the threshold voltage distribution may be applied. Depending on the state of the threshold voltage distribution, the cumulative weight and the valley weight may be different. In the following, reference is made to Figure 15 for a method of differently applying the valley weight and the cumulative weight according to the state in the threshold voltage distribution.

[0149] Figure 15 is a diagram showing a method of generating an optimal read voltage corresponding to multiple states on a threshold voltage distribution according to an embodiment. Compared with Figure 13 , in Figure 15 , when generating an optimal read voltage corresponding to the state of the threshold voltage distribution, different cumulative weights may be applied according to the state of the threshold voltage distribution. The description already given in Figure 13 is omitted.

[0150] A memory controller (e.g., Figure 1 the memory controller 110) may generate a first optimal read level Voc1. The first optimal read level Voc1 may be the optimal read level corresponding to the first programming state p1. The memory controller may generate the first optimal read level Voc1 based on a first cumulative read level Vc1 and a first valley read level Vv1. The first valley read level Vv1 may be the valley read level corresponding to the first valley V1 in the first sum distribution SD1. The first cumulative read level Vc1 may be a cumulative read level derived based on a cumulative cell count function between the first programming state p1 and the second programming state p2.

[0151] The memory controller may generate the first optimal read level Voc1 by applying a first valley weight Wv1 and a first cumulative weight Wc1. The memory controller may generate the first optimal read level Voc1 by applying the first valley weight Wv1 to the first valley read level Vv1 and applying the first cumulative weight Wc1 to the first cumulative read level Vc1. The first cumulative weight Wc1 may be greater than the first valley weight Wv1.

[0152] The memory controller may generate a second optimal read level Voc2. The second optimal read level Voc2 may be the optimal read level corresponding to the third programming state p3. The memory controller may generate the second optimal read level Voc2 based on a second cumulative read level Vc2 and a second valley read level Vv2. The second valley read level Vv2 may be the valley read level corresponding to the second valley V2 in the second sum distribution SD2. The second cumulative read level Vc2 may be a cumulative read level derived based on a cumulative cell count function between the third programming state p3 and the fourth programming state p4.

[0153] The memory controller may generate the second optimal read level Voc2 by applying a second valley weight Wv2 and a second cumulative weight Wc2. The memory controller may generate the second optimal read level Voc2 by applying the second valley weight Wv2 to the second valley read level Vv2 and applying the second cumulative weight Wc2 to the second cumulative read level Vc2. The second cumulative weight Wc2 may be greater than the second valley weight Wv2. The second valley weight Wv2 may be different from the first valley weight Wv1, and the second cumulative weight Wc2 may be different from the first cumulative weight Wc1. In one embodiment, the first cumulative weight Wc1 may be less than the second cumulative weight Wc2.

[0154] As an example, the optimal read level for each state in the threshold voltage distribution may be generated by applying different valley weights Wv and cumulative weights Wc. For example, when the memory cells are TLC, for an erased state (e.g.,Figure 6 E) in and the first programming state P1 to the sixth programming state (e.g., Figure 6 P6) in each of the valley weights Wv and the cumulative weights Wc used to generate the optimal read level can be different from each other. However, the valley weight Wv and the cumulative weight Wc are not limited thereto, and the valley weight Wv and the cumulative weight Wc used to generate the optimal read level Voc for some states in the threshold voltage distribution can be the same. For example, the valley weight Wv and the cumulative weight Wc used to generate the optimal read level for each of the first programming state P1 and the second programming state P2 can be the same. When generating the optimal read level for the fifth programming state (e.g., Figure 6 P5) and the sixth programming state P6 in each of the valley weights Wv and the cumulative weights Wc used to generate the optimal read level can be the same. The valley weight Wv and the cumulative weight Wc used when generating the optimal read level of the first programming state P1 can be different from the valley weight Wv and the cumulative weight Wc used when generating the optimal read level of the sixth programming state P6.

[0155] The memory controller can generate an optimal read level by applying the cumulative weight and the valley weight corresponding to each state in the threshold voltage distribution, so that in the state corresponding to the threshold voltage, an optimal read level reflecting the error between the valley read level and the optimal read level can be generated. Therefore, an optimal read level capable of reducing errors can be generated.

[0156] Figure 16 is a flowchart for explaining a method of operating a memory controller according to an embodiment. Specifically, Figure 16 illustrates Figure 1 the operation method of the memory controller 110. The description of the method of operating the memory controller that has been given is omitted. Figure 16 in

[0157] In operation S1610, the memory controller can obtain a plurality of read points by performing a valley search operation. The valley search operation can be an operation of searching for valleys between the threshold voltage distributions of memory cells included in the memory device. The valley search operation can be an operation of searching for valleys formed at the intersection points of the threshold voltage distributions of the first state and the second state adjacent to the first state among the plurality of states representing the values stored in the memory cells in the threshold voltage distribution. The plurality of read points can include a plurality of read levels and cumulative cell count values respectively corresponding to the plurality of read levels.

[0158] The cumulative cell count value can be a value that cumulatively counts, in sequence, the number of memory cells corresponding to each of a plurality of read levels. The cumulative cell count value can be obtained by performing a counting operation (e.g., on-cell or off-cell counting) on read data read using the plurality of read levels via a valley search operation. As an example, the memory controller can obtain a plurality of read points from the memory device. However, the memory controller is not necessarily limited thereto, and the memory controller can obtain the plurality of read points via a valley search operation.

[0159] In operation S1620, the memory controller can generate a valley read level corresponding to a valley based on the plurality of read points. The memory controller can generate the valley read level via a valley search operation. The plurality of read levels can be set via a valley search operation, and the cumulative cell count value corresponding to the plurality of read levels can be obtained. As an example, the plurality of read levels can be preset, and the plurality of read levels can be spaced apart from each other by a specific distance. For example, the memory controller can use at least four read points to generate a valley read level corresponding to one state in the threshold voltage distribution.

[0160] The memory controller can generate a valley read level based on the cumulative cell count value. The memory controller can model a memory cell counting function based on the cumulative cell count value and generate a valley read level based on the memory cell counting function. As an example, the memory controller can generate a quadratic function as the memory cell counting function. For example, the lowest point of the memory cell counting function can be the valley, and the threshold voltage corresponding to the valley can be the valley read level. However, the valley read level is not necessarily limited thereto, and the valley read level can be generated by various methods.

[0161] In operation S1630, the memory controller can model a cumulative cell counting function between threshold voltage distributions based on the plurality of read points and can generate a cumulative read level based on the modeled cumulative cell counting function. The memory controller can model a cumulative cell counting function between threshold voltage distributions based on the plurality of read levels and the cumulative cell count values respectively corresponding to the plurality of read levels.

[0162] The memory controller can model a cumulative cell counting function that uses the plurality of read levels as inputs and outputs the cumulative cell count values corresponding to the plurality of read levels. The cumulative cell counting function can refer to a function representing the sequential cumulative value of the number of memory cells corresponding to the threshold voltage.

[0163] The memory controller may model the cumulative cell count function based on at least four read levels and cumulative cell count values corresponding to each of the at least four read levels. In one embodiment, the memory controller may model the cumulative cell count function based on four read points including four read levels and four cumulative cell count values corresponding to each of the four read levels. As an example, the memory controller may model the cumulative cell count function as a cubic function based on the four read points.

[0164] The memory controller may generate a cumulative read level based on the modeled cumulative cell count function. In one embodiment, the memory controller may generate a cumulative read level corresponding to an ideal cell count value based on the cumulative cell count function. The memory controller may obtain an output ideal cell count value as an input of the cumulative read level from the cumulative cell count function. The ideal cell count value may be a value obtained by evenly dividing the number of memory cells included in the memory device into multiple states in a threshold voltage distribution.

[0165] In operation S1640, the memory controller may generate an optimal read level based on a valley read level and the cumulative read level. The memory controller may generate the optimal read level by applying a valley weight to the valley read level and applying a cumulative weight to the cumulative read level. In one embodiment, the valley weight and the cumulative weight may be positive numbers, and the cumulative weight may be greater than the valley weight.

[0166] As an example, the memory controller can generate an optimal read level for each state in the threshold voltage distribution by applying the same valley weight and cumulative weight. The memory controller can generate a first optimal read level. The first optimal read level can be the optimal read level corresponding to the first state. The memory controller can generate the first optimal read level based on the first cumulative read level and the first valley read level. The memory controller can generate a second optimal read level. The second optimal read level can be the optimal read level corresponding to the second state. The memory controller can generate the second optimal read level based on the second cumulative read level and the second valley read level. The memory controller can generate the first optimal read level and the second optimal read level by applying the same valley weight and cumulative weight. The memory controller can generate the first optimal read level by applying the valley weight to the first valley read level and applying the cumulative weight to the first cumulative read level. The memory controller can generate the second optimal read level by applying the same valley weight as that applied when generating the first optimal read level to the second valley read level and applying the same cumulative weight as that applied when generating the first optimal read level to the second cumulative read level Vc2. As an example, when the memory cell is TLC, the optimal read level for each state in the threshold voltage distribution can be generated by applying the same valley weight and cumulative weight.

[0167] As an example, the memory controller can generate an optimal read level by applying a cumulative weight and a valley weight corresponding to each state in the threshold voltage distribution. The memory controller can generate an optimal read level by applying different cumulative weights and valley weights according to the states in the threshold voltage distribution.

[0168] The memory controller can generate the first optimal read level based on the first cumulative read level and the first valley read level. The memory controller can generate the first optimal read level by applying the first valley weight to the first valley read level and applying the first cumulative weight to the first cumulative read level. The first cumulative weight can be greater than the first valley weight. The memory controller can generate the second optimal read level by applying the second valley weight to the second valley read level and applying the second cumulative weight to the second cumulative read level. The second cumulative weight can be greater than the second valley weight. The second valley weight can be different from the first valley weight, and the second cumulative weight can be different from the first cumulative weight. In one embodiment, the first cumulative weight can be less than the second cumulative weight.

[0169] In an embodiment, Figure 16The method of operating a memory controller as shown may further include performing an error correction operation on data read from a memory device before operation S1610. When the error correction operation on the read data fails, operations S1610 to S1640 may be performed.

[0170] Figure 17 FIG. shows a system to which a storage device according to an embodiment is applied. Figure 17 The storage devices 1300a and 1300b may be the memory systems described in the embodiments (e.g., Figure 1 the memory system 100). Figure 17 The system 1000 may be substantially a mobile system, such as a mobile phone, a smart phone, a tablet personal computer (PC), a wearable device, a health care device, or an Internet of Things (IoT) device. However, Figure 17 the system 1000 is not limited to a mobile system and may be a personal computer, a laptop computer, a server, a media player, or an in-vehicle device such as a navigation device.

[0171] Referring Figure 17 , the system 1000 may include a main processor 1100, memories 1200a and 1200b, and storage devices 1300a and 1300b, and may further include one or more of an image capture device 1410, a user input device 1420, a sensor 1430, a communication device 1440, a display 1450, a speaker 1460, a power supply device 1470, and a connection interface 1480.

[0172] The main processor 1100 may control the overall operation of the system 1000, and more specifically, control the operations of other components forming the system 1000. The main processor 1100 may be implemented as a general-purpose processor, a dedicated processor, or an application processor.

[0173] The main processor 1100 may include one or more CPU cores 1110, and may further include a controller 1120 for controlling the memories 1200a and 1200b and / or the storage devices 1300a and 1300b. According to an embodiment, the main processor 1100 may further include an accelerator 1130, which is a dedicated circuit for high-speed data operations such as artificial intelligence (AI) data operations. Such an accelerator 1130 may include a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU), and may be implemented as a separate chip physically independent of other components of the main processor 1100.

[0174] Memories 1200a and 1200b can be used as main memory devices of system 1000, and may include volatile memories such as SRAM and / or DRAM, but may also include non-volatile memories such as flash memory, PRAM, and / or RRAM. Memories 1200a and 1200b may also be implemented in the same package as main processor 1100.

[0175] Storage devices 1300a and 1300b can be used as non-volatile storage devices that store data whether powered or not, and may have a relatively large storage capacity compared to memories 1200a and 1200b. Storage devices 1300a and 1300b may include memory controllers 1310a and 1310b and non-volatile memories (NVM) 1320a and 1320b that store data under the control of memory controllers 1310a and 1310b. Non-volatile memory devices 1320a and 1320b may include flash memories having a two-dimensional (2D) structure or a three-dimensional (3D) vertical NAND (V-NAND) structure, but may also include other types of non-volatile memories such as PRAM and / or RRAM. Figures 1 to 16 The memory system (e.g., Figure 1 the memory system 100) described in Figure 17 can be applied to

[0176] Storage devices 1300a and 1300b may be included in system 1000 in a state physically separated from main processor 1100, or may be implemented in the same package as main processor 1100. Additionally, storage devices 1300a and 1300b may have a form such as a solid-state device (SSD) or a memory card, and may be detachably coupled to other components of the system through an interface such as connection interface 1480 described below. Such storage devices 1300a and 1300b may be devices that apply standard protocols such as UFS, eMMC, or Non-Volatile Memory Express (NVMe), but are not necessarily limited thereto.

[0177] Image capture device 1410 may capture still images or moving images, and may be a camera, a camcorder, and / or a network camera. User input device 1420 may receive various types of data inputs from a user of system 1000, and may be a touchpad, a keypad, a keyboard, a mouse, and / or a microphone, etc. Sensor 1430 may detect various types of physical quantities that can be obtained from the outside of system 1000 and convert the sensed physical quantities into electrical signals. Such a sensor 1430 may be a temperature sensor, a pressure sensor, an illumination sensor, a position sensor, an acceleration sensor, a biosensor, and / or a gyro sensor.

[0178] The communication device 1440 can transmit and receive signals with other devices external to the system 1000 according to various communication protocols. Such a communication device 1440 can be implemented to include an antenna, a transceiver, and / or a modem. The display 1450 and the speaker 1460 can be used as output devices for outputting visual information and auditory information to the user of the system 1000, respectively. The power supply device 1470 can appropriately convert the power supplied from the battery built into the system 1000 and / or an external power supply, and supply the converted power to each component of the system 1000.

[0179] The connection interface 1480 can provide a connection between the system 1000 and an external device connected to the system 1000, and can exchange data with the system 1000. The connection interface 1480 can be implemented in various interface methods such as ATA, SATA, e-SATA, SCSI, SAS, PCI, PCIe, NVMe, IEEE1394, USB, SD card, multimedia card (MMC), eMMC, UFS, embedded universal flash storage (eUFS), and (CF) card interfaces.

[0180] Although example embodiments have been specifically shown and described, it should be understood that various changes in form and detail can be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A memory controller configured to control a memory device including a plurality of memory cells, the memory controller comprising: A valley search manager configured to perform a valley search operation to search for a valley between threshold voltage distributions associated with the plurality of memory cells and obtain a valley read level corresponding to the valley; And A read level generator configured to: model a cumulative cell count function between the threshold voltage distributions based on a plurality of read levels; Generate a cumulative read level between the threshold voltage distributions based on the cumulative cell count function; And generate an optimal read level based on the valley read level and the cumulative read level.

2. The memory controller according to claim 1, wherein, The read level generator is further configured to generate the optimal read level by applying a valley weight to the valley read level and a cumulative weight to the cumulative read level, and wherein the cumulative weight is greater than the valley weight, and the valley weight and the cumulative weight are positive numbers.

3. The memory controller according to claim 2, wherein, The cumulative weight is twice the valley weight.

4. The memory controller according to claim 2, wherein, The read level generator is further configured to: Generate a first optimal read level corresponding to a first state among a plurality of states representing values stored in the plurality of memory cells in the threshold voltage distribution; Generate a second optimal read level corresponding to a second state having a threshold voltage level higher than that of the first state; And Generate the first optimal read level corresponding to the first state and the second optimal read level corresponding to the second state by applying the valley weight and the cumulative weight to the valley read level and the cumulative read level, respectively.

5. The memory controller according to claim 2, wherein, The read level generator is further configured to: Generate a first optimal read level corresponding to a first state among a plurality of states representing values stored in the plurality of memory cells; Generate a second optimal read level corresponding to a second state having a higher threshold voltage level than the first state; Apply a first valley weight and a first cumulative weight to the valley read level and the cumulative read level, respectively, to generate the first optimal read level corresponding to the first state; And Generate the second optimal read level corresponding to the second state by applying a second valley weight and a second cumulative weight to the valley read level and the cumulative read level, respectively, and wherein the second valley weight is different from the first valley weight, and the second cumulative weight is different from the first cumulative weight.

6. The memory controller according to claim 5, wherein, The first cumulative weight applied to the first optimal read level is less than the second cumulative weight applied to the second optimal read level.

7. The memory controller according to claim 1, wherein, The read level generator is further configured to generate the cumulative read level corresponding to an ideal cell count value based on the cumulative cell count function, The ideal cell count value is obtained by equally dividing the number of the plurality of memory cells included in the memory device into a plurality of states representing values stored in the plurality of memory cells, and wherein the cumulative read level is configured to cause the ideal cell count value to be observed based on the value stored in the plurality of memory cells.

8. The memory controller according to claim 1, wherein, The read level generator is further configured to model the cumulative cell count function as a cubic function based on at least four read levels and at least four cumulative cell count values respectively corresponding to the at least four read levels.

9. The memory controller according to claim 1, wherein, Based on the first threshold voltage distribution and the second threshold voltage distribution respectively corresponding to two adjacent states being symmetric to each other, the optimal read level is equal to the valley read level, and wherein the two adjacent states are included among the plurality of states respectively representing values stored in the plurality of memory cells.

10. The memory controller according to claim 1, wherein, The valley search manager is further configured to: obtain cumulative cell count values respectively corresponding to the plurality of read levels through the valley search operation; and generate the valley read level based on the cumulative cell count values.

11. The memory controller according to claim 1, wherein The valley search manager is further configured to generate the valley read level based on the valley cell count value, and wherein the valley cell count value is the difference between a first cumulative cell count value corresponding to a first read level among the plurality of read levels and a second cumulative cell count value corresponding to a second read level adjacent to the first read level.

12. A method of operating a memory controller, the method comprising: performing a valley search operation that searches for a valley between threshold voltage distributions associated with a plurality of memory cells to obtain a plurality of read points including a plurality of read levels and cumulative cell count values respectively corresponding to the plurality of read levels; generating a valley read level corresponding to the valley based on the plurality of read points; modeling a cumulative cell count function between the threshold voltage distributions based on the plurality of read points, and generating a cumulative read level between the threshold voltage distributions based on the cumulative cell count function; and generating an optimal read level by applying a valley weight to the valley read level and applying a cumulative weight to the cumulative read level.

13. The method according to claim 12, wherein, The valley weight and the cumulative weight are positive numbers, and the cumulative weight is greater than the valley weight.

14. The method according to claim 12, wherein, Generating the optimal read level includes: applying a first valley weight and a first cumulative weight to the valley read level and the cumulative read level respectively to generate a first optimal read level corresponding to a first state among the plurality of states representing values stored in the plurality of memory cells in the threshold voltage distribution; and applying a second valley weight different from the first valley weight and a second cumulative weight different from the first cumulative weight to the valley read level and the cumulative read level respectively to generate a second optimal read level corresponding to a second state having a threshold voltage level higher than that of the first state.

15. The method according to claim 12, wherein, Generating the optimal read level includes: Apply a first valley weight and a first cumulative weight to generate a first optimal read level corresponding to a first state among multiple states representing values stored in the multiple memory cells; and Generate a second optimal read level corresponding to a second state having a threshold voltage level higher than that of the first state by applying a second valley weight and a second cumulative weight to the valley read level and the cumulative read level, respectively, and wherein the first valley weight is the same as the second valley weight, and the first cumulative weight is the same as the second cumulative weight.

16. The method according to claim 12, wherein Generating the cumulative read level further includes: Modeling the cumulative cell count function as a cubic function based on the multiple read points; and Generating the cumulative read level corresponding to an ideal cell count value based on the cumulative cell count function.

17. The method according to claim 12, wherein The multiple read points include four read points corresponding to four read levels and four cumulative cell count values corresponding to each of the four read levels, and wherein modeling the cumulative cell count function includes using the four read points to model the cumulative cell count function.

18. The method according to claim 12, the method further includes performing an error correction operation on given data read from a memory device, and based on the failure of the error correction operation on the given data, performing the generation of the optimal read level.

19. A memory system, the memory system includes: A memory device; And A memory controller, wherein the memory device is configured to generate cumulative cell count values corresponding to multiple read levels respectively during a valley search operation for searching for a valley between threshold voltage distributions associated with multiple memory cells, and wherein the memory controller is configured to: receive the cumulative cell count values and generate a valley read level corresponding to the valley based on the cumulative cell count values; model a cumulative cell count function that takes the multiple read levels as inputs and outputs the cumulative cell count values corresponding to the multiple read levels respectively; generate a cumulative read level based on the cumulative cell count function; and generate an optimal read level based on the valley read level and the cumulative read level.

20. The memory system according to claim 19, wherein, The memory controller is further configured to generate the optimal read level based on Equation 1 below, [Equation 1] Voc = Wv × Vv + Wc × Vc, wherein Voc is the optimal read level, Wv is the valley weight, Vv is the valley read level, Wc is the cumulative weight, Vc is the cumulative read level, and Wv and Wc are positive numbers, and wherein the valley weight Wv is less than the cumulative weight Wc.

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