Memory device and repair method thereof

Abstract

A memory device and a repair method thereof are provided. A memory device includes a first memory bank including a first memory cell connected to a first word line, a second memory bank including a second memory cell connected to a second word line corresponding to the first word line, and a repair circuit, the repair circuit is configured to repair the first word line and the second word line together or to separately repair the first word line or the second word line based on a location of a failed memory cell included in the first memory cell and the second memory cell.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority of Korean Patent Application No. 10 - 2024 - 0003581, filed with the Korean Intellectual Property Office on January 9, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] Example embodiments of the present disclosure described herein relate to a semiconductor memory device, and more particularly, to a memory device including repaired memory cells and a method for repairing the same. Background art

[0004] Semiconductor memories can be mainly classified into volatile memories or non - volatile memories. Volatile memories (e.g., DRAM or SRAM) have fast read and write speeds, but when the power is turned off, the data stored in the volatile memory disappears. In contrast, non - volatile memories can retain data even when the power is turned off. Therefore, non - volatile memories can be used to store content that must be preserved regardless of whether power is supplied.

[0005] A representative example of a volatile memory device is DRAM. The memory cells of a volatile memory device can include a single N - type transistor serving as a switch and a single capacitor for storing charge (data). Binary information “1” or “0” can correspond to the presence or absence of charge in the capacitor of the memory cell, e.g., whether the terminal voltage of the cell capacitor is high or low. The memory cells can be connected to word lines and bit lines. The bit lines can be connected to sense amplifiers. The sense amplifiers can sense the data stored in the memory cells through the bit lines based on the voltage applied to the word lines.

[0006] Volatile memory devices can include memory cells that fail (i.e., are defective) during the manufacturing process. The failed memory cells can reduce the reliability of the volatile memory device. To ensure the reliability of the volatile memory device, the volatile memory device can include additional redundant memory cells to replace the failed memory cells. However, a method is needed to effectively repair the failed memory cells with a limited number of redundant memory cells. Summary of the invention

[0007] Example embodiments of the present disclosure provide a memory device that changes a repair mode of a memory bank based on the distribution of failed memory cells.

[0008] According to an embodiment, a memory device includes: a first bank including first memory cells connected to a first word line; a second bank including second memory cells connected to a second word line corresponding to the first word line; and a repair circuit configured to repair the first word line and the second word line together or to repair the first word line or the second word line separately based on the positioning of defective memory cells included in the first memory cells and the second memory cells.

[0009] According to an embodiment, a memory device includes: a first bank including a first word line group; a second bank including a second word line group corresponding to the first word line group; a row decoder configured to select word lines of the first bank and the second bank based on an address received from an external device; and a repair circuit configured to provide a spare word line driving signal to the row decoder such that when the first word line group or the second word line group is selected based on the address, bank repair mode information corresponding to the first word line group or the second word line group is checked, and the first word line group and the second word line group are repaired together or the first word line group or the second word line group is repaired separately based on the bank repair mode information.

[0010] According to an embodiment, a method for repairing a memory device includes: comparing an address received from an external device with bank repair mode information to determine a repair mode for each bank included in the memory device; determining a repair mode of a first bank corresponding to the address based on a comparison result; when the repair mode is determined to be a first repair mode, repairing defective word lines included in the first bank and word lines corresponding to the defective word lines in a second bank together in a first repair operation; and when the repair mode is determined to be a second repair mode, repairing defective word lines included in the first bank and defective word lines included in the second bank separately in a second repair operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other objects and features of the present disclosure will become apparent by describing embodiments of the present disclosure in detail with reference to the accompanying drawings.

[0012] Figure 1 is a block diagram showing a memory system according to an exemplary embodiment.

[0013] Figure 2 is showing Figure 1 of a memory device.

[0014] Figure 3 is showing according to Figure 2 of a first repair mode of a memory device.

[0015] Figure 4 is showing according to Figure 2Diagram of the repair operation of the second repair mode of the memory device.

[0016] Figure 5 Shows Figure 2 Diagram of an example of the repair circuit.

[0017] Figure 6 Shows Figure 5 Diagram of an example of the repair control circuit.

[0018] Figure 7 Shows the repair fuse selection signal for selecting Figure 6 the repair fuse.

[0019] Figure 8 Shows Figure 6 Diagram of an example of the first repair word line selection circuit.

[0020] Figure 9 Shows Figure 6 Diagram of an example of the second repair word line selection circuit.

[0021] Figure 10 Shows Figure 6 Diagram of the operation of the latch and switch in the first repair mode.

[0022] Figure 11 Shows Figure 8 Diagram of the operation of the logic circuit in the first repair mode.

[0023] Figure 12 Shows Figure 9 Diagram of the operation of the logic circuit in the first repair mode.

[0024] Figure 13 Shows Figure 6 Diagram of the operation of the latch and switch in the second repair mode.

[0025] Figure 14 Shows Figure 8 Diagram of the operation of the logic circuit in the second repair mode.

[0026] Figure 15 Shows Figure 9 Diagram of the operation of the logic circuit in the second repair mode.

[0027] Figure 16 Shows the flowchart of the repair method for Figure 2 the memory device.

[0028] Figure 17 Shows the repair method for the bank included in the Figure 2 memory cell array. Detailed Description

[0029] Hereinafter, example embodiments of the present disclosure will be described in detail and clearly to such an extent that a person of ordinary skill in the art can easily implement the inventive concept.

[0030] Hereinafter, DRAM will be used as an example for illustrating the features and functions of the present disclosure. However, a person of ordinary skill in the art can easily understand other features and performances from the information disclosed herein. The present disclosure can be implemented by other embodiments or applied to other embodiments. In addition, without departing from the scope, spirit, and other purposes of the present disclosure, the detailed description can be modified or changed according to viewpoints and applications.

[0031] Figure 1 is a block diagram illustrating a memory system according to an example embodiment. Refer to Figure 1 , the memory system 1000 may include a memory controller 1100 and a memory device 1200.

[0032] According to an example embodiment, the memory controller 1100 may perform an access operation of writing data to the memory device 1200 or reading data stored in the memory device 1200. For example, the memory controller 1100 may generate a command CMD and an address ADDR for writing data to the memory device 1200 or reading data stored in the memory device 1200. The memory controller 1100 may include a control circuit for controlling the memory device 1200, at least one of a system-on-chip (SoC) such as an application processor (AP), a central processing unit (CPU), a digital signal processor (DSP), and a graphics processing unit (GPU).

[0033] According to an example embodiment, the memory controller 1100 may provide various signals to the memory device 1200 to control the overall operation of the memory device 1200. For example, the memory controller 1100 may control memory access operations of the memory device 1200, such as a read operation and a write operation. The memory controller 1100 may provide the command CMD and the address ADDR to the memory device 1200 to write data DATA into the memory device 1200 or read data DATA from the memory device 1200.

[0034] According to an example embodiment, the memory controller 1100 may generate various types of commands CMD to control the memory device 1200. For example, the memory controller 1100 may generate a bank request corresponding to a bank operation for changing the state of a bank among banks to read or write data DATA.

[0035] As an example, a bank request may include an activate request for changing the state of a bank among the banks to an active state. The memory device 1200 may activate a row included in the bank, such as a word line, in response to the activate request. The bank request may include a precharge request for changing the bank from the active state to a standby state after completion of reading or writing of the data DATA.

[0036] In addition, the memory controller 1100 may generate an input / output (I / O) request (e.g., a column address strobe (CAS) request) for the memory device 1200 to perform a read operation or a write operation of the data DATA. As an example, the I / O request may include a read request for reading the data DATA from the activated bank. The I / O request may include a write request for writing the data DATA into the activated bank.

[0037] Furthermore, the memory controller 1100 may generate a refresh command to control a refresh operation of the bank. However, the types of the commands CMD described herein are merely exemplary, and there may be other types of commands CMD.

[0038] According to an exemplary embodiment, the memory device 1200 may output the data DATA requested to be read by the memory controller 1100 to the memory controller 1100, or may store the data DATA requested to be written by the memory controller 1100 in a memory cell of the memory device 1200. The memory device 1200 may input and output the data DATA based on the command CMD and the address ADDR. The memory device 1200 may include a bank.

[0039] The memory device 1200 may be a volatile memory device, such as a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate (DDR) DRAM, a DDR SDRAM, a low power double data rate (LPDDR) SDRAM, a graphics double data rate (GDDR) SDRAM, a Rambus dynamic random access memory (RDRAM), and a static random access memory (SRAM), etc. Alternatively, the memory device 1200 may be implemented as a non-volatile memory device, such as a resistive RAM (RRAM), a phase change memory (PRAM), a magnetoresistive memory (MRAM), a ferroelectric memory (FRAM), a spin transfer torque RAM (STT-RAM), etc. In this specification, the advantages of the present disclosure have been described with respect to the DRAM, but the exemplary embodiments are not limited thereto.

[0040] According to an exemplary embodiment, a bank may include a memory cell array divided by bank, a row decoder, a column decoder, sense amplifiers, a write driver, etc. The bank may store data DATA requested to be written to the memory device 1200 through the write driver and may read the requested data DATA using the sense amplifiers. The bank may further include components for a refresh operation to store and maintain data in the cell array, or an address-based selection circuit.

[0041] According to an exemplary embodiment, the memory device 1200 may include a repair circuit 100. For example, the memory device 1200 may include defective (i.e., faulty) memory cells. The memory device 1200 may replace a word line including at least one defective memory cell (hereinafter referred to as a defective word line) with a redundant word line.

[0042] According to an exemplary embodiment, when repairing a defective word line, the repair circuit 100 may determine a repair mode. For example, the memory device 1200 may repair a defective word line according to a first repair mode or a second repair mode. In the first repair mode, word lines included in two banks and corresponding to each other are repaired together. In the second repair mode, each of the two banks is repaired separately. The repair circuit 100 may determine the repair mode of the selected word line based on the address of the selected word line.

[0043] Figure 2 is a block diagram of Figure 1 the memory device shown. Referring to Figure 2 , the memory device 1200 may include a memory cell array 1210, an address buffer 1220, a row decoder 1221, a column decoder 1222, bit line sense amplifiers 1230, a command decoder 1240, control logic 1250, and an input / output circuit 1260. Additionally, the memory device 1200 may include a repair circuit 100.

[0044] According to an exemplary embodiment, the memory cell array 1210 may include a plurality of memory cells arranged in a matrix of rows and columns. For example, the memory cell array 1210 may include a plurality of word lines WL and a plurality of bit lines BL connected to the memory cells. The plurality of word lines WL may be connected to the rows of the memory cells, and the plurality of bit lines BL may be connected to the columns of the memory cells.

[0045] According to an exemplary embodiment, the address buffer 1220 may receive from Figure 1The memory controller 1100 receives an address ADDR. For example, the address ADDR may include a row address RA for addressing rows of the memory cell array 1210 and a column address CA for addressing columns of the memory cell array 1210. The address buffer 1220 may send the row address RA to the row decoder 1221 and may send the column address CA to the column decoder 1222.

[0046] According to an example embodiment, the row decoder 1221 may select one of a plurality of word lines WL connected to the memory cell array 1210. The row decoder 1221 may decode the row address RA received from the address buffer 1220 to select a single word line corresponding to the row address RA and may activate the selected word line.

[0047] According to an example embodiment, the column decoder 1222 may select a predetermined bit line from a plurality of bit lines BL of the memory cell array 1210. The column decoder 1222 may decode the column address CA received from the address buffer 1220 to select a predetermined bit line BL corresponding to the column address CA.

[0048] According to an example embodiment, the bit line sense amplifier 1230 may be connected to the bit lines BL of the memory cell array 1210. For example, the bit line sense amplifier 1230 may sense a change in voltage of a selected one of the plurality of bit lines BL and may amplify and output the change in voltage.

[0049] According to an example embodiment, the command decoder 1240 may decode a write enable signal / WE, a row address strobe signal / RAS, a column address strobe signal / CAS, and a chip select signal / CS received from the memory controller 1100 such that control signals corresponding to a command CMD are generated in the control logic 1250. The command CMD may include an active request, a read request, a write request, or a precharge request.

[0050] The control logic 1250 may control the overall operation of the bit line sense amplifier 1230 through control signals corresponding to the command CMD. The control logic 1250 may generate control signals such that the bit line sense amplifier 1230 operates as a single-ended sense amplifier. Additionally, the control logic 1250 may control the overall operation of the memory device 1200.

[0051] According to an example embodiment, the input / output circuit 1260 may output data DATA to the memory controller 1100 through a data pad based on the sensed and amplified voltage from the bit line sense amplifier 1230. For example, the input / output circuit 1260 may include an input buffer or an output buffer. The input buffer or the output buffer may be connected to the data pad. The input / output circuit 1260 may perform a serialization operation or a deserialization operation on the data DATA.

[0052] According to an example embodiment, the repair circuit 100 may repair a failed word line with a redundant word line. For example, the repair circuit 100 may receive a row address RA from the address buffer 1220. The repair circuit 100 may determine whether to repair the word line corresponding to the row address RA.

[0053] According to an example embodiment, when the word line corresponding to the row address RA is a failed word line, the repair circuit 100 may generate a spare word line driving signal SNWEI based on the row address RA. The row decoder 1221 may activate the redundant word line (or redundant memory cell) corresponding to the row address RA based on the spare word line driving signal SNWEI.

[0054] According to an example embodiment, the repair circuit 100 may store position information about the failed word line including the failed memory cell. For example, the position information of the failed word line may be confirmed during an initial test of the memory device 1200. The repair circuit 100 may determine a repair mode based on the position information of the failed word line. The memory device 1200 may perform a first repair mode and a second repair mode depending on the position of the failed word line.

[0055] Figure 3 is a diagram showing a repair operation of a first repair mode of a memory device according to Figure 2 of. Figure 4 is a diagram showing a repair operation of a second repair mode of a memory device according to Figure 2 of. Referring to Figures 2 to 4 , the memory device 1200 may selectively perform a repair operation according to the first repair mode or the second repair mode.

[0056] According to an example embodiment, the memory cell array 1210 may include a plurality of banks. For example, in Figure 3 and Figure 4 , the memory device 1200 may perform a repair operation on the first bank BANK1 and the second bank BANK2 of the memory cell array 1210. However, this is an example, and the memory cell array 1210 may include a plurality of banks, and the memory device 1200 may group two banks among the plurality of banks and perform a repair operation with respect to the grouped banks.

[0057] According to an example embodiment, the first bank BANK1 may include a plurality of word lines, and each word line may be connected to a plurality of memory cells. The second bank BANK2 may include a plurality of word lines, and each word line may be connected to a plurality of memory cells. As an example, the first bank BANK1 may include the eleventh word line WL11 to the eighteenth word line WL18. The second bank BANK2 may include the twenty-first word line WL21 to the twenty-eighth word line WL28.

[0058] According to an example embodiment, a plurality of word lines may be divided into a plurality of word line groups. A word line group may include at least one word line.

[0059] As an example, in the first memory bank BANK1, the eleventh word line group WG11 may include the eleventh word line WL11 and the twelfth word line WL12. The twelfth word line group WG12 may include the thirteenth word line WL13 and the fourteenth word line WL14. The thirteenth word line group WG13 may include the fifteenth word line WL15 and the sixteenth word line WL16. The fourteenth word line group WG14 may include the seventeenth word line WL17 and the eighteenth word line WL18.

[0060] As an example, in the second memory bank BANK2, the twenty - first word line group WG21 may include the twenty - first word line WL21 and the twenty - second word line WL22. The twenty - second word line group WG22 may include the twenty - third word line WL23 and the twenty - fourth word line WL24. The twenty - third word line group WG23 may include the twenty - fifth word line WL25 and the twenty - sixth word line WL26. The twenty - fourth word line group WG24 may include the twenty - seventh word line WL27 and the twenty - eighth word line WL28.

[0061] According to an example embodiment, the word line groups of the first memory bank BANK1 may respectively correspond to the word line groups of the second memory bank BANK2. For example, the eleventh word line group WG11 may correspond to the twenty - first word line group WG21. The twelfth word line group WG12 may correspond to the twenty - second word line group WG22. The thirteenth word line group WG13 may correspond to the twenty - third word line group WG23. The fourteenth word line group WG14 may correspond to the twenty - fourth word line group WG24.

[0062] Reference Figure 3 , in the first repair mode, the memory device 1200 may repair the corresponding word line groups of the first memory bank BANK1 and the second memory bank BANK2 together. For example, the memory device 1200 may repair the eleventh word line group WG11 of the first memory bank BANK1 and the twenty - first word line group WG21 of the second memory bank BANK2 together. The memory device 1200 may repair the fourteenth word line group WG14 of the first memory bank BANK1 and the twenty - fourth word line group WG24 of the second memory bank BANK2 together.

[0063] According to an example embodiment, when failed memory cells are symmetrically located in the first bank BANK1 and the second bank BANK2, the memory device 1200 may repair a failed word line in the first repair mode. When repairing the failed word line in the first repair mode, the memory device 1200 may use one repair fuse to simultaneously repair the eleventh word line group WG11 of the first bank BANK1 and the twenty - first word line group WG21 of the second bank BANK2. Thus, compared with the second repair mode in which one repair fuse can be used to repair one bank, the memory device 1200 can repair twice as many failed word lines with one repair fuse in the first repair mode. However, when the failed memory cells are concentrated in one bank, normal (i.e., without failure or fault) word lines may also be repaired in the first repair mode, which may waste repair resources.

[0064] Reference Figure 4 , in the second repair mode, the memory device 1200 may repair the first bank BANK1 and the second bank BANK2 separately. For example, the memory device 1200 may repair the eleventh word line group WG11 and the twelfth word line group WG12 of the first bank BANK1. At this time, the twenty - first word line group WG21 and the twenty - second word line group WG22 of the second bank BANK2 corresponding to the eleventh word line group WG11 and the twelfth word line group WG12 may not be repaired. The memory device 1200 may repair the twenty - third word line group WG23 and the twenty - fourth word line group WG24 of the second bank BANK2. At this time, the thirteenth word line group WG13 and the fourteenth word line group WG14 of the first bank BANK1 corresponding to the twenty - third word line group WG23 and the twenty - fourth word line group WG24 are not repaired.

[0065] According to an example embodiment, when failed memory cells are asymmetrically located in the first bank BANK1 and the second bank BANK2, the memory device 1200 may repair the failed word line in the second repair mode. When repairing the failed word line in the second repair mode, the memory device 1200 may use one repair fuse to repair one bank. Thus, compared with the first repair mode, repairing the same number of word line groups in the second repair mode may require twice as many repair fuses. However, when the failed memory cells are concentrated in one bank, compared with the first repair mode, the second repair mode can save repair resources.

[0066] Figure 5 is a diagram Figure 2 of an example of the repair circuit. Reference Figure 5 , the repair circuit 100 may include a mode selection circuit 110, a mode information register 120, and a repair control circuit 130.

[0067] According to an example embodiment, the mode selection circuit 110 may generate a repair fuse selection signal FS and a repair mode signal MODE based on a row address RA. For example, the mode selection circuit 110 may receive a bank repair mode information BRMI from a mode information register 120. The bank repair mode information BRMI may include information indicating a repair mode of each bank. The mode selection circuit 110 may check the repair mode of a currently activated bank based on the row address RA and the bank repair mode information BRMI.

[0068] According to an example embodiment, the mode information register 120 may store the bank repair mode information BRMI indicating a repair mode of each bank. For example, the memory device 1200 may confirm the location of defective memory cells through testing before product shipment. The bank repair mode information BRMI may be generated based on the location of the defective memory cells. As an example, in two corresponding banks, when the defective memory cells are distributed and located in corresponding word line groups of the two banks, the bank repair mode information BRMI may indicate a first repair mode. In two corresponding banks, when the defective memory cells are concentrated in one bank, the bank repair mode information BRMI may indicate a second repair mode.

[0069] According to an example embodiment, the repair control circuit 130 may generate a spare word line drive signal SNWEI based on the repair fuse selection signal FS and the repair mode signal MODE. For example, the spare word line drive signal SNWEI may include a first bank spare word line drive signal SNWEI_B1 corresponding to a first bank BANK1 and a second bank spare word line drive signal SNWEI_B2 corresponding to a second bank BANK2.

[0070] Figure 6 is a diagram showing Figure 5 an example of the repair control circuit. Figure 7 is a diagram showing a repair fuse selection signal for selecting Figure 6 a repair fuse. Referring to Figure 6 and Figure 7 , the repair control circuit 130 may include a plurality of repair fuses F1 to F8. Each of the plurality of repair fuses F1 to F8 may include redundancy enable information PRENI1 to PRENI8.

[0071] According to an example embodiment, the repair control circuit 130 may include a latch and a switch corresponding to a first bank BANK1. For example, the repair control circuit 130 may include an eleventh latch LAT11 to an eighteenth latch LAT18. The repair control circuit 130 may include an eleventh switch SW11 to an eighteenth switch SW18 corresponding to the eleventh latch LAT11 to the eighteenth latch LAT18, respectively.

[0072] As an example, the first redundant enable information PRENI1 to the fourth redundant enable information PRENI4 output from the first repair fuse F1 to the fourth repair fuse F4 can be sent to the first repair word line selection circuit 131 through the eleventh latch LAT11 to the fourteenth latch LAT14.

[0073] As an example, the fifth redundant enable information PRENI5 to the eighth redundant enable information PRENI8 output from the fifth repair fuse F5 to the eighth repair fuse F8 can be sent to the third repair word line selection circuit 133 through the fifteenth latch LAT15 to the eighteenth latch LAT18.

[0074] According to the exemplary embodiment, the repair control circuit 130 may include latches and switches corresponding to the second bank BANK2. For example, the repair control circuit 130 may include the twenty-first latch LAT21 to the twenty-eighth latch LAT28. The repair control circuit 130 may include the twenty-first switch SW21 to the twenty-eighth switch SW28 corresponding to the twenty-first latch LAT21 to the twenty-eighth latch LAT28 respectively.

[0075] As an example, the first redundant enable information PRENI1 to the fourth redundant enable information PRENI4 output from the first repair fuse F1 to the fourth repair fuse F4 can be sent to the second repair word line selection circuit 132 through the twenty-first latch LAT21 to the twenty-fourth latch LAT24.

[0076] As an example, the fifth redundant enable information PRENI5 to the eighth redundant enable information PRENI8 output from the fifth repair fuse F5 to the eighth repair fuse F8 can be sent to the fourth repair word line selection circuit 134 through the twenty-fifth latch LAT25 to the twenty-eighth latch LAT28.

[0077] According to the exemplary embodiment, the redundant enable information stored in the plurality of repair fuses F1 to F8 can be commonly used for the first bank BANK1 and the second bank BANK2. For example, the first redundant enable information PRENI1 to the eighth redundant enable information PRENI8 can be sent to the repair word line selection circuits 131 and 133 corresponding to the first bank BANK1, and can also be sent to the repair word line selection circuits 132 and 134 corresponding to the second bank BANK2.

[0078] Reference Figure 7 , it can be based on from Figure 5The mode selection circuit 110 receives a repair fuse selection signal FS to activate a plurality of switches included in the repair control circuit 130. For example, the eleventh switch SW11, the twelfth switch SW12, the fifteenth switch SW15, and the sixteenth switch SW16 corresponding to the first bank BANK1 can be turned on or off based on the eleventh fuse selection signal FS11. The thirteenth switch SW13, the fourteenth switch SW14, the seventeenth switch SW17, and the eighteenth switch SW18 corresponding to the first bank BANK1 can be turned on or off based on the twelfth fuse selection signal FS12.

[0079] In addition, the twenty-third switch SW23, the twenty-fourth switch SW24, the twenty-seventh switch SW27, and the twenty-eighth switch SW28 corresponding to the second bank BANK2 can be turned on or off based on the twenty-first fuse selection signal FS21. The twenty-first switch SW21, the twenty-second switch SW22, the twenty-fifth switch SW25, and the twenty-sixth switch SW26 corresponding to the second bank BANK2 can be turned on or off based on the twenty-second fuse selection signal FS22.

[0080] According to an exemplary embodiment, in the first repair mode, the eleventh fuse selection signal FS11, the twelfth fuse selection signal FS12, the twenty-first fuse selection signal FS21, and the twenty-second fuse selection signal FS22 can all be activated. When the eleventh fuse selection signal FS11, the twelfth fuse selection signal FS12, the twenty-first fuse selection signal FS21, and the twenty-second fuse selection signal FS22 are all activated, all the switches can be turned on. And the redundancy enable information PRENI can be sent to all the repair word line selection circuits 131, 132, 133, and 134 corresponding to the first bank BANK1 and the second bank BANK2. Therefore, the first repair mode can be executed, in which the corresponding word line groups of the first bank BANK1 and the second bank BANK2 are repaired together.

[0081] According to an exemplary embodiment, in the second repair mode, the eleventh fuse selection signal FS11 and the twenty-first fuse selection signal FS21 can be activated. The twelfth fuse selection signal FS12 and the twenty-second fuse selection signal FS22 can be deactivated. Therefore, different redundancy enable information PRENI can be sent to the repair word line selection circuits 131 and 133 corresponding to the first bank BANK1 and the repair word line selection circuits 132 and 134 corresponding to the second bank BANK2. Therefore, the second repair mode can be executed, in which the word line groups that do not correspond to each other in the first bank BANK1 and the second bank BANK2 are repaired separately.

[0082] Figure 8 is shownFigure 6 The figure of an example of the first repair word line selection circuit. Figure 8 The first repair word line selection circuit 131 is shown as an example, but the remaining repair word line selection circuits corresponding to the first memory bank BANK1 (e.g., the third repair word line selection circuit 133) may have the same configuration and characteristics. Refer to Figure 8 , the first repair word line selection circuit 131 may include a plurality of logic circuits.

[0083] According to an example embodiment, the first repair word line selection circuit 131 may include an eleventh NAND circuit ND11, a twelfth NAND circuit ND12, and a first NOR circuit NR1. For example, the eleventh NAND circuit ND11 may perform a NAND operation on the first redundancy enable information PRENI1 and the second redundancy enable information PRENI2, and output a first bank signal BA1. The twelfth NAND circuit ND12 may perform a NAND operation on the third redundancy enable information PRENI3 and the fourth redundancy enable information PRENI4, and output a second bank signal BA2. The first NOR circuit NR1 may perform a NOR operation on the first bank signal BA1 and the second bank signal BA2, and output a combined bank signal BA12.

[0084] In addition, the first repair word line selection circuit 131 may include a thirteenth NAND circuit ND13, a fourteenth NAND circuit ND14, and a fifteenth NAND circuit ND15. For example, the thirteenth NAND circuit ND13 may perform a NAND operation on the complementary signal BA12B of the combined bank signal BA12 and the first repair mode signal MODE1, and output a first repair decision signal BM1. The fourteenth NAND circuit ND14 may perform a NAND operation on the first bank signal BA1 and the second repair mode signal MODE2, and output a second repair decision signal BM2. The fifteenth NAND circuit ND15 may perform a NAND operation on the first repair decision signal BM1 and the second repair decision signal BM2, and output a first bank spare word line drive signal SNWEI_B1.

[0085] Figure 9 Is a figure showing Figure 6 The figure of an example of the second repair word line selection circuit. Figure 9 The second repair word line selection circuit 132 is shown as an example, but the remaining repair word line selection circuits corresponding to the second memory bank BANK2 (e.g., the fourth repair word line selection circuit 134) may have the same configuration and characteristics. Refer to Figure 9 , the second repair word line selection circuit 132 may include a plurality of logic circuits.

[0086] According to an exemplary embodiment, the second repair word line selection circuit 132 may include a twenty-first NAND circuit ND21, a twenty-second NAND circuit ND22, and a second NOR circuit NR2. For example, the twenty-first NAND circuit ND21 may perform a NAND operation on a first redundancy enable information PRENI1 and a second redundancy enable information PRENI2, and output a first body signal BA1. The twenty-second NAND circuit ND22 may perform a NAND operation on a third redundancy enable information PRENI3 and a fourth redundancy enable information PRENI4, and output a second body signal BA2. The second NOR circuit NR2 may perform a NOR operation on the first body signal BA1 and the second body signal BA2, and output a combined body signal BA12.

[0087] Additionally, the second repair word line selection circuit 132 may include a twenty-third NAND circuit ND23, a twenty-fourth NAND circuit ND24, and a twenty-fifth NAND circuit ND25. For example, the twenty-third NAND circuit ND23 may perform a NAND operation on a complementary signal BA12B of the combined body signal BA12 and a first repair mode signal MODE1, and output a third repair decision signal BM3. The twenty-fourth NAND circuit ND24 may perform a NAND operation on the second body signal BA2 and a second repair mode signal MODE2, and output a fourth repair decision signal BM4. The twenty-fifth NAND circuit ND25 may perform a NAND operation on the third repair decision signal BM3 and the fourth repair decision signal BM4, and output a second body spare word line drive signal SNWEI_B2.

[0088] As another example, the second repair word line selection circuit 132 may jointly use the eleventh NAND circuit ND11, the twelfth NAND circuit ND12, and the first NOR circuit NR1 of the first repair word line selection circuit 131, instead of the twenty-first NAND circuit ND21, the twenty-second NAND circuit ND22, and the second NOR circuit NR2. The twenty-first NAND circuit ND21 may calculate the same output signal as the eleventh NAND circuit ND11 based on the same input signals. The twenty-second NAND circuit ND22 may calculate the same output signal as the twelfth NAND circuit ND12 based on the same input signals. The second NOR circuit NR2 may calculate the same output signal as the first NOR circuit NR1 based on the same input signals.

[0089] Figures 10 to 12 is a diagram showing Figure 5 the operation of the repair control circuit in the first repair mode. Figure 10 is a diagram showing Figure 6 the operation of the latch and switch in the first repair mode. Figure 11 is a diagram showingFigure 8 Diagram of the operation of the logic circuit in the first repair mode. Figure 12 Shows Figure 9 Diagram of the operation of the logic circuit in the first repair mode. Figures 10 to 12 The first repair word line selection circuit 131 and the second repair word line selection circuit 132 are shown as examples, but the remaining repair word line selection circuits can also operate in the same manner as the first repair word line selection circuit 131 and the second repair word line selection circuit 132.

[0090] Refer to Figures 10 to 12 , when the failed memory cell is located in the eleventh word line group WG11 of the first bank BANK1 corresponding to the first repair fuse F1, the first repair fuse F1 can store the changed first redundant enable information PRENI1. For example, when the corresponding word line group is normal, one repair fuse can store a high level (logic 1), and when the corresponding word line group includes a failed memory cell, one repair fuse can store a low level (logic 0).

[0091] According to an exemplary embodiment, in the first repair mode, the eleventh fuse selection signal FS11, the twelfth fuse selection signal FS12, the twenty-first fuse selection signal FS21, and the twenty-second fuse selection signal FS22 can all be activated. When the eleventh fuse selection signal FS11, the twelfth fuse selection signal FS12, the twenty-first fuse selection signal FS21, and the twenty-second fuse selection signal FS22 are all activated, all switches can be turned on, and the first redundant enable information PRENI1 to the fourth redundant enable information PRENI4 can be sent to both the first repair word line selection circuit 131 and the second repair word line selection circuit 132. As an example, when the failed memory cell is located in the eleventh word line group WG11 of the first bank BANK1, the first redundant enable information PRENI1 can have a low level, and the second to fourth redundant enable information PRENI2, PRENI3, and PRENI4 can have a high level.

[0092] According to an exemplary embodiment, in Figure 11 , when at least one of the first to fourth redundant enable information PRENI1, PRENI2, PRENI3, and PRENI4 is at a low level, the one-two bank signal BA12 can have a low level. As an example, since the first redundant enable information PRENI1 is at a low level, the first bank signal BA1 is at a high level. Since both the third redundant enable information PRENI3 and the fourth redundant enable information PRENI4 are at a high level, the second bank signal BA2 is at a low level. Therefore, the one-two bank signal BA12 is at a low level.

[0093] According to an exemplary embodiment, the first repair word line selection circuit 131 (or the repair control circuit 130) may receive a repair mode signal MODE from Figure 5 the mode selection circuit 110. For example, the repair mode signal MODE may include a first repair mode signal MODE1 and a second repair mode signal MODE2. The first repair mode signal MODE1 and the second repair mode signal MODE2 may be complementary signals. In the first repair mode, the first repair mode signal MODE1 may be activated, and the second repair mode signal MODE2 may be deactivated.

[0094] According to an exemplary embodiment, in the first repair mode, since the first repair mode signal MODE1 is at a high level, the first repair decision signal BM1 may be determined according to the complementary signal BA12B of the one-two body signal BA12. In Figure 11 this case, since the failed memory cell is located in the eleventh word line group WG11 and the complementary signal BA12B of the one-two body signal BA12 is at a high level, the first repair decision signal BM1 is at a low level. Since the second repair mode signal MODE2 is at a low level, the second repair decision signal BM2 is at a high level.

[0095] Therefore, the first body spare word line driving signal SNWEI_B1 may have a high level. For example, when the first body spare word line driving signal SNWEI_B1 is at a high level, the eleventh word line group WG11 may be repaired. When the first body spare word line driving signal SNWEI_B1 is at a low level, the eleventh word line group WG11 may not be repaired.

[0096] According to an exemplary embodiment, in Figure 12 this case, when at least one of the first to fourth redundant enable information PRENI1, PRENI2, PRENI3, and PRENI4 is at a low level, the one-two body signal BA12 may have a low level. As an example, since the first redundant enable information PRENI1 is at a low level, the first body signal BA1 is at a high level. Since the third redundant enable information PRENI3 and the fourth redundant enable information PRENI4 are both at a high level, the second body signal BA2 is at a low level. Therefore, the one-two body signal BA12 is at a low level.

[0097] According to an exemplary embodiment, in the first repair mode, since the first repair mode signal MODE1 is at a high level, the third repair decision signal BM3 may be determined according to the complementary signal BA12B of the one-two body signal BA12. In Figure 12Among them, since the failed memory cell is located in the eleventh word line group WG11 and the complementary signal BA12B of the one-two body signal BA12 is at a high level, the third repair decision signal BM3 is at a low level. Since the second repair mode signal MODE2 is at a low level, the fourth repair decision signal BM4 is at a high level.

[0098] Therefore, the second body spare word line drive signal SNWEI_B2 can have a high level. As an example, when the second body spare word line drive signal SNWEI_B2 is at a high level, the twenty-first word line group WG21 can be repaired. When the second body spare word line drive signal SNWEI_B2 is at a low level, the twenty-first word line group WG21 may not be repaired.

[0099] Therefore, in the first repair mode, when the failed memory cell is located in the eleventh word line group WG11 of the first memory bank BANK1, the eleventh word line group WG11 and the twenty-first word line group WG21 can be repaired together.

[0100] Figures 13 to 15 is a diagram showing Figure 5 the operation of the repair control circuit in the second repair mode. Figure 13 is a diagram showing Figure 6 the operation of the latch and switch in the second repair mode. Figure 14 is a diagram showing Figure 8 the operation of the logic circuit in the second repair mode. Figure 15 is a diagram showing Figure 9 the operation of the logic circuit in the second repair mode. Figures 13 to 15 The first repair word line selection circuit 131 and the second repair word line selection circuit 132 are shown as examples, but the remaining repair word line selection circuits also operate in the same manner as the first repair word line selection circuit 131 and the second repair word line selection circuit 132.

[0101] Refer to Figures 13 to 15 , when the failed memory cell is located in the eleventh word line group WG11 of the first memory bank BANK1 corresponding to the first repair fuse F1, the first repair fuse F1 can store the changed first redundant enable information PRENI1. For example, when the corresponding word line group is normal, one repair fuse can store a high level (logic 1), and when the corresponding word line group includes a failed memory cell, one repair fuse can store a low level (logic 0).

[0102] According to the exemplary embodiment, in the second repair mode, the eleventh fuse selection signal FS11 and the twenty-first fuse selection signal FS21 can be activated. The twelfth fuse selection signal FS12 and the twenty-second fuse selection signal FS22 can be deactivated. Accordingly, the eleventh switch SW11, the twelfth switch SW12, the twenty-third switch SW23, and the twenty-fourth switch SW24 are turned on. The thirteenth switch SW13, the fourteenth switch SW14, the twenty-first switch SW21, and the twenty-second switch SW22 can be turned off.

[0103] According to the exemplary embodiment, according to the on or off state of the switches, the first redundant enable information PRENI1 and the second redundant enable information PRENI2 can be sent to the first repair word line selection circuit 131. Additionally, the third redundant enable information PRENI3 and the fourth redundant enable information PRENI4 can be sent to the second repair word line selection circuit 132.

[0104] As an example, when the failed memory cell is located in the eleventh word line group WG11 of the first bank BANK1, the first redundant enable information PRENI1 can be at a low level, and the second to fourth redundant enable information PRENI2, PRENI3, and PRENI4 can be at a high level.

[0105] According to the exemplary embodiment, in Figure 14 Since the first repair word line selection circuit 131 only receives the first redundant enable information PRENI1 and the second redundant enable information PRENI2, the one-two body signal BA12 can be determined by the first redundant enable information PRENI1 and the second redundant enable information PRENI2. As an example, since the first redundant enable information PRENI1 is at a low level, the first body signal BA1 is at a high level. Since the first body signal BA1 is at a high level, the one-two body signal BA12 is at a low level.

[0106] According to the exemplary embodiment, the first repair word line selection circuit 131 (or the repair control circuit 130) can receive the repair mode signal MODE from Figure 5 the mode selection circuit 110. For example, the repair mode signal MODE can include a first repair mode signal MODE1 and a second repair mode signal MODE2. The first repair mode signal MODE1 and the second repair mode signal MODE2 can be complementary signals. In the second repair mode, the first repair mode signal MODE1 can be deactivated, and the second repair mode signal MODE2 can be activated.

[0107] According to an exemplary embodiment, in the second repair mode, since the first repair mode signal MODE1 is at a low level, the first repair decision signal BM1 can be at a high level. Since the second repair mode signal MODE2 is at a high level, the second repair decision signal BM2 can be determined according to the first body signal BA1. In Figure 14 , since the failed memory cell is located in the eleventh word line group WG11 and the first body signal BA1 is at a high level, the second repair decision signal BM2 is at a low level.

[0108] Therefore, the first body spare word line drive signal SNWEI_B1 can have a high level. As an example, when the first body spare word line drive signal SNWEI_B1 is at a high level, the eleventh word line group WG11 can be repaired. When the first body spare word line drive signal SNWEI_B1 is at a low level, the eleventh word line group WG11 may not be repaired.

[0109] According to an exemplary embodiment, in Figure 15 , since the second repair word line selection circuit 132 only receives the third redundancy enable information PRENI3 and the fourth redundancy enable information PRENI4, the first and second body signal BA12 can be determined by the third redundancy enable information PRENI3 and the fourth redundancy enable information PRENI4. For example, since both the third redundancy enable information PRENI3 and the fourth redundancy enable information PRENI4 are at a high level, the second body signal BA2 is at a low level. Since the second body signal BA2 is at a low level, the first and second body signal BA12 is at a high level.

[0110] According to an exemplary embodiment, in the second repair mode, since the first repair mode signal MODE1 is at a low level, the third repair decision signal BM3 is at a high level. Since the second repair mode signal MODE2 is at a high level, the fourth repair decision signal BM4 can be determined according to the second body signal BA2. In Figure 15 , since there is no failed memory cell in the twenty-first word line group WG21, the second body signal BA2 is at a low level, and thus the fourth repair decision signal BM4 is at a high level.

[0111] According to an exemplary embodiment, since both the third repair decision signal BM3 and the fourth repair decision signal BM4 are at a high level, the second body spare word line drive signal SNWEI_B2 can have a low level. As an example, when the second body spare word line drive signal SNWEI_B2 is at a high level, the twenty-first word line group WG21 can be repaired. When the second body spare word line drive signal SNWEI_B2 is at a low level, the twenty-first word line group WG21 may not be repaired.

[0112] Accordingly, in the second repair mode, when the failed memory cell is located in the eleventh word line group WG11 of the first bank BANK1, the eleventh word line group WG11 is repaired, and the twenty-first word line group WG21 may not be repaired. That is to say, in the second repair mode, the first bank BANK1 and the second bank BANK2 can be repaired separately.

[0113] Figure 16 is a flowchart showing a repair method of a memory device for Figure 2 . Referring to Figures 2 to 16 , the memory device 1200 can determine a repair mode for a failed memory cell included in the memory cell array 1210 based on an address ADDR received from the memory controller 1100.

[0114] According to an exemplary embodiment, in operation S110, the memory device 1200 can compare bank repair mode information BRMI with an address ADDR received from the memory controller 1100. For example, the address buffer 1220 can receive the address ADDR and output a row address RA and a column address CA. The repair circuit 100 can store bank repair mode information BRMI including information indicating a repair mode of each bank based on the location information of the failed memory cell.

[0115] According to an exemplary embodiment, in operation S120, the memory device 1200 can determine a repair mode based on the comparison result in operation S110. For example, the repair circuit 100 can compare the bank repair mode information BRMI and the row address RA.

[0116] As an example, the mode information register 120 can store the bank repair mode information BRMI. The mode selection circuit 110 can check the repair mode of the currently activated bank based on the row address RA and the bank repair mode information BRMI. The mode selection circuit 110 can generate a repair fuse selection signal FS and a repair mode signal MODE based on the row address RA and the bank repair mode information BRMI.

[0117] According to an exemplary embodiment, in operation S130, the memory device 1200 can check whether the determined repair mode is the first repair mode. When the determined repair mode is the first repair mode ( Figure 16 is in), the memory device 1200 can perform operation S140. When the determined repair mode is the second repair mode ( Figure 16 is not in), the memory device 1200 can perform operation S150.

[0118] According to an example embodiment, in operation S140, the memory device 1200 may repair a defective word line including defective memory cells in the first bank and the second bank together with a corresponding word line. For example, in a first repair mode, redundant enable information PRENI1 to PRENI8 stored in a plurality of repair fuses F1 to F8 may all be sent to a repair word line selection circuit corresponding to the first bank BANK1 (e.g., the first repair word line selection circuit 131 or the third repair word line selection circuit 133) and a repair word line selection circuit corresponding to the second bank BANK2 (e.g., the second repair word line selection circuit 132 or the fourth repair word line selection circuit 134). Accordingly, the eleventh word line group WG11 of the first bank BANK1 and the twenty-first word line group WG21 of the second bank BANK2 corresponding to the eleventh word line group WG11 may be repaired together.

[0119] According to an example embodiment, in operation S150, the memory device 1200 may repair defective word lines of the first bank BANK1 and defective word lines of the second bank BANK2 separately. For example, in a second repair mode, some of the redundant enable information PRENI1 to PRENI8 stored in a plurality of repair fuses F1 to F8 may be sent to a repair word line selection circuit corresponding to the first bank BANK1 (e.g., the first repair word line selection circuit 131 or the third repair word line selection circuit 133). Other parts of the redundant enable information PRENI1 to PRENI8 stored in a plurality of repair fuses F1 to F8 may be sent to a repair word line selection circuit corresponding to the second bank BANK2 (e.g., the second repair word line selection circuit 132 or the fourth repair word line selection circuit 134). Accordingly, defective word lines of the first bank BANK1 may be repaired separately from defective word lines of the second bank BANK2.

[0120] Figure 17 is a diagram illustrating a method of repairing banks included in Figure 2 the memory cell array. Referring to Figure 17 , the memory cell array 1210 may include a plurality of banks. The plurality of banks may be set to different repair modes depending on the distribution positions of defective memory cells.

[0121] As an example, the plurality of banks may include first to fourth banks 1211, 1212, 1213, and 1214. The first bank 1211 may correspond to the second bank 1212, and the first bank 1211 and the second bank 1212 may share the same first repair fuse. The third bank 1213 may correspond to the fourth bank 1214, and the third bank 1213 and the fourth bank 1214 may share the same second repair fuse.

[0122] When the failed memory cells are symmetrically distributed in the first bank 1211 and the second bank 1212, the failed word lines of the first bank 1211 and the second bank 1212 can be repaired in the first repair mode. Additionally, when the failed memory cells are concentrated in any one of the third bank 1213 and the fourth bank 1214, the failed word lines of the third bank 1213 and the fourth bank 1214 can be repaired in the second repair mode. That is, the first bank pair (the first bank 1211 and the second bank 1212) and the second bank pair (the third bank 1213 and the fourth bank 1214) can be set to the first repair mode or the second repair mode independently of each other.

[0123] According to the present disclosure, the repair resources can be effectively utilized by changing the repair mode of the bank according to the distribution position of the failed memory cells.

[0124] Although the present disclosure has been described with reference to the embodiments of the present disclosure, it will be apparent to those of ordinary skill in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A memory device, comprising: A first bank, including first memory cells connected to a first word line; A second bank, including second memory cells connected to a second word line corresponding to the first word line; And A repair circuit, based on the location of defective memory cells included in the first memory cells and the second memory cells, the repair circuit is configured to repair the first word line and the second word line together, or is configured to repair the first word line or the second word line separately.

2. The memory device according to claim 1, wherein, The repair circuit includes: A mode information register, configured to store bank repair mode information according to the location of the defective memory cells; A mode selection circuit, configured to generate a fuse selection signal and a repair mode signal based on an address received from an external device and the bank repair mode information; and A repair control circuit, configured to generate a spare word line drive signal based on the fuse selection signal and the repair mode signal.

3. The memory device according to claim 2, further comprising: A row decoder, configured to activate a selected word line corresponding to the address in the first bank or the second bank, Wherein, the row decoder is configured to replace the selected word line with a redundant word line based on the spare word line drive signal.

4. The memory device according to claim 2, wherein, The repair control circuit includes: Repair fuses, including redundancy enable information; A first repair word line selection circuit, configured to generate a first bank spare word line drive signal corresponding to the first word line based on the redundancy enable information; A second repair word line selection circuit, configured to generate a second bank spare word line drive signal corresponding to the second word line based on the redundancy enable information; A first latch, configured to send the redundancy enable information to the first repair word line selection circuit based on a first fuse selection signal; and A second latch, configured to send the redundancy enable information to the second repair word line selection circuit based on a second fuse selection signal.

5. The memory device according to claim 4, wherein, When a first repair mode for repairing the first word line and the second word line together is determined based on the bank repair mode information, all the first latches are configured to be turned on by the first fuse selection signal, and all the second latches are configured to be turned on by the second fuse selection signal.

6. The memory device according to claim 5, wherein, The first repair word line selection circuit is configured to perform a logic operation on the redundancy enable information sent through the first latch to output the first bank spare word line drive signal for repairing the first word line, Wherein, the second repair word line selection circuit is configured to perform a logic operation on the redundancy enable information sent through the second latch to output the second bank spare word line drive signal for repairing the second word line.

7. The memory device according to claim 4, wherein, When a second repair mode for repairing the first word line or the second word line separately is determined based on the bank repair mode information, only a part of the first latches are configured to be turned on by the first fuse selection signal, and only a part of the second latches are configured to be turned on by the second fuse selection signal.

8. The memory device according to claim 7, wherein, When a failed memory cell is located in the first word line, the first repair word line selection circuit is configured to: perform a logic operation on a part of the redundancy enable information transmitted through a part of the first latch to output a first bank spare word line driving signal for repairing the first word line.

9. The memory device according to claim 8, wherein, When a failed memory cell is located in the second word line, the second repair word line selection circuit is configured to: perform a logic operation on another part of the redundancy enable information transmitted through a part of the second latch to output a second bank spare word line driving signal for repairing the second word line.

10. The memory device according to claim 4, wherein, The first repair word line selection circuit and the second repair word line selection circuit are configured to perform a logic operation on the redundancy enable information and the repair mode signal to generate the first bank spare word line driving signal and the second bank spare word line driving signal.

11. A memory device, comprising: A first bank, including a first word line group; A second bank, including a second word line group corresponding to the first word line group; A row decoder, configured to select word lines of the first bank and the second bank based on an address received from an external device; And A repair circuit, configured to provide a spare word line driving signal to the row decoder, such that when the first word line group or the second word line group is selected based on the address, bank repair mode information corresponding to the first word line group or the second word line group is checked, and the first word line group and the second word line group are repaired together, or the first word line group or the second word line group is repaired separately based on the bank repair mode information.

12. The memory device according to claim 11, wherein, The repair circuit includes: A mode information register, configured to store the bank repair mode information including position information of a failed memory cell; A mode selection circuit, configured to generate a fuse selection signal and a repair mode signal based on the address and the bank repair mode information; and A repair control circuit, configured to generate the spare word line driving signal based on the fuse selection signal and the repair mode signal.

13. The memory device according to claim 11, wherein, The repair circuit includes: A repair fuse, including redundancy enable information; A first repair word line selection circuit, configured to generate a first bank spare word line driving signal corresponding to the first word line group based on the redundancy enable information; A second repair word line selection circuit, configured to generate a second bank spare word line driving signal corresponding to the second word line group based on the redundancy enable information; A first latch, configured to transmit the redundancy enable information to the first repair word line selection circuit based on a first fuse selection signal; and A second latch, configured to transmit the redundancy enable information to the second repair word line selection circuit based on a second fuse selection signal.

14. The memory device according to claim 11, further comprising: A third bank, including a third word line group; And A fourth bank, including a fourth word line group corresponding to the third word line group, wherein the first bank and the second bank are configured to be set to a first repair mode to repair the first word line group and the second word line group together, and Among them, the third memory bank and the fourth memory bank are configured to be set to a second repair mode to separately repair the third word line group or the fourth word line group.

15. A repair method for a memory device, comprising: comparing an address received from an external device with bank repair mode information to determine a repair mode for each of a plurality of memory banks included in the memory device; determining a repair mode of a first memory bank corresponding to the address among the plurality of memory banks based on the comparison result; when the repair mode is determined to be a first repair mode, repairing, in a first repair operation, defective word lines included in the first memory bank among the plurality of memory banks and word lines corresponding to the defective word lines in a second memory bank; and when the repair mode is determined to be a second repair mode, separately repairing, in a second repair operation, the defective word lines included in the first memory bank and the defective word lines included in the second memory bank.

16. The method according to claim 15, wherein, When defective memory cells are distributed in the first memory bank and the second memory bank, the bank repair mode information is configured to be set to indicate the first repair mode.

17. The method according to claim 15, wherein, When defective memory cells are concentrated in one of the first memory bank or the second memory bank, the bank repair mode information is configured to be set to indicate the second repair mode.

18. The method according to claim 15, wherein The determining the repair mode is configured to include: generating a fuse selection signal and a repair mode signal based on the address and the bank repair mode information.

19. The method according to claim 18, wherein, In the first repair operation, the fuse selection signal is configured to be set such that redundancy enable information is equally sent to a first repair word line selection circuit corresponding to the first memory bank and a second repair word line selection circuit corresponding to the second memory bank, and wherein the repair mode signal is configured to be set to a first repair mode signal.

20. The method according to claim 18, wherein In the second repair operation, the fuse selection signal is configured to be set such that a part of the redundancy enable information is sent to a first repair word line selection circuit corresponding to the first memory bank, and another part of the redundancy enable information is sent to a second repair word line selection circuit corresponding to the second memory bank, and wherein the repair mode signal is configured to be set to a second repair mode signal.

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