Power supply system for universal integrated chip card and terminal equipment

Abstract

The invention relates to the technical field of communication, and discloses a power supply system and terminal equipment for a universal integrated chip card, and an internal power supply module of the power supply system is configured to provide an internal power supply provided by an internal power supply end to a system power supply output end under the control of a logic control module; the external power supply switch module is configured to provide an external power supply provided by an external power supply end to a system power supply output end under the control of the logic control module; a first delay unit of the logic control module is configured to delay a second logic signal for a first time period and then output the second logic signal under the control of a first input end and a second input end; the second delay unit is configured to delay the first logic signal for a second time period and then output the first logic signal under the control of the first input end and the second input end, and the first time period is larger than the second time period. The terminal equipment comprises the power supply system. According to the invention, transient large current generated during power supply switching can be eliminated, the product stability is improved, and the risk is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of communication technologies, and in particular, to a power supply system for a universal integrated circuit card and a terminal device. Background Art

[0002] Currently, mobile phones are no longer simple communication tools. They have become portable entertainment tools and have evolved into reliable payment tools, enabling convenient and fast payments in fields such as consumption, shopping, and transportation through mobile phones. Mobile payment using the Near Field Communication (NFC) solution has gradually become a hot topic of research for mobile operators, mobile phone manufacturers, and UICC card manufacturers. NFC is the most feasible solution for mobile non-contact payment services, and the Single Wire Protocol (SWP) connection solution is part of the NFC technology. The SWP protocol used in NFC is a single-wire interface protocol for transmitting information based on the current-voltage change of the C6 pin between the contactless front end (CLF) and the universal integrated circuit card (UICC). When the UICC communicates with the CLF, the SWP communication protocol requires that the power supply circuit for the UICC generally needs to provide two power supplies for the UICC to choose from, such as choosing an external power supply of 1.8V or 3.3V, or choosing an internal power supply of 1.8V.

[0003] The power supply circuit of the UICC used in the prior art controls whether to choose an external power supply or an internal power supply through the output of a logic control module, and completes the switching process between the two power supplies through a switch control. However, the prior art is prone to generating a transient large current during the process of switching from the internal power supply of 1.8V to the external power supply of 3.3V. This large current may cause components in the circuit to be damaged due to overcurrent, posing a risk to the circuit.

[0004] Therefore, how to eliminate the transient large current generated during power supply switching, improve product stability, and reduce risks is a technical problem that needs to be urgently solved by those skilled in the art. Summary of the Invention

[0005] To solve the above technical problems, the present disclosure provides a power supply system for a universal integrated circuit card and a terminal device to solve the problem that the power supply circuit for the UICC in the prior art is prone to generating a transient large current during power supply switching, posing a risk to the circuit.

[0006] The present disclosure provides a power supply system for a universal integrated circuit card, including a voltage module, a logic control module, an internal power supply module, an external power supply switch module, and a system power output terminal;

[0007] The voltage module includes an externally supplied power supply terminal, an internal power supply terminal, and a voltage output terminal;

[0008] The logic control module includes a first input terminal, a second input terminal, a first output terminal, a second output terminal, and a third output terminal; the logic control module is configured to: under the control of the first input terminal and the second input terminal, the first output terminal outputs a first logic signal, and the second output terminal and the third output terminal output a second logic signal; wherein, the first logic signal and the second logic signal are inverted;

[0009] The internal power supply module is configured to: under the control of the first output terminal, the voltage output terminal, and the internal power supply terminal, supply the internal power supply provided by the internal power supply terminal to the system power output terminal;

[0010] The externally supplied power switch module is configured to: under the control of the second output terminal, the third output terminal, and the externally supplied power supply terminal, supply the externally supplied power supply provided by the externally supplied power supply terminal to the system power output terminal;

[0011] The logic control module further includes a first delay unit and a second delay unit;

[0012] The first delay unit is configured to: under the control of the first input terminal and the second input terminal, delay the second logic signal by a first time period and then output it;

[0013] The second delay unit is configured to: under the control of the first input terminal and the second input terminal, delay the first logic signal by a second time period and then output it; wherein, the first time period is greater than the second time period.

[0014] Optionally, the difference between the first time period and the second time period is 800 ns.

[0015] Optionally, the internal power supply module includes a first PMOS transistor, a second PMOS transistor, and an internal inverter;

[0016] The input terminal of the internal inverter is connected to the first output terminal, the output terminal of the internal inverter is connected to the gate of the first PMOS transistor, the first pole of the first PMOS transistor is connected to the voltage output terminal, the second pole of the first PMOS transistor is connected to the gate of the second PMOS transistor, the first pole of the second PMOS transistor is connected to the internal power supply terminal, and the second pole of the second PMOS transistor is connected to the system power output terminal.

[0017] Further optionally, a current limiting circuit unit is further included between the gate of the second PMOS transistor and the second pole of the second PMOS transistor.

[0018] Further optionally, the externally supplied power switch module includes a third PMOS transistor and a fourth PMOS transistor;

[0019] The gate of the third PMOS transistor is connected to the second output terminal, the gate of the fourth PMOS transistor is connected to the third output terminal, the first poles of the third PMOS transistor and the fourth PMOS transistor are both connected to the external power supply terminal, and the second poles of the third PMOS transistor and the fourth PMOS transistor are both connected to the system power output terminal.

[0020] Optionally, the logic control module further includes a first inverter, an AND gate, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, and an eighth inverter;

[0021] The input terminal of the first inverter is connected to the first input terminal, and the input terminal of the fifth inverter is connected to the second input terminal;

[0022] The output terminal of the first inverter is connected to one input terminal of the AND gate, and the output terminal of the fifth inverter is connected to the other input terminal of the AND gate;

[0023] The output terminal of the AND gate is connected to the input terminal of the second inverter, the output terminal of the second inverter is connected to the input terminal of the second delay unit, the output terminal of the second delay unit is connected to the input terminal of the third inverter, the output terminal of the third inverter is connected to the input terminal of the fourth inverter, and the output terminal of the fourth inverter is connected to the first output terminal;

[0024] The output terminal of the fifth inverter is further connected to the input terminal of the first delay unit, the output terminal of the first delay unit is connected to the input terminal of the sixth inverter, the output terminal of the sixth inverter is respectively connected to the input terminals of the seventh inverter and the eighth inverter, the output terminal of the seventh inverter is connected to the second output terminal, and the output terminal of the eighth inverter is connected to the third output terminal.

[0025] Further optionally, the first delay unit includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a ninth inverter;

[0026] The gates of the fifth PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, and the gate of the first NMOS transistor are all connected to the output terminal of the fifth inverter;

[0027] The first pole of the fifth PMOS transistor is connected to the first pole of the ninth PMOS transistor, the second pole of the fifth PMOS transistor is connected to the first pole of the sixth PMOS transistor, the second pole of the sixth PMOS transistor is connected to the first pole of the seventh PMOS transistor, the second pole of the seventh PMOS transistor is connected to the first pole of the eighth PMOS transistor, and the second pole of the eighth PMOS transistor is respectively connected to the first pole of the first NMOS transistor, the gate of the second NMOS transistor, the input terminal of the ninth inverter, and the second pole of the ninth PMOS transistor;

[0028] The second pole of the first NMOS transistor is respectively connected to the first pole and the second pole of the second NMOS transistor;

[0029] The gate of the ninth PMOS transistor and the output terminal of the ninth inverter are both connected to the input terminal of the sixth inverter.

[0030] Further optionally, the second delay unit includes a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a tenth inverter, an eleventh inverter, and a twelfth inverter;

[0031] The input terminal of the tenth inverter is connected to the output terminal of the second inverter;

[0032] The gates of the tenth PMOS transistor, the eleventh PMOS transistor, the twelfth PMOS transistor, the thirteenth PMOS transistor, and the gate of the third NMOS transistor are all connected to the output terminal of the tenth inverter;

[0033] The first pole of the tenth PMOS transistor is connected to the first pole of the fourteenth PMOS transistor, the second pole of the tenth PMOS transistor is connected to the first pole of the eleventh PMOS transistor, the second pole of the eleventh PMOS transistor is connected to the first pole of the twelfth PMOS transistor, the second pole of the twelfth PMOS transistor is connected to the first pole of the thirteenth PMOS transistor, and the second pole of the thirteenth PMOS transistor is respectively connected to the first pole of the third NMOS transistor, the gate of the fourth NMOS transistor, the input terminal of the eleventh inverter, and the second pole of the fourteenth PMOS transistor;

[0034] The second pole of the third NMOS transistor is respectively connected to the first pole and the second pole of the fourth NMOS transistor;

[0035] The gate of the fourteenth PMOS transistor and the output terminal of the eleventh inverter are both connected to the input terminal of the twelfth inverter, and the output terminal of the twelfth inverter is connected to the input terminal of the third inverter.

[0036] Optionally, the voltage module includes a selection and switching unit and an external power supply detection unit;

[0037] One input terminal of the selection and switching unit is connected to the external power supply terminal, another input terminal of the selection and switching unit is connected to the internal power supply terminal, and the output terminal of the selection and switching unit is connected to the voltage output terminal; the external power supply detection unit is connected to the external power supply terminal.

[0038] Based on the same inventive concept, the present disclosure also provides a terminal device, and the terminal device includes the above-mentioned power supply system for a general integrated chip card.

[0039] The technical solution provided by the embodiments of the present disclosure has the following advantages compared with the prior art:

[0040] The power supply system for a general integrated chip card provided by the present disclosure sets that the logic control module further includes a first delay unit and a second delay unit. The first delay unit is configured to, under the control of a first input end and a second input end, delay a second logic signal and output it after a first time period. The second delay unit is configured to, under the control of the first input end and the second input end, delay a first logic signal and output it after a second time period. The first time period is greater than the second time period. That is, through the second delay unit, the moment of turning off the internal power supply module is delayed by the second time period, and through the first delay unit, the moment of turning on the external power supply switch module is delayed by the first time period. The first time period is greater than the second time period. The first logic signal output by the first output end is delayed by the second time period, ensuring that after the internal power supply module is completely turned off, the second logic signal output by the second output end and the third output end is delayed by a first time period longer than the second time period. At this time, the delay of the second time period has ensured that the internal power supply module is completely turned off, and after the time difference between the first time period and the second time period, it is further ensured that the internal power supply module is completely turned off. The second logic signal output by the second output end and the third output end then controls the external power supply switch module to turn on, that is, the external power supply provided by the external power supply terminal is connected to the system power output terminal only after a first time period of delay. Thus, it is possible to avoid the transient large current from flowing back into the circuit structure of the internal power supply module when the external power supply switch module is already turned on and the internal power supply module has not been completely turned off, which is beneficial to eliminating the transient large current generated during power supply switching, improving the product stability, and reducing risks. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The accompanying drawings herein are incorporated into and constitute a part of this specification, showing embodiments consistent with the present disclosure and, together with the specification, are used to explain the principles of the present disclosure.

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0043] Figure 1 is a schematic structural diagram of a power supply system for a general integrated chip card provided by an embodiment of the present disclosure;

[0044] Figure 2 is a schematic diagram of the principle of easily generating transient large current during power supply switching;

[0045] Figure 3 is another schematic structural diagram of a power supply system for a general integrated chip card provided by an embodiment of the present disclosure;

[0046] Figure 4 isFigure 3 A structural schematic diagram of a logic control module;

[0047] Figure 5 Another structural schematic diagram of a power supply system for a general integrated chip card provided by an embodiment of the present disclosure;

[0048] Figure 6 Another structural schematic diagram of a power supply system for a general integrated chip card provided by an embodiment of the present disclosure;

[0049] Figure 7 is Figure 6 A circuit structural schematic diagram of a logic control module in;

[0050] Figure 8 is Figure 7 A circuit structural schematic diagram of a first delay unit in;

[0051] Figure 9 is Figure 7 A circuit structural schematic diagram of a second delay unit in;

[0052] Figure 10 is Figure 6 A circuit structural schematic diagram of a voltage module in;

[0053] Figure 11 A structural schematic block diagram of a terminal device provided by an embodiment of the present disclosure. Specific embodiments

[0054] In order to be able to more clearly understand the above objects, features, and advantages of the present disclosure, the solutions of the present disclosure will be further described below. It should be noted that, without conflict, the embodiments of the present disclosure and the features in the embodiments may be combined with each other.

[0055] Many specific details are set forth in the following description in order to fully understand the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only a part of the embodiments of the present disclosure, rather than all the embodiments.

[0056] Please refer to Figure 1 , Figure 1 A structural schematic diagram of a power supply system for a general integrated chip card provided by an embodiment of the present disclosure. The power supply system 000 for a general integrated chip card provided by this embodiment includes a voltage module 10, a logic control module 20, an internal power supply module 30, an external power supply switch module 40, and a system power output terminal SIMVCC;

[0057] The voltage module 10 includes an external power supply power supply terminal PMUVCC, an internal power supply power supply terminal VDDNV, and a voltage output terminal VO1;

[0058] The logic control module 20 includes a first input terminal EN1, a second input terminal EN2, a first output terminal CTRL1, a second output terminal CTRL2, and a third output terminal CTRL3; the logic control module 20 is configured to: under the control of the first input terminal EN1 and the second input terminal EN2, the first output terminal CTRL1 outputs a first logic signal, and the second output terminal CTRL2 and the third output terminal CTRL3 output a second logic signal; wherein, the first logic signal and the second logic signal are inverted;

[0059] The internal power supply module 30 is configured to: under the control of the first output terminal CTRL1, the voltage output terminal VO1, and the internal power supply terminal VDDNV, supply the internal power supply provided by the internal power supply terminal VDDNV to the system power supply output terminal SIMVCC;

[0060] The external power supply switch module 40 is configured to: under the control of the second output terminal CTRL2, the third output terminal CTRL3, and the external power supply terminal PMUVCC, supply the external power supply provided by the external power supply terminal PMUVCC to the system power supply output terminal SIMVCC;

[0061] The logic control module 20 further includes a first delay unit 201 and a second delay unit 202;

[0062] The first delay unit 201 is configured to: under the control of the first input terminal EN1 and the second input terminal EN2, delay the second logic signal by a first time period t1 and then output it;

[0063] The second delay unit 202 is configured to: under the control of the first input terminal EN1 and the second input terminal EN2, delay the first logic signal by a second time period t2 and then output it; wherein, the first time period t1 is greater than the second time period t2.

[0064] Specifically, the power supply system provided in this embodiment can be used for a power supply circuit that powers the UICC, that is, this embodiment provides a power supply system for a universal integrated chip card. The power supply system 000 mainly includes a voltage module 10, a logic control module 20, an internal power supply module 30, and an external power supply switch module 40. The voltage module 10 includes an external power supply power supply terminal PMUVCC, an internal power supply power supply terminal VDDNV, and a voltage output terminal VO1. Among them, the external power supply power supply terminal PMUVCC is used to input an external power supply, and the external power supply voltage is 1.8V or 3.3V. The internal power supply power supply terminal VDDNV is used to provide an internal power supply, and the internal power supply voltage is 1.8V. The voltage module 10 can be an NWELL voltage module. The voltage module 10 is a substrate voltage selection module designed to prevent the substrate voltage of the PMOS transistor in the circuit from being higher than the source terminal voltage when the power supply is switched. According to the requirements of the SWP communication protocol, when the universal integrated chip card selects to be powered by an external power supply, it is necessary to have both a 3.3V power supply voltage and meet the power supply requirement of having a 1.8V power supply voltage. The external power supply power supply terminal PMUVCC can provide these two power supply voltages of 1.8V and 3.3V; when the universal integrated chip card selects to be powered by an internal power supply, the internal power supply power supply terminal VDDNV provides a 1.8V power supply voltage. When the universal integrated chip card selects to be powered by an internal power supply, the system power supply output terminal SIMVCC outputs 1.8V provided by the internal power supply power supply terminal VDDNV; when the universal integrated chip card selects to be powered by an external power supply, the system power supply output terminal SIMVCC outputs 1.8V provided by the external power supply power supply terminal PMUVCC or the system power supply output terminal SIMVCC outputs 3.3V provided by the external power supply power supply terminal PMUVCC. The output power supply of the system power supply output terminal SIMVCC in this embodiment is controlled by the logic control module 20. Through the control of the first input terminal EN1 and the second input terminal EN2, the first output terminal CTRL1 outputs a first logic signal, and the second output terminal CTRL2 and the third output terminal CTRL3 output a second logic signal that is the inverse of the first logic signal; and the first logic signal output by the first output terminal CTRL1 is used to control the conduction and cut-off of the internal power supply module 30, and the second logic signal output by the second output terminal CTRL2 and the third output terminal CTRL3 is used to control the conduction and cut-off of the external power supply switch module 40. The logic control module 20 is used to provide control signals for the switching transistors in each module.

[0065] The conduction condition of the internal power supply module 30 is that the first logic signal output by the first output terminal CTRL1 is an enabling signal (the enabling signal indicates a signal that can turn on the internal power supply module 30). At this time, the second logic signal output by the second output terminal CTRL2 and the third output terminal CTRL3 is inverted with respect to the first logic signal, that is, the second logic signal is a non-enabling signal (the non-enabling signal indicates a signal that cannot turn on the external power supply switch module 40). At this time, the internal power supply module 30 is turned on, while the external power supply switch module 40 is turned off. Under the control of the voltage output terminal VO1 and the internal power supply terminal VDDNV connected to the internal power supply module 30, the internal power supply provided by the internal power supply terminal VDDNV can be supplied to the system power output terminal SIMVCC, that is, the system power output terminal SIMVCC outputs the internal power supply voltage.

[0066] The conduction condition of the external power supply switch module 40 is that the second logic signal output by the second output terminal CTRL2 and the third output terminal CTRL3 is an enabling signal (the enabling signal indicates a signal that can turn on the external power supply switch module 40). At this time, the first logic signal output by the first output terminal CTRL1 is inverted with respect to the second logic signal, that is, the first logic signal is a non-enabling signal (the non-enabling signal indicates a signal that cannot turn on the internal power supply module 30). At this time, the internal power supply module 30 is turned off, while the external power supply switch module 40 is turned on. Under the control of the external power supply terminal PMUVCC connected to the external power supply switch module 40, the external power supply provided by the external power supply terminal PMUVCC can be supplied to the system power output terminal SIMVCC, that is, the system power output terminal SIMVCC outputs the external power supply voltage.

[0067] The power supply system 000 for the general integrated chip card in this embodiment can control whether the system power output terminal SIMVCC selects the external power supply provided by the external power supply terminal PMUVCC or the internal power supply provided by the internal power supply terminal VDDNV through the logic signals output by the first output terminal CTRL1, the second output terminal CTRL2, and the third output terminal CTRL3 of the logic control module 20. Through the switch control of the first input terminal EN1 and the second input terminal EN2 of the logic control module 20, the mutual switching process between the two power supplies can be completed, making the selection of the power supply voltage of the power supply system 000 more flexible and reliable.

[0068] However, the applicant further discovered that when the 1.8V provided by the internal power supply terminal VDDNV of the voltage module 10 is switched to the 3.3V provided by the external power supply terminal PMUVCC, under the output control of the logic control module 20, the internal power supply module 30 is turned off and the external power switch module 40 is also turned on, resulting in that when the internal power supply module 30 is not completely turned off, the 3.3V provided by the external power supply terminal PMUVCC is connected to the conduction path of the system power output terminal SIMVCC, generating a transient large current (pulse width of about 50ns, peak value of about 700mA), which is then turned on by the internal power supply module 30. At this time, the internal power supply module 30 is not completely turned off, so the transient large current is easily backflowed into the internal power supply module 30. Figure 2 As shown, Figure 2 This is a schematic diagram of a transient large current that is easily generated when the power source is switched. This transient large current may cause the circuit structure and electronic components in the internal power module 30 to be damaged due to overcurrent, making the power circuit of the entire power supply system at risk.

[0069] In order to better solve the above problems, Figure 3 and Figure 4 As shown, Figure 3 is another structural schematic diagram of a power supply system for a universal integrated chip card provided in an embodiment of the present disclosure, Figure 4 yes Figure 3A schematic structural diagram of a logic control module. In this embodiment, the logic control module 20 is further provided with a first delay unit 201 and a second delay unit 202. Among them, the first delay unit 201 is configured to output the second logic signal after delaying it for a first time period t1 under the control of the first input end EN1 and the second input end EN2; the second delay unit 202 is configured to output the first logic signal after delaying it for a second time period t2 under the control of the first input end EN1 and the second input end EN2. Among them, the first time period t1 is greater than the second time period t2, that is, through the second delay unit 202 included in the logic control module 20, the moment of turning off the internal power supply module 30 is delayed by the second time period t2, and through the first delay unit 201 included in the logic control module 20, the moment of turning on the external power supply switch module 40 is delayed by the first time period t1. The first time period t1 is greater than the second time period t2, and the first logic signal output by the first output end CTRL1 is delayed by the second time period t2, ensuring that after the internal power supply module 30 is completely turned off, the second logic signal output by the second output end CTRL2 and the third output end CTRL3 is delayed by a first time period t1 longer than the second time period t2. At this time, the delay of the second time period t2 has ensured that the internal power supply module 30 is completely turned off, and after passing through the difference time between the first time period t1 and the second time period t2, it further ensures that the internal power supply module 30 is completely turned off; the second logic signal output by the second output end CTRL2 and the third output end CTRL3 controls the external power supply switch module 40 to turn on again, that is, the 3.3V provided by the external power supply power supply terminal PMUVCC is connected to the system power supply output terminal SIMVCC only after being delayed by the first time period t1. Thus, it is possible to avoid the transient large current from flowing back into the circuit structure of the internal power supply module 30 when the external power supply switch module 40 is already turned on and the internal power supply module 30 has not been completely turned off, which is beneficial to eliminating the transient large current generated during power supply switching, improving the product stability, and reducing the risk.

[0070] Optionally, the logic control module 20 provided in this embodiment further includes a first delay unit 201 and a second delay unit 202; the first delay unit 201 is configured to output the second logic signal after delaying it for a first time period t1 under the control of a first input end EN1 and a second input end EN2; the second delay unit 202 is configured to output the first logic signal after delaying it for a second time period t2 under the control of the first input end EN1 and the second input end EN2; where the first time period t1 is greater than the second time period t2, and the difference between the first time period t1 and the second time period t2 is 800 ns. For example, the first time period t1 can be 1.8 μs, and the second time period t2 can be 1 μs. Thus, under the control of the first input end EN1 and the second input end EN2, the second delay unit 202 delays the non-enabled first logic signal (assuming the non-enabled first logic signal is high level, as shown in Figure 4 shown) and outputs it after a delay of 1 μs. Under the control of the first input end EN1 and the second input end EN2, the first delay unit 201 delays the enabled second logic signal (assuming the enabled second logic signal is low level, as shown in Figure 4 shown) output by the second output end CTRL1 and the third output end CTRL3 and outputs it after a delay of 1.8 μs. That is, after the non-enabled first logic signal controls the internal power supply module 30 to be completely turned off and is completely turned off for 0.8 μs (800 ns), the enabled second logic signal controls the external power supply switch module 40 to conduct. At this time, the 3.3V provided by the external power supply terminal PMUVCC is connected to the system power supply output terminal SIMVCC, which can avoid generating transient large current when the external power supply switch module 40 has been conducted while the internal power supply module 30 has not been completely turned off, which is beneficial to improving the product stability and reducing risks.

[0071] In this embodiment, the difference between the first time period t1 and the second time period t2 is further set to 800 ns. That is, after the non-enabled first logic signal controls the internal power supply module 30 to be completely turned off and is completely turned off for 800 ns, the enabled second logic signal controls the external power supply switch module 40 to conduct, which can ensure that after the internal power supply module 30 has been completely turned off for a sufficient length of time, the switch of the external power supply switch module 40 is turned on, avoiding the influence of transient large current on the circuit, and can also avoid the delay time from being too long. For example, if the difference between the first time period t1 and the second time period t2 exceeds 800 ns, it will affect the establishment of the power signal in the entire power supply system 000, and can ensure that the power signal can be output from the system power supply output terminal SIMVCC as soon as possible for the UICC to use.

[0072] In some alternative embodiments, please refer to Figures 1 - 4 and Figure 5 , Figure 5FIG. 0 is another schematic structural diagram of the power supply system for a general integrated chip card. In the power supply system 000 for a general integrated chip card provided in this embodiment, the internal power supply module 30 includes a first PMOS transistor PM1, a second PMOS transistor PM2, and an internal inverter INV0; the input terminal of the internal inverter INV0 is connected to the first output terminal CTRL1, the output terminal of the internal inverter INV0 is connected to the gate of the first PMOS transistor PM1, the first pole of the first PMOS transistor PM1 is connected to the voltage output terminal VO1, the second pole of the first PMOS transistor PM1 is connected to the gate of the second PMOS transistor PM2, the first pole of the second PMOS transistor PM2 is connected to the internal power supply terminal VDDNV, and the second pole of the second PMOS transistor PM2 is connected to the system power output terminal SIMVCC.

[0073] The externally supplied power switch module 40 includes a third PMOS transistor PM3 and a fourth PMOS transistor PM4; the gate of the third PMOS transistor PM3 is connected to the second output terminal CTRL2, the gate of the fourth PMOS transistor PM4 is connected to the third output terminal CTRL3, the first poles of the third PMOS transistor PM3 and the fourth PMOS transistor PM4 are both connected to the externally supplied power supply terminal PMUVCC, and the second poles of the third PMOS transistor PM3 and the fourth PMOS transistor PM4 are both connected to the system power output terminal SIMVCC.

[0074] This embodiment explains the circuit structures that can be set for the internal power supply module 30 and the externally supplied power switch module 40 in the power supply system 000. The internal power supply module 30 includes a first PMOS transistor PM1, a second PMOS transistor PM2, and an internal inverter INV0. The conduction and cutoff of the first PMOS transistor PM1 are controlled by the first logic signal output from the first output terminal CTRL1. The externally supplied power switch module 40 includes a third PMOS transistor PM3 and a fourth PMOS transistor PM4. The conduction and cutoff of the third PMOS transistor PM3 and the fourth PMOS transistor PM4 are controlled by the second logic signals output from the second output terminal CTRL2 and the third output terminal CTRL3.

[0075] Specifically, when the system power output terminal SIMVCC needs to select the internal power supply of 1.8V to supply power to the general integrated chip card, under the control of the first input terminal EN1 and the second input terminal EN2 of the logic control module 20, when the first logic signal output by the first output terminal CTRL1 is an enabling signal (such as a low level representing the enabling signal), the low level signal output by the first output terminal CTRL1 passes through the internal inverter INV0 and then outputs a high level. The gate of the first PMOS transistor PM1, that is, the voltage of the V1 node, is at a high level, and the first PMOS transistor PM1 is turned off. Since the gate of the second PMOS transistor PM2 is connected to the second pole of the first PMOS transistor PM1 and the first PMOS transistor PM1 is turned off, the gate of the second PMOS transistor PM2, that is, the voltage of the V2 node, will be pulled to the ground, that is, V2 = 0. And the first pole of the second PMOS transistor PM2 is connected to the internal power supply terminal VDDNV, so at this time the second PMOS transistor PM2 is turned on, and the power supply voltage of the system power output terminal SIMVCC is equal to the internal power supply voltage of 1.8V provided by the internal power supply terminal VDDNV. And at this time, under the control of the first input terminal EN1 and the second input terminal EN2 of the logic control module 20, when the second logic signals output by the second output terminal CTRL2 and the third output terminal CTRL3 are non-enabling signals (such as a high level representing the non-enabling signal), both the third PMOS transistor PM3 and the fourth PMOS transistor PM4 are turned off, and the external power supply provided by the external power supply terminal PMUVCC cannot be supplied to the system power output terminal SIMVCC.

[0076] When the system power output terminal SIMVCC needs to select an external power supply of 3.3V to supply power to the general integrated chip card, under the control of the first input terminal EN1 and the second input terminal EN2 of the logic control module 20, when the first logic signal output by the first output terminal CTRL1 is a non-enable signal (such as a high level representing a non-enable signal), the high-level signal output by the first output terminal CTRL1 passes through the internal inverter INV0 and then outputs a low level. The gate of the first PMOS transistor PM1, that is, the voltage of the V1 node, is at a low level, and the first PMOS transistor PM1 is turned on. Since the gate of the second PMOS transistor PM2 is connected to the second pole of the first PMOS transistor PM1 and the first PMOS transistor PM1 is turned on, the voltage of the gate of the second PMOS transistor PM2, that is, the voltage of the V2 node, is equal to the voltage of the voltage output terminal VO1. Since the external power supply provided by the external power supply terminal PMUVCC is 3.3V at this time, the voltage of the voltage output terminal VO1 of the voltage module 10 is equal to the external power supply provided by the external power supply terminal PMUVCC, which is 3.3V. And the first pole of the second PMOS transistor PM2 is connected to the internal power supply terminal VDDNV. Therefore, the voltage of the gate of the second PMOS transistor PM2, that is, the voltage of the V2 node, is 3.3V at this time, which is greater than the internal power supply voltage of 1.8V provided by the internal power supply terminal VDDNV of the first pole of the second PMOS transistor PM2. So the second PMOS transistor PM2 is turned off at this time, and the internal power supply provided by the internal power supply terminal VDDNV cannot be supplied to the system power output terminal SIMVCC. At this time, under the control of the first input terminal EN1 and the second input terminal EN2 of the logic control module 20, when the second logic signals output by the second output terminal CTRL2 and the third output terminal CTRL3 are enable signals (such as a low level representing an enable signal), the third PMOS transistor PM3 and the fourth PMOS transistor PM4 are both turned on, and the external power supply provided by the external power supply terminal PMUVCC is supplied to the system power output terminal SIMVCC, and the power supply voltage of the system power output terminal SIMVCC is equal to the external power supply voltage of 3.3V provided by the external power supply terminal PMUVCC.

[0077] If the logic control module 20 does not include the first delay unit 201 and the second delay unit 202 (such as Figure 1As shown in the figure, when the logic control module 20 completes the process of switching the power supply voltage of the system power supply output SIMVCC from the internal power supply voltage of 1.8V provided by the internal power supply terminal VDDNV to the external power supply voltage of 3.3V provided by the external power supply terminal PMUVCC, the high-level signal output by the first output terminal CTRL1 outputs a low level after passing through the internal inverter INV0. The first PMOS transistor PM1 conducts, generating an instantaneous current that causes a voltage drop at the voltage output terminal VO1. At the same time, the third PMOS transistor PM3 and the fourth PMOS transistor PM4 also conduct, and the generated instantaneous current will further reduce the voltage of the external power supply terminal PMUVCC, and then slowly rise. However, during this slow rise process, the first PMOS transistor PM1 conducts, and the voltage of the V2 node at the gate of the second PMOS transistor PM2 is equal to the voltage of the voltage output terminal VO1, and the voltage of the voltage output terminal VO1 has a voltage drop, resulting in the voltage of the V2 node at the gate of the second PMOS transistor PM2 being equal to the voltage of the voltage output terminal VO1 and being lower than the internal power supply voltage of 1.8V provided by the internal power supply terminal VDDNV, that is, the voltage of the voltage output terminal VO1 will have a level lower than 1.8V due to the voltage drop. Therefore, PM2 cannot be immediately turned off. Then, the voltage of the voltage output terminal VO1 slowly rises to 3.3V. When the voltage of the voltage output terminal VO1 rises to be greater than 1.8V, the second PMOS transistor PM2 can be completely turned off. Therefore, when the logic control module 20 completes the process of switching the power supply voltage of the system power supply output SIMVCC from the internal power supply voltage of 1.8V provided by the internal power supply terminal VDDNV to the external power supply voltage of 3.3V provided by the external power supply terminal PMUVCC, the second PMOS transistor PM2 cannot be immediately turned off, resulting in a large current generated by the voltage of the external power supply terminal PMUVCC flowing back into the internal power supply module 30 in reverse, generating a pulsed large current with a pulse width of about 50ns and a peak value of 700mA in the loop. The current flows from the external power supply terminal PMUVCC through the third PMOS transistor PM3 and the fourth PMOS transistor PM4 and into the second pole of the second PMOS transistor PM2 of the internal power supply module 30, posing a relatively large risk.

[0078] It should be noted that in this embodiment, if the logic control module 20 does not include the first delay unit 201 and the second delay unit 202, when the power supply voltage of the system power supply output terminal SIMVCC is switched from the internal power supply voltage of 1.8V provided by the internal power supply terminal VDDNV to the external power supply voltage of 3.3V provided by the external power supply terminal PMUVCC, the reason why the second PMOS transistor PM2 cannot be immediately turned off is that when the power supply voltage of the system power supply output terminal SIMVCC selects the external power supply, the logic control module 20 controls the third PMOS transistor PM3 and the fourth PMOS transistor of the external power supply switch module 40 to conduct. At the moment of conduction, due to the existence of the path load, a voltage drop will occur at the external power supply terminal PMUVCC. At the same time, because other circuits that may be included in the voltage module 10 (such as the external power supply detection unit 102 mentioned in the subsequent embodiment) will also start to work when the external power supply terminal PMUVCC is powered on, there is also a large load connected to the external power supply terminal PMUVCC at the moment of starting to work, and the first PMOS transistor PM1 of the internal power supply module 30 is also conducting, resulting in a greater voltage drop at the voltage output terminal VO1. The output voltage of the voltage output terminal VO1 will be lower than the level of the external power supply terminal PMUVCC. Through simulation, it is found that the output voltage of the voltage output terminal VO1 due to the voltage drop has dropped to 1V (less than 1.8V) here, and then slowly rises to 3.3V provided by the external power supply terminal PMUVCC. Therefore, at the moment of power supply switching, the gate potential of the V2 node, that is, the second PMOS transistor PM2, is equal to the output voltage of the voltage output terminal VO1, but less than 1.8V, that is, the gate potential of the second PMOS transistor PM2 is less than the second pole potential of the second PMOS transistor PM2, resulting in the second PMOS transistor PM2 not being able to be immediately turned off. It is necessary to wait until the output voltage of the voltage output terminal VO1 slowly rises above 1.8V before the second PMOS transistor PM2 can be completely turned off.

[0079] Therefore, as Figure 5As shown in the figure, in this embodiment, the logic control module 20 is further provided with a first delay unit 201 and a second delay unit 202. The second delay unit 202 delays and outputs the first logic signal of the first output terminal CTRL1, and the first delay unit 201 delays and outputs the second logic signals of the second output terminal CTRL2 and the third output terminal CTRL3. After ensuring that the second PMOS transistor PM2 of the internal power supply module 30 has been completely turned off for a sufficient duration, the third PMOS transistor PM3 and the fourth PMOS transistor PM4 of the external power supply switch module 40 are turned on. The first logic signal of the first output terminal CTRL1 is first set to a high level to ensure that the gate voltage of the second PMOS transistor PM2, that is, the voltage of the V2 node, is equal to the voltage of the voltage output terminal VO1 and is also equal to the 3.3V of the external power supply terminal PMUVCC. The gate voltage of the second PMOS transistor PM2 is completely greater than the internal power supply voltage of 1.8V provided by the internal power supply terminal VDDNV of the first pole of the second PMOS transistor PM2. After the second PMOS transistor PM2 is completely turned off, the difference between the first time period t1 and the second time period t2 is about 800ns, that is, after a delay of 800ns, the second logic signals of the second output terminal CTRL2 and the third output terminal CTRL3 are set to a low level, so that the external power supply terminal PMUVCC flows through the third PMOS transistor PM3 and the fourth PMOS transistor PM4 and is transmitted to the system power output terminal SIMVCC. This can avoid a large voltage drop in the power supply voltage due to simultaneous current draw and further avoid the occurrence of transient large current backflow caused by conduction, eliminate the risks existing in the original circuit, and is beneficial to improving product stability.

[0080] Optionally, as Figure 6 shown, Figure 6 is another structural schematic diagram of the power supply system for a general integrated chip card provided by the embodiment of the present disclosure. The internal power supply module 30 of this embodiment further includes a current limiting circuit unit 301, and the current limiting circuit unit 301 is connected between the gate of the second PMOS transistor and the second pole of the second PMOS transistor. The current limiting circuit unit 301 can prevent the internal power supply module 30 from burning out the circuit due to various factors by passing a large forward current. It is a redundant protection circuit, but its current limiting ability is limited and it cannot limit a large transient current. Therefore, in this embodiment, the logic control module 20 is further provided with a first delay unit 201 and a second delay unit 202 to eliminate the risks caused by transient large currents to the circuit and further improve product stability.

[0081] It can be understood that the current limiting circuit unit 301 included in the internal power supply module 30 of this embodiment can also be controlled by the logic signal output by the logic control module 20. The specific circuit structure of the current limiting circuit unit 301 is not limited in this embodiment, and it only needs to meet the requirement of being able to limit a large forward current passing through the internal power supply module 30. During specific implementation, it can be set according to the structure of the current limiting circuit in related technologies.

[0082] In some alternative embodiments, please refer to Figure 6 、 Figures 7 - 9 , Figure 7 is Figure 6 a schematic circuit diagram of a logic control module in Figure 8 is Figure 7 a schematic circuit diagram of a first delay unit in Figure 9 is Figure 7 a schematic circuit diagram of a second delay unit in. In the power supply system 000 provided in this embodiment, the logic control module 20 further includes a first inverter INV1, an AND gate AND1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, a seventh inverter INV7, and an eighth inverter INV8;

[0083] The input end of the first inverter INV1 is connected to the first input end EN1, and the input end of the fifth inverter INV5 is connected to the second input end EN2;

[0084] The output end of the first inverter INV1 is connected to one input end of the AND gate AND1, and the output end of the fifth inverter INV5 is connected to the other input end of the AND gate AND1;

[0085] The output end of the AND gate AND1 is connected to the input end of the second inverter INV2, the output end of the second inverter INV is connected to the input end of the second delay unit 202, the output end of the second delay unit 202 is connected to the input end of the third inverter INV3, the output end of the third inverter INV3 is connected to the input end of the fourth inverter INV4, and the output end of the fourth inverter INV4 is connected to the first output end CTRL1;

[0086] The output end of the fifth inverter INV5 is further connected to the input end of the first delay unit 201, the output end of the first delay unit 201 is connected to the input end of the sixth inverter INV6, the output end of the sixth inverter INV6 is respectively connected to the input ends of the seventh inverter INV7 and the eighth inverter INV8, the output end of the seventh inverter INV7 is connected to the second output end CTRL2, and the output end of the eighth inverter INV8 is connected to the third output end CTRL3.

[0087] Optionally, as Figure 8As shown, the first delay unit 201 includes a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a seventh PMOS transistor PM7, an eighth PMOS transistor PM8, a ninth PMOS transistor PM9, a first NMOS transistor NM1, a second NMOS transistor NM2, and a ninth inverter INV9;

[0088] The gates of the fifth PMOS transistor PM5, the sixth PMOS transistor PM6, the seventh PMOS transistor PM7, the eighth PMOS transistor PM8, and the gate of the first NMOS transistor NM1 are all connected to the output terminal of the fifth inverter INV5;

[0089] The first pole of the fifth PMOS transistor PM5 is connected to the first pole of the ninth PMOS transistor PM9, the second pole of the fifth PMOS transistor PM5 is connected to the first pole of the sixth PMOS transistor PM6, the second pole of the sixth PMOS transistor PM6 is connected to the first pole of the seventh PMOS transistor PM7, the second pole of the seventh PMOS transistor PM7 is connected to the first pole of the eighth PMOS transistor PM8, and the second pole of the eighth PMOS transistor PM8 is respectively connected to the first pole of the first NMOS transistor NM1, the gate of the second NMOS transistor NM2, the input terminal of the ninth inverter INV9, and the second pole of the ninth PMOS transistor PM9;

[0090] The second pole of the first NMOS transistor NM1 is respectively connected to the first pole and the second pole of the second NMOS transistor NM2;

[0091] The gate of the ninth PMOS transistor PM9 and the output terminal of the ninth inverter INV9 are both connected to the input terminal of the sixth inverter INV6.

[0092] Optionally, as Figure 9 As shown, the second delay unit 202 includes a tenth PMOS transistor PM10, an eleventh PMOS transistor PM11, a twelfth PMOS transistor PM12, a thirteenth PMOS transistor PM13, a fourteenth PMOS transistor PM14, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a tenth inverter INV10, an eleventh inverter INV11, and a twelfth inverter INV12;

[0093] The input terminal of the tenth inverter INV10 is connected to the output terminal of the second inverter INV2;

[0094] The gates of the tenth PMOS transistor PM10, the eleventh PMOS transistor PM11, the twelfth PMOS transistor PM12, the thirteenth PMOS transistor PM13, and the gate of the third NMOS transistor NM3 are all connected to the output terminal of the tenth inverter INV10;

[0095] The first pole of the tenth PMOS transistor PM10 is connected to the first pole of the fourteenth PMOS transistor PM14. The second pole of the tenth PMOS transistor PM10 is connected to the first pole of the eleventh PMOS transistor PM11. The second pole of the eleventh PMOS transistor PM11 is connected to the first pole of the twelfth PMOS transistor PM12. The second pole of the twelfth PMOS transistor PM12 is connected to the first pole of the thirteenth PMOS transistor PM13. The second pole of the thirteenth PMOS transistor PM13 is respectively connected to the first pole of the third NMOS transistor NM3, the gate of the fourth NMOS transistor NM4, the input terminal of the eleventh inverter INV11, and the second pole of the fourteenth PMOS transistor PM14;

[0096] The second pole of the third NMOS transistor NM3 is respectively connected to the first pole and the second pole of the fourth NMOS transistor NM4;

[0097] The gate of the fourteenth PMOS transistor PM14 and the output terminal of the eleventh inverter INV11 are both connected to the input terminal of the twelfth inverter INV12. The output terminal of the twelfth inverter INV12 is connected to the input terminal of the third inverter INV3.

[0098] This embodiment explains a specific circuit connection structure that the logic control module 20 can set. When the logic control module 20 controls the conduction and cutoff of the internal power supply module 30 and the external power supply switch module 40, assume that the power supply voltage at the system power supply output terminal SIMVCC needs to be switched from the internal power supply voltage of 1.8V provided by the internal power supply terminal VDDNV to the external power supply voltage of 3.3V provided by the external power supply terminal PMUVCC. To clearly explain the working principle of the logic control module 20 in this embodiment, in the subsequent embodiment part, the low level is defined as 0 and the high level is defined as 1 for explanation.

[0099] At this time, the logic control module 20 controls the internal power supply module 30 to be cutoff and the external power supply switch module 40 to be conducted. Specifically, the first input terminal EN1 is set to 0, which is inverted to 1 by the first inverter INV1. The second input terminal EN2 provides a square wave signal. If the second input terminal EN2 first has a falling edge of 0 and then a rising edge of 1, after being inverted by the fifth inverter INV5, it first has a rising edge of 1 and then a falling edge of 0. Then, one input terminal of the AND gate AND1 is 1, and the other input terminal first has a rising edge of 1 and then a falling edge of 0. After being inverted by the second inverter INV2, the output is first a falling edge of 0 and then a rising edge of 1. Then, after passing through the second delay unit 202, the rising edge of 1 is delayed by the second time period t2 (such as 1 μs) and then output (the second delay unit 202 can be understood as a rising edge delay unit). During the second time period t2, the falling edge of 0 is still output. The waveform output from the output terminal of the second delay unit 202 is as Figure 7As shown, after two inversions by the third inverter INV3 and the fourth inverter INV4, the waveform of the first output terminal CTRL1, which first has a falling edge of 0 and then a rising edge of 1, is output. That is, the first output terminal CTRL1 outputs a high level of 1, the first PMOS transistor PM1 of the internal power supply module 30 conducts, and the second PMOS transistor PM2 is cut off. At the same time, after being inverted by the fifth inverter INV5 into a waveform that first has a rising edge of 1 and then a falling edge of 0, and after passing through the first delay unit 201, the first delay unit 201 delays the falling edge of 0 for the first time period t1 (such as 1.8 μs) and then outputs it (the first delay unit 201 can be understood as a falling edge delay unit). During the first time period t1, a rising edge of 1 is still output. The waveform output from the output terminal of the first delay unit 201 is as Figure 7 As shown, after two inversions by the sixth inverter INV6 and the seventh inverter INV7, the waveform of the second output terminal CTRL2, which first has a rising edge of 1 and then a falling edge of 0, is output. After two inversions by the sixth inverter INV6 and the eighth inverter INV8, the waveform of the third output terminal CTRL3, which first has a rising edge of 1 and then a falling edge of 0, is output. That is, the second output terminal CTRL2 outputs a low level of 0, and the third output terminal CTRL3 outputs a low level of 0. The third PMOS transistor PM3 and the fourth PMOS transistor PM4 of the externally supplied power switch module 40 are both conducting. Since the first delay unit 201 delays the falling edge signals of the second output terminal CTRL2 and the third output terminal CTRL3, that is, the low level signals that control the conduction of the third PMOS transistor PM3 and the fourth PMOS transistor PM4, for the first time period t1 (such as 1.8 μs) and then outputs them, that is, after delaying the first time period t1 (such as 1.8 μs), a falling edge of 0 is output. During the first time period t1, a falling edge of 0 is still output. After the internal power supply module 30 is completely turned off and completely turned off for 0.8 μs (t1 - t2 = 800 ns), the low level falling edge signal that controls the conduction of the third PMOS transistor PM3 and the fourth PMOS transistor PM4 is output, delaying the control of the externally supplied power switch module 40 to conduct. At this time, the 3.3V provided by the externally supplied power supply terminal PMUVCC is connected to the system power supply output terminal SIMVCC, which can avoid generating a transient large current when the externally supplied power switch module 40 has already conducted while the internal power supply module 30 has not been completely turned off, which is beneficial to improving the product stability and reducing risks.

[0100] This embodiment further explains an optional circuit connection structure of the first delay unit 201 and the second delay unit 202, such as Figure 8 and Figure 9As shown, the first delay unit 201 and the second delay unit 202 can both be RC delay circuits. In the delay circuit, MOS transistors are used as resistors and capacitors. The output slew rate of the inverter is reduced through RC delay, and the flip time of the inverter is extended. Optionally, several buffers (not shown in the figure) can also be set before the first output terminal CTRL1, the second output terminal CTRL2, and the third output terminal CTRL3 to form a delay function for the signal, thereby completing the elimination of the impact and risk of the transient large current generated during power supply switching on the entire circuit structure.

[0101] It can be understood that for the first delay unit 201 and the second delay unit 202 in this embodiment, MOS transistors are preferably selected as resistors and capacitors, which can save the layout area by using MOS transistors as capacitors. Using MOS transistors as resistors can flexibly adjust the resistance value by adjusting the gate voltage, which is beneficial to the flexible setting of the delay time of the first delay unit 201 and the second delay unit 202.

[0102] It can be understood that since the first delay unit 201 in this embodiment can be understood as a falling-edge delay unit and the second delay unit 202 can be understood as a rising-edge delay unit, there is a slight difference in the main part of the circuit structure of the second delay unit 202 compared with that of the first delay unit 201, that is, the second delay unit 202 has one more tenth inverter and twelfth inverter than the first delay unit 201 to change the rising edge of the delay instead of the falling edge delayed by the first delay unit 201.

[0103] It can be understood that the delay time of the first delay unit 201 and the second delay unit 202 in this embodiment can be determined by the RC constant in the RC delay circuit. The size and number of MOS transistors used as resistors and capacitors can determine the resistance value and capacitance value, thereby setting the length of the delay time.

[0104] In this embodiment, taking the first delay unit 201 as an example, the working principle of its delay can be understood as follows. The first delay unit 201 is a falling-edge delay unit. Falling-edge delay means the delay when the voltage signal changes from 1 to 0. At this time, the NMOS transistor is turned off and the PMOS transistor is turned on. For the inverter circuit, only one PMOS transistor is required. The fifth PMOS transistor PM5, the sixth PMOS transistor PM6, the seventh PMOS transistor PM7, and the eighth PMOS transistor PM8 are the resistors R in the RC delay circuit. By increasing the number of PMOS transistors in series, the length of the entire PMOS transistor is increased. The larger the length of the entire PMOS transistor, the larger the resistance value of the entire PMOS transistor. And the second NMOS transistor NM2 is the capacitor C in the RC delay circuit, and its capacitance value is increased by increasing its size. In the RC delay circuit, the larger the values of the resistor R and the capacitor C, the longer it takes for the power supply voltage to charge the capacitor. The input node voltage value of the ninth inverter INV9 is a signal of a slow charging process. The function of the ninth inverter INV9 is to ensure that the polarity of the output signal is the same as the input while reversing the input node voltage of the ninth inverter INV9 to restore a faster falling edge. The working principle of the second delay unit 202 is the same. An additional tenth inverter is added after the input of the second delay unit 202 to convert the input rising edge into a falling edge before starting the delay. An additional twelfth inverter is added before the output of the second delay unit 202 to ensure that the polarity of the output is the same as the input polarity.

[0105] It can be understood that the setting positions of the first delay unit 201 and the second delay unit 202 in the logic control module 20 in this embodiment can be Figure 7The schematic first delay unit 201 is arranged between the fifth inverter INV5 and the sixth inverter INV6, and the second delay unit 202 is arranged between the second inverter INV2 and the third inverter INV3. Or in some other alternative embodiments, the arrangement positions of the first delay unit 201 and the second delay unit 202 in the logic control module 20 can also be shifted backward together to behind the sixth inverter INV6 and the third inverter INV3, that is, the first delay unit 201 is arranged between the sixth inverter INV6 and the seventh inverter INV7, and the second delay unit 202 is arranged between the third inverter INV3 and the fourth inverter INV4 (not shown in the figure). Due to the presence of inverter structures in the logic control module, when setting the first delay unit 201 and the second delay unit 202, a delay unit needs to be added at the same position of the two paths, namely the first logic signal output path and the second logic signal output path, without changing the original logic path. Therefore, although the arrangement positions of the first delay unit 201 and the second delay unit 202 in the logic control module 20 can also be shifted backward together to behind the sixth inverter INV6 and the third inverter INV3, it should be noted whether the signal is a rising-edge delay or a falling-edge delay. At this time, the internal circuits of the first delay unit 201 and the second delay unit 202 are slightly different from Figure 8 and Figure 9 If the first delay unit 201 is moved from in front of the sixth inverter INV6, which is arranged at Figure 7 , to behind the sixth inverter INV6, then it is necessary to design the first delay unit 201 to be modified from a falling-edge delay unit to a rising-edge delay unit. Similarly, if the second delay unit 202 is moved from in front of the third inverter INV3, which is arranged at Figure 7 , to behind the third inverter INV3, then it is necessary to design the second delay unit 202 to be modified from a rising-edge delay unit to a falling-edge delay unit. This embodiment will not elaborate on this, and specific settings can be made according to the actual circuit requirements.

[0106] In some alternative embodiments, please refer to Figures 6 - 9 and Figure 10 . Figure 10 is Figure 6 a schematic circuit structure diagram of the voltage module in

[0107] In this embodiment, the voltage module 10 includes a selection and switching unit 101 and an external power supply detection unit 102;

[0108] One input terminal of the selection and switching unit 101 is connected to the external power supply terminal PMUVCC, another input terminal of the selection and switching unit 101 is connected to the internal power supply terminal VDDNV, and the output terminal of the selection and switching unit 101 is connected to the voltage output terminal VO1;

[0108] The external power supply detection unit 102 is connected to the external power supply terminal PMUVCC.

[0109] In this embodiment, it is explained that the voltage module 10 for managing power supply and providing a stable operating voltage for a general integrated chip card may include an external power supply terminal PMUVCC, an internal power supply terminal VDDNV, and a voltage output terminal VO1. The external power supply terminal PMUVCC is used to input an external power supply, and the external power supply voltage is 1.8V or 3.3V. The internal power supply terminal VDDNV is used to provide an internal power supply, and the internal power supply voltage is 1.8V. The voltage module 10 may further include a selection and switching unit 101 and an external power supply detection unit 102.

[0110] When the system power supply output terminal SIMVCC selects the internal power supply to supply power to the general integrated chip card, the selection and switching unit 101 selects the internal power supply provided by the internal power supply terminal VDDNV and outputs it to the voltage output terminal VO1; when the system power supply output terminal SIMVCC selects the external power supply to supply power to the general integrated chip card, the selection and switching unit 101 selects the external power supply provided by the external power supply terminal PMUVCC and outputs it to the voltage output terminal VO1. Since the external power supply terminal PMUVCC provides an external power supply, the voltage module 10 may further be provided with an external power supply detection unit 102 to constantly detect the level signal of the external power supply terminal PMUVCC to ensure that the system power supply output terminal SIMVCC obtains the voltage value of the required external power supply.

[0111] In some alternative embodiments, please refer to Figure 11 , Figure 11 FIG. is a schematic structural block diagram of a terminal device provided by an embodiment of the present disclosure. An embodiment of the present disclosure provides a terminal device 111, which may include the power supply system 000 for a general integrated chip card in any of the foregoing embodiments. The terminal device 111 in this embodiment may be a portable or mobile computing device such as a mobile phone, a tablet computer, a laptop computer, a desktop computer, a gaming device, an in-vehicle electronic device, or a wearable intelligent device, as well as other electronic devices such as an electronic database, an automobile, and a bank automated teller machine. The wearable intelligent device includes devices with complete functions and large sizes that can implement complete or partial functions without relying on a smart phone, such as a smart watch or smart glasses, etc., and also includes devices that only focus on a certain type of application function and need to cooperate with other devices such as a smart phone, such as various smart bracelets and smart jewelry for physical sign monitoring. The terminal device 111 provided by the embodiment of the present disclosure has the beneficial effects of the power supply system 000 for a general integrated chip card provided by the embodiment of the present disclosure. For specific descriptions of the power supply system 000, reference may be made to the foregoing embodiments, and details are not repeated herein.

[0112] It should be noted that in this text, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the said element.

[0113] The above are only specific embodiments of the present disclosure, enabling those skilled in the art to understand or implement the present disclosure. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to these embodiments described herein, but rather will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A power supply system for a general integrated chip card, characterized in that, It includes a voltage module, a logic control module, an internal power supply module, an external power supply switch module, and a system power supply output terminal; The voltage module includes an external power supply power supply terminal, an internal power supply power supply terminal, and a voltage output terminal; The logic control module includes a first input terminal, a second input terminal, a first output terminal, a second output terminal, and a third output terminal; the logic control module is configured to: under the control of the first input terminal and the second input terminal, the first output terminal outputs a first logic signal, and the second output terminal and the third output terminal output a second logic signal; wherein, the first logic signal and the second logic signal are inverted; The internal power supply module is configured to: under the control of the first output terminal, the voltage output terminal, and the internal power supply power supply terminal, supply the internal power supply provided by the internal power supply power supply terminal to the system power supply output terminal; The external power supply switch module is configured to: under the control of the second output terminal, the third output terminal, and the external power supply power supply terminal, supply the external power supply provided by the external power supply power supply terminal to the system power supply output terminal; The logic control module further includes a first delay unit and a second delay unit; The first delay unit is configured to: under the control of the first input terminal and the second input terminal, delay the second logic signal by a first time period and then output it; The second delay unit is configured to: under the control of the first input terminal and the second input terminal, delay the first logic signal by a second time period and then output it; wherein, the first time period is greater than the second time period.

2. The power supply system for a general integrated chip card according to claim 1, wherein The difference between the first time period and the second time period is 800 ns.

3. The power supply system for a general integrated chip card according to claim 1, characterized in that, The internal power supply module includes a first PMOS transistor, a second PMOS transistor, and an internal inverter; The input terminal of the internal inverter is connected to the first output terminal, the output terminal of the internal inverter is connected to the gate of the first PMOS transistor, the first pole of the first PMOS transistor is connected to the voltage output terminal, the second pole of the first PMOS transistor is connected to the gate of the second PMOS transistor, the first pole of the second PMOS transistor is connected to the internal power supply power supply terminal, and the second pole of the second PMOS transistor is connected to the system power supply output terminal.

4. The power supply system for a general integrated chip card according to claim 3, wherein A current limiting circuit unit is further included between the gate and the second pole of the second PMOS transistor.

5. The power supply system for a general integrated chip card according to claim 3, characterized in that, The external power supply switch module includes a third PMOS transistor and a fourth PMOS transistor; The gate of the third PMOS transistor is connected to the second output terminal, the gate of the fourth PMOS transistor is connected to the third output terminal, the first poles of the third PMOS transistor and the fourth PMOS transistor are both connected to the external power supply power supply terminal, and the second poles of the third PMOS transistor and the fourth PMOS transistor are both connected to the system power supply output terminal.

6. The power supply system for a general integrated chip card according to claim 1, characterized in that, The logic control module further includes a first inverter, an AND gate, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, and an eighth inverter; The input terminal of the first inverter is connected to the first input terminal, and the input terminal of the fifth inverter is connected to the second input terminal; The output terminal of the first inverter is connected to one input terminal of the AND gate, and the output terminal of the fifth inverter is connected to the other input terminal of the AND gate; The output terminal of the AND gate is connected to the input terminal of the second inverter, the output terminal of the second inverter is connected to the input terminal of the second delay unit, the output terminal of the second delay unit is connected to the input terminal of the third inverter, the output terminal of the third inverter is connected to the input terminal of the fourth inverter, and the output terminal of the fourth inverter is connected to the first output terminal; The output terminal of the fifth inverter is further connected to the input terminal of the first delay unit, the output terminal of the first delay unit is connected to the input terminal of the sixth inverter, the output terminal of the sixth inverter is respectively connected to the input terminals of the seventh inverter and the eighth inverter, the output terminal of the seventh inverter is connected to the second output terminal, and the output terminal of the eighth inverter is connected to the third output terminal.

7. The power supply system for a general integrated chip card according to claim 6, characterized in that, The first delay unit includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a ninth inverter; The gates of the fifth PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, and the gate of the first NMOS transistor are all connected to the output terminal of the fifth inverter; The first pole of the fifth PMOS transistor is connected to the first pole of the ninth PMOS transistor, the second pole of the fifth PMOS transistor is connected to the first pole of the sixth PMOS transistor, the second pole of the sixth PMOS transistor is connected to the first pole of the seventh PMOS transistor, the second pole of the seventh PMOS transistor is connected to the first pole of the eighth PMOS transistor, and the second pole of the eighth PMOS transistor is respectively connected to the first pole of the first NMOS transistor, the gate of the second NMOS transistor, the input terminal of the ninth inverter, and the second pole of the ninth PMOS transistor; The second pole of the first NMOS transistor is respectively connected to the first pole and the second pole of the second NMOS transistor; The gate of the ninth PMOS transistor and the output terminal of the ninth inverter are both connected to the input terminal of the sixth inverter.

8. The power supply system for a general integrated chip card according to claim 7, characterized in that, The second delay unit includes a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a tenth inverter, an eleventh inverter, and a twelfth inverter; The input terminal of the tenth inverter is connected to the output terminal of the second inverter; The gates of the tenth PMOS transistor, the eleventh PMOS transistor, the twelfth PMOS transistor, the thirteenth PMOS transistor, and the gate of the third NMOS transistor are all connected to the output terminal of the tenth inverter; The first pole of the tenth PMOS transistor is connected to the first pole of the fourteenth PMOS transistor, the second pole of the tenth PMOS transistor is connected to the first pole of the eleventh PMOS transistor, the second pole of the eleventh PMOS transistor is connected to the first pole of the twelfth PMOS transistor, the second pole of the twelfth PMOS transistor is connected to the first pole of the thirteenth PMOS transistor, and the second pole of the thirteenth PMOS transistor is respectively connected to the first pole of the third NMOS transistor, the gate of the fourth NMOS transistor, the input terminal of the eleventh inverter, and the second pole of the fourteenth PMOS transistor; The second pole of the third NMOS transistor is respectively connected to the first pole and the second pole of the fourth NMOS transistor; The gate of the fourteenth PMOS transistor and the output terminal of the eleventh inverter are both connected to the input terminal of the twelfth inverter, and the output terminal of the twelfth inverter is connected to the input terminal of the third inverter.

9. The power supply system for a general integrated chip card according to claim 1, characterized in that, The voltage module includes a selection and switching unit and an external power supply detection unit; One input terminal of the selection and switching unit is connected to the external power supply terminal, another input terminal of the selection and switching unit is connected to the internal power supply terminal, and the output terminal of the selection and switching unit is connected to the voltage output terminal; The external power supply detection unit is connected to the external power supply terminal.

10. A terminal device, characterized in that, It includes the power supply system for a general integrated chip card according to any one of claims 1-9.

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