ESD protection circuit and power device circuit device

Abstract

The invention relates to an ESD protection circuit and a power device circuit device. The ESD protection circuit comprises a first clamping diode string, a second clamping diode string, a third clamping diode string and an ESD discharge device. Wherein the first clamping diode string and the third clamping diode string are connected between a grid electrode and a source electrode of the GaN power device in a series connection mode with opposite polarities, and an anode of the second clamping diode string is respectively connected with a cathode of the first clamping diode string and a cathode of the third clamping diode string. The cathode of the second clamping diode string is connected with the grid electrode of the ESD discharge device. Through a back-to-back diode string structure with opposite polarities, electric leakage of the protection device at the grid electrode and the source electrode under a non-ESD event can be suppressed, a positive / reverse ESD trigger threshold value is independently controlled through a voltage division path, and the compatibility of the ESD protection circuit with negative voltage turn-off and grid electrode negative voltage test is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular, to an electrostatic discharge (ESD) protection circuit and a power device circuit device. Background Art

[0002] Wide bandgap semiconductor (such as GaN, SiC, etc.) power devices have become a research hotspot in the field of power electronics due to their advantages such as high breakdown electric field and high electron mobility. Among them, lateral GaN power devices are mainly based on the AlGaN / GaN heterojunction structure and can be divided into the following according to the threshold voltage: Enhancement type (normally off type, Vth>0): A special gate structure (such as a P-GaN gate) is required to deplete the 2DEG to achieve the normally off characteristic, but there is a problem of weak ESD protection ability (due to small junction capacitance and low breakdown voltage). Depletion type (normally on type, Vth<0): It has the advantages of high gate voltage swing and high reliability, but negative voltage is required for turn-off, which increases the driving complexity.

[0003] Currently, the ESD protection ability of enhancement type devices is insufficient, while depletion type devices rely on negative voltage turn-off, resulting in the difficulty for existing ESD protection schemes to be compatible with both working modes. In addition, the compatibility between the gate negative voltage test (used to detect gate defects) and the ESD protection circuit also faces challenges. There is an urgent need for a general ESD protection scheme that can adapt to the negative voltage test of enhancement type devices and support the negative voltage turn-off requirement of depletion type devices. Summary of the Invention

[0004] In order to avoid, as much as possible, the problem that the ESD protection circuit in the related art is incompatible with the application scenario of negative voltage turn-off and the gate negative voltage test for detecting gate-related defects. The present application provides an ESD protection circuit and a power device circuit device.

[0005] On the one hand, an ESD protection circuit is provided, and the following technical solution is adopted: An ESD protection circuit for connecting with a GaN power device, the ESD protection circuit includes: A first clamping diode string, a second clamping diode string, a third clamping diode string, and an ESD discharge device, wherein the first clamping diode string and the third clamping diode string are connected between the gate and the source of the GaN power device in a series connection with opposite polarities, the anode of the second clamping diode string is respectively connected to the cathode of the first clamping diode string and the cathode of the third clamping diode string, and the cathode of the second clamping diode string is connected to the gate of the ESD discharge device.

[0006] With the above technical solution, by using a back-to-back diode string structure with opposite polarities, the leakage between the gate and the source is suppressed during non-ESD events, and the positive / negative ESD trigger thresholds are independently controlled through a voltage division path, improving the compatibility with negative voltage turn-off and gate negative voltage testing.

[0007] Optionally, the first clamping diode string and the third clamping diode string are connected between the gate and the source of the GaN power device in a series connection with opposite polarities. This connection method includes: The anode of the first clamping diode string is used to connect to the gate of the GaN power device and the drain of the ESD discharge device respectively. The cathode of the first clamping diode string is connected to the anode of the second clamping diode string and the cathode of the third clamping diode string respectively. The anode of the third clamping diode string is used to connect to the source of the GaN power device and the source of the ESD discharge device respectively.

[0008] With the above technical solution, a bidirectional blocking structure is formed by a diode string with reverse polarities in series. During non-ESD events (such as negative voltage turn-off or forward bias operation), the leakage path between the gate and the source is completely isolated, and at the same time, a low-impedance discharge path is provided for ESD events.

[0009] Optionally, the ESD discharge device is a low-voltage enhancement-mode transistor, which has a gate, a source, and a drain. The gate of the ESD discharge device is connected to the cathode of the second clamping diode string. The source of the ESD discharge device is used to connect to the source of the GaN power device. The drain of the ESD discharge device is used to connect to the gate of the GaN power device. Here, the term "low voltage" refers to a low voltage relative to the ESD voltage on the gate of the GaN power device. An ESD event may generate a transient high voltage of several thousand volts or even higher. Here, "low voltage" means that the ESD discharge transistor should be able to conduct under conditions far lower than this voltage value, so as to discharge the static charge in time.

[0010] With the above technical solution, using a low-voltage enhancement-mode device as the ESD discharge device means that it can conduct at a lower gate voltage, so that it can quickly respond and provide a discharge path at the initial stage of an ESD event, and timely guide the static charge accumulated on the gate to the source, avoiding damage to the gate of the protected GaN power device caused by high voltage. Optionally, the first clamping diode string and the second clamping diode string form a forward ESD trigger path to control the forward ESD starting voltage.

[0011] Optionally, the ESD discharge device is a bidirectional enhanced transistor with a gate and symmetric first and second drains. The gate of the ESD discharge device is connected to the cathode of the second clamping diode string. The first drain of the ESD discharge device is connected to the source of the GaN power device, and the second drain of the ESD discharge device is connected to the gate of the GaN power device.

[0012] With the above technical solution, the symmetric layout of the two drains reduces the parasitic inductance and capacitance differences, making the positive / negative ESD response speeds consistent and avoiding protection delay caused by asymmetric paths. And the drain symmetry also reduces the on-resistance, which can reduce the energy loss and heat accumulation in ESD events.

[0013] Optionally, a temperature-sensitive resistor network is also connected between the gate of the ESD discharge device and the cathode of the second clamping diode string.

[0014] With the above technical solution, the temperature-sensitive resistor network can automatically adjust the conduction threshold of the above ESD discharge device according to temperature changes to compensate for the influence of temperature on the trigger voltage.

[0015] Optionally, the first clamping diode string and the second clamping diode string form a forward ESD trigger path to control the forward ESD startup voltage.

[0016] With the above technical solution, through the series voltage division of the first clamping diode string and the second clamping diode string, the forward ESD trigger threshold is accurately set to ensure that the ESD discharge device conducts quickly in a forward ESD event and avoid gate damage due to overvoltage.

[0017] Optionally, the third clamping diode string and the second clamping diode string form a reverse ESD trigger path to control the reverse ESD startup voltage.

[0018] With the above technical solution, through the series voltage division of the third clamping diode string and the second clamping diode string, the reverse ESD trigger threshold is independently adjusted to make the ESD discharge device conduct quickly in a reverse ESD event and protect the gate from negative transient high-voltage impact.

[0019] Optionally, the ESD discharge device is configured to conduct when a forward ESD event or a reverse ESD event occurs to release energy.

[0020] By adopting the above technical solution, the ESD discharge device provides a low-impedance discharge path in both forward and reverse ESD events, significantly improving the absorption efficiency of ESD energy.

[0021] Optionally, the number of diode structures in the first clamping diode string, the second clamping diode string, and the third clamping diode string is adjustable.

[0022] With the above technical solution, by flexibly increasing or decreasing the number of diode structures, it is possible to adapt to the customized requirements of different processes or application scenarios for the forward / reverse ESD trigger voltage, enhancing the versatility of circuit design.

[0023] Optionally, at least one of the first clamping diode string, the second clamping diode string, and the third clamping diode string has a programmable switching element.

[0024] With the above technical solution, by using the programmable switching element, it is possible to dynamically adjust the number of series diode structures through an external control signal, thereby real-time adjusting the forward or reverse ESD trigger threshold.

[0025] Optionally, the number of diode structures in one of the first clamping diode string and the second clamping diode string is adjusted to adjust the forward ESD trigger voltage; The number of diode structures in one of the third clamping diode string and the second clamping diode string is adjusted to adjust the reverse ESD trigger voltage.

[0026] With the above technical solution, by independently adjusting the number of diode structures in the forward / reverse ESD trigger paths, it is possible to achieve fine control of the forward and reverse trigger voltages, avoiding the threshold coupling problem caused by the shared path in traditional circuits.

[0027] Optionally, the diode structures in the first clamping diode string, the second clamping diode string, and the third clamping diode string include Schottky diodes.

[0028] By adopting the above technical solution, by using the high breakdown voltage and low leakage characteristics of Schottky diodes, the reliability and anti-interference ability of the ESD protection circuit are improved.

[0029] Optionally, the diode structures in the first clamping diode string, the second clamping diode string, and the third clamping diode string include diode-connected enhancement-mode field-effect transistors.

[0030] With the above technical solution, through diode-connected enhancement-mode field-effect transistors, high compatibility with GaN processes is achieved, while reducing the impact of parasitic capacitance on the dynamic response of the circuit.

[0031] On the other hand, a power device circuit device is provided, adopting the following technical solution: A power device circuit device includes: An ESD protection circuit; and A GaN power device, connected to the ESD protection circuit; Wherein, the ESD protection circuit includes: A first clamping diode string, a second clamping diode string, and a third clamping diode string, wherein the first clamping diode string and the third clamping diode string are connected between the gate and the source of the GaN power device in a series connection with opposite polarities; and An ESD discharge device, wherein the anode of the second clamping diode string is respectively connected to the first clamping diode string and the third clamping diode string, and the cathode of the second clamping diode string is connected to the gate of the ESD discharge device.

[0032] Adopting the above technical solution, by integrating the ESD protection circuit with the GaN power device, while ensuring the normal operation of the device, a two-way ESD protection capability is provided, significantly improving the reliability and lifespan of the power system.

[0033] Optionally, the gate of the GaN power device is respectively connected to the anode of the first clamping diode string and the drain of the ESD discharge device, and the source of the GaN power device is respectively connected to the anode of the third clamping diode string and the source of the ESD discharge device.

[0034] Adopting the above technical solution, by respectively connecting the gate of the GaN power device to the anode of the first clamping diode string and the drain of the ESD discharge device, a discharge path is provided for a forward ESD event, and by respectively connecting the source of the GaN power device to the anode of the third clamping diode string and the source of the ESD discharge device, a discharge path is provided for a reverse ESD event.

[0035] Optionally, the ESD protection circuit and the GaN power device are integrated on the same chip, and the layouts of the first clamping diode string and the third clamping diode string are symmetrically arranged around the gate-source path of the GaN power device.

[0036] Adopting the above technical solution, by integrating the ESD protection circuit and the GaN power device on the same chip, and the layouts of the first clamping diode string and the third clamping diode string are symmetrically arranged around the gate-source path of the GaN device, and by shortening the key node spacing through a metal interconnection layer, the influence of parasitic capacitance on the dynamic response can be reduced.

[0037] In summary, the present application includes at least one of the following beneficial technical effects: 1. By means of a back-to-back diode string structure with opposite polarities, the leakage current path between the gate and the source is suppressed under non-ESD events, and the positive / negative ESD trigger thresholds are independently controlled through a voltage division path, enhancing the compatibility with negative voltage turn-off and gate negative voltage tests; 2. Through the series voltage division of the first clamping diode string and the second clamping diode string, the forward ESD trigger threshold is precisely set to ensure that the ESD discharge device conducts quickly during a forward ESD event, avoiding gate damage due to overvoltage; 3. Through the series voltage division of the third clamping diode string and the second clamping diode string, the reverse ESD trigger threshold is independently adjusted to enable the ESD discharge device to conduct quickly during a reverse ESD event, protecting the gate from negative transient high-voltage impacts; 4. By independently adjusting the number of diode structures in the positive / negative ESD trigger paths, fine control of the positive and reverse trigger voltages is achieved, avoiding the threshold coupling problem caused by the shared path in traditional circuits; 5. Through an enhancement-mode field-effect transistor connected by diodes, high compatibility with the GaN process is achieved, while reducing the influence of parasitic capacitance on the dynamic response of the circuit; 6. By integrating the ESD protection circuit with the GaN power device, while ensuring the normal operation of the device, bidirectional ESD protection capabilities are provided, significantly enhancing the reliability and lifespan of the power system. Description of the Drawings

[0038] Figure 1 is a circuit schematic diagram of the ESD protection circuit of a GaN power device in the related art; Figure 2 is a circuit schematic diagram of the ESD protection circuit of Embodiment 1 of the present application; Figure 3 is a circuit schematic diagram of the ESD protection circuit of Embodiment 2 of the present application; Figure 4 is a circuit schematic diagram of the ESD protection circuit of Embodiment 3 of the present application.

[0039] Description of the Reference Numerals: 110, ESD protection circuit; 111, clamping diode string; 112, resistor; 113, ESD discharge device; 120, GaN power device; 210, ESD protection circuit; 211, first clamping diode string; 212, second clamping diode string; 213, third clamping diode string; 214, ESD discharge device; 220, GaN power device. Detailed Embodiments

[0040] The following further elaborates on the present application in conjunction with the attached Figures 1 to 4 drawings.

[0041] To enhance the ESD event resistance of GaN power devices, Figure 1 An ESD protection circuit of a related-art GaN power device is shown.

[0042] As Figure 1 shown, the ESD protection circuit 110 is connected to the GaN power device 120. The ESD protection circuit 110 includes a clamping diode string 111, a resistor 112, and an ESD discharge device 113. The GaN power device 120 is a device to be protected, which has a gate (G), a drain (D), and a source (S).

[0043] The working principle of the ESD protection circuit 110 is as follows: When a positive ESD event occurs at the gate of the GaN power device 120 relative to the source, the clamping diode string 111 conducts, and the conduction current forms a positive voltage drop across the resistor 112. When the voltage of the positive voltage drop is higher than the threshold voltage of the ESD discharge device 113, the ESD discharge device 113 conducts, releasing the positive ESD energy from the gate of the GaN power device 120, so that the gate voltage of the GaN power device 120 does not exceed its positive withstand voltage; and when a negative ESD event occurs at the gate of the GaN power device 120 relative to the source, the ESD discharge device 113 conducts in the reverse direction, releasing the negative ESD energy from the gate of the GaN power device 120, so that the gate voltage of the GaN power device 120 does not exceed its negative withstand voltage.

[0044] However, the ESD protection circuit in the related art still has the following defects: (1) The ESD protection circuit 110 has a large conduction current when there is a reverse voltage bias between the gate and the source of the GaN power device 120, resulting in incompatibility between the ESD protection circuit 110 and the gate negative voltage test for detecting defects related to the gate of the GaN power device 120, making it difficult for the GaN power device 120 to have both reliability and ESD tolerance; (2) When there is a reverse voltage bias between the gate and the source of the GaN power device 120, the ESD discharge device 113 conducts in the reverse direction and enters the saturation region, and the voltage drop between the gate and the source of the GaN power device 120 is clamped by the voltage drop between the gate and the drain of the ESD discharge device 113, making the ESD protection circuit 110 unable to be compatible with application scenarios of depletion-mode GaN power devices that require negative voltage turn-off.

[0045] On the one hand, an embodiment of the present application discloses an ESD protection circuit 210 for connecting to a GaN power device 220. The ESD protection circuit 210 includes: The first clamping diode string 211, the second clamping diode string 212, the third clamping diode string 213, and the ESD discharge device 214. Among them, the first clamping diode string 211 and the third clamping diode string 213 are connected between the gate and the source of the GaN power device 220 in a series connection with opposite polarities. The anode of the second clamping diode string 212 is respectively connected to the cathode of the first clamping diode string 211 and the cathode of the third clamping diode string 213, and the cathode of the second clamping diode string 212 is connected to the gate of the ESD discharge device 214.

[0046] Embodiment 1 Refer to Figure 2 , the ESD protection circuit 210 is used to be respectively connected to the gate and the source of the GaN power device 220. The ESD protection circuit 210 includes the first clamping diode string 211, the second clamping diode string 212, the third clamping diode string 213, and the ESD discharge device 214.

[0047] The anode of the first clamping diode string 211 is respectively connected to the gate of the GaN power device 220 and the drain of the ESD discharge device 214. The cathode of the first clamping diode string 211 is respectively connected to the anode of the second clamping diode string 212 and the cathode of the third clamping diode string 213. The cathode of the second clamping diode string 212 is connected to the gate of the ESD discharge device 214. The anode of the third clamping diode string 213 is respectively connected to the source of the GaN power device 220 and the source of the ESD discharge device 214.

[0048] The gate of the ESD discharge device 214 is respectively connected to the first clamping diode string 211 and the third clamping diode string 213. The first clamping diode string 211 and the second clamping diode string 212 form a forward ESD trigger path for controlling the forward ESD startup voltage. The third clamping diode string 213 and the second clamping diode string 212 form a reverse ESD trigger path for controlling the reverse ESD startup voltage. The ESD discharge device 214 is used to conduct and release energy when a forward ESD event or a reverse ESD event occurs.

[0049] The ESD discharge device 214 can be a low-voltage enhancement device (such as a GaN high electron mobility transistor), having a gate, a source, and a drain. The gate of the ESD discharge device 214 is connected to the cathode of the second clamping diode string 212. The source of the ESD discharge device 214 is used to be connected to the source of the GaN power device, and the drain of the ESD discharge device is used to be connected to the gate of the GaN power device. Here, the term "low voltage" refers to a low voltage relative to the ESD voltage on the gate of the GaN power device. An ESD event may generate a transient high voltage of thousands of volts or even higher. The "low voltage" here means that the ESD discharge tube should be able to conduct under conditions far lower than this voltage value, so as to discharge the static charge in time. When a forward ESD event or a reverse ESD event occurs, the ESD discharge device 214 can conduct in time to release energy.

[0050] A temperature-sensitive resistor network (not shown in the figure) may also be connected between the gate of the ESD discharge device 214 and the cathode of the second clamping diode string 212. The temperature-sensitive resistor network can automatically adjust the conduction threshold of the above-mentioned ESD discharge device according to the temperature change to compensate for the influence of temperature on the trigger voltage. The second clamping diode string 212 is shared by the forward ESD trigger path and the reverse ESD trigger path, so that the overall area of the ESD protection circuit 210 can be reduced, and the chip area is thus reduced.

[0051] The first clamping diode string 211 and the third clamping diode string 213 connected in series with opposite polarities are connected between the gate and the source of the GaN power device 220, so that the leakage path between the gate and the source of the GaN power device 220 under non-ESD events is blocked.

[0052] The number of diode structures in the first clamping diode string 211, the second clamping diode string 212, and the third clamping diode string 213 is adjustable. Among them, the forward ESD startup voltage is adjusted by adjusting the number of diode structures in the first clamping diode string 211 and / or the second clamping diode string 212, and the reverse ESD startup voltage is adjusted by adjusting the number of diode structures in the third clamping diode string 213 and the second clamping diode string 212.

[0053] At least one of the first clamping diode string 211, the second clamping diode string 212, and the third clamping diode string 213 has a programmable switching element (such as a MOSFET (metal-oxide-semiconductor field effect transistor)). By using the programmable switching element, the number of diode structures connected in series can be dynamically adjusted through an external control signal, so as to adjust the forward or reverse ESD trigger threshold in real time. The diode structures in the first clamping diode string 211, the second clamping diode string 212, and the third clamping diode string 213 can be metal / AlGaN Schottky diodes.

[0054] The GaN power device 220 can be an enhancement-mode power high electron mobility transistor or a depletion-mode high electron mobility transistor. The implementation principle of Embodiment 1 is as follows: 1. The first clamping diode string 211 and the third clamping diode string 213 connected in series with opposite polarities can block the leakage current path under non-ESD events.

[0055] When a negative voltage turn-off or gate negative voltage test is performed, a negative voltage is applied to the gate of the GaN power device 220 (i.e., the source voltage is higher than the gate voltage). At this time, the first clamping diode string 211 will be cut off due to reverse bias, blocking the leakage current path from the source to the gate of the GaN power device 220. When the gate is forward-biased (such as during normal operation), at this time the third clamping diode string 213 is reverse-biased and cut off, blocking the leakage current path from the gate to the source of the GaN power device 220.

[0056] That is to say, under non-ESD events (such as negative voltage turn-off, gate negative voltage test, or normal operation), there is no leakage current path between the gate and the source of the GaN power device 220, thus avoiding the problem that the ESD protection circuit in the related art is incompatible with the application scenarios of negative voltage turn-off and gate negative voltage test.

[0057] 2. An independent positive / negative ESD trigger path design is adopted.

[0058] When a positive ESD event (a sudden increase in the gate voltage of the GaN power device 220) occurs, after the first clamping diode string 211 and the second clamping diode string 212 are voltage-divided, the conduction threshold of the ESD discharge device 214 is reached, driving the ESD discharge device 214 to conduct, and forming a low-impedance path to discharge the positive ESD energy.

[0059] When a reverse ESD event occurs (the source voltage of the GaN power device 220 suddenly rises), after the third clamping diode string 213 and the second clamping diode string 212 divide the voltage, the ESD discharge device 214 is driven to conduct reversely to discharge the reverse ESD energy. Since the reverse ESD trigger path is formed by the independent third clamping diode string 213, the leakage problem of the reverse bias path in the ESD protection circuit of the related technology can be avoided.

[0060] 3. The ESD discharge device 214 can perform dynamic response.

[0061] The voltage division of the clamping diode string can be precisely controlled according to the conduction threshold of the ESD discharge device 214. During negative voltage turn-off or gate negative voltage test, since the voltage division path does not reach the conduction threshold of the ESD discharge device 214, the ESD discharge device 214 remains off, avoiding interference with normal negative voltage operation. When an ESD event occurs, regardless of positive / negative transients, the ESD discharge device 214 quickly conducts to provide a low-resistance discharge path to protect the gate of the GaN power device 220 from high-voltage damage.

[0062] 4. The voltage division path can be flexibly adjusted.

[0063] By increasing or decreasing the number of diode structures in the first clamping diode string 211 / the third clamping diode string 213, the positive / negative ESD trigger voltage can be independently adjusted. The positive ESD trigger voltage is determined by the series connection number of the diode structures in the first clamping diode string 211 and the second clamping diode string 212, and the reverse ESD trigger voltage is determined by the series connection number of the diode structures in the third clamping diode string 213 and the second clamping diode string 212. By adjusting the positive / negative ESD trigger voltage, it can be ensured that in the negative voltage turn-off or gate negative voltage test scenario, the trigger voltage of the ESD protection circuit is much higher than the normal operating voltage, avoiding mis-triggering.

[0064] Embodiment 2 Referring to Figure 3 This embodiment is different from Embodiment 1 in that the diode structures in the first clamping diode string 211, the second clamping diode string 212, and the third clamping diode string 213 can be diode-connected enhancement-mode field-effect transistors. Using diode-connected enhancement-mode field-effect transistors can obtain lower leakage current compared with metal / AlGaN Schottky diodes, and has better integration and process compatibility.

[0065] The implementation principle of Embodiment 2 is as follows: 1. Compared with metal / AlGaN Schottky diodes, diode-connected enhancement-mode field-effect transistors have lower leakage current, especially under reverse bias and high-temperature conditions. The lower leakage current can reduce the power consumption of the protection circuit during normal operation and avoid interfering with the normal functions of the protected devices.

[0066] 2. Since the protected GaN power device 220 itself is also a kind of field-effect transistor, using a similar field-effect transistor structure as the ESD protection device can simplify the manufacturing process, improve the integration level, and reduce the production cost. In actual production, the same or similar process steps can be used to manufacture the ESD protection circuit 210 and the GaN power device 220.

[0067] Embodiment 3 Refer to Figure 4 , the difference between this embodiment and Embodiment 1 is that the ESD discharge device 214 is a bidirectional conduction enhancement-mode transistor (such as a GaN bidirectional conduction enhancement-mode field-effect transistor), which has a gate and symmetric first and second drain electrodes. The gate of the ESD discharge device 214 is connected to the cathode of the second clamping diode string 212, the first drain electrode of the ESD discharge device 214 is connected to the source electrode of the GaN power device 220, and the second drain electrode of the ESD discharge device 214 is connected to the gate electrode of the GaN power device 220. Using a bidirectional conduction enhancement-mode transistor has better structural symmetry and positive / negative ESD response speed consistency compared with a unidirectional low-voltage enhancement-mode transistor.

[0068] The implementation principle of Embodiment 3 is as follows: 1. The symmetric layout of the two drain electrodes reduces the parasitic inductance and capacitance differences, makes the positive / negative ESD response speeds consistent, and avoids protection delay caused by path asymmetry.

[0069] 2. The drain electrode symmetry also reduces the on-resistance, which can reduce the energy loss and heat accumulation in ESD events.

[0070] On the other hand, Embodiment 4 of the present application also discloses a power device circuit device. Also refer to Figures 2 to 4 , the power device circuit device includes an ESD protection circuit and a GaN power device 220. The connection between the ESD protection circuit and the GaN power device 220 is in a monolithic integrated structure, and the structure of the ESD protection circuit can be the ESD protection circuit 210 described in any one of Embodiments 1 to 3.

[0071] Among them, the gate of the GaN power device 220 is connected to the anode of the first clamping diode string 211 and the drain of the ESD discharge device 214, and the source of the GaN power device 220 is connected to the anode of the third clamping diode string 213 and the source of the ESD discharge device 214.

[0072] The ESD protection circuit 210 and the GaN power device 220 can be integrated on the same chip, and the layouts of the first clamping diode string 211 and the third clamping diode string 213 are symmetrically arranged around the gate-source path of the GaN power device 220. Through physical layout optimization, the diode strings of the ESD protection circuit 210 are symmetrically arranged with the gate-source path of the GaN power device 220, and the key node spacing is shortened through the metal interconnection layer, which can reduce the influence of parasitic resistance and inductance on the dynamic response.

[0073] The implementation principle of a power device circuit device according to an embodiment of the present application is as follows: by integrating an ESD protection circuit and a GaN power device, while ensuring the normal operation of the device, a bidirectional ESD protection capability is provided, significantly improving the reliability and lifespan of the power system.

[0074] The above are all preferred embodiments of the present application, and the protection scope of the present application is not limited thereby. Therefore, all equivalent changes made according to the structure, shape, and principle of the present application shall be covered within the protection scope of the present application.

Claims

1. An ESD protection circuit for connection with a GaN power device (220), characterized in that, The ESD protection circuit includes: A first clamping diode string (211), a second clamping diode string (212), a third clamping diode string (213), and an ESD discharge device (214). The first clamping diode string (211) and the third clamping diode string (213) are connected between the gate and the source of the GaN power device (220) in a series connection with opposite polarities. The anode of the second clamping diode string (212) is respectively connected to the cathode of the first clamping diode string (211) and the cathode of the third clamping diode string (213), and the cathode of the second clamping diode string (212) is connected to the gate of the ESD discharge device (214).

2. The ESD protection circuit according to claim 1, wherein The first clamping diode string (211) and the third clamping diode string (213) are connected between the gate and the source of the GaN power device (220) in a series connection with opposite polarities. This connection method includes: The anode of the first clamping diode string (211) is used to be respectively connected to the gate of the GaN power device (220) and the drain of the ESD discharge device (214). The cathode of the first clamping diode string (211) is respectively connected to the anode of the second clamping diode string (212) and the cathode of the third clamping diode string (213). The anode of the third clamping diode string (213) is used to be respectively connected to the source of the GaN power device (220) and the source of the ESD discharge device (214).

3. The ESD protection circuit according to claim 1, wherein The ESD discharge device (214) is an enhancement-mode transistor, having a gate, a source, and a drain. The gate of the ESD discharge device (214) is connected to the cathode of the second clamping diode string (212). The source of the ESD discharge device (214) is connected to the source of the GaN power device (220). The drain of the ESD discharge device (214) is connected to the gate of the GaN power device (220). Alternatively, the ESD discharge device (214) is a bidirectional conduction enhancement-mode transistor, having a gate and symmetric first and second drains. The gate of the ESD discharge device (214) is connected to the cathode of the second clamping diode string (212). The first drain of the ESD discharge device (214) is connected to the source of the GaN power device (220). The second drain of the ESD discharge device (214) is connected to the gate of the GaN power device (220). Wherein, a temperature-sensitive resistor network is further connected between the gate of the ESD discharge device (214) and the cathode of the second clamping diode string (212).

4. The ESD protection circuit according to claim 1, characterized in that, The first clamping diode string (211) and the second clamping diode string (212) form a forward ESD trigger path to control the forward ESD startup voltage. Alternatively, the third clamping diode string (213) and the second clamping diode string (212) form a reverse ESD trigger path to control the reverse ESD startup voltage.

5. The ESD protection circuit according to claim 4, characterized in that, The ESD discharge device (214) is configured to conduct to release energy when a forward ESD event or a reverse ESD event occurs.

6. The ESD protection circuit according to claim 4, wherein The number of diode structures in the first clamping diode string (211), the second clamping diode string (212), and the third clamping diode string (213) is adjustable; Wherein, at least one of the first clamping diode string (211), the second clamping diode string (212), and the third clamping diode string (213) has a programmable switching element.

7. The ESD protection circuit according to claim 6, wherein The number of diode structures in one of the first clamping diode string (211) and the second clamping diode string (212) is adjusted to adjust the forward ESD trigger voltage; The number of diode structures in one of the third clamping diode string (213) and the second clamping diode string (212) is adjusted to adjust the reverse ESD trigger voltage.

8. The ESD protection circuit according to any one of claims 1-7, characterized in that, The diode structures in the first clamping diode string (211), the second clamping diode string (212), and the third clamping diode string (213) include Schottky diodes or diode-connected enhancement-mode field effect transistors.

9. A power device circuit device, characterized in that, Comprising: An ESD protection circuit (210), including: A first clamping diode string (211), a second clamping diode string (212), and a third clamping diode string (213), wherein the first clamping diode string (211) and the third clamping diode string (213) are connected in series with opposite polarities between the gate and the source of the GaN power device (220); An ESD discharge device (214), wherein the anode of the second clamping diode string (212) is respectively connected to the cathode of the first clamping diode string (211) and the cathode of the third clamping diode string (213), and the cathode of the second clamping diode string (212) is connected to the gate of the ESD discharge device (214); and A GaN power device (220), connected to the ESD protection circuit (210), and the connection method includes: the gate of the GaN power device (220) is respectively connected to the anode of the first clamping diode string (211) and the drain of the ESD discharge device (214), and the source of the GaN power device (220) is respectively connected to the anode of the third clamping diode string (213) and the source of the ESD discharge device (214).

10. The power device circuit device according to claim 9, characterized in that, The ESD protection circuit (210) and the GaN power device (220) are integrated on the same chip, and the layouts of the first clamping diode string (211) and the third clamping diode string (213) are symmetrically arranged around the gate-source path of the GaN power device (220).

Images