Signal amplification circuit, chip and electronic equipment

Abstract

The embodiment of the invention provides a signal amplification circuit, a chip and electronic equipment, the signal amplification circuit is used for amplifying differential mode voltage between a first differential input signal and a second differential input signal, the signal amplification circuit comprises an amplification module, the amplification module comprises a first operational amplifier; the common-mode voltage compensation module is used for controlling the voltage of the first input end and the second input end of the first operational amplifier; when the input common-mode voltage of the first differential input signal and the input common-mode voltage of the second differential input signal are changed, the common-mode voltage compensation module controls the voltage of the first input end and the voltage of the second input end of the first operational amplifier to be kept at a first preset value. The problem that the voltage of the first input end and the voltage of the second input end of the first operational amplifier change along with the input common-mode voltage of the first differential input signal and the input common-mode voltage of the second differential input signal can be solved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and particularly relates to a signal amplification circuit, a chip, and an electronic device. Background Art

[0002] Currently, a Programmable Gain Amplifier (PGA) is a circuit whose voltage gain can be controlled by programming. The programmable gain amplifier is often used as the pre-stage circuit of an analog-to-digital converter to improve the signal-to-noise ratio of the measurement system.

[0003] In the related art, since the programmable gain amplifier with a capacitive architecture has high common-mode voltage rejection ability, the programmable gain amplifier with a capacitive architecture is widely used. However, during the operation of the programmable gain amplifier with a capacitive architecture, the voltages at the non-inverting input terminal and the inverting input terminal of the operational amplifier are in a floating state. When the input common-mode voltage of the differential input signal changes, the voltages at the non-inverting input terminal and the inverting input terminal will change accordingly, which may cause the voltages at the non-inverting input terminal and the inverting input terminal to exceed the maximum common-mode input voltage range of the operational amplifier. Summary of the Invention

[0004] In view of the above problems, embodiments of this application provide a signal amplification circuit, a chip, and an electronic device to solve the above technical problems.

[0005] In a first aspect, an embodiment of this application provides a signal amplification circuit for amplifying the differential-mode voltage between a first differential input signal and a second differential input signal. The signal amplification circuit includes:

[0006] An amplification module, which includes a first operational amplifier;

[0007] A common-mode voltage compensation module for controlling the voltages at the first input terminal and the second input terminal of the first operational amplifier;

[0008] Wherein, when the input common-mode voltages of the first differential input signal and the second differential input signal change, the common-mode voltage compensation module controls the voltages at the first input terminal and the second input terminal of the first operational amplifier to remain at a first preset value.

[0009] In a second aspect, an embodiment of this application further provides a chip, including the above signal amplification circuit.

[0010] In a third aspect, an embodiment of this application further provides an electronic device, including the above chip or signal amplification circuit.

[0011] In this application, a common-mode voltage compensation module is used to control the voltages at the first input terminal and the second input terminal of the first operational amplifier. When the input common-mode voltage magnitudes of the first differential input signal and the second differential input signal change, the common-mode voltage compensation module can control the voltages at the first input terminal and the second input terminal of the first operational amplifier to remain at a first preset value unchanged, thereby avoiding the phenomenon that the voltages at the first input terminal and the second input terminal of the first operational amplifier change with the input common-mode voltage of the first differential input signal and the second differential input signal, and further causing the voltages at the first input terminal and the second input terminal of the first operational amplifier to exceed its maximum common-mode input voltage range.

[0012] These aspects or other aspects of this application will be more clearly understood in the following description of the embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of this application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of this application. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0014] Figure 1 FIG. shows a schematic diagram of a programmable gain amplifier with a capacitive architecture in the related art.

[0015] Figure 2 FIG. shows a schematic diagram of a signal amplification circuit in an embodiment of this application.

[0016] Figure 3 FIG. shows another schematic diagram of a signal amplification circuit in an embodiment of this application.

[0017] Figure 4 FIG. shows another schematic diagram of a signal amplification circuit in an embodiment of this application.

[0018] Figure 5 FIG. shows another schematic diagram of a signal amplification circuit in an embodiment of this application.

[0019] Figure 6 FIG. shows another schematic diagram of a signal amplification circuit in an embodiment of this application.

[0020] Figure 7 FIG. shows another schematic diagram of a signal amplification circuit in an embodiment of this application.

[0021] Figure 8 FIG. shows another schematic diagram of a signal amplification circuit in an embodiment of this application.

[0022] Figure 9Another schematic diagram of the signal amplification circuit in the embodiments of the present application is shown.

[0023] Among them, 10 is the amplification module, 20 is the common-mode voltage compensation module, 201 is the voltage control unit, 21 is the first inverting amplification sub-unit, 22 is the second inverting amplification sub-unit, 23 is the first quantizer, and 24 is the second quantizer;

[0024] The first differential input signal Vip, the second differential input signal Vin, the first differential amplified signal Vop, the second differential amplified signal Von, the first operational amplifier OP, the first compensation capacitor C01, and the second compensation capacitor C02;

[0025] The first switch S1, the second switch S2, the first input capacitor Ci1, the second input capacitor Ci2, the first feedback capacitor Cf1, and the second feedback capacitor Cf2;

[0026] The first sub-operational amplifier AMP1, the second sub-operational amplifier AMP2, the third sub-operational amplifier AMP3, the fourth sub-operational amplifier AMP4, the preset reference voltage Vref, the first impedance element Z1, the second impedance element Z2, the third impedance element Z3, the fourth impedance element Z4, the first reverse voltage Vo1, the second reverse voltage Vo2, the first digital signal D1[N:1], and the second digital signal D2[N:1]. Detailed implementation manners

[0027] The following details the implementation manners of the present application. The examples of the implementation manners are shown in the accompanying drawings, where the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions throughout. The implementation manners described below with reference to the accompanying drawings are exemplary only for explaining the present application and should not be construed as limiting the present application.

[0028] To enable those skilled in the art of the present technology to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative efforts fall within the scope of protection of the present application.

[0029] In the embodiments of the present application, it should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0030] Moreover, the term "comprising", "including" or any other variation thereof is intended to cover non-exclusive inclusion, such that a process, method, article or apparatus comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or apparatus. Without further limitation, an element defined by the phrase "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element.

[0031] In the description of the embodiments of the present application, words such as "example" or "for example" are used to give examples, explanations or descriptions. Any embodiment or design described as "for example" or "example" in the embodiments of the present application is not construed as being more preferred or having more advantages than another embodiment or design. The use of words such as "example" or "for example" is intended to present relative concepts in a clear manner.

[0032] In addition, "a plurality of" in the embodiments of the present application means two or more. In view of this, "a plurality of" in the embodiments of the present application can also be understood as "at least two". "At least one" can be understood as one or more, for example, understood as one, two or more. For example, including at least one means including one, two or more, and does not limit which ones are included. For example, including at least one of A, B and C, then what can be included are A, B, C, A and B, A and C, B and C, or A and B and C.

[0033] It should be noted that in the embodiments of the present application, "and / or" describes the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / ", unless otherwise specified, generally represents an "or" relationship between the associated objects before and after.

[0034] It should be pointed out that "connection" in the embodiments of the present application can be understood as electrical connection, and the connection of two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0035] In the circuit structure provided by the embodiments of the present application, nodes such as the first node and the second node do not represent actual existing components, but represent the convergence points of relevant couplings in the circuit diagram. That is to say, these nodes are nodes equivalent to the convergence points of relevant couplings in the circuit diagram.

[0036] A programmable gain amplifier is a circuit whose voltage gain can be controlled by programming. Refer to Figure 1 , Figure 1Shows a schematic diagram of a programmable gain amplifier in a capacitive architecture in the related art. The programmable gain amplifier of the capacitive architecture includes an operational amplifier OP, an input capacitor C1, an input capacitor C2, a feedback capacitor C3, a feedback capacitor C4, a reset switch S1, a reset switch S2, a reset switch S3, and a reset switch S4. The programmable gain amplifier has a reset stage and an amplification stage.

[0037] In the reset stage of the programmable gain amplifier, the reset switches S1, S2, S3, and S4 are closed, and the operational amplifier OP is connected in the form of unity gain negative feedback. At this time, the voltages at the non-inverting input terminal and the inverting output terminal of the operational amplifier OP are equal to the output common-mode voltage of the operational amplifier OP, that is, VXP = VXN = VCMO. Therefore, the charges QXP accumulated by the input capacitor C1 and the feedback capacitor C3, and the charges QXN accumulated by the input capacitor C2 and the feedback capacitor C4 are respectively:

[0038] QXP = QC1 + QC3 = (VCMO - VCM) * Cp + 0

[0039] QXN = QC2 + QC4 = (VCMO - VCM) * Cp + 0

[0040] Among them, QC1 is the charge accumulated by the input capacitor C1, QC2 is the charge accumulated by the input capacitor C2, QC3 is the charge accumulated by the feedback capacitor C3, QC4 is the charge accumulated by the feedback capacitor C4, VCMO is the output common-mode voltage of the operational amplifier, and Cp is the capacitance value of the input capacitor C1 and the input capacitor C2.

[0041] In the amplification stage of the programmable gain amplifier, the reset switches S1, S2, S3, and S4 are opened, and the operational amplifier OP outputs differential amplified signals Vop and Von. Based on charge conservation, the charges QXP accumulated by the input capacitor C1 and the feedback capacitor C3, and the charges QXN accumulated by the input capacitor C1 and the feedback capacitor C3 are respectively:

[0042] QXP = QC1 + QC3 = (VXP - Vip) * Cp + (VXP - Von) * Cn

[0043] QXN = QC2 + QC4 = (VXN - Vin) * Cp + (VXN - Vop) * Cn

[0044] Among them, VXP is the voltage at the non-inverting input terminal of the operational amplifier OP, VXN is the voltage at the inverting input terminal of the operational amplifier OP, and Cn is the capacitance value of the feedback capacitor C3 and the feedback capacitor C4.

[0045] Combining the above formulas, we can obtain:

[0046] 2(VCMO - VCM)*Cp = (VXP - Vip)*Cp + (VXP - Von)*Cn + (VXN - Vin)*Cp + (VXN - Vop)*Cn

[0047] 2(VCMO - VCM)*Cp = (VXP + VXN)*(Cp + Cn) - (Vip + Vin)*Cp - (Vop + Von)*Cn

[0048] According to the common - mode voltage calculation formula, it can be known that VCMO = (Von + Vop) / 2, VCMI = (Vin + Vip) / 2, where VCMO is the output common - mode voltage of the operational amplifier, and VCMI is the common - mode voltage of the differential input signals Vip and Vin. Therefore, the above formula can be transformed into:

[0049] 2(VCMO - VCM)*Cp = (VXP + VXN)*(Cp + Cn) - 2VCMI*Cp - 2VCMO*Cn

[0050] (VXP + VXN)*(Cp + Cn) = 2VCMO*(Cp + Cn) + 2VCMI*Cp - 2VCM*Cn

[0051] Due to the virtual - short and virtual - open characteristics of the operational amplifier OP, it can be known that VXP = VXN. Therefore, the above formula can be transformed into:

[0052] 2VXP*(Cp + Cn) = 2VCMO*(Cp + Cn) + 2VCMI*Cp - 2VCM*Cn

[0053]

[0054] It can be seen from the above formula that if the common - mode voltage VCM is equal to the common - mode voltage VCMI of the differential input signals Vip and Vin, term and term cancel each other out. Therefore, the voltages VXP and VXN at the non - inverting input terminal and the inverting input terminal of the operational amplifier OP are equal to the output common - mode voltage VCMO of the operational amplifier.

[0055] However, since the input - node voltage of the operational amplifier OP is in a floating state for a long time during the amplification stage and the voltage magnitude is affected by the common - mode voltage of the differential input signals Vip and Vin, when the common - mode voltage of the differential input signals Vip and Vin changes, term and term cannot cancel each other out, which will cause the voltages VXP and VXN at the non - inverting input terminal and the inverting input terminal of the operational amplifier OP to change.

[0056] For example, when the input common-mode voltage VCMI of the differential input signals Vip and Vin drops by ΔV, the input node voltages VXP and VXN of the operational amplifier OP will drop by Cp / (Cp + Cn)*ΔV, which may cause the voltages VXP and VXN of the operational amplifier input nodes to exceed the allowable maximum common-mode input voltage range of the operational amplifier. For example, when both the input transistor and the input-stage tail current transistor of the operational amplifier OP are NMOS transistors, the input node voltage of the operational amplifier OP drops by Cp / (Cp + Cn)*ΔV, which may cause the input-stage tail current transistor of the operational amplifier OP to enter the linear region, thereby causing the operational amplifier OP to deviate from the normal operating state.

[0057] To this end, the present application provides a signal amplification circuit, a chip, and an electronic device, which will be described in detail below respectively.

[0058] First, refer to Figure 2 , Figure 2 FIG. shows a schematic diagram of a signal amplification circuit in an embodiment of the present application. Among them, the signal amplification circuit is used to amplify the differential-mode voltage between the first differential input signal Vip and the second differential input signal Vin. The signal amplification circuit includes an amplification module 10 and a common-mode voltage compensation module 20.

[0059] Specifically, the amplification module 10 is used to access the first differential input signal Vip and the second differential input signal Vin, and amplify the differential-mode voltage between the first differential input signal Vip and the second differential input signal Vin, and finally output a first differential amplified signal Vop and a second differential amplified signal Von to improve the signal-to-noise ratio of the signal measurement system. For example, taking the amplification factor of the amplification module 10 as k, the first differential input signal Vip, the second differential input signal Vin input to the amplification module 10, the first differential amplified signal Vop and the second differential amplified signal Von output by the amplification module 10 can satisfy the following relationship:

[0060] (Vip - Vin)*k = (Vop - Von)

[0061] As an example, refer to Figure 3 , Figure 3Another schematic diagram of the signal amplification circuit in the embodiment of the present application is shown. Among them, the amplification module 10 includes a first operational amplifier OP, a first input capacitor Ci1, a second input capacitor Ci2, a first feedback capacitor Cf1, and a second feedback capacitor Cf2. The capacitance values of the first input capacitor Ci1 and the second input capacitor Ci2 are equal, and the capacitance values of the first feedback capacitor Cf1 and the second feedback capacitor Cf2 are equal. The first end of the first input capacitor Ci1 is used to access the first differential input signal Vip, and the second end of the first input capacitor Ci1 is connected to the first input terminal of the first operational amplifier OP. The first end of the second input capacitor Ci2 is used to access the second differential input signal Vin, and the second end of the second input capacitor Ci2 is connected to the second input terminal of the first operational amplifier OP. The first end of the first feedback capacitor Cf1 is connected to the first input terminal of the first operational amplifier OP, and the second end of the first feedback capacitor Cf1 is connected to the second output terminal of the first operational amplifier OP. The first end of the second feedback capacitor Cf2 is connected to the second input terminal of the first operational amplifier OP, and the second end of the second feedback capacitor Cf2 is connected to the first output terminal of the first operational amplifier OP.

[0062] In the above embodiment, the first operational amplifier OP, the first input capacitor Ci1, the second input capacitor Ci2, the first feedback capacitor Cf1, and the second feedback capacitor Cf2 form a capacitive differential amplification circuit. According to the characteristics of the differential amplification circuit, the first differential input signal Vip and the second differential input signal Vin input to the amplification module 10 and the first differential amplification signal Vop and the second differential amplification signal Von output by the amplification module 10 satisfy the following relational expressions:

[0063]

[0064] Among them, CF is the capacitance value of the first feedback capacitor Cf1 and the second feedback capacitor Cf2, and CI is the capacitance value of the first input capacitor Ci1 and the second input capacitor Ci2.

[0065] It can be seen that the amplification factor of the amplification module 10 is equal to the capacitance ratio of the input capacitors (i.e., the first input capacitor Ci1 and the second input capacitor Ci2) to the feedback capacitors (i.e., the first feedback capacitor Cf1 and the second feedback capacitor Cf2). By controlling the capacitance values of the input capacitors and / or the feedback capacitors, the amplification factor of the amplification module 10 can be changed.

[0066] It can be understood that, of the operational amplifier (first operational amplifier OP, first sub-operational amplifier AMP1, second sub-operational amplifier AMP2, etc.) referred to in the present application, one of the first input terminal and the second input terminal refers to the non-inverting input terminal of the operational amplifier, and the other refers to the inverting input terminal of the operational amplifier, and one of the first output terminal and the second output terminal of the operational amplifier refers to the non-inverting output terminal of the operational amplifier, and the other refers to the inverting output terminal of the operational amplifier.

[0067] The common-mode voltage compensation module 20 is used to control the voltages at the first input terminal and the second input terminal of the first operational amplifier OP, wherein when the input common-mode voltages of the first differential input signal Vip and the second differential input signal Vin change, the common-mode voltage compensation module 20 controls the voltages at the first input terminal and the second input terminal of the first operational amplifier OP to remain at a first preset value, so as to avoid the phenomenon that the voltages at the first input terminal and the second input terminal of the first operational amplifier OP change with the input common-mode voltages of the first differential input signal Vip and the second differential input signal Vin.

[0068] In some embodiments of the present application, the common-mode voltage compensation module 20 can be coupled to the first input terminal and the second input terminal of the first operational amplifier OP through a compensation capacitor, and by changing the amount of charge accumulated in the compensation capacitor, the amount of charge accumulated in the first input capacitor Ci1, the second input capacitor Ci2, the first feedback capacitor Cf1, and the second feedback capacitor Cf2 is indirectly changed, thereby controlling the voltage of the first input terminal and the second input terminal of the first operational amplifier OP to remain at a first preset value.

[0069] For example, when the input common-mode voltage of the first differential input signal Vip and the second differential input signal Vin increases, the common-mode voltage compensation module 20 increases the amount of charge accumulated in the compensation capacitor. According to the law of charge conservation, the amount of charge accumulated in the first input capacitor Ci1, the second input capacitor Ci2, the first feedback capacitor Cf1, and the second feedback capacitor Cf2 decreases, thereby reducing the voltage at the first input terminal and the second input terminal of the first operational amplifier OP.

[0070] On the contrary, when the input common-mode voltage of the first differential input signal Vip and the second differential input signal Vin decreases, the common-mode voltage compensation module 20 reduces the amount of charge accumulated in the compensation capacitor. According to the law of charge conservation, the amount of charge accumulated in the first input capacitor Ci1, the second input capacitor Ci2, the first feedback capacitor Cf1, and the second feedback capacitor Cf2 increases, thereby increasing the voltage at the first input terminal and the second input terminal of the first operational amplifier OP.

[0071] In the embodiments of the present application, the present application controls the voltages of the first input terminal and the second input terminal of the first operational amplifier OP through the common-mode voltage compensation module 20. When the input common-mode voltage magnitudes of the first differential input signal Vip and the second differential input signal Vin change, the common-mode voltage compensation module 20 can control the voltages of the first input terminal and the second input terminal of the first operational amplifier OP to remain at a first preset value unchanged, thereby avoiding the phenomenon that the voltages of the first input terminal and the second input terminal of the first operational amplifier OP change with the input common-mode voltage of the first differential input signal Vip and the second differential input signal Vin, and further causing the voltages of the first input terminal and the second input terminal of the first operational amplifier OP to exceed its maximum common-mode input voltage range.

[0072] In some embodiments of the present application, referring to Figure 3 , Figure 3 FIG. shows a schematic diagram of a signal processing circuit in the embodiments of the present application. The common-mode voltage compensation module 20 includes a voltage control unit 201, a first compensation capacitor C01, and a second compensation capacitor C02. The capacitance values of the first compensation capacitor C01 and the second compensation capacitor C02 are equal. The first end of the first compensation capacitor C01 is connected to the first input terminal of the first operational amplifier OP, the second end of the first compensation capacitor C01 is connected to the voltage control unit 201, the first end of the second compensation capacitor C02 is connected to the second input terminal of the first operational amplifier OP, the second end of the second compensation capacitor C02 is connected to the voltage control unit 201, and the voltage control unit 201 can control the voltages of the second ends of the first compensation capacitor C01 and the second compensation capacitor C02 to keep the voltages of the first input terminal and the second input terminal of the first operational amplifier OP at a first preset value.

[0073] Specifically, in the reset stage, the first switch S1 and the second switch S2 are closed. Taking the capacitance values of the first compensation capacitor C01 and the second compensation capacitor C02 as equal as an example, at this time, the sum of the charges QXP accumulated by the first input capacitor Ci1, the first feedback capacitor Cf1, and the first compensation capacitor C01, and the sum of the charges QXN accumulated by the second input capacitor Ci2, the second feedback capacitor Cf2, and the second compensation capacitor C02 are respectively:

[0074] QXP = (VCMO - VCM) * Ci + (VCMO - VC1) * C0

[0075] QXN = (VCMO - VCM) * Ci + (VCMO - VC2) * C0

[0076] Wherein, VCMO is the output common-mode voltage of the first operational amplifier OP, Ci is the capacitance value of the first input capacitor Ci1 and the second input capacitor Ci2, C0 is the capacitance value of the first compensation capacitor C01 and the second compensation capacitor C02, VC1 is the voltage at the second terminal of the first compensation capacitor C01 during the reset phase, and VC2 is the voltage at the second terminal of the second compensation capacitor C02 during the reset phase.

[0077] During the amplification phase, the first switch S1 and the second switch S2 are turned off. Based on the law of conservation of charge, the sum of the charges accumulated by the first input capacitor Ci1, the first feedback capacitor Cf1, and the first compensation capacitor C01, and the charges accumulated by the second input capacitor Ci2, the second feedback capacitor Cf2, and the second compensation capacitor C02 are respectively:

[0078] QXP = (VXP - Vip) * Ci + (VXP - Von) * Cf + (VXP - VC1’) * C0

[0079] QXN = (VXN - Vin) * Ci + (VXN - Vop) * Cf + (VXN - VC2’) * C0

[0080] Wherein, VXP is the voltage at the first input terminal of the first operational amplifier OP, VXN is the voltage at the second input terminal of the first operational amplifier OP, VC1’ is the voltage at the second terminal of the first compensation capacitor C01 during the amplification phase, and VC2’ is the voltage at the second terminal of the second compensation capacitor C02 during the amplification phase.

[0081] By combining the above formulas, we can obtain:

[0082] 2(VCMO - VCM)Ci + (VCMO - VC1)C0 + (VCMO - VC2)C0

[0083] = (VXP - Vip)Ci + (VXP - Von)Cf + (VXN - Vin)Ci + (VXN - Von)Cf + (VXP - VC1’)C0 + (VXP

[0084] - VC1’)C0

[0085] = (VXP + VXN)(Ci + Cf + C0) - (Vip + Vin)Ci - (Vop + Von)Cf - (VC1’ + VC2’)*C0

[0086] According to the common-mode voltage calculation formula, we know that VCMO = (Von + Vop) / 2 and VCMI = (Vin + Vip) / 2. Therefore, the above formula can be transformed into:

[0087] (VXP + VXN)(Ci + Cf + C0) = 2VCMO(Ci + Cf + C0) + 2VCMI * Ci - 2VCM * Ci + (VC1’ + VC2’ - VC1 - VC2) * C0

[0088] Due to the virtual short and virtual open characteristics of the first operational amplifier OP, it can be known that VXP = VXN. Therefore, the above formula can be transformed into:

[0089] 2VXP(Ci + Cf + C0) = 2VCMO(Ci + Cf + C0) + 2VCMI * Ci - 2VCM * Ci + (VC1’ + VC2’ - VC1 - VC2) * C0

[0090]

[0091] It can be seen from the above formula that if VCMI = VCM and VC1’ + VC2’ = VC1 + VC2, then the voltages VXP and VXN at the first input terminal and the second input terminal of the first operational amplifier OP are equal to its output common-mode voltage VCMO; conversely, if the common-mode voltage of the differential input signals Vip and Vin changes such that VCMI ≠ VCM, then the voltage control unit 201 controls the second-terminal voltages VC1’ and VC2’ of the first compensation capacitor C01 and the second compensation capacitor C02, so that in the above formula term, term, and term are cancelled out, then it can be ensured that the voltages VXP and VXN at the first input terminal and the second input terminal of the first operational amplifier OP are equal to its output common-mode voltage VCMO and remain unchanged.

[0092] It should be noted that the first compensation capacitor C01 and the second compensation capacitor C02 shown in Figure 3 are single capacitors, but it is not limited thereto. The first compensation capacitor C01 and the second compensation capacitor C02 can also be multiple capacitors. For example, the first compensation capacitor C01 and the second compensation capacitor C02 can also be multiple capacitors with the capacitance values of the digital-to-analog converter arranged in binary.

[0093] In some embodiments of the present application, the ratio of the first input capacitor Ci1 to the first compensation capacitor C01 is equal to the first ratio; wherein, when the input common-mode voltage magnitudes of the first differential input signal Vip and the second differential input signal Vin change, the absolute value of the ratio between the change amount of the second-terminal voltages of the first compensation capacitor C01 and the second compensation capacitor C02 and the change amount of the input common-mode voltage is equal to the first ratio.

[0094] For example, assume that, relative to the reset phase, the change in the input common-mode voltage during the amplification phase is ΔVCMI, and the change in the voltage at the second terminals of the first compensation capacitor C01 and the second compensation capacitor C02 is ΔVC (i.e., VC1’ - VC1 = ΔVC and VC2’ - VC2 = ΔVC in the above formula). Then the above formula can be transformed into:

[0095]

[0096] As can be seen from the above formula, since usually VCMI = VCM, and cancel each other out. Therefore, to ensure that the voltages VXP and VXN at the first input terminal and the second input terminal of the first operational amplifier OP are equal to its output common-mode voltage VCMO and remain unchanged, the following relational expression needs to be satisfied:

[0097]

[0098] By transforming the above formula, we can obtain:

[0099]

[0100] As can be seen from the above formula, when the magnitudes of the input common-mode voltages of the first differential input signal Vip and the second differential input signal Vin change, the voltage control unit 201 controls the voltages at the second terminals of the first compensation capacitor C01 and the second compensation capacitor C02 such that the absolute value of the ratio between the change in the voltages at the second terminals of the first compensation capacitor C01 and the second compensation capacitor C02 and the change in the input common-mode voltage is equal to the first ratio, then it can be ensured that the voltages VXP and VXN at the first input terminal and the second input terminal of the first operational amplifier OP are equal to its output common-mode voltage VCMO and remain unchanged.

[0101] It should be noted that when the first compensation capacitor C01 and the second compensation capacitor C02 are single capacitors, the change in the voltages at the second terminals of the first compensation capacitor C01 and the second compensation capacitor C02 refers to the change in the plate voltages of the single capacitors; while when the first compensation capacitor C01 and the second compensation capacitor C02 are multiple capacitors, for example, when the first compensation capacitor C01 and the second compensation capacitor C02 are multiple capacitors with the capacitance values of the digital-to-analog converter distributed in binary, the change in the voltages at the second terminals of the first compensation capacitor C01 and the second compensation capacitor C02 can be calculated based on the reference voltage of the analog-to-digital converter and the number of bits by which the digital signal changes. For example, assume that the number of bits by which the digital signal D[N:1] changes are D[k1], D2[k2],..., D[km - 1], D[km], then the change in the voltages at the second terminals of the first compensation capacitor C01 and the second compensation capacitor C02 can be calculated according to the following formula:

[0102] △VC = {△D[k1]*W(k1) + △D[k2]*W(k2) +... + △D[km - 1]*W(km - 1) + △D[km]*W(km)}*VREF

[0103] Wherein, W(ki) is the weight corresponding to the ki-th bit of the digital signal, and its magnitude is 1 / 2 ki , ΔD[ki] is the change amount of the ki-th bit of the digital signal D[N:1]. If D[ki] changes from 0 to 1, then ΔD[ki] = 1; if D[ki] changes from 1 to 0, then ΔD[ki] = -1.

[0104] It can be understood that when the first compensation capacitor C01 and the second compensation capacitor C02 are multiple capacitors with the capacitance values of the digital-to-analog converter distributed in binary, the total capacitance value of the multiple capacitors distributed in binary of the digital-to-analog converter is used as the capacitance values of the first compensation capacitor C01 and the second compensation capacitor C02.

[0105] In some embodiments of the present application, referring to Figure 4 , Figure 4 , shows another schematic diagram of the signal amplification circuit in the embodiments of the present application. Among them, the voltage control unit 201 includes a first inverting amplification sub-unit 21 and a second inverting amplification sub-unit 22; the first inverting amplification sub-unit 21 is used to output a first reverse voltage Vo1 according to the voltage of the first input terminal of the first operational amplifier OP, and the second inverting amplification sub-unit 22 is used to output a second reverse voltage Vo2 according to the voltage of the second input terminal of the first operational amplifier OP.

[0106] It should be noted that the first reverse voltage Vo1 can control the voltage of the second terminal of the first compensation capacitor C01, the second reverse voltage Vo2 can control the voltage of the second terminal of the second compensation capacitor C02, the first reverse voltage Vo1 is negatively correlated with the voltage of the first input terminal of the first operational amplifier OP, and the second reverse voltage Vo2 is negatively correlated with the voltage of the second input terminal of the first operational amplifier OP.

[0107] For example, when the input common-mode voltage of the first differential input signal Vip and the second differential input signal Vin increases, resulting in an increase in the voltages of the first input terminal and the second input terminal of the first operational amplifier OP, then the first reverse voltage Vo1 and the second reverse voltage Vo2 decrease; conversely, when the input common-mode voltage of the first differential input signal Vip and the second differential input signal Vin decreases, resulting in a decrease in the voltages of the first input terminal and the second input terminal of the first operational amplifier OP, then the first reverse voltage Vo1 and the second reverse voltage Vo2 increase.

[0108] For example, taking the second terminal of the first compensation capacitor C01 being connected to the first reverse voltage Vo1 and the second terminal of the second compensation capacitor C02 being connected to the second reverse voltage Vo2 as an example, according to the foregoing content, the voltage calculation formulas for the first input terminal and the second input terminal of the first operational amplifier OP, VXP and VXN, can be:

[0109]

[0110] where △Vo is the change amount of the first reverse voltage Vo1 and the second reverse voltage Vo2.

[0111] It can be seen from the above formula that since the first reverse voltage Vo1 is negatively correlated with the voltage of the first input terminal of the first operational amplifier OP, and the second reverse voltage Vo2 is negatively correlated with the voltage of the second input terminal of the first operational amplifier OP, when △VCMI is positive, △Vo is negative; when △VCMI is negative, △Vo is positive. Therefore, the term and can cancel each other out so that the voltages VXP and VXN of the first input terminal and the second input terminal of the first operational amplifier OP remain unchanged.

[0112] In some embodiments of the present application, the amplification factors of the first inverting amplification subunit 21 and the second inverting amplification subunit 22 are equal, the sum of the capacitance values of the first input capacitor Ci1, the first feedback capacitor Cf1, and the first compensation capacitor C01 is equal to the first capacitance value, the ratio of the capacitance value of the first compensation capacitor C01 to the first capacitance value is equal to the first ratio, and the product of the first ratio and the amplification factor of the first inverting amplification subunit 21 is equal to 1. That is to say, the first input capacitor Ci1, the first feedback capacitor Cf1, the first compensation capacitor C01, and the amplification factor of the first inverting amplification subunit 21 satisfy the following relational expression:

[0113]

[0114] where k0 is the amplification factor of the first inverting amplification subunit 21 and the second inverting amplification subunit 22.

[0115] For example, assuming that the input common-mode voltage change amount is △VCMI, then the voltage change amounts of the first input terminal and the second input terminal of the first operational amplifier OP, VXP and VXN, and the change amounts of the first reverse voltage Vo1 and the second reverse voltage Vo2 are:

[0116]

[0117] △Vo = -k0 * △VXP

[0118] As can be seen from the foregoing, to ensure that the voltages VXP and VXN at the first input terminal and the second input terminal of the first operational amplifier OP are equal to its output common-mode voltage VCMO and remain unchanged, the following relational expressions need to be satisfied:

[0119]

[0120] Substituting the calculation formulas for the voltages VXP and VXN at the first input terminal and the second input terminal of the first operational amplifier OP, and the change amounts of the first reverse voltage Vo1 and the second reverse voltage Vo2 into the above formula, we can obtain:

[0121]

[0122] It can be seen that since Therefore, the above relational expressions can be made to hold, and finally, it is ensured that the voltages VXP and VXN at the first input terminal and the second input terminal of the first operational amplifier OP are equal to its output common-mode voltage VCMO and remain unchanged.

[0123] In some embodiments of the present application, referring to Figure 5 , Figure 5 shows another schematic diagram of the signal amplification circuit in the embodiments of the present application. Among them, the first inverting amplification sub-unit 21 includes a first impedance element Z1, a second impedance element Z2, and a first sub-operational amplifier AMP1; the first end of the first impedance element Z1 is connected to the first input terminal of the first operational amplifier OP, and the second end of the first impedance element Z1 is connected to the first input terminal of the first sub-operational amplifier AMP1; the first end of the second impedance element Z2 is connected to the first input terminal of the first sub-operational amplifier AMP1, and the second end of the second impedance element Z2 is connected to the output terminal of the first sub-operational amplifier AMP1; the second input terminal of the first sub-operational amplifier AMP1 is connected to a preset reference voltage Vref, and the output terminal of the first sub-operational amplifier AMP1 is used to output the first reverse voltage Vo1.

[0124] The second inverting amplification sub-unit 22 includes a third impedance element Z3, a fourth impedance element Z4, and a second sub-operational amplifier AMP2; the first end of the third impedance element Z3 is connected to the second input terminal of the first operational amplifier OP, and the second end of the third impedance element Z3 is connected to the first input terminal of the second sub-operational amplifier AMP2; the first end of the fourth impedance element Z4 is connected to the first input terminal of the second sub-operational amplifier AMP2, and the second end of the fourth impedance element Z4 is connected to the output terminal of the second sub-operational amplifier AMP2; the second input terminal of the second sub-operational amplifier AMP2 is connected to a preset reference voltage Vref, and the output terminal of the second sub-operational amplifier AMP2 is used to output the second reverse voltage Vo2.

[0125] It should be noted that the first impedance element Z1, the second impedance element Z2, and the first sub - operational amplifier AMP1 form an inverting amplifier, and the third impedance element Z3, the fourth impedance element Z4, and the second sub - operational amplifier AMP2 form another inverting amplifier. According to the characteristics of the inverting amplifier, it can be known that the first inverted voltage Vo1 and the second inverted voltage Vo2 satisfy the following relational expressions:

[0126]

[0127] Among them, Z02 is the impedance of the second impedance element Z2 and the fourth impedance element Z4, and Z01 is the impedance of the first impedance element Z1 and the third impedance element Z3.

[0128] It can be seen that Z02 / Z01 is the amplification factor of the first inverting amplification sub - unit 21 and the second inverting amplification sub - unit 22. When the first input capacitance Ci1, the first feedback capacitance Cf1, the first compensation capacitance C01, and the amplification factor of the first inverting amplification sub - unit 21 satisfy the following relational expressions Then it can be ensured that the voltages VXP and VXN at the first input terminal and the second input terminal of the first operational amplifier OP are equal to its output common - mode voltage VCMO and remain unchanged.

[0129] It can be understood that the first impedance element Z1, the second impedance element Z2, the third impedance element Z3, and the fourth impedance element Z4 are Figure 5 capacitors in []. In fact, it is not limited to this. The first impedance element Z1, the second impedance element Z2, the third impedance element Z3, and the fourth impedance element Z4 can also be resistors.

[0130] In some embodiments of the present application, referring to Figure 6 , Figure 6 shows another schematic diagram of the signal amplification circuit in the embodiments of the present application. Among them, the first inverting amplification sub - unit 21 further includes a third sub - operational amplifier AMP3; the first input terminal of the third sub - operational amplifier AMP3 is connected to the first input terminal of the first operational amplifier OP, the second input terminal of the third sub - operational amplifier AMP3 is connected to the output terminal of the third sub - operational amplifier AMP3, and the output terminal of the third sub - operational amplifier AMP3 is connected to the first end of the first impedance element Z1. The second inverting amplification sub - unit 22 further includes a fourth sub - operational amplifier AMP4; the first input terminal of the fourth sub - operational amplifier AMP4 is connected to the second input terminal of the first operational amplifier OP, the second input terminal of the fourth sub - operational amplifier AMP4 is connected to the output terminal of the fourth sub - operational amplifier AMP4, and the output terminal of the fourth sub - operational amplifier AMP4 is connected to the first end of the third impedance element Z3.

[0131] It should be noted that the connection mode of the third sub - operational amplifier AMP3 and the fourth sub - operational amplifier AMP4 forms a voltage follower, which can isolate the amplification module 10 from the voltage control unit 201 and avoid the phenomenon that the circuit structure of the voltage control unit 201 (such as the first impedance element Z1 and the third impedance element Z3) affects the voltages at the first input terminal and the second input terminal of the first operational amplifier OP.

[0132] In some embodiments of the present application, for example, in the embodiment where the first compensation capacitor C01 and the second compensation capacitor C02 are multiple capacitors with the capacitance values of the digital - to - analog converter arranged in binary, refer to Figure 7 , Figure 7 which shows another schematic diagram of the signal amplification circuit in the embodiment of the present application. The voltage control unit 201 further includes a first quantizer 23 and a second quantizer 24. The first compensation capacitor C01 includes multiple first sub - capacitors C1,1...C1,n - 1, C1,n, and the first end of each first sub - capacitor is connected to the first input terminal of the first operational amplifier OP; the second compensation capacitor C02 includes multiple second sub - capacitors C2,1...C2,n - 1, C2,n, and the first end of each second sub - capacitor is connected to the second input terminal of the first operational amplifier OP.

[0133] It should be noted that the capacitance values of the multiple first sub - capacitors C1,1...C1,n - 1, C1,n are arranged in binary magnitude to form the capacitance of the digital - to - analog converter, and the capacitance values of the multiple second sub - capacitors C2,1...C2,n - 1, C2,n are arranged in binary magnitude to form the capacitance of the digital - to - analog converter. The first quantizer 23 can output a first digital signal D1[N:1] according to the first reverse voltage Vo1, so as to control the voltage at the second end of each first sub - capacitor through the first digital signal D1[N:1]; the second quantizer 24 can output a second digital signal D2[N:1] according to the second reverse voltage Vo2, so as to control the voltage at the second end of each second sub - capacitor through the second digital signal D2[N:1], and finally ensure that the voltages at the first input terminal and the second input terminal of the first operational amplifier OP remain unchanged through the analog signal output by the digital - to - analog converter.

[0134] For example, assuming that the change amount of the input common - mode voltage is △VCMI, and the change amounts of the voltages at the first input terminal and the second input terminal of the first operational amplifier OP are △VXP and △VXN respectively, then the change amounts of the first reverse voltage Vo1 and the second reverse voltage Vo2 are:

[0135]

[0136] At this time, it will cause the first digital signal D1[N:1] output by the first quantizer 23 and the second digital signal D2[N:1] output by the second quantizer 24 to change. Assuming that the number of bits changed by the first digital signal D1[N:1] are D1[k1], D1[k2],..., D1[km-1], D1[km] respectively, the analog quantity corresponding to the change amount of the first digital signal D1[N:1] is:

[0137] △Vo1={ΔD1[k1]*W(k1)+ΔD1[k2]*W(k2)+...+ΔD1[km-1]*W(km-1)+ΔD1[km]*W(km)}*V REF

[0138] Among them, V REF is the reference voltage of the digital-to-analog converter, and W(ki) is the weight corresponding to the ki-th bit D1[ki] in the first digital signal D1[N:1], and its magnitude is 1 / 2 ki , ΔD1[ki] is the change amount of the ki-th bit of the first digital signal D1[N:1]. If D1[ki] changes from 0 to 1, then ΔD1[ki] = 1; if D1[ki] changes from 1 to 0, then ΔD1[ki] = -1.

[0139] According to the voltage conservation, the change amount of the common-mode voltage at the first input terminal of the first operational amplifier OP caused by the change of the first digital signal D1[N:1] is:

[0140]

[0141] Among them, C 1,tot is the sum of the capacitance values of multiple first sub-capacitors C1,1...C1,n-1, C1,n, and C 1,ki is the first sub-capacitor corresponding to the number of bits changed by the first digital signal D1[N:1].

[0142] It can be seen from the above formula that by setting the values of C 1,tot , Ci, Cf, Z1 and Z2, so that after the formula holds, the change amounts of VXP and VXN caused by the changes of the first digital signal D1[N:1], the second digital signal D2[N:1] and the common-mode input voltage VCMI cancel each other out. Therefore, the voltage at the input terminal of the first operational amplifier OP can be ensured to be stable. It can be understood that the second quantizer 24 and multiple second sub-capacitors C2,1...C2,n-1, C2,n are the same, which will not be elaborated here.

[0143] It should be noted that the above content regarding the signal processing circuit is intended to clearly illustrate the implementation verification process of this application. Those skilled in the art can also make equivalent modification designs or further designs under the guidance of this application. For example, refer to Figure 8 , Figure 8 which shows another schematic diagram of the signal processing circuit in an embodiment of this application. This application can also set a voltage follower between the first compensation capacitor C01 and the first sub-operational amplifier AMP1, and set a voltage follower between the second compensation capacitor C02 and the second sub-operational amplifier AMP2 to control the second terminal voltage of the first compensation capacitor C01 and the second compensation capacitor C02 through the voltage follower. Another example, refer to Figure 9 , Figure 9 which shows another schematic diagram of the signal processing circuit in an embodiment of this application. The common-mode voltage compensation module 20 of this application can also use an analog-to-digital converter to convert the input node voltage of the first operational amplifier OP into a digital signal, and then output a digital signal through a preset digital logic circuit to control a digital-to-analog converter to perform feedback compensation on the input terminal voltage of the first operational amplifier OP.

[0144] An embodiment of this application also provides a chip, which includes the above-mentioned signal processing circuit. A chip (Integrated Circuit, IC) is also called a chip, and this chip can be but is not limited to an SOC (System on Chip, chip-level system) chip, a SIP (system in package, system-level package) chip. Since the chip of this application has the signal processing circuit described in the above embodiment, it has all the beneficial effects of the signal processing circuit in the above embodiment, which will not be elaborated here.

[0145] An embodiment of this application also provides an electronic device, which includes a device main body and a chip as described above disposed inside the device main body. The electronic device can be but is not limited to a weighing scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a car charger, an adapter, a display, a USB (Universal Serial Bus, universal serial bus) expansion dock, a stylus, true wireless earphones, a car center console screen, a car, a smart wearable device, a mobile terminal, a smart home device. The smart wearable device includes but is not limited to a smart watch, a smart bracelet, a cervical massager. The mobile terminal includes but is not limited to a smart phone, a laptop computer, a tablet computer, a POS (point of sales terminal, sales point terminal) machine. The smart home device includes but is not limited to a smart socket, a smart rice cooker, a smart sweeper, a smart light.

[0146] The above are only the preferred embodiments of the present application, and do not impose any form of limitation on the present application. Although the present application has been disclosed above with the preferred embodiments, it is not intended to limit the present application. Any person skilled in the art can make some changes or modifications to equivalent embodiments with equivalent changes within the scope of the technical solution of the present application. However, as long as it does not depart from the content of the technical solution of the present application, any brief modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application still fall within the scope of the technical solution of the present application.

Claims

1. A signal amplification circuit, characterized in that The signal amplification circuit is used to amplify the differential-mode voltage between the first differential input signal and the second differential input signal. The signal amplification circuit includes: an amplification module, the amplification module including a first operational amplifier; a common-mode voltage compensation module, the common-mode voltage compensation module being used to control the voltages of the first input terminal and the second input terminal of the first operational amplifier; wherein, when the magnitudes of the input common-mode voltages of the first differential input signal and the second differential input signal change, the common-mode voltage compensation module controls the voltages of the first input terminal and the second input terminal of the first operational amplifier to remain at a first preset value.

2. The signal amplification circuit according to claim 1, characterized in that, The common-mode voltage compensation module includes a first compensation capacitor, a second compensation capacitor, and a voltage control unit; a first end of the first compensation capacitor is connected to the first input terminal of the first operational amplifier, and a second end of the first compensation capacitor is connected to the voltage control unit; a first end of the second compensation capacitor is connected to the second input terminal of the first operational amplifier, and a second end of the second compensation capacitor is connected to the voltage control unit; wherein, the voltage control unit is used to control the voltages of the second ends of the first compensation capacitor and the second compensation capacitor so that the voltages of the first input terminal and the second input terminal of the first operational amplifier remain at the first preset value.

3. The signal amplification circuit according to claim 2, wherein The amplification module further includes a first input capacitor and a second input capacitor; the capacitance values of the first input capacitor and the second input capacitor are equal, the capacitance values of the first compensation capacitor and the second compensation capacitor are equal, and the capacitance ratio of the first input capacitor to the first compensation capacitor is equal to a first ratio; wherein, when the magnitudes of the input common-mode voltages of the first differential input signal and the second differential input signal change, the absolute value of the ratio between the change amount of the voltages of the second ends of the first compensation capacitor and the second compensation capacitor and the change amount of the input common-mode voltage is equal to the first ratio.

4. The signal amplification circuit according to claim 3, wherein The voltage control unit includes a first inverting amplification sub-unit and a second inverting amplification sub-unit; the first inverting amplification sub-unit is used to output a first reverse voltage according to the voltage of the first input terminal of the first operational amplifier, and the first reverse voltage is used to control the voltage of the second end of the first compensation capacitor; the second inverting amplification sub-unit is used to output a second reverse voltage according to the voltage of the second input terminal of the first operational amplifier, and the second reverse voltage is used to control the voltage of the second end of the second compensation capacitor; wherein, the first reverse voltage is negatively correlated with the voltage of the first input terminal of the first operational amplifier, and the second reverse voltage is negatively correlated with the voltage of the second input terminal of the first operational amplifier.

5. The signal amplification circuit according to claim 4, wherein The first inverting amplification sub-unit includes a first impedance element, a second impedance element, and a first sub-operational amplifier; a first end of the first impedance element is connected to the first input terminal of the first operational amplifier, and a second end of the first impedance element is connected to the first input terminal of the first sub-operational amplifier; The first end of the second impedance element is connected to the first input end of the first sub-operational amplifier, and the second end of the second impedance element is connected to the output end of the first sub-operational amplifier; A preset reference voltage is applied to the second input end of the first sub-operational amplifier, and the output end of the first sub-operational amplifier is used to output the first reverse voltage.

6. The signal amplification circuit according to claim 5, wherein The first inverting amplification sub-unit further includes a third sub-operational amplifier; The first input end of the third sub-operational amplifier is connected to the first input end of the first operational amplifier, the second input end of the third sub-operational amplifier is connected to the output end of the third sub-operational amplifier, and the output end of the third sub-operational amplifier is connected to the first end of the first impedance element.

7. The signal amplification circuit according to claim 5, wherein The voltage control unit further includes a first quantizer, the first compensation capacitor includes a plurality of first sub-capacitors, and the first end of each first sub-capacitor is connected to the first input end of the first operational amplifier; The first quantizer is used to output a first digital signal according to the first reverse voltage, and the first digital signal is used to control the voltage at the second end of each first sub-capacitor.

8. The signal amplification circuit according to claim 4, wherein The second inverting amplification sub-unit includes a third impedance element, a fourth impedance element, and a second sub-operational amplifier; The first end of the third impedance element is connected to the second input end of the first operational amplifier, and the second end of the third impedance element is connected to the first input end of the second sub-operational amplifier; The first end of the fourth impedance element is connected to the first input end of the second sub-operational amplifier, and the second end of the fourth impedance element is connected to the output end of the second sub-operational amplifier; A preset reference voltage is applied to the second input end of the second sub-operational amplifier, and the output end of the second sub-operational amplifier is used to output the second reverse voltage.

9. The signal amplification circuit according to claim 8, wherein The second inverting amplification sub-unit further includes a fourth sub-operational amplifier; The first input end of the fourth sub-operational amplifier is connected to the second input end of the first operational amplifier, the second input end of the fourth sub-operational amplifier is connected to the output end of the fourth sub-operational amplifier, and the output end of the fourth sub-operational amplifier is connected to the first end of the third impedance element.

10. The signal amplification circuit according to claim 8, wherein, The voltage control unit further includes a second quantizer, the second compensation capacitor includes a plurality of second sub-capacitors, and the first end of each second sub-capacitor is connected to the second input end of the first operational amplifier; The second quantizer is used to output a second digital signal according to the second reverse voltage, and the second digital signal is used to control the voltage at the second end of each second sub-capacitor.

11. A chip, characterized in that, Including the signal amplification circuit according to any one of claims 1 to 10 above.

12. An electronic device, characterized in that, Including a device main body and a chip as described in claim 11 above provided on the device main body.

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