Thin gate oxide high-voltage anti-backflow circuit of analog circuit and control method of thin gate oxide high-voltage anti-backflow circuit

Abstract

The invention provides a thin gate oxide high-voltage anti-backflow circuit of an analog circuit and a control method thereof. The thin gate oxide high-voltage anti-backflow circuit comprises an input end and an output end, the power tube PM1 is used for controlling a main current path; a source electrode of the anti-backflow power tube PM2 is connected with the output end, a drain electrode of the anti-backflow power tube PM2 is connected with a drain electrode of the PM1, and a grid electrode is connected to the bias current module through a resistor R1; the Zener diodes Z1 and Z2 are used for clamping the gate-source voltage to a preset reverse bias voltage; the input end of the comparator is respectively connected with the input end and the output end, and the output end of the comparator controls the on-off of the bias current module through the NM3; the bias current module is used for providing bias current for the R1 through mirror current; and the NM3 is used for isolating the high voltage of the output end voltage. According to the invention, the high-voltage MOS tube and the bias clamping circuit are reasonably arranged under the thin gate oxide process, so that the whole circuit structure is simple, the occupied hardware resources are small, the layout area and the number of mask layers are reduced, and the chip manufacturing cost is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and particularly to a thin gate oxide high-voltage anti-backflow circuit for analog circuits and a control method thereof. Background Art

[0002] In a high-voltage PMOS linear voltage regulator or other analog circuits, if the output voltage is higher than the input voltage, it will leak electricity to the input end through the substrate diode, resulting in the system being unable to ensure stable operation. At the same time, in a common high-voltage BCD process, the substrate and the source of the PLDMOS are often short-circuited and cannot be separated, which means that when the drain potential rises relative to the source or the substrate potential, a conduction path will always be formed, and it is difficult to block the backflow only by one PLDMOS. If a PDEMOS is used, since its substrate can be separated from the source, theoretically, the substrate and the gate can be connected to the drain to force it to turn off. However, the on-resistance per unit area of the PDEMOS is relatively large, and it is usually not suitable as a high-power transistor. Moreover, after connecting the substrate and the gate to the drain, the breakdown voltage of the drain is insufficient, which easily limits the high-voltage operating range of the circuit or even causes component damage.

[0003] Existing solutions (such as CN118841926A) propose to directly control the gate potential of the PMOS with a comparator composed of a triode. When the source potential is higher than the drain potential, the PMOS is turned off, thus avoiding the backflow from the source to the drain. However, there are still limitations when facing the situation where the substrate and the source of the PLDMOS cannot be separated or the breakdown voltage of the drain of the PDEMOS is insufficient. Summary of the Invention

[0004] To overcome the deficiencies of the prior art, the present invention proposes a thin gate oxide high-voltage anti-backflow circuit for analog circuits and a control method thereof. With the help of a multi-stage Zener array and substrate potential lifting technology, the output end can work safely within a wide voltage range, and through logical control and a high-voltage isolation transistor, the high voltage is isolated from the key sensitive nodes, thereby improving the breakdown voltage of the circuit and meeting the requirements of various high-voltage scenarios.

[0005] To achieve the above object, a thin gate oxide high-voltage anti-backflow circuit applied to an analog circuit according to the present invention includes:

[0006] An input end and an output end;

[0007] A power transistor PM1, which is a thin gate oxide laterally double-diffused P-type metal oxide semiconductor transistor, whose source is connected to the input end and whose drain is connected to the output end, and is used for controlling the main current path;

[0008] An anti-backflow power transistor PM2, which is a thin gate oxide P-type metal oxide semiconductor transistor, whose source is connected to the input end, whose drain is connected to the drain of PM1, and whose gate is connected to the bias current module through a resistor R1;

[0009] Zener diodes Z1 and Z2 are respectively connected between the gates and sources of power transistors PM1 and PM2 for clamping the gate-source voltage to a preset reverse bias voltage;

[0010] A comparator, with its input terminals respectively connected to the input terminal and the output terminal, and its output terminal controls the on / off of the bias current module through a high-voltage N-type laterally diffused transistor NM3;

[0011] The bias current module includes low-voltage N-type metal oxide semiconductor transistors NM1 and NM2, which provide a bias current for R1 through mirror current;

[0012] The high-voltage N-type laterally diffused transistor NM3 has its drain connected to the bias current module, its source grounded, and its gate controlled by the output of the comparator, for isolating the high voltage of the output terminal voltage;

[0013] Among them, when the input terminal voltage is lower than the output terminal voltage, the comparator outputs a low level, the high-voltage N-type laterally diffused transistor NM3 is turned off, both power transistors PM1 and PM2 are turned off, the reverse current is blocked, and there is no static power consumption at the output terminal voltage.

[0014] Furthermore, the device type of the power transistor PM2 is selected according to the level of the output terminal voltage:

[0015] When the output terminal voltage is lower than 5 volts, the power transistor PM2 is a low-voltage P-type metal oxide semiconductor transistor in a high-voltage well;

[0016] When the output terminal voltage is higher than 5 volts, the power transistor PM2 is a high-voltage P-type laterally diffused transistor or a high-voltage P-type depletion-mode laterally diffused transistor;

[0017] The reverse breakdown voltages of the Zener diodes Z1 and Z2 are 6 volts, for protecting the gate oxide withstand voltage of the power transistors PM1 and PM2;

[0018] The resistor R1 is a polysilicon resistor, for adjusting the conduction state of the power transistor PM2;

[0019] The NM1 and NM2 form an accurate current mirror to ensure the stability of the bias current.

[0020] Furthermore, when the input terminal voltage is floating or grounded, the comparator outputs a low level, both the power transistor PM2 and the power transistor PM1 are turned off, and there is no static current loss at both the output terminal voltage and the input terminal voltage;

[0021] The withstand voltage capacity of the high-voltage N-type laterally diffused transistor NM3 covers the highest operating voltage of the output terminal voltage, and its off state can completely isolate the high voltage of the output terminal.

[0022] Further, the gate oxide layer thickness of all metal-oxide semiconductor devices is the thin gate oxide thickness corresponding to the 5V process to reduce the chip area;

[0023] The substrate diodes D1 and D2 of the power transistors PM1 and PM2 have opposite polarities and are not conducting in the off state;

[0024] The circuit is applicable to high-voltage low-dropout linear voltage regulation or analog circuits that require an anti-backflow function, and is compatible with standard semiconductor processes.

[0025] 5. A control method for a thin gate oxide high-voltage anti-backflow circuit of an analog circuit, applicable to a thin gate oxide high-voltage anti-backflow circuit of an analog circuit, includes:

[0026] Step S1: When it is detected that the output voltage is higher than the input voltage, trigger the charge pump at a frequency proportional to the voltage difference to generate a negative voltage, limit the negative voltage within a specified range through a non-linear clamping network, and then apply the negative voltage to the gate of the power transistor;

[0027] Step S2: After confirming that the output voltage is greater than the input voltage, first use the fast turn-off pulse generated by the differential circuit to cut off the bias current of the anti-backflow power transistor, then release the gate charge of the main power transistor through the delayed signal of the integration circuit, and finally determine the turn-off timing of the high-voltage isolation transistor by the logic AND gate;

[0028] Step S3: Compare the voltage difference. When the voltage difference exceeds 0.5V and the rate of change is positive, directly cut off the bias current. When the voltage difference is lower than 0.2V, calculate and adjust the bias current in real time using the given proportional, integral, and differential coefficients;

[0029] Step S4: Input the voltage difference into the Sigma-Delta modulator to generate the pulse density D, then output a pulse sequence with an NMOS switch of a fixed conduction time, and set the average bypass current according to the product of the pulse density D and the peak current;

[0030] Step S5: Connect a configurable Zener array in parallel between the drain and gate of the power transistor and adjust the number of Zeners with the help of a dynamic fuse. At the same time, when it is detected that the output voltage is higher than the input voltage, raise the substrate potential of the anti-backflow power transistor to the output voltage plus 2V;

[0031] Step S6: Limit the gate-source voltage of all thin gate oxide devices (PM1, PM2, NM1~NM3) to below 6V through Zener diodes, and uniformly manufacture these devices using the 5V process.

[0032] Further, step S1 is specifically as follows:

[0033] Step S11: Continuously measure the output voltage and the input voltage through a comparator or a sampling circuit, and provide a "trigger signal" when it is determined that the output voltage is higher than the input voltage;

[0034] Step S12: Set the oscillation or switching frequency of the charge pump according to the "trigger signal" and the magnitude of the voltage difference : where k is a proportion coefficient designed internally, and start the pumping operation to generate a negative potential;

[0035] Step S13: Connect the negative potential output by the charge pump to a network containing a Zener diode and a variable resistor, and use the reverse breakdown characteristic of the Zener diode and the voltage drop generated by the variable resistor to keep the negative potential near :

[0036]

[0037] Wherein, : the negative voltage applied to the gate of the power transistor, which is the potential value in the clamping network.

[0038] : the regulated voltage value of the Zener diode during reverse breakdown, which can be determined by process or selection, such as 6V or other suitable values.

[0039] : the leakage current that may exist in the clamping network; it can be measured or estimated according to the leakage characteristics of the device in the design.

[0040] : variable resistor or temperature compensation resistor, used to adjust the resistance value when detecting changes in temperature or process conditions;

[0041] Step S14: Connect the above-mentioned negative potential to the gate ports of the power transistors (PM1, PM2) through internal wiring or external interconnection, and maintain the low leakage characteristic of this wiring path.

[0042] Further, step S2 is specifically as follows:

[0043] Step S21: Differentiate the signal of "output voltage higher than input voltage", set the RC constant of the differentiating circuit (such as ), and obtain a fast negative pulse with a time constant of about 10 ns;

[0044] Step S22: Output the differentiating pulse directly or through a gate circuit to the control end of the bias current source, and quickly cut off the bias current of the anti-backflow power transistor PM2;

[0045] Step S23: Integrate the same signal of "output voltage higher than input voltage", set the RC constant of the integrating circuit (such as ), and obtain a slowly varying voltage with a time constant of approximately 1 µs;

[0046] Step S24: Lead the output of the integration circuit to the gate control path of the main power transistor PM1, gradually release the gate charge of PM1, and turn it off after the bias is cut off;

[0047] Step S25: Perform a logical AND operation on the comparator output CMP OUT and the inverted signal INT of the integration circuit output OUT to obtain the gate signal of the high-voltage isolation transistor NM3, so as to determine the final switching state of NM3.

[0048] Further, step S3 specifically includes:

[0049] Sample the voltage difference and calculate the sign of, and determine whether the condition of " and " is satisfied;

[0050] Step S32: When the above conditions are confirmed, send a turn-off instruction to the bias current source to turn off the bias current and maintain this state until the condition change is detected again;

[0051] Step S33: At , calculate according to the given PID parameters (K p , K i , K d ):

[0052] ;

[0053] where, K p : The coefficient (proportional coefficient) proportional to the current voltage difference;

[0054] K i : The coefficient (integral coefficient) proportional to the integral of the voltage difference;

[0055] K d : The coefficient (differential coefficient) proportional to the rate of change of the voltage difference;

[0056] and output the result to the control port of the bias current source;

[0057] Step S34: Continuously detect using a window comparator, and when it crosses the 0.2 V or 0.5 V threshold, change the control mode of the bias current source (switch between "direct turn-off" and "PID regulation").

[0058] Further, step S4 specifically includes:

[0059] Step S41: Input the voltage difference into a similar modulation circuit and convert it into pulse density internally according to the slope factor ;

[0060] Step S42: Set the single-pulse conduction time (such as 10 ns), let the modulator output a series of pulse signals at the calculated pulse density D, and control the interleaving relationship between this pulse sequence and other clocks or communication frequency bands of the system;

[0061] Step S43: Connect the pulse sequence to the gate of the NMOS switch NM4, making it conduct when the pulse is at a high level and turn off when at a low level;

[0062] Step S44: Make the peak current during conduction be a specified value constantly, and obtain

[0063] ;

[0064] wherein : the average current controlled by the pulse density;

[0065] Thus, an average bypass current based on the duty cycle is obtained.

[0066] Further, Step S5 is specifically as follows:

[0067] Step S51: Connect multiple Zener diodes in parallel between the drain and gate of the power transistor, and connect them in series through internal or external wiring, so that the total breakdown voltage satisfies:

[0068] ;

[0069] wherein, : the total breakdown or total regulated voltage value obtained by connecting Zener diodes and ordinary diodes in series;

[0070] N: the actual number of Zener diodes participating in the series connection;

[0071] : the reverse breakdown voltage of a single Zener diode;

[0072] : the voltage drop of an ordinary diode when conducting forward;

[0073] And modify the series-connected Zener number N through the dynamic fuse.

[0074] Step S52: After detecting that the output voltage is higher than the preset value, trigger the internal fuse to blow, increase the Zener series number N, and complete the configuration change for high-voltage working conditions;

[0075] Step S53: When it is determined that the output voltage is higher than the input voltage, raise the substrate of PM2 to V OUT +2V through the substrate bias network or an external reference power supply, and maintain this substrate bias;

[0076] Step S6 is specifically as follows:

[0077] Step S61: Select a Zener diode compatible with the 5V process and connect it in parallel across the gate-source terminals of PM1, PM2, and NM1~NM3 so that the gate-source voltage does not exceed approximately 6V;

[0078] Step S62: In layout and manufacturing, stipulate that all involved MOS devices are laid out according to the 5V thin gate oxide specification, and reserve a placement area for the clamping diode in the design layout;

[0079] Step S63: Connect the Zener diode clamping node to between the gate and source of each MOS device through metal interconnection or via holes between layers, and avoid direct coupling of large current nodes with this clamping path during circuit wiring.

[0080] Compared with the prior art, the beneficial effects of the present invention are:

[0081] 1. The present invention provides a thin gate oxide high-voltage anti-backflow circuit for an analog circuit and its control method. By reasonably arranging high-voltage MOS transistors and bias clamping circuits under the thin gate oxide process, and combining functional units such as charge pumps and comparators to hierarchically control the main power transistor and the anti-backflow transistor, the overall circuit architecture is simple, the hardware resources occupied are small, which helps to reduce the board layout area and the number of mask layers, and reduces the chip manufacturing cost.

[0082] 2. The present invention provides a thin gate oxide high-voltage anti-backflow circuit for an analog circuit and its control method. When the circuit is in an off state or abnormal situations such as the output terminal voltage being higher than the input terminal voltage, the gate bias and substrate potential of the power transistor will be automatically switched to the deep-off or lifted state, and the excess bias current will be turned off or become a pulsed minimum flow, so that a very low static power consumption is maintained without affecting the core function.

[0083] 3. The present invention provides a thin gate oxide high-voltage anti-backflow circuit for an analog circuit and its control method. With the help of a multi-stage Zener array and substrate potential lifting technology, the output terminal can work safely within a wide voltage range, and through logical control and cooperation with high-voltage isolation transistors, high voltages are isolated from key sensitive nodes, thereby improving the voltage withstand capacity of the circuit and meeting the requirements of various high-voltage scenarios.

[0084] 4. The present invention provides a thin gate oxide high-voltage anti-backflow circuit for analog circuits and its control method, which can be implemented in common process platforms such as BCD and CMOS. In addition, the overall circuit design does not rely on special mask layers or proprietary materials, making it have good versatility and mass producibility, which helps to quickly introduce mass production and reuse in different processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0085] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the following drawings are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0086] Figure 1 is the circuit structure diagram

[0087] Figure 2 is the schematic diagram of the steps of the present invention

[0088] Figure 3 is the equivalent circuit structure diagram of Fig4 in the anti-backflow state DETAILED DESCRIPTION OF THE EMBODIMENTS

[0089] The following will more clearly and completely elaborate the technical solutions of the present invention by describing the preferred embodiments of the present invention in conjunction with the drawings.

[0090] As Figure 1 shown, it is the circuit structure diagram of the present invention, where PM1 is a power transistor, which is a thin gate oxide PLDMOS, and PM2 is an anti-backflow power transistor, which is also a thin gate oxide PMOS. According to the magnitude of the output voltage, a high-voltage PLDMOS or a low-voltage PMOS in a high-voltage well can be selected. R1 is a poly resistor, and Z1 and Z2 are Zener diodes, whose reverse bias voltage is about 6V, used to protect the gate oxides of PM1 and PM2 from being damaged by high voltage. NM1 and NM2 are low-voltage NMOSs, and NM3 is a high-voltage NLDMOS. CMP is a comparator that compares the magnitudes of VIN and VOUT voltages.

[0091] During normal operation, PM1 is controlled by a drive circuit, such as an error amplifier, etc., and is in the conducting state. Ib is the bias current. Through the mirror relationship between NM1 and NM2, a current bias is provided for the resistor R1 to make PM2 in a fully conducting state. NM1 and NM2 are low-voltage NMOSs with accurate mirroring. At this time, VIN is higher than the VOUT voltage, and CMP outputs a high potential, and NM3 is in a fully conducting state. NM3 is a high-voltage NLDMOS, which can withstand the high voltage at the VOUT end and isolate the high voltage for NM2 at the same time. At this time, PM1 is in the conducting state, PM2 is in the fully conducting state, and the system operates normally.

[0092] When VIN exists and the voltage is lower than the VOUT voltage, the output of the CMP comparator is at a low voltage. At this time, the current bias disappears, the GATE and SOURCE terminals of PM2 are short-circuited by a resistor, PM2 is completely turned off, and at the same time, the CMP comparator also controls the internal circuit to turn off PM1. At this time, the equivalent structure of the circuit is as Figure 3 shown. Under this equivalent structure, both PM1 and PM2 are completely turned off, forming a complete electrical isolation from VIN to VOUT. The substrate diodes D1 and D2 have opposite polarities and will not conduct either. Figure 1 NM3 in [[ ]] is also completely turned off, and there is no static current consumption at the VOUT terminal. This structure not only ensures that no current flows from VOUT to VIN, but also ensures that there is no static power consumption of VOUT to GND.

[0093] At this time, if the VOUT voltage is lower than 5V, PM2 can select a low-voltage PMOS located in the high-voltage well, and the voltage difference between its four ports will not exceed 5V. If the VOUT voltage is higher than 5V, then a high-voltage PLDMOS or a high-voltage PDEMOS is selected, depending on which device occupies a smaller layout area.

[0094] When VIN is floating or VIN is grounded, the internal bias current of the chip disappears, the output of the VIN and VOUT comparator is low, and PM2 is completely turned off. At this time, there is no static loss at both the VIN and VOUT terminals, and the chip power consumption is extremely low. At the same time, PM2 can withstand the high voltage at the VOUT terminal.

[0095] Whether VIN is higher than VOUT or VOUT is higher than VIN, the gate-source voltage of all MOSs is clamped at the Zener voltage or below 6V. Therefore, all MOSs can adopt the thin gate oxide process, that is, the process with a 5V gate oxide thickness, which greatly reduces the area of the chip.

[0096] As Figure 2 shown, the control method is as follows:

[0097] Step S1: When it is detected that the output voltage is higher than the input voltage, trigger the charge pump to generate a negative voltage at a frequency proportional to the voltage difference, limit the negative voltage within a specified range through a non-linear clamping network, and then apply the negative voltage to the gate of the power transistor;

[0098] Step S2: After confirming that the output voltage is greater than the input voltage, first use the fast turn-off pulse generated by the differential circuit to cut off the bias current of the anti-backflow power transistor, then release the gate charge of the main power transistor through the delayed signal of the integration circuit, and finally determine the turn-off timing of the high-voltage isolation transistor by the logic AND gate;

[0099] Step S3: Compare the voltage difference. When the voltage difference exceeds 0.5V and the change rate is positive, directly cut off the bias current. When the voltage difference is lower than 0.2V, calculate and adjust the bias current in real time using the given proportional, integral, and differential coefficients;

[0100] Step S4: Input the voltage difference into a Sigma-Delta modulator to generate a pulse density D, then output a pulse sequence through an NMOS switch with a fixed on-time, and set the average bypass current according to the product of the pulse density D and the peak current;

[0101] Step S5: Connect a configurable Zener array in parallel between the drain and gate of the power transistor and adjust the number of Zeners with the help of a dynamic fuse. At the same time, when it is detected that the output voltage is higher than the input voltage, raise the substrate potential of the anti-backflow power transistor to the output voltage plus 2V;

[0102] Step S6: Limit the gate-source voltage of all thin gate oxide devices to below 6V through Zener diodes, and uniformly manufacture these devices using a 5V process.

[0103] As a specific implementation, select a 5V thin gate oxide process and uniformly arrange the gate oxide thickness of all MOS devices when designing the layout, making PM1 and PM2 P-type transistors, and NM1, NM2, and NM3 N-type transistors, and reserve a clamping area for the Zener diode during layout. Connect the input terminal and the output terminal to the pins or pads of the chip respectively, and compare the voltages of these two ports through a comparator. When the comparator determines that the output terminal voltage is higher than the input terminal voltage, it outputs a high-level trigger signal to the subsequent control unit.

[0104] After receiving the trigger signal, the charge pump circuit starts to work and sets the operating frequency to be proportional to the difference between the output terminal voltage and the input terminal voltage, thereby generating a negative potential. To avoid excessive pulling down of the negative potential, connect a network composed of a Zener diode and a variable resistor in series at the output terminal of the charge pump, and considering the influence of the internal leakage current, limit the negative potential within a specific negative voltage range by this network. Connect this negative potential to the gates of PM1 and PM2 to guide them into a deep-off state.

[0105] The high-level signal output by the comparator triggers both the differentiating circuit and the integrating circuit simultaneously. The time constant of the differentiating circuit can be set at a relatively short magnitude (e.g., about 10 nanoseconds) to generate an extremely fast pulse signal, thereby immediately turning off the bias current source for driving PM2. The time constant of the integrating circuit is set at a relatively large magnitude (e.g., about 1 microsecond), causing the voltage output by it to change slowly, so as to gradually release the gate charge of PM1 after the bias of PM2 is cut off. The gate signal of the high-voltage isolation transistor NM3 is controlled by a logical AND gate. The inputs of this gate include the output of the comparator and the inverted signal of the output of the integrating circuit, and through reasonable logical combination, NM3 is coordinated with the turn-off sequence of PM1 and PM2.

[0106] Regarding the regulation of the bias current, first monitor the voltage difference between the output terminal and the input terminal and the change rate of this voltage difference. If the voltage difference exceeds a certain threshold and is still rising, directly send a turn-off instruction to the bias current source to keep the bias current at zero. When the voltage difference drops below a lower threshold, switch to regulating the bias current according to the results calculated by the proportional, integral, and differential coefficients, and set appropriate units for these three coefficients in the circuit to accurately control the tiny bias current flowing through PM2 or other components. To meet the requirements for a small amount of reverse current in a specific scenario, a pulse density modulation unit can also be adopted. By sending the difference between the output voltage and the input voltage into a modulator with a slope factor set, a pulse sequence is obtained, and intermittent conduction is achieved by cooperating with a fixed-width pulse conduction time. The peak current of each conduction can be set to a relatively high but extremely short value, and the overall average current magnitude is determined by the density of the pulse appearance.

[0107] To adapt to a higher voltage environment, several Zener diodes and PN junction diodes are connected in parallel between the drain and gate of PM1 and PM2. The number of Zener diodes in series is dynamically changed through a fusible link structure to increase the total breakdown voltage in stages. When it is detected that the output terminal voltage exceeds a certain excessive threshold, the fuse is melted to increase the number of Zener diodes in series, thereby raising the voltage level that the device can withstand. At the same time, through a bias network or an external reference, the substrate potential of PM2 is raised to a certain amplitude higher than the output terminal voltage to prevent the substrate parasitic diode from conducting. For all MOS transistors used in the entire circuit, Zener diodes are connected in parallel between the gate and the source, and their breakdown voltages are selected to be about 6V, so that each MOS transistor can maintain a safe gate-source voltage under the condition of a large potential difference that may occur. During layout, sufficient silicon area is reserved for devices such as Zener diodes and fusible links, and attention is paid to isolating the large current and the protection path to meet the design rules during mass production.

[0108] The above specific embodiments only describe the preferred embodiments of the present invention, rather than limiting the protection scope of the present invention. Without departing from the design concept and spirit of the present invention, various deformations, substitutions and improvements made by those of ordinary skill in the art to the technical solutions of the present invention according to the written description and drawings provided by the present invention shall fall within the protection scope of the present invention. The protection scope of the present invention is determined by the claims.

Claims

1. A thin gate oxide high-voltage anti-backflow circuit for analog circuits, characterized in that, Comprising: An input terminal and an output terminal; A power transistor PM1, which is a thin-gate-oxide laterally diffused P-type metal oxide semiconductor transistor, whose source is connected to the input terminal, and whose drain is connected to the drain of PM2, and is used for controlling the main current path; An anti-backflow power transistor PM2, which is a thin-gate-oxide laterally diffused P-type metal oxide semiconductor transistor, whose source is connected to the output terminal, and whose drain is connected to the drain of PM1, and whose gate is connected to the bias current module through a resistor R1; Zener diodes Z1 and Z2, which are respectively connected between the gate and the source of the power transistor PM1 and the power transistor PM2, and are used for clamping the gate-source voltage to a preset reverse bias voltage; The input terminals of the comparator are respectively connected to the input terminal and the output terminal, and the output terminal of the comparator controls the on / off of the bias current module through a high-voltage N-type laterally diffused transistor NM3; The bias current module includes low-voltage N-type metal oxide semiconductor transistors NM1 and NM2, and provides a bias current for R1 through mirror current; A high-voltage N-type laterally diffused transistor NM3, whose drain is connected to the bias current module, whose source is connected to the drain of NM2, and whose gate is controlled by the output of the comparator, and is used for isolating the high voltage of the output terminal voltage; Wherein, when the input terminal voltage is lower than the output terminal voltage, the comparator outputs a low level, the high-voltage N-type laterally diffused transistor NM3 is turned off, both the power transistor PM1 and the power transistor PM2 are turned off, the backflow current is blocked, and there is no static power consumption at the output terminal voltage.

2. The thin gate oxide high-voltage anti-backflow circuit for an analog circuit according to claim 1, wherein The device type of the power transistor PM2 is selected according to the level of the output terminal voltage: When the output terminal voltage is lower than 5 volts, the power transistor PM2 is a low-voltage P-type metal oxide semiconductor transistor in a high-voltage well; When the output terminal voltage is higher than 5 volts, the power transistor PM2 is a high-voltage P-type laterally diffused transistor or a high-voltage P-type double-diffused transistor; The reverse breakdown voltages of the Zener diodes Z1 and Z2 are 6 volts, and are used for protecting the gate oxide withstand voltage of the power transistor PM1 and the power transistor PM2; The resistor R1 is a polysilicon resistor, and is used for adjusting the conduction state of the power transistor PM2; The NM1 and NM2 form an accurate current mirror to ensure the stability of the bias current.

3. The thin gate oxide high-voltage anti-backflow circuit of an analog circuit according to claim 1, wherein When the input terminal voltage is floating or grounded, the comparator outputs a low level, both the power transistor PM2 and the power transistor PM1 are turned off, and there is no static current loss at both the output terminal voltage and the input terminal voltage; The withstand voltage capacity of the high-voltage N-type laterally diffused transistor NM3 covers the highest operating voltage of the output terminal voltage, and its high voltage at the output terminal can be completely isolated in the off state.

4. The thin gate oxide high-voltage anti-backflow circuit of an analog circuit according to claim 1, wherein The gate oxide layer thickness of all metal oxide semiconductor devices is the thin-gate-oxide thickness corresponding to the 5V process to reduce the chip area; The substrate diodes D1 and D2 of the power transistor PM1 and the power transistor PM2 have opposite polarities and are not conducting in the off state; The circuit is applicable to high-voltage low-dropout linear voltage regulation or analog circuits that require an anti-backflow function, and is compatible with standard semiconductor processes.

5. A control method for a thin gate oxide high-voltage anti-backflow circuit of an analog circuit, applicable to the thin gate oxide high-voltage anti-backflow circuit of an analog circuit described in any one of claims 1-4, characterized in that, Including: Step S1: When it is detected that the output voltage is higher than the input voltage, trigger a charge pump to generate a negative voltage at a frequency proportional to the voltage difference, limit the negative voltage within a specified range through a non-linear clamping network, and then apply the negative voltage to the gate of the power transistor; Step S2: After confirming that the output voltage is greater than the input voltage, first use the fast turn-off pulse generated by the differential circuit to cut off the bias current of the anti-backflow power transistor, then release the gate charge of the main power transistor through the delayed signal of the integration circuit, and finally determine the turn-off timing of the high-voltage isolation transistor by the logic AND gate; Step S3: Compare the voltage difference. When the voltage difference exceeds 0.5V and the change rate is positive, directly cut off the bias current. When the voltage difference is lower than 0.2V, calculate and adjust the bias current in real time using the given proportional, integral, and differential coefficients; Step S4: Input the voltage difference into the Sigma-Delta modulator to generate the pulse density D, then output a pulse sequence with an NMOS switch of a fixed conduction time, and set the average bypass current according to the product of the pulse density D and the peak current; Step S5: Connect a configurable Zener array in parallel between the drain and gate of the power transistor and adjust the number of Zeners with the help of a dynamic fuse. At the same time, when it is detected that the output voltage is higher than the input voltage, raise the substrate potential of the anti-backflow power transistor to the output voltage plus 2V; Step S6: Limit the gate-source voltage of all thin-gate-oxide devices to below 6V through Zener diodes, and uniformly manufacture these devices using a 5V process.

6. A control method for a thin gate oxide high-voltage anti-backflow circuit of an analog circuit according to claim 5, characterized in that, Step S1 is specifically as follows: Step S11: Continuously measure the output voltage and the input voltage through a comparator or a sampling circuit, and provide a "trigger signal" when it is determined that the output voltage is higher than the input voltage; Step S12: Set the oscillation or switching frequency of the charge pump according to the "trigger signal" and the magnitude of the voltage difference : , where k is a proportionality coefficient designed internally, and start the pumping operation to generate a negative potential; Step S13: Connect the negative potential output by the charge pump to the network containing the Zener diode and the variable resistor, and utilize the reverse breakdown characteristic of the Zener diode and the voltage drop generated by the variable resistor to maintain the negative potential at nearby: Among them, : The negative voltage applied to the gate of the power transistor, which is the potential value in the clamping network; : The regulated voltage value of the Zener diode when it undergoes reverse breakdown; : Leakage current that may exist in the clamping network; : Variable resistor or temperature compensation resistor; Step S14: Connect the above negative potential to the gate ports of the power transistors PM1 and PM2 through internal wiring or external interconnection, and maintain the low leakage characteristic of the wiring path.

7. A control method for a thin gate oxide high-voltage anti-backflow circuit of an analog circuit according to claim 5, characterized in that Step S2 is specifically as follows: Step S21: Differentiate the signal of "output voltage higher than input voltage", set the RC constant of the differential circuit, and obtain a fast negative pulse with a time constant of about 10ns; Step S22: Output the differential pulse directly or through a gate circuit to the control terminal of the bias current source to quickly cut off the bias current of the anti-backflow power transistor PM2; Step S23: Integrate the same signal of "output voltage higher than input voltage", set the RC constant of the integration circuit, and obtain a slowly varying voltage with a time constant of about 1µs; Step S24: Lead the output of the integration circuit to the gate control path of the main power transistor PM1 to gradually release the gate charge of PM1, so that it turns off after the bias is cut off; Step S25: Perform a logical AND operation on the comparator output CMP OUT and the inverted signal INT output by the integration circuit OUT to obtain the gate signal of the high-voltage isolation transistor NM3, which is used to determine the final switching state of NM3.

8. A control method for a thin gate oxide high-voltage anti-backflow circuit of an analog circuit according to claim 5, characterized in that, Step S3 specifically includes: Step S31: Sample the voltage difference and calculate the sign of, and determine whether it satisfies the condition of " and "; Step S32: When confirming the condition in Step S31, send a turn-off instruction to the bias current source to turn off the bias current and maintain the state until the condition change is detected again; Step S33: At , calculate according to the given PID parameters (K p , K i , K d ): ； where K p : a coefficient (proportionality coefficient) proportional to the current voltage difference; K i : a coefficient (integration coefficient) proportional to the integrated value of the voltage difference; K d : a coefficient (differential coefficient) proportional to the rate of change of the voltage difference; And output the result to the control port of the bias current source; Step S34: Use a window comparator to continuously detect it. When it crosses the 0.2V or 0.5V threshold, change the control mode of the bias current source.

9. A control method for a thin gate oxide high-voltage anti-backflow circuit of an analog circuit according to claim 5, characterized in that, Step S4 specifically includes: Step S41: Input the voltage difference into a similar modulation circuit and convert it into pulse density internally according to the slope factor ; Step S42: Set the single-pulse conduction time, let the modulator output a series of pulse signals with the calculated pulse density D, and control the interleaving relationship between the pulse sequence and other system clocks or communication frequency bands; Step S43: Connect the pulse sequence to the gate of the NMOS switch NM4, make it conduct when the pulse is at a high level, and turn off when it is at a low level; Step S44: Make the peak current during conduction be a specified value constantly, and obtain ； Among them : The average current obtained by pulse density control; Thus, an average bypass current based on the time duty cycle is obtained.

10. A control method for a thin gate oxide high-voltage anti-backflow circuit of an analog circuit according to claim 5, characterized in that, Step S5 is specifically as follows: Step S51: Connect multiple Zener diodes in parallel between the drain and gate of the power transistor, and connect them in series through internal or external wiring so that the total breakdown voltage satisfies: ； Among them, : The total breakdown or total regulated voltage value obtained by connecting Zener diodes and ordinary diodes in series; N: The number of Zener diodes actually participating in the series connection; : Reverse breakdown voltage of a single Zener diode; : The voltage drop of a common diode when it is forward-conducting; And modify the number of series-connected Zener diodes N through the dynamic fuse; Step S52: After detecting that the output voltage is higher than the preset value, trigger the internal fuse to blow, increase the number of series-connected Zener diodes N, and complete the configuration change for high-voltage working conditions; Step S53: When it is determined that the output voltage is higher than the input voltage, raise the substrate of PM2 to V OUT +2V through the substrate bias network or an external reference power supply, and maintain the substrate bias; Step S6 is specifically as follows: Step S61: Select a Zener diode compatible with the 5V process and connect it in parallel at the gate-source terminals of PM1, PM2, and NM1~NM3 so that the gate-source voltage does not exceed about 6V; Step S62: Specify in the layout and manufacturing that all involved MOS devices are laid out according to the 5V thin gate oxide specification, and reserve the placement area for the clamping diode in the design layout; Step S63: Connect the Zener diode clamping node between the gate and source of each MOS device through metal interconnection or via holes between layers, and avoid direct coupling between the high-current node and the clamping path during circuit wiring.

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