A thin gate oxide high-voltage anti-backflow circuit for analog circuits and its control method

Abstract

The present invention proposes a thin-gate-oxide high-voltage backflow prevention circuit for an analog circuit and a control method thereof. The circuit comprises an input terminal and an output terminal; a power transistor PM1 for controlling the main current path; an anti-backflow power transistor PM2, whose source is connected to the output terminal, whose drain is connected to the drain of PM1, and whose gate is connected to a bias current module via a resistor R1; Zener diodes Z1 and Z2 for clamping the gate-source voltage to a preset reverse bias voltage; a comparator whose input terminal is connected to the input terminal and the output terminal, respectively, and whose output terminal controls the on / off of the bias current module via a resistor NM3; a bias current module that provides bias current to R1 via a mirrored current; and NM3 for isolating the high voltage of the output terminal voltage. By rationally arranging the high-voltage MOS transistors and the bias clamping circuit using a thin-gate-oxide process, the present invention simplifies the overall circuit architecture and minimizes hardware resource usage, thereby helping to reduce layout area and the number of mask layers, thereby lowering chip manufacturing costs.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a thin-gate-oxide high-voltage backflow prevention circuit for an analog circuit and a control method thereof. Background Art

[0002] In high-voltage PMOS linear regulators or other analog circuits, if the output voltage is higher than the input voltage, current will leak to the input through the substrate diode, causing the system to be unable to ensure stable operation. At the same time, in common high-voltage BCD processes, the substrate and source of PLDMOS are often short-circuited and cannot be separated. This means that when the drain potential increases relative to the source or substrate, a conduction path will always be formed, making it difficult to block backflow with only a single PLDMOS. If PDEMOS is used instead, since its substrate can be separated from the source, theoretically both the substrate and the gate can be connected to the drain to force shutdown. However, the on-resistance per unit area of PDEMOS is relatively large, making it generally unsuitable for use as a high-power transistor. Moreover, after connecting both the substrate and the gate to the drain, the drain's voltage resistance is insufficient, which can easily limit the circuit's high-voltage range and even cause component damage.

[0003] Existing solutions (such as CN118841926A) have proposed using a comparator composed of transistors to directly control the gate potential of the PMOS. When the source potential is higher than the drain potential, the PMOS is turned off, thereby preventing backflow from the source to the drain. However, this approach still has limitations when the PLDMOS substrate and source cannot be separated or the PDEMOS drain voltage resistance is insufficient. Summary of the Invention

[0004] In order to overcome the shortcomings of the existing technology, the present invention proposes a thin-gate-oxide high-voltage anti-backflow circuit for analog circuits and a control method thereof. With the help of a multi-level Zener array and substrate potential raising technology, the output end can operate safely within a wider voltage range, and through logic control and high-voltage isolation tubes, the high voltage is isolated from key sensitive nodes, thereby improving the circuit's voltage resistance and meeting the needs of various high-voltage scenarios.

[0005] To achieve the above-mentioned object, the present invention provides a thin-gate-oxide high-voltage backflow prevention circuit for analog circuits, comprising:

[0006] Input and output terminals;

[0007] The power transistor PM1 is a thin gate oxide laterally double diffused P-type metal oxide semiconductor transistor, with its source connected to the input terminal and its drain connected to the output terminal, used for main current path control;

[0008] The anti-backflow power transistor PM2 is a thin-gate-oxide P-type metal oxide semiconductor transistor, whose source is connected to the input terminal, the drain is connected to the drain of PM1, and the gate is connected to the bias current module through the resistor R1;

[0009] Zener diodes Z1 and Z2 are connected between the gate and source of power transistors PM1 and PM2, respectively, and are used to clamp the gate-source voltage to a preset reverse bias voltage;

[0010] The comparator has its input connected to the input and output terminals respectively, and the output terminal controls the on / off of the bias current module through the high-voltage N-type lateral double diffuser NM3;

[0011] A bias current module, including low-voltage N-type metal oxide semiconductor transistors NM1 and NM2, provides a bias current for R1 through a mirror current;

[0012] A high-voltage N-type lateral double diffused tube NM3, whose drain is connected to the bias current module, source is grounded, and gate is controlled by the comparator output, and is used to isolate the high voltage of the output terminal voltage;

[0013] Among them, when the input voltage is lower than the output voltage, the comparator outputs a low level, the high-voltage N-type lateral double diffuser NM3 is turned off, the power tube PM1 and the power tube PM2 are both turned off, the backflow current is blocked, and the output voltage has no static power consumption.

[0014] Furthermore, the device type of the power transistor PM2 is selected according to the level of the output terminal voltage:

[0015] When the output voltage is lower than 5V, the power transistor PM2 is a low-voltage P-type metal oxide semiconductor transistor in the high-voltage well;

[0016] When the output voltage is higher than 5V, the power tube PM2 is a high-voltage P-type lateral double diffused tube or a high-voltage P-type depletion lateral double diffused tube;

[0017] The reverse breakdown voltage of the Zener diodes Z1 and Z2 is 6V, which is used to protect the gate oxide withstand voltage of the power transistors PM1 and PM2;

[0018] The resistor R1 is a polysilicon resistor used to adjust the conduction state of the power transistor PM2;

[0019] The NM1 and NM2 form a precise current mirror to ensure the stability of the bias current.

[0020] Furthermore, when the input voltage is floating or grounded, the comparator outputs a low level, the power transistors PM2 and PM1 are both turned off, and there is no static current consumption for both the output voltage and the input voltage;

[0021] The voltage resistance of the high-voltage N-type lateral double diffuser NM3 covers the highest operating voltage of the output terminal voltage, and in the off state, the high voltage of the output terminal can be completely isolated.

[0022] Furthermore, the gate oxide thickness of all metal oxide semiconductor devices is a thin gate oxide thickness corresponding to the 5V process to reduce the chip area;

[0023] The substrate diodes D1 and D2 of the power transistors PM1 and PM2 have opposite polarities and are non-conductive in the off state;

[0024] The circuit is suitable for high-voltage and low-voltage-difference linear voltage regulation or analog circuits requiring backflow prevention functions, and is compatible with standard semiconductor process implementation.

[0025] 5. A control method for a thin-gate-oxide high-voltage backflow prevention circuit for an analog circuit, applicable to a thin-gate-oxide high-voltage backflow prevention circuit for an analog circuit, comprising:

[0026] Step S1: When it is detected that the output voltage is higher than the input voltage, the charge pump is triggered to generate a negative voltage at a frequency proportional to the voltage difference, the negative voltage is limited to a specified range through a nonlinear clamping network, and then the negative voltage is applied to the gate of the power tube;

[0027] Step S2: After confirming that the output voltage is greater than the input voltage, the bias current of the anti-backflow power tube is first cut off using the fast shutdown pulse generated by the differential circuit. Then, the gate charge of the main power tube is released through the delayed signal of the integration circuit. Finally, the logic AND gate determines the shutdown timing of the high-voltage isolation tube.

[0028] Step S3: Compare the voltage difference. When the voltage difference exceeds 0.5V and the rate of change is positive, the bias current is directly cut off. When the voltage difference is less than 0.2V, the bias current is calculated using given proportional, integral, and differential coefficients and adjusted in real time.

[0029] Step S4: Inputting the voltage difference into a Sigma-Delta modulator to generate a pulse density D, then outputting a pulse train using an NMOS switch with a fixed on-time, and setting an average bypass current based on the product of the pulse density D and the peak current;

[0030] Step S5: Connect a configurable Zener array in parallel between the drain and gate of the power tube and adjust the number of Zeners with the help of dynamic fuses. At the same time, when it is detected that the output voltage is higher than the input voltage, the substrate potential of the anti-backflow power tube is increased to the output voltage plus 2V;

[0031] Step S6: limiting the gate-source voltage of all thin-gate oxide devices (PM1, PM2, NM1-NM3) to below 6V through Zener diodes, and uniformly adopting a 5V process to manufacture these devices.

[0032] Furthermore, step S1 is specifically as follows:

[0033] Step S11: Continuously measure the output voltage and the input voltage through a comparator or sampling circuit, and provide a "trigger signal" when it is determined that the output voltage is higher than the input voltage;

[0034] Step S12: According to the “trigger signal” and the voltage difference The size of , sets the oscillation or switching frequency of the charge pump: , where k is an internally designed proportionality coefficient, and begins pumping operation to generate a negative potential;

[0035] Step S13: Connect the negative potential output by the charge pump to a network containing a Zener diode and a variable resistor, and use the reverse breakdown characteristics of the Zener diode and the voltage drop generated by the variable resistor to keep the negative potential at nearby:

[0036]

[0037] in, : The potential value of the negative voltage applied to the power tube gate in the clamping network.

[0038] : The regulated voltage value of the Zener diode during reverse breakdown can be determined by process or selection, such as 6V or other adaptive values.

[0039] : Leakage current that may exist in the clamping network; during design, it can be measured or estimated based on the device leakage characteristics.

[0040] : Variable resistor or temperature compensation resistor, used to adjust resistance when changes in temperature or process conditions are detected;

[0041] Step S14: Connect the negative potential to the gate ports of the power transistors (PM1, PM2) through internal wiring or external interconnection, and maintain the low leakage characteristics of the wiring path.

[0042] Furthermore, step S2 is specifically as follows:

[0043] Step S21: Perform differential processing on the signal of “output voltage is higher than input voltage” and set the RC constant of the differential circuit (such as ), and obtain a fast negative pulse with a time constant of about 10ns;

[0044] Step S22: Outputting the differential pulse directly or through a gate circuit to the control end of the bias current source to quickly cut off the bias current of the anti-backflow power transistor PM2;

[0045] Step S23: Integrate the same “output voltage is higher than input voltage” signal and set the RC constant of the integration circuit (e.g. ), and obtain a slowly varying voltage with a time constant of about 1µs;

[0046] Step S24: directing the output of the integration circuit to the gate control path of the main power transistor PM1, gradually releasing the gate charge of PM1 so that it is turned off again after the bias is cut off;

[0047] Step S25: Comparator output CMP OUT The inverted signal INT output by the integration circuit OUT A logical AND operation is performed to obtain a gate signal of the high-voltage isolation transistor NM3, which is used to determine the final switching state of NM3.

[0048] Furthermore, step S3 specifically includes:

[0049] Voltage difference Take samples and calculate The symbol of , judge whether it satisfies " and "Conditions;

[0050] Step S32: When the above conditions are confirmed, a shutdown instruction is sent to the bias current source to make the bias current And maintain this state until the condition change is detected again;

[0051] Step S33: When the given PID parameters (K p ,K i ,K d )calculate:

[0052] ;

[0053] Among them, K p : A coefficient proportional to the current voltage difference (proportional coefficient);

[0054] K i : A coefficient proportional to the integral of the voltage difference (integral coefficient);

[0055] K d : Coefficient proportional to the rate of change of voltage difference (differential coefficient);

[0056] And output the result to the control port of the bias current source;

[0057] Step S34: Use the window comparator to compare Continuous detection is performed, and when it crosses the 0.2V or 0.5V threshold, the control mode of the bias current source is changed (switching between "direct shutdown" and "PID regulation").

[0058] Furthermore, step S4 specifically includes:

[0059] Step S41: The voltage difference Input to a similar modulation circuit and internally based on the slope factor Convert to pulse density;

[0060] Step S42: Setting the single pulse on-time (e.g., 10 ns) to allow the modulator to output a pulse sequence with the calculated pulse density D, and controlling the interleaving relationship between the pulse sequence and other system clocks or communication frequency bands;

[0061] Step S43: Connect the pulse sequence to the gate of the NMOS switch NM4, so that it is turned on when the pulse is at a high level and turned off when the pulse is at a low level;

[0062] Step S44: Make the peak current during conduction constant at a specified value, and obtain the value by adjusting the pulse density D.

[0063] ;

[0064] in : Average current obtained by pulse density control;

[0065] This results in an average bypass current based on the time duty cycle.

[0066] Furthermore, step S5 is specifically as follows:

[0067] Step S51: Connect multiple Zener diodes in parallel between the drain and gate of the power tube, and connect them in series through internal or external wiring so that the total breakdown voltage satisfies:

[0068] ;

[0069] in, : The total breakdown or total regulated voltage obtained by connecting a Zener and a normal diode in series;

[0070] N: the number of Zener diodes actually connected in series;

[0071] : Reverse breakdown voltage of a single Zener diode;

[0072] : The voltage drop of an ordinary diode when it is forward-conducting;

[0073] And the number N of Zeners in series is modified through dynamic fuses.

[0074] Step S52: After detecting that the output voltage is higher than the preset value, the internal fuse is triggered to blow, and the number of Zeners connected in series N is increased to complete the configuration change for the high voltage working condition;

[0075] Step S53: When it is determined that the output voltage is higher than the input voltage, the substrate of PM2 is raised to V OUT +2V, and maintain the substrate bias;

[0076] Step S6 is specifically as follows:

[0077] Step S61: Select a Zener diode compatible with the 5V process and connect it in parallel to the gate-source terminals of PM1, PM2, and NM1-NM3 so that the gate-source voltage does not exceed about 6V;

[0078] Step S62: During layout and manufacturing, it is stipulated that all involved MOS devices are laid out according to 5V thin gate oxide specifications, and a placement area for clamping diodes is reserved in the design layout;

[0079] Step S63: Connect the Zener diode clamping node between the gate and source of each MOS device through metal interconnection or interlayer vias, and avoid direct coupling of high current nodes with the clamping path during circuit wiring.

[0080] Compared with the prior art, the present invention has the following beneficial effects:

[0081] 1. The present invention provides a thin-gate-oxide high-voltage backflow prevention circuit for analog circuits and its control method. By rationally laying out high-voltage MOS transistors and bias clamping circuits in a thin-gate-oxide process, and combining functional units such as charge pumps and comparators to hierarchically control the main power transistors and backflow prevention transistors, the overall circuit architecture is simple and hardware resources are minimal, thereby helping to reduce board layout area and the number of mask layers, thereby lowering chip manufacturing costs.

[0082] 2. The present invention provides a thin-gate-oxide high-voltage backflow prevention circuit for an analog circuit and a control method thereof. When the circuit is in an off state or in abnormal situations such as when the output voltage is higher than the input voltage, the gate bias and substrate potential of the power tube will be automatically switched to a deep off or raised state, and the excess bias current will be turned off or converted to a pulsed minimum flow, thereby maintaining extremely low static power consumption without affecting the core function.

[0083] 3. The present invention provides a thin-gate-oxide high-voltage anti-backflow circuit for an analog circuit and a control method thereof. With the help of a multi-level Zener array and substrate potential raising technology, the output end can operate safely within a wider voltage range, and through logic control and high-voltage isolation tubes, the high voltage is isolated from key sensitive nodes, thereby improving the circuit's voltage resistance and meeting the needs of various high-voltage scenarios.

[0084] 4. The present invention provides a thin-gate-oxide high-voltage backflow prevention circuit for analog circuits and a control method thereof, which can be implemented in common BCD, CMOS and other process platforms. In addition, the overall circuit design does not rely on special mask layers or proprietary materials, making it highly versatile and manufacturable, facilitating rapid introduction into mass production and reuse in different processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0085] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0086] Figure 1 Circuit diagram

[0087] Figure 2 This is a schematic diagram of the steps of the present invention

[0088] Figure 3 Fig. 4 is the equivalent circuit structure diagram in the anti-backflow state DETAILED DESCRIPTION

[0089] The technical solutions of the present invention will be more clearly and completely explained below through description of preferred embodiments of the present invention in conjunction with the accompanying drawings.

[0090] like Figure 1 Figure 1 shows the circuit structure of the present invention. PM1 is a thin-gate-oxide PLDMOS power transistor, while PM2 is a thin-gate-oxide PMOS power transistor with backflow protection. Depending on the output voltage, either a high-voltage PLDMOS or a low-voltage PMOS in a high-voltage well can be used. R1 is a poly resistor. Z1 and Z2 are Zener diodes with a reverse bias voltage of approximately 6V, protecting the gate oxides of PM1 and PM2 from high-voltage damage. NM1 and NM2 are low-voltage NMOS transistors, while NM3 is a high-voltage NLDMOS transistor. CMP is a comparator that compares the VIN and VOUT voltages.

[0091] During normal operation, PM1 is controlled by the driver circuitry, such as the error amplifier, and is in the on state. Ib is the bias current. Through the mirroring relationship between NM1 and NM2, it provides a current bias to resistor R1, keeping PM2 fully on. NM1 and NM2 are low-voltage NMOS transistors, ensuring accurate mirroring. At this point, VIN is higher than VOUT, CMP outputs a high voltage, and NM3 is fully on. NM3 is a high-voltage NLDMOS transistor, capable of withstanding the high voltage at VOUT and also isolating NM2 from the high voltage. At this point, PM1 is on, PM2 is fully on, and the system is operating normally.

[0092] When VIN exists and the voltage is lower than VOUT, the CMP comparator outputs a low voltage. At this time, the current bias disappears, the GATE and SOURCE terminals of PM2 are short-circuited by resistors, and PM2 is completely turned off. At the same time, the CMP comparator also controls the internal circuit to turn off PM1. The equivalent structure of the circuit at this time is as follows: Figure 3 As shown in FIG, in this equivalent structure, PM1 and PM2 are both completely turned off, forming a complete electrical isolation from VIN to VOUT, and the substrate diodes D1 and D2 have opposite polarities and will not conduct. Figure 1 NM3 in the circuit is also completely shut down, and there is no static current consumption at VOUT. This structure ensures that no current flows from VOUT to VIN, and also ensures that VOUT has no static power consumption to GND.

[0093] At this time, if the VOUT voltage is lower than 5V, PM2 can select a low-voltage PMOS located in the high-voltage well, and the voltage difference of its four ports will not exceed 5V. If the VOUT voltage is higher than 5V, high-voltage PLDMOS or high-voltage PDEMOS is selected, depending on which device occupies a smaller layout area.

[0094] When VIN is floating or grounded, the internal bias current of the chip disappears, the VIN and VOUT comparator outputs are low, and PM2 is completely shut down. At this time, there is no static loss at either VIN or VOUT, and the chip power consumption is extremely low. At the same time, PM2 can withstand high voltage at VOUT.

[0095] Regardless of whether VIN is higher than VOUT or VOUT is higher than VIN, the gate-source voltage of all MOS is clamped at the Zener voltage or below 6V, so all MOS can use a thin gate oxide process, that is, a process with a gate oxide thickness of 5V, which greatly reduces the chip area.

[0096] like Figure 2 As shown, the control method is as follows:

[0097] Step S1: When it is detected that the output voltage is higher than the input voltage, the charge pump is triggered to generate a negative voltage at a frequency proportional to the voltage difference, the negative voltage is limited to a specified range through a nonlinear clamping network, and then the negative voltage is applied to the gate of the power tube;

[0098] Step S2: After confirming that the output voltage is greater than the input voltage, the bias current of the anti-backflow power tube is first cut off using the fast shutdown pulse generated by the differential circuit. Then, the gate charge of the main power tube is released through the delayed signal of the integration circuit. Finally, the logic AND gate determines the shutdown timing of the high-voltage isolation tube.

[0099] Step S3: Compare the voltage difference. When the voltage difference exceeds 0.5V and the rate of change is positive, the bias current is directly cut off. When the voltage difference is less than 0.2V, the bias current is calculated using given proportional, integral, and differential coefficients and adjusted in real time.

[0100] Step S4: Inputting the voltage difference into a Sigma-Delta modulator to generate a pulse density D, then outputting a pulse train using an NMOS switch with a fixed on-time, and setting an average bypass current based on the product of the pulse density D and the peak current;

[0101] Step S5: Connect a configurable Zener array in parallel between the drain and gate of the power tube and adjust the number of Zeners with the help of dynamic fuses. At the same time, when it is detected that the output voltage is higher than the input voltage, the substrate potential of the anti-backflow power tube is increased to the output voltage plus 2V;

[0102] Step S6: limiting the gate-source voltage of all thin-gate oxide devices to below 6V through Zener diodes, and uniformly adopting a 5V process to manufacture these devices.

[0103] As a specific implementation, a 5V thin gate oxide process is used, and the gate oxide thickness of all MOS devices is uniformly arranged during layout design. PM1 and PM2 are P-type transistors, and NM1, NM2, and NM3 are N-type transistors. A clamping area for Zener diodes is reserved during layout. The input and output terminals are connected to chip pins or pads, respectively, and the voltages at these two ports are compared using a comparator. When the comparator determines that the output voltage is higher than the input voltage, it outputs a high-level trigger signal to the subsequent control unit.

[0104] Upon receiving a trigger signal, the charge pump circuit begins operating, setting its operating frequency proportional to the difference between the output and input voltages. This generates a negative potential. To prevent this negative potential from being pulled too far down, a network consisting of a Zener diode and a variable resistor is connected in series with the charge pump output. Combined with internal leakage current, this network limits the negative potential to a specific negative voltage range. This negative potential is connected to the gates of PM1 and PM2, placing them in a deep shutdown state.

[0105] The high-level signal output by the comparator simultaneously triggers the differentiator and integrator circuits. The time constant of the differentiator circuit can be set to a relatively short level (e.g., approximately 10 nanoseconds) to generate an extremely fast pulse signal, thereby immediately shutting off the bias current source driving PM2. The time constant of the integrator circuit is set to a relatively long level (e.g., approximately 1 microsecond), allowing its output voltage to change slowly. This gradually releases the gate charge of PM1 after PM2's bias is cut off. The gate signal of high-voltage isolation transistor NM3 is controlled by a logic AND gate. The inputs of this gate include the comparator output and the inverted output signal of the integrator circuit. Through a reasonable logic combination, NM3 coordinates the shutdown sequence of PM1 and PM2.

[0106] To regulate the bias current, the voltage difference between the output and input terminals and the rate of change of that voltage difference are monitored. If the voltage difference exceeds a certain threshold and continues to rise, a shutdown command is directly sent to the bias current source, maintaining the bias current at zero. When the voltage difference drops below a lower threshold, the bias current is regulated using the results calculated using the proportional, integral, and differential coefficients. Appropriate units are set for these three coefficients in the circuit to accurately control the tiny bias current flowing through PM2 or other components. To meet the requirements for small reverse currents in specific scenarios, a pulse density modulation unit can also be used. The difference between the output and input voltages is fed into a modulator with a slope factor to generate a pulse train. This is combined with a fixed-width pulse on-time to achieve intermittent conduction. The peak current of each on-time can be set to a relatively high but extremely short value, and the density of the pulses determines the overall average current.

[0107] To accommodate higher voltage environments, several Zener diodes and PN junction diodes are connected in parallel between the drain and gate of PM1 and PM2. A fuse structure dynamically adjusts the number of Zener diodes in series, increasing the total breakdown voltage in stages. When the output voltage exceeds a certain threshold, the fuse is blown to increase the number of Zener diodes in series, thereby raising the device's withstand voltage. Simultaneously, a bias network or external reference is used to raise PM2's substrate potential to a certain level above the output voltage to prevent conduction of the substrate parasitic diode. For all MOS transistors used in the circuit, a Zener diode is connected in parallel between the gate and source, with a breakdown voltage of approximately 6V. This ensures that each MOS transistor maintains a safe gate-source voltage under potentially large potential differences. During layout, sufficient silicon area is reserved for components such as Zeners and fuses, and proper isolation between high-current paths and protection paths is ensured to meet design rules in mass production.

[0108] The above-described specific embodiments merely describe preferred embodiments of the present invention and do not limit the scope of protection of the present invention. Any modifications, substitutions, and improvements made to the technical solution of the present invention by a person skilled in the art based on the textual description and drawings provided herein, without departing from the design concept and spirit of the present invention, shall fall within the scope of protection of the present invention. The scope of protection of the present invention is determined by the claims.

Claims

1. A thin gate oxide high voltage backflow prevention circuit for an analog circuit, characterized in that: include: Input and output terminals; Power transistor PM1 is a thin-gate-oxide laterally diffused P-type metal oxide semiconductor transistor, with its source connected to the input terminal and its drain connected to the drain of PM2, used for main current path control; The anti-backflow power transistor PM2 is a thin gate oxide laterally diffused P-type metal oxide semiconductor transistor, whose source is connected to the output terminal, the drain is connected to the drain of PM1, and the gate is connected to the bias current module through the resistor R1; Zener diodes Z1 and Z2 are connected between the gate and source of power transistors PM1 and PM2, respectively, and are used to clamp the gate-source voltage to a preset reverse bias voltage; The input end of the comparator is connected to the input end and the output end respectively, and the output end of the comparator controls the on / off of the bias current module through the high-voltage N-type lateral diffuser NM3; A bias current module, including low-voltage N-type metal oxide semiconductor transistors NM1 and NM2, provides a bias current for R1 through a mirror current; High-voltage N-type lateral diffused transistor NM3, whose drain is connected to the bias current module, source is connected to the drain of NM2, and gate is controlled by the comparator output, and is used to isolate the high voltage of the output terminal voltage; Among them, when the input voltage is lower than the output voltage, the comparator outputs a low level, the high-voltage N-type lateral diffuser NM3 is turned off, the power tube PM1 and the power tube PM2 are both turned off, the backflow current is blocked, and the output voltage has no static power consumption.

2. The thin gate oxide high voltage backflow prevention circuit for analog circuits according to claim 1, characterized in that: The device type of the power tube PM2 is selected according to the level of the output voltage: When the output voltage is lower than 5V, the power transistor PM2 is a low-voltage P-type metal oxide semiconductor transistor in the high-voltage well; When the output voltage is higher than 5V, the power tube PM2 is a high-voltage P-type lateral diffused tube or a high-voltage P-type double diffused tube; The reverse breakdown voltage of the Zener diodes Z1 and Z2 is 6V, which is used to protect the gate oxide withstand voltage of the power transistors PM1 and PM2; The resistor R1 is a polysilicon resistor used to adjust the conduction state of the power transistor PM2; The NM1 and NM2 form a precise current mirror to ensure the stability of the bias current.

3. The thin gate oxide high voltage backflow prevention circuit for analog circuits according to claim 1, characterized in that: When the input voltage is floating or grounded, the comparator outputs a low level, the power tube PM2 and the power tube PM1 are both turned off, and there is no static current consumption for the output voltage and the input voltage; The voltage resistance of the high-voltage N-type lateral diffuser NM3 covers the maximum operating voltage of the output terminal, and the high voltage of the output terminal can be completely isolated in the off state.

4. The thin gate oxide high voltage backflow prevention circuit for analog circuits according to claim 1, characterized in that: The gate oxide thickness of all metal oxide semiconductor devices is thin gate oxide thickness corresponding to 5V process to reduce chip area; The substrate diodes D1 and D2 of the power transistors PM1 and PM2 have opposite polarities and are non-conductive in the off state; The circuit is suitable for high-voltage and low-voltage-difference linear voltage regulation or analog circuits requiring backflow prevention functions, and is compatible with standard semiconductor process implementation.

5. A control method for a thin-gate-oxide high-voltage backflow prevention circuit of an analog circuit, applicable to a thin-gate-oxide high-voltage backflow prevention circuit of an analog circuit according to any one of claims 1 to 4, characterized in that: include: Step S1: When it is detected that the output voltage is higher than the input voltage, the charge pump is triggered to generate a negative voltage at a frequency proportional to the voltage difference, the negative voltage is limited to a specified range through a nonlinear clamping network, and then the negative voltage is applied to the gate of the power tube; Step S2: After confirming that the output voltage is greater than the input voltage, the bias current of the anti-backflow power tube is first cut off using the fast shutdown pulse generated by the differential circuit. Then, the gate charge of the main power tube is released through the delayed signal of the integration circuit. Finally, the logic AND gate determines the shutdown timing of the high-voltage isolation tube. Step S3: Compare the voltage difference. When the voltage difference exceeds 0.5V and the rate of change is positive, the bias current is directly cut off. When the voltage difference is less than 0.2V, the bias current is calculated using given proportional, integral, and differential coefficients and adjusted in real time. Step S4: Inputting the voltage difference into a Sigma-Delta modulator to generate a pulse density D, then outputting a pulse train using an NMOS switch with a fixed on-time, and setting an average bypass current based on the product of the pulse density D and the peak current; Step S5: Connect a configurable Zener array in parallel between the drain and gate of the power tube and adjust the number of Zeners with the help of dynamic fuses. At the same time, when it is detected that the output voltage is higher than the input voltage, the substrate potential of the anti-backflow power tube is increased to the output voltage plus 2V; Step S6: limiting the gate-source voltage of all thin-gate oxide devices to below 6V through Zener diodes, and uniformly adopting a 5V process to manufacture these devices.

6. The thin-gate-oxide high-voltage backflow prevention circuit control method for an analog circuit according to claim 5, characterized in that: Step S1 is specifically as follows: Step S11: Continuously measure the output voltage and input voltage through a comparator or sampling circuit, and provide a "trigger signal" when it is determined that the output voltage is higher than the input voltage; Step S12: According to the "trigger signal" and the voltage difference The size of , sets the oscillation or switching frequency of the charge pump: , where k is an internally designed proportionality coefficient, and begins pumping operation to generate a negative potential; Step S13: Connect the negative potential output by the charge pump to a network containing a Zener diode and a variable resistor, and use the reverse breakdown characteristics of the Zener diode and the voltage drop generated by the variable resistor to keep the negative potential at nearby: in, : The potential value of the negative voltage applied to the power tube gate in the clamping network; : The regulated voltage value of the Zener diode during reverse breakdown; : Possible leakage current in the clamping network; : variable resistor or temperature compensation resistor; Step S14: Connect the negative potential to the gate terminals of the power transistors PM1 and PM2 through internal wiring or external interconnection, and maintain low leakage characteristics of the wiring path.

7. The method for controlling a thin-gate-oxide high-voltage backflow prevention circuit for an analog circuit according to claim 5, wherein: Step S2 is specifically as follows: Step S21: performing differentiation processing on the "output voltage is higher than the input voltage" signal, setting the RC constant of the differentiation circuit, and obtaining a fast negative pulse with a time constant of approximately 10ns; Step S22: Outputting the differential pulse directly or through a gate circuit to the control end of the bias current source to quickly cut off the bias current of the anti-backflow power transistor PM2; Step S23: Integrate the same "output voltage higher than input voltage" signal, set the RC constant of the integration circuit, and obtain a slowly varying voltage with a time constant of approximately 1µs; Step S24: directing the output of the integration circuit to the gate control path of the main power transistor PM1, gradually releasing the gate charge of PM1 so that it is turned off again after the bias is cut off; Step S25: Comparator output CMP OUT The inverted signal INT output by the integration circuit OUT A logical AND operation is performed to obtain a gate signal of the high-voltage isolation transistor NM3, which is used to determine the final switching state of NM3.

8. The method for controlling a thin-gate-oxide high-voltage backflow prevention circuit of an analog circuit according to claim 5, wherein: Step S3 specifically includes: Step S31: Voltage difference Sampling and calculation The symbol of , judge whether it satisfies" and "Conditions; Step S32: When the condition of step S31 is confirmed, a shutdown instruction is sent to the bias current source to make the bias current And maintain the state until the condition change is detected again; Step S33: When the given PID parameters (K p ,K i ,K d )calculate: ； Among them, K p : A coefficient proportional to the current voltage difference (proportional coefficient); K i : A coefficient proportional to the integral of the voltage difference (integral coefficient); K d : Coefficient proportional to the rate of change of voltage difference (differential coefficient); And output the result to the control port of the bias current source; Step S34: Use the window comparator to compare Continuous detection is performed, and when it crosses the 0.2V or 0.5V threshold, the control mode of the bias current source is changed.

9. The method for controlling a thin-gate-oxide high-voltage backflow prevention circuit of an analog circuit according to claim 5, wherein: Step S4 specifically includes: Step S41: The voltage difference Input to a similar modulation circuit and internally based on the slope factor Convert to pulse density; Step S42: Setting the single pulse on-time so that the modulator outputs a pulse sequence with the calculated pulse density D, and controlling the interleaving relationship between the pulse sequence and other system clocks or communication frequency bands; Step S43: Connect the pulse sequence to the gate of the NMOS switch NM4, so that it is turned on when the pulse is at a high level and turned off when the pulse is at a low level; Step S44: Make the peak current during conduction constant at a specified value, and obtain the value by adjusting the pulse density D. ； in : Average current obtained by pulse density control; This results in an average bypass current based on the time duty cycle.

10. The thin-gate-oxide high-voltage backflow prevention circuit control method for analog circuits according to claim 5, characterized in that: Step S5 is specifically as follows: Step S51: Connect multiple Zener diodes in parallel between the drain and gate of the power tube, and connect them in series through internal or external wiring so that the total breakdown voltage satisfies: ； in, : The total breakdown or total regulated voltage obtained by connecting a Zener and a normal diode in series; N: the number of Zener diodes actually connected in series; : Reverse breakdown voltage of a single Zener diode; : The voltage drop of an ordinary diode when it is forward-conducting; And modify the number N of Zeners in series through dynamic fuses; Step S52: After detecting that the output voltage is higher than the preset value, the internal fuse is triggered to blow, and the number of Zeners connected in series N is increased to complete the configuration change for the high voltage working condition; Step S53: When it is determined that the output voltage is higher than the input voltage, the substrate of PM2 is raised to V OUT +2V, and maintain substrate bias; Step S6 is specifically as follows: Step S61: Select a Zener diode compatible with the 5V process and connect it in parallel to the gate-source terminals of PM1, PM2, and NM1-NM3 so that the gate-source voltage does not exceed about 6V; Step S62: During layout and manufacturing, it is stipulated that all involved MOS devices are laid out according to 5V thin gate oxide specifications, and a placement area for clamping diodes is reserved in the design layout; Step S63: Connect the Zener diode clamping node between the gate and source of each MOS device through metal interconnection or interlayer vias, and avoid direct coupling between the high current node and the clamping path during circuit wiring.

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