High-density circuit with wide line width and narrow line spacing and manufacturing method thereof

Abstract

The invention discloses a high-density circuit with wide line width and narrow line spacing and a manufacturing method thereof, and the manufacturing method comprises the steps: providing a processing board, the outermost layer of the processing board is a copper foil layer, and the copper foil layer is divided into a circuit processing region and a PAD processing region; performing primary circuit manufacturing on the processing board to manufacture a circuit pattern prototype on the circuit processing area, and processing a concave arc part on a part, connected with the circuit pattern prototype, on the PAD processing area; widening and thickening the rudiment of the circuit pattern through electroplating to obtain the circuit pattern, and thickening the whole PAD processing area at the same time; obtaining an intermediate plate; carrying out secondary circuit manufacturing on the intermediate plate so as to manufacture a bonding pad on the thickened PAD processing area; and the bonding pad is smoothly and firmly connected with the circuit pattern through the thickened concave arc part, so that high-density circuit manufacturing is completed. The manufacturing method is simple, reasonable and easy to operate, the obtained circuit has the advantages of being wide in line width, narrow in line distance, excellent in conductivity and the like, and market requirements are met.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit boards, and particularly to a high-density circuit with wide line widths and narrow line spacings and a manufacturing method thereof. Background Art

[0002] Currently, in the processing of printed circuit boards, for high-density wiring boards with "line widths of 2 mil or more and line spacings of less than 2 mil", based on the conventional circuit manufacturing process (such as lamination → drilling → electroless copper plating → outer layer → optical inspection), it is impossible to manufacture products that meet the requirements of line widths and line spacings, and the conductivity between the circuit patterns and pads manufactured based on the conventional circuit manufacturing process is also poor, thus unable to meet market demands. In view of this, the present invention is specifically proposed. Summary of the Invention

[0003] In order to overcome the above defects, the present invention provides a high-density circuit with wide line widths and narrow line spacings and a manufacturing method thereof. The manufacturing method is simple, reasonable, easy to operate and implement, and the resulting circuit has the characteristics of wide line widths, narrow line spacings, excellent electrical conductivity, etc., well meeting market demands.

[0004] The technical solution adopted by the present invention to solve its technical problems is: a manufacturing method of a high-density circuit with wide line widths and narrow line spacings, including:

[0005] Providing a processing board, the outermost layer of the processing board is a copper foil layer, and a circuit processing area and a PAD processing area are defined on the copper foil layer;

[0006] Performing a first circuit manufacturing on the processing board to manufacture a circuit pattern prototype on the circuit processing area, and simultaneously processing a concave arc portion at a position on the PAD processing area that is connected to the circuit pattern prototype;

[0007] Widening and thickening the circuit pattern prototype through an electroplating process to obtain a circuit pattern, and simultaneously thickening the entire PAD processing area through the electroplating process; at this time, an intermediate board is obtained;

[0008] Performing a second circuit manufacturing on the intermediate board to manufacture pads on the thickened PAD processing area; wherein, the pads are smoothly and firmly connected to the circuit pattern through the thickened concave arc portion; thus, the manufacturing of the high-density circuit is completed.

[0009] As a further improvement of the present invention, the methods of the first circuit manufacturing and the second circuit manufacturing are the same, and both include pre-treatment before film lamination, coating of an anti-etching photosensitive film, exposure, development, etching, and film stripping processes performed in sequence.

[0010] As a further improvement of the present invention, the processing parameters for exposure are as follows: the spacing between exposure materials is 1.5 - 2 mil, and the exposure energy is 80 - 120 MJ;

[0011] The processing parameters for development are as follows: the development speed is 3.5 - 4.5 m / min.

[0012] As a further improvement of the present invention, when performing the first circuit production, the exposure compensation value of the PAD processing area is designed to be 2 mil.

[0013] As a further improvement of the present invention, the electroplating process uses a vertical electroplating process, and the processing parameters of the electroplating process are as follows: the current density is 8 - 10 ASF, and the electroplating time is 50 - 60 min.

[0014] As a further improvement of the present invention, the line width of the circuit pattern prototype is 40 ± 2 μm, and the line pitch is 50 ± 2 μm;

[0015] The line width of the circuit pattern is 60 ± 2 μm, and the line pitch is 30 ± 2 μm.

[0016] As a further improvement of the present invention, after completing the first circuit production and the second circuit production, AOI inspection processes are respectively provided.

[0017] The present invention also provides a high-density circuit with wide line width and narrow line pitch, which is manufactured by using the manufacturing method of the high-density circuit with wide line width and narrow line pitch described in the present invention.

[0018] The beneficial effects of the present invention are as follows: ① The present invention obtains a high-density circuit with a wide line width (60 ± 2 μm) and a narrow line pitch (30 ± 2 μm) by the method of "first manufacturing a circuit pattern prototype and then electroplating to increase the width and thickness". Moreover, the high-density circuit has good thick copper uniformity and flat upper and lower surfaces, thus well meeting the market demand. ② When manufacturing the circuit pattern prototype, the present invention also processes a concave arc portion at the position on the PAD processing area and connected to the circuit pattern prototype. In this way, during the subsequent process of manufacturing the solder pad, due to the concave arc portion, the solder pad can be smoothly and firmly connected to the circuit pattern, greatly improving the conductive / conductive performance of the high-density circuit. ③ The manufacturing method of the high-density circuit of the present invention is simple, reasonable, novel, easy to implement in production, and the obtained high-density circuit has a high yield and good quality. Description of the Drawings

[0019] Figure 1 It is a process flow chart of the manufacturing method of the high-density circuit with wide line width and narrow line pitch described in Embodiment 1 of the present invention;

[0020] Figure 2Schematic cross-sectional structure diagram of the processing board described in Embodiment 1 of the present invention;

[0021] Figure 3 Schematic partial cross-sectional structure diagram of the board obtained after the first circuit production on the processing board described in Embodiment 1 of the present invention;

[0022] Figure 4 Schematic partial cross-sectional structure diagram of the intermediate board obtained in Embodiment 1 of the present invention;

[0023] Figure 5 Schematic structure diagram when the circuit pattern and the obtained pads are connected together in Embodiment 1 of the present invention.

[0024] The following description is made in conjunction with the accompanying drawings:

[0025] 1. Processing board; 10. Copper foil layer; 11. Insulating layer; 12. Core board; 2. Circuit pattern prototype; 3. Concave arc part; 4. Circuit pattern; 5. Pad; 6. Copper plating layer. Detailed implementation manners

[0026] The following describes in detail the preferred embodiments of the present invention in conjunction with the accompanying drawings.

[0027] Embodiment 1:

[0028] Please refer to Atta Figure 1 to Atta Figure 5 As shown, Embodiment 1 provides a high-density circuit manufacturing method with wide line widths and narrow line spacings, including the following manufacturing steps:

[0029] S1: Provide a processing board 1, the outermost layer of the processing board 1 is a copper foil layer 10, and a circuit processing area and a PAD processing area are defined on the copper foil layer 10.

[0030] Specifically, for the convenience of describing the manufacturing principle of the high-density circuit manufacturing method with wide line widths and narrow line spacings described in this application, in Embodiment 1, the processing board 1 is taken as an example of "a board that has completed the inner layer circuit production and the double-sided lamination and build-up operation", but it can be understood that the processing board 1 is not limited thereto and can be determined according to the specific processing requirements of the product.

[0031] When the processing board 1 uses the above board, its specific structure is: see Atta Figure 2As shown in the figure, the processing board 1 is provided with a core board 12 and two copper foil layers 10 respectively laminated and fixed on the front and back sides of the core board 12 through insulating layers 11. Among them, inner layer circuits are formed on the front and back sides of the core board 12 respectively (since the production of inner layer circuits is not the key improvement point of this application, it will not be elaborated here and can be carried out by using the conventional circuit production process in the field of circuit boards). The insulating layer 11 can be but is not limited to prepreg materials, and in this Embodiment 1, there are no restrictive requirements for the thicknesses of the insulating layer 11 and the copper foil layer 10, which are determined according to the product design requirements.

[0032] In addition, according to the circuit production data, the circuit processing area and the PAD processing area are respectively divided on the two copper foil layers 10.

[0033] S2: Perform the first circuit production on the processing board 1 to produce a circuit pattern prototype 2 in the circuit processing area, and simultaneously process a concave arc portion 3 at the position on the PAD processing area that is connected to the circuit pattern prototype 2.

[0034] Specifically, the circuit production method preferably implemented for the processing board 1 in this Embodiment 1 is: after sequentially performing pre-treatment before film lamination, coating with an anti-etching photosensitive film, exposure, development, etching, and film stripping on the processing board 1, a circuit pattern prototype 2 is produced in the circuit processing area, and the concave arc portion 3 is processed at the position on the PAD processing area that is connected to the circuit pattern prototype 2.

[0035] The above circuit production method is further described as follows:

[0036] ① Pre-treatment before film lamination: It is to sequentially perform roughening, cleaning, and drying treatments on the two copper foil layers 10 of the processing board 1 to enhance the bonding force between the anti-etching photosensitive dry film and the copper foil layer 10 in the subsequent processes. Among them, the roughening treatment can preferably be but is not limited to ceramic grinding plate or micro-etching treatment, etc.

[0037] ② Coating with an anti-etching photosensitive film: It is to attach the anti-etching photosensitive dry film to the copper foil layer 10. Further, the film laminating operation can be implemented by a vacuum film laminator, and the film laminating pressure of the vacuum film laminator is preferably controlled at 2 - 4 kg / cm 2 ; thereby, high film laminating flatness can be achieved, and the bonding force between the anti-etching photosensitive dry film and the copper foil layer 10 can be further improved.

[0038] ③ Exposure, development: Exposure is to expose some areas of the anti-etching photosensitive dry film according to the operation data; development is to remove the unexposed areas of the anti-etching photosensitive dry film. In this Embodiment 1, the specific processing conditions for the exposure and development operations are also preferably controlled as:

[0039] The processing conditions for the exposure are as follows: an LDL exposure machine with high alignment accuracy and high exposure precision is used. The spacing of the exposure data is 1.5 - 2 mil (preferably 1.75 mil), and the exposure energy is 80 - 120 MJ. In particular, in this Example 1, the exposure compensation value for the PAD processing area is designed to be 2 mil (it can be understood that the exposure compensation value at the part on the PAD processing area and connected to the circuit pattern prototype 2 is also 2 mil), so as to better fabricate the concave arc portion 3.

[0040] The processing conditions for the development are as follows: the development speed is 3.5 - 4.5 m / min.

[0041] ④ Etching and stripping: For etching, an alkaline etching solution is used to remove the part of the copper foil layer 10 that is not covered by the anti - corrosion photosensitive dry film; for stripping, a strong alkaline solution is used to remove the anti - corrosion photosensitive dry film. At this time, the circuit pattern prototype 2 (as shown in the attached Figure 3 figure) and the concave arc portion 3 are fabricated on the copper foil layer 10.

[0042] In this Example 1, the structural parameters of the obtained circuit pattern prototype 2 are as follows: the line width of the circuit pattern prototype 2 is designed to be 40 ± 2 μm, and the line pitch is designed to be 50 ± 2 μm. It can be understood that the line width of the obtained circuit pattern prototype 2 in this Example 1 is smaller than the line width of the finally obtained circuit pattern 4, and the line pitch of the obtained circuit pattern prototype 2 is larger than the line pitch of the finally obtained circuit pattern 4, which provides necessary processing conditions for the electroplating and trimming of the circuit pattern in the subsequent process.

[0043] The structural parameters of the concave arc portion 3 are as follows: the concave arc portion 3 is in the shape of a minor arc, which can better realize the splicing of the circuit pattern 4 obtained in the subsequent process and the pad 5.

[0044] In addition, in the process of the first circuit fabrication of the processing board 1 in this Example 1, the following processes are also included: ① Before the pre - treatment of film lamination, the processing board 1 needs to be baked and drilled. Among them, baking is to age the incompletely cured epoxy resin in the insulating layer 11 and at the same time release the stress in the processing board 1; drilling is to process tool holes at the preset positions of the processing board 1 by mechanical drilling and / or laser drilling. The tool holes include through - holes (used to connect the finally obtained circuit pattern 4 with the inner - layer circuit on the core board 12), alignment holes, etc. ② After the stripping treatment, the board needs to be cleaned and baked, and the obtained circuit pattern prototype 2 and the concave arc portion 3 need to be subjected to AOI inspection (i.e., automatic optical inspection).

[0045] S3: The circuit pattern prototype 2 is widened and thickened through an electroplating process to obtain the circuit pattern 4. At the same time, the overall thickness of the PAD processing area is also increased through the electroplating process, and then an intermediate board is obtained.

[0046] Specifically, in this Embodiment 1, a vertical electroplating process is used to widen and thicken the circuit pattern prototype 2 and to thicken the PAD processing area, so as to deposit a copper plating layer 6 with a set thickness on the circuit pattern prototype 2 and the PAD processing area respectively. At this time, the circuit pattern prototype 2 and the copper plating layer 6 thereon together constitute the circuit pattern 4 (as shown in the appendix Figure 4 ), and the PAD processing area and the copper plating layer 6 thereon together constitute the PAD processing area A (to distinguish it from the PAD processing area).

[0047] Furthermore, in this Embodiment 1, the processing parameters of the electroplating process are preferably controlled as follows: the current density is 8 - 10 ASF, and the electroplating time is 50 - 60 min.

[0048] Furthermore, the thicknesses of the copper plating layers 6 located on the circuit pattern prototype 2 and the PAD processing area respectively are the same (such as both being 12 ± 2 μm), but the thickness of the copper plating layer 6 in this embodiment is not limited and is specifically determined according to the product design requirements.

[0049] Furthermore, the structural parameters of the circuit pattern 4 obtained in this Embodiment 1 are as follows: the line width of the circuit pattern 4 is 60 ± 2 μm, and the line pitch is 30 ± 2 μm. It can be understood that the circuit pattern 4 has the characteristics of a wide line width and a narrow line pitch, and the overall layout shows a high density.

[0050] S4: A second circuit production is performed on the intermediate board to fabricate pads 5 on the thickened PAD processing area. Among them, the pads 5 are smoothly and firmly connected to the circuit pattern 4 through the thickened concave arc portion 3, that is, the production of a high-density circuit is completed.

[0051] Specifically, the circuit production method preferably implemented on the intermediate board in this Embodiment 1 is as follows: after the intermediate board is successively subjected to pre-treatment before film lamination, application of an anti-etching photosensitive film, exposure, development, etching, and film stripping processes, the pads 5 are fabricated on the PAD processing area A. Note: The principle of the circuit production method implemented on the intermediate board in this Embodiment 1 is the same as the principle of the circuit production method implemented on the processing board 1 above, so it will not be elaborated here.

[0052] It can be understood that through the setting of the concave arc portion 3, the pads 5 can be more smoothly and firmly connected to the circuit pattern 4. For details, please refer to the appendix Figure 5 shown.

[0053] In addition, during the second circuit manufacturing process for the intermediate board in this Embodiment 1, the following processes are further included: after the film stripping treatment, the board needs to be cleaned and baked, and the obtained circuit pattern 4 and pads 5 are subjected to AOI inspection.

[0054] As can be seen from the above, ① in this application, a high-density circuit with a wide line width (60 ± 2 μm) and a narrow line pitch (30 ± 2 μm) is obtained by the method of "first making the circuit pattern prototype and then electroplating to increase the width and thickness". Moreover, the thick copper of this high-density circuit has good uniformity, and the upper and lower surfaces are flat, thus well meeting the market demand. ② When making the circuit pattern prototype in this application, a concave arc part is also processed at the position on the PAD processing area and connected to the circuit pattern prototype; in this way, when making the pads in the subsequent process, through the concave arc part, the pads can be smoothly and firmly connected to the circuit pattern, greatly improving the conductive / conductive performance of this high-density circuit. ③ The manufacturing method of the high-density circuit in this application is simple, reasonable, novel, easy to implement in production, and the obtained high-density circuit has a high yield and good quality.

[0055] Embodiment 2:

[0056] This Embodiment 2 provides a high-density circuit with a wide line width and a narrow line pitch, which is manufactured by using the manufacturing method of the high-density circuit with a wide line width and a narrow line pitch described in the above Embodiment 1.

[0057] Specifically, the structure of the high-density circuit with a wide line width and a narrow line pitch is as follows: Please refer to the attached Figure 5 As shown, the high-density circuit includes a circuit pattern 4 and pads 5. The line width of the circuit pattern 4 is 60 ± 2 μm, the line pitch is 30 ± 2 μm, and the circuit pattern 4 is smoothly and firmly connected to the pads 5 through the concave arc part 3 in the shape of an inferior arc.

[0058] As can be seen from the above, the high-density circuit has the characteristics of a wide line width, a narrow line pitch, and excellent conductive performance.

[0059] In summary, the manufacturing method of the high-density circuit with a wide line width and a narrow line pitch in the present invention is simple, reasonable, easy to operate and implement, and the obtained circuit has the characteristics of a wide line width, a narrow line pitch, and excellent conductive performance, well meeting the market demand.

[0060] Numerous specific details have been set forth in the above description to facilitate a full understanding of the present invention. However, the above description is only a preferred embodiment of the present invention, and the present invention can be implemented in many other ways different from those described herein. Therefore, the present invention is not limited by the specific embodiments disclosed above. At the same time, any person skilled in the art can make many possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above, or modify it into an equivalent embodiment with equivalent changes. All those that do not depart from the technical solution of the present invention, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention, still fall within the scope of the protection of the technical solution of the present invention.

Claims

1. A manufacturing method for high-density circuits with wide line widths and narrow line spacings, characterized in that: Including: Providing a processing board (1), the outermost layer of the processing board (1) is a copper foil layer (10), and a circuit processing area and a PAD processing area are defined on the copper foil layer (10); Performing a first circuit production on the processing board (1) to produce a circuit pattern prototype (2) on the circuit processing area, and simultaneously processing a concave arc portion (3) at a position on the PAD processing area and connected to the circuit pattern prototype (2); Widening and thickening the circuit pattern prototype (2) through an electroplating process to obtain a circuit pattern (4), and simultaneously thickening the entire PAD processing area through the electroplating process; at this time, an intermediate board is obtained; Performing a second circuit production on the intermediate board to produce pads (5) on the thickened PAD processing area; wherein, the pads (5) are smoothly and firmly connected to the circuit pattern (4) through the thickened concave arc portion (3); that is, the production of high-density circuits is completed.

2. The method for manufacturing a high-density circuit with a wide line width and a narrow line pitch according to claim 1, wherein: The methods of the first circuit production and the second circuit production are the same, and both include, in sequence, pre-treatment before film lamination, coating with an anti-etching photosensitive film, exposure, development, etching, and film stripping processing.

3. The method for manufacturing a high-density circuit with a wide line width and a narrow line pitch according to claim 2, wherein: The processing parameters of the exposure are: the exposure data pitch is 1.5 - 2 mil, and the exposure energy is 80 - 120 MJ; The processing parameters of the development are: the development speed is 3.5 - 4.5 m / min.

4. The method for manufacturing a high-density circuit with wide line widths and narrow line spacings according to claim 2, wherein: When performing the first circuit production, the exposure compensation value of the PAD processing area is designed to be 2 mil.

5. The method for manufacturing a high-density circuit with wide line widths and narrow line spacings according to claim 1, wherein: The electroplating process adopts a vertical electroplating process, and the processing parameters of the electroplating process are: the current density is 8 - 10 ASF, and the electroplating time is 50 - 60 min.

6. The method for manufacturing a high-density circuit with wide line widths and narrow line spacings according to claim 1, wherein: The line width of the circuit pattern prototype (2) is 40 ± 2 μm, and the line pitch is 50 ± 2 μm; The line width of the circuit pattern (4) is 60 ± 2 μm, and the line pitch is 30 ± 2 μm.

7. The method for manufacturing a high-density circuit with wide and narrow line widths and line spacings according to claim 1, characterized in that: After completing the first circuit production and the second circuit production, AOI detection processes are respectively provided.

8. A high-density circuit with a wide line width and a narrow line pitch, characterized in that: Manufactured by using the high-density circuit production method with wide line widths and narrow line pitches as described in any one of claims 1 - 7.

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