Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, and electronic equipment, the semiconductor device comprises a plurality of layers of vertically stacked memory cells and a control electrode penetrating through different layers and extending along a direction vertical to a substrate, and each memory cell comprises a first transistor and a second transistor which are distributed along a first direction; the first transistor comprises a first electrode extending in the direction perpendicular to the substrate, a first gate electrode and a first semiconductor layer surrounding and connected with the side wall of the first electrode. The first gate electrode comprises a first part surrounding the side wall of the first electrode and a second part extending in the first direction from the first part; the second transistor comprises a second gate electrode extending in the direction perpendicular to the substrate and a second semiconductor layer surrounding the second gate electrode, and the second semiconductor layer is connected with the first gate electrode; the control electrodes and the memory cells are arranged along a second direction. According to the scheme provided by the embodiment, a double-gate control structure is realized by providing the control electrode, and the control electrode does not additionally increase the device area, so that the device density can be improved.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to, but are not limited to, device design and manufacturing in the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.

[0003] In order to reduce the cost of products as much as possible, people hope to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's needs for current products. Summary of the invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The present application provides a semiconductor device and a manufacturing method thereof, and an electronic device, which reduce the device area and improve the density.

[0006] The present application provides a semiconductor device, comprising: a plurality of memory cells stacked in a direction perpendicular to a substrate, and a control electrode, wherein each layer of the memory cells comprises: a first transistor and a second transistor; the second transistor and the first transistor of the same memory cell are distributed in a first direction parallel to the substrate;

[0007] The first transistor comprises a first gate electrode, a first semiconductor layer, and a first electrode; the first electrode extends in a direction perpendicular to the substrate, and the first electrodes of the first transistors at the same position in different layers are connected to form an integrated structure; the first semiconductor layer surrounds and connects the side wall of the first electrode; the first gate electrode comprises a first portion surrounding the side wall of the first electrode and a second portion extending from the first portion along the first direction, and the first portion of the first gate electrode is arranged on a side of the first semiconductor layer away from the first electrode;

[0008] The second transistor comprises a second gate electrode and a second semiconductor layer, the second gate electrode extends in a direction perpendicular to the substrate, the second gate electrodes of the second transistors at the same position in different layers are connected to form an integrated structure, the second semiconductor layer surrounds the side wall of the second gate electrode, and the second semiconductor layer is connected to the side wall of the first gate electrode facing away from the first electrode;

[0009] The control electrode penetrates through the different layers and extends along a direction perpendicular to the substrate. The control electrode is distributed on the sidewall of the first gate electrode of the first transistor on a side facing away from the first electrode, and is also distributed on the sidewall of the second semiconductor layer of the second transistor on a side facing away from the second gate electrode. The control electrode and the storage unit are arranged along a second direction parallel to the substrate, and the first direction and the second direction intersect.

[0010] In some embodiments, the semiconductor device further includes: an insulating layer and a conductive layer that are alternately distributed in sequence from top to bottom along a direction perpendicular to the substrate; a first hole that penetrates through the insulating layer and the conductive layer;

[0011] In the first hole, a third gate insulating layer surrounding the control electrode and the control electrode are distributed in sequence from outside to inside.

[0012] In some embodiments, the semiconductor device further includes:

[0013] a second hole that penetrates through the insulating layer and the conductive layer, the second hole communicates with the first hole, and a groove extending along the second direction and communicating with the second hole is provided between adjacent insulating layers, and an opening direction of the groove faces away from the second hole;

[0014] In the second hole, the first gate electrode, a first gate insulating layer, the first semiconductor layer, and the first electrode are distributed in sequence from outside to inside, and the first gate electrode and the first gate insulating layer extend from the second hole to the sidewall of the groove.

[0015] In some embodiments, an aperture of a first sub-hole of the second hole located in the insulating layer is smaller than an aperture of a second sub-hole of the second hole located in the conductive layer.

[0016] In some embodiments, the semiconductor device further includes: a third hole that penetrates through the insulating layer and the conductive layer, and the third hole communicates with the first hole and the second hole;

[0017] In the third hole, the second semiconductor layer, a second gate insulating layer, and the second gate electrode are distributed in sequence from outside to inside.

[0018] In some embodiments, an aperture of a third sub-hole of the third hole located in the insulating layer is smaller than an aperture of a fourth sub-hole of the third hole located in the conductive layer.

[0019] In some embodiments, the semiconductor device includes a plurality of the control electrodes. Two control electrodes are distributed on the sidewall of the second semiconductor layer of the same storage unit on a side facing away from the second gate electrode, and the two control electrodes are spaced apart along the second direction.

[0020] In some embodiments, each layer includes a plurality of memory cells arrayed along the first direction and the second direction, and only one control electrode is provided between two adjacent memory cells along the second direction.

[0021] In some embodiments, the first gate electrodes of the first transistors in the same column distributed along the second direction in the same layer are connected to form an integral structure.

[0022] In some embodiments, the semiconductor device further includes: a first bit line disposed in the groove, and the first bit line is connected to the first semiconductor layer of the first transistors in the same column distributed along the second direction in the same layer.

[0023] In some embodiments, the first transistors adjacent along the first direction are connected to different first bit lines.

[0024] In some embodiments, the semiconductor device further includes: a second bit line extending along the second direction, and the second bit line is connected to the second semiconductor layer of the second transistors in the same column distributed along the second direction in the same layer.

[0025] In some embodiments, the second transistors adjacent along the first direction are connected to different second bit lines.

[0026] Embodiments of the present disclosure provide a method for manufacturing a semiconductor device, including:

[0027] Providing a substrate, and sequentially and alternately depositing an insulating film and a sacrificial layer film on the substrate to form a stacked structure including insulating layers and sacrificial layers alternately arranged;

[0028] Patterning the stacked structure to form a plurality of first holes penetrating the stacked structure and first trenches extending along the second direction, and between adjacent first trenches and between the first holes adjacent along the second direction, a first transistor region and a second transistor region distributed along the first direction are included;

[0029] Forming second holes penetrating the stacked structure in a direction perpendicular to the substrate in the first transistor region, laterally etching the sacrificial layer based on each second hole such that the aperture of the second hole in the sacrificial layer is larger than the aperture in the insulating layer, and such that the second hole communicates with the first trench and the first hole; forming a first gate electrode, a first semiconductor layer, and a first electrode extending in a direction perpendicular to the substrate in the second hole, the first semiconductor layer surrounding the sidewall of the first electrode, and the first gate electrode including a first portion surrounding the sidewall of the first electrode and a second portion extending from the first portion to the first trench;

[0030] Form a third hole in the second transistor region that penetrates the stacked structure in a direction perpendicular to the substrate. Laterally etch the sacrificial layer based on each of the third holes such that the third holes communicate with the first holes and the second holes. Form a second gate electrode of the second transistor extending in a direction perpendicular to the substrate and a second semiconductor layer surrounding the sidewalls of the second gate electrode in the third holes, and connect the second semiconductor layer to the first gate electrode;

[0031] Form a control electrode extending in a direction perpendicular to the substrate in the first hole.

[0032] In some embodiments, when laterally etching the sacrificial layer based on each of the second holes, the sacrificial layer is also laterally etched based on the first trench such that the positive projection of the first sub-trench of the insulating layer on the substrate falls within the positive projection of the second sub-trench of the sacrificial layer on the substrate, and the aperture of the second hole located in the first sub-hole of the insulating layer is smaller than the aperture of the second hole located in the second sub-hole of the sacrificial layer;

[0033] The forming of the first gate electrode, the first semiconductor layer, and the first electrode of the first transistor in the second hole includes:

[0034] Form a first gate electrode thin film covering the inner walls of the second hole and the inner walls of the first trench, etch away the first gate electrode thin film located in the first sub-hole and the first sub-trench to form a first gate electrode covering the inner walls of the second sub-hole and the inner walls of the second sub-trench; form a first gate insulating layer covering the inner walls of the second hole and the first trench;

[0035] Deposit a first semiconductor thin film in the second hole and the first trench where the first gate electrode and the first gate insulating layer are formed, etch away the first semiconductor thin film in the first sub-hole and the first sub-trench to form a first semiconductor layer covering the inner walls of the second sub-hole, and the first semiconductor layer separates the second hole and the first trench;

[0036] Form a first electrode filling the second hole.

[0037] In some embodiments, the method further includes: forming a second trench extending in a second direction on a side of the second transistor region away from the first trench; when laterally etching the sacrificial layer based on each of the third holes, the sacrificial layer is also laterally etched based on the second trench such that the positive projection of the third sub-trench of the insulating layer on the substrate falls within the positive projection of the fourth sub-trench of the sacrificial layer on the substrate, the aperture of the third hole located in the third sub-hole of the insulating layer is smaller than the aperture of the third hole located in the fourth sub-hole of the sacrificial layer, and the second trench communicates with the third hole; form a second bit line extending in the second direction in the fourth sub-trench;

[0038] Forming a second gate electrode of the second transistor extending in a direction perpendicular to the substrate and a second semiconductor layer surrounding the sidewall of the second gate electrode in the third hole includes:

[0039] Forming a second semiconductor thin film covering the inner wall of the third hole by deposition in the third hole, etching and removing the second semiconductor thin film located in the third sub-hole to form a second semiconductor layer covering the inner wall of the fourth sub-hole;

[0040] Sequentially forming a second gate insulating layer covering the inner wall of the third hole and a second gate electrode filling the third hole in the third hole where the second semiconductor layer is formed.

[0041] An embodiment of the present disclosure provides an electronic device, including the semiconductor device described in any one of the above embodiments, or a semiconductor device formed by the manufacturing method of the above semiconductor device.

[0042] The present application includes a semiconductor device and a manufacturing method thereof, and an electronic device, wherein the semiconductor device includes: a plurality of storage units and control electrodes stacked in a direction perpendicular to a substrate, wherein each layer of the storage units includes: a first transistor and a second transistor; the second transistor and the first transistor of the same storage unit are distributed in a first direction parallel to the substrate; the first transistor includes a first gate electrode, a first semiconductor layer, and a first electrode; the first electrode extends in a direction perpendicular to the substrate, and the first electrodes of the first transistors at the same position in different layers are connected to form an integrated structure; the first semiconductor layer surrounds and connects the side wall of the first electrode; the first gate electrode includes a first portion surrounding the side wall of the first electrode and a second portion extending from the first portion along the first side wall; the second The side wall of the semiconductor layer is away from the second gate electrode; the second transistor includes a second gate electrode and a second semiconductor layer, the second gate electrode extends in a direction perpendicular to the substrate, the second gate electrodes of the second transistors at the same position in different layers are connected to form an integrated structure, the second semiconductor layer surrounds the side wall of the second gate electrode, and the second semiconductor layer is connected to the side wall of the first gate electrode away from the first electrode; the control electrode runs through the different layers and extends in a direction perpendicular to the substrate, the control electrode is distributed on the side wall of the first gate electrode of the first transistor away from the first electrode, and, is distributed on the side wall of the second semiconductor layer of the second transistor away from the second gate electrode, the control electrode and the storage unit are arranged along the second direction, and the first direction and the second direction intersect. The semiconductor device provided in this embodiment improves the control capability by providing a control electrode to realize a 2T0C structure with dual gate control, and the control electrode is arranged on the side wall of the first gate electrode of the first transistor away from the first electrode, and the second semiconductor layer of the second transistor is away from the side wall of the second gate electrode and is arranged with the storage unit along the second direction, that is, the control electrode is arranged in the spacing area between the storage units distributed along the second direction. Therefore, the control electrode can be set without additionally increasing the device area, which can improve the device density and reduce the cost.

[0043] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the schemes described in the description and the drawings.

[0044] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The accompanying drawings are used to provide an understanding of the technical solution of the present application and form a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0046] Figure 1A Top view of a semiconductor device provided for an exemplary embodiment Figure 1B For the Figure 1A Cross-sectional view taken along the AA' direction in Figure 1C For the Figure 1A Cross-sectional view taken along the BB' direction in

[0047] Figure 2A Top view of a semiconductor device provided for an exemplary embodiment after forming a stacked structure Figure 2B For the Figure 2A Cross-sectional view taken along the AA' direction in Figure 2C For the Figure 2A Cross-sectional view taken along the BB' direction in

[0048] Figure 3A Top view of a semiconductor device provided for an exemplary embodiment after forming a first hole, a second insulating layer, and a dummy layer Figure 3B For the Figure 3A Cross-sectional view taken along the AA' direction in Figure 3C For the Figure 3A Cross-sectional view taken along the BB' direction in

[0049] Figure 4A Top view of a semiconductor device provided for an exemplary embodiment after forming a second hole and a first trench Figure 4B For the Figure 4A Cross-sectional view taken along the AA' direction in Figure 4C For the Figure 4A Cross-sectional view taken along the BB' direction in

[0050] Figure 5A Top view of a semiconductor device provided for an exemplary embodiment after laterally etching a sacrificial layer Figure 5B For the Figure 5A Cross-sectional view taken along the AA' direction in Figure 5C For the Figure 5A Cross-sectional view taken along the BB' direction in

[0051] Fig. 6A Top view of a semiconductor device provided for an exemplary embodiment after forming a first gate electrode Figure 6B For the Fig. 6A Cross-sectional view taken along the AA' direction in Figure 6C For the Fig. 6A Cross-sectional view taken along the BB' direction in

[0052] Fig. 7A Top view of a semiconductor device provided for an exemplary embodiment after forming a first barrier layer Figure 7B For the Fig. 7A Cross-sectional view in the AA' direction Figure 7C is the cross-sectional view along Fig. 7A in the BB' direction;

[0053] Fig. 8A is a top view of the etched first barrier layer provided by an exemplary embodiment, Figure 8B is the cross-sectional view along Fig. 8A in the AA' direction, Figure 8C is the cross-sectional view along Fig. 8A in the BB' direction;

[0054] Fig. 9A is a top view of the etched first gate electrode provided by an exemplary embodiment, Fig. 9B is the cross-sectional view along Fig. 9A in the AA' direction, Fig. 9C is the cross-sectional view along Fig. 9A in the BB' direction;

[0055] Fig. 10A is a top view of the etched and removed first barrier layer provided by an exemplary embodiment, Fig. 10B is the cross-sectional view along Fig. 10A in the AA' direction, Fig. 10C is the cross-sectional view along Fig. 10A in the BB' direction;

[0056] Fig.11A is a top view of the formed first gate insulating layer provided by an exemplary embodiment, Fig. 11B is the cross-sectional view along Fig.11A in the AA' direction, Fig. 11C is the cross-sectional view along Fig.11A in the BB' direction;

[0057] Fig. 12A is a top view of the formed first semiconductor layer provided by an exemplary embodiment, Fig. 12B is the cross-sectional view along Fig. 12A in the AA' direction, Fig. 12C is the cross-sectional view along Fig. 12A in the BB' direction;

[0058] Fig.13A is a top view of the formed first electrode provided by an exemplary embodiment, Fig. 13B is the cross-sectional view along Fig.13A in the AA' direction, Fig. 13C is the cross-sectional view along Fig.13A in the BB' direction;

[0059] Fig.14A is a top view of the formed second barrier layer provided by an exemplary embodiment, Fig. 14B is the cross-sectional view along Fig.14A A cross-sectional view in the AA' direction, Fig. 14C is the cross-sectional view along Fig.14A in the BB' direction;

[0060] Fig.15A is a top view after etching and removing the first conductive thin film in the first trench provided by an exemplary embodiment, Fig. 15B is the cross-sectional view along Fig.15A in the AA' direction, Fig. 15C is the cross-sectional view along Fig.15A in the BB' direction;

[0061] Fig.16A is a top view after etching the first semiconductor layer provided by an exemplary embodiment, Fig. 16B is the cross-sectional view along Fig.16A in the AA' direction, Fig. 16C is the cross-sectional view along Fig.16A in the BB' direction;

[0062] Fig.17A is a top view after forming the first bit line provided by an exemplary embodiment, Fig. 17B is the cross-sectional view along Fig.17A in the AA' direction, Fig. 17C is the cross-sectional view along Fig.17A in the BB' direction;

[0063] Fig.18A is a top view after disconnecting the first bit lines of different layers provided by an exemplary embodiment, Fig.18B is the cross-sectional view along Fig.18A in the AA' direction, Fig.18C is the cross-sectional view along Fig.18A in the BB' direction;

[0064] Fig.19A is a top view after forming the third insulating layer provided by an exemplary embodiment, Fig.19B is the cross-sectional view along Fig.19A in the AA' direction, Fig.19C is the cross-sectional view along Fig.19A in the BB' direction;

[0065] Fig. 20A is a top view after etching and removing the second insulating layer and the dummy layer provided by an exemplary embodiment, Fig. 20B is the cross-sectional view along Fig. 20A in the AA' direction, Fig. 20C is the cross-sectional view along Fig. 20A in the BB' direction;

[0066] Fig.21A is a top view after forming the third gate insulating layer and the control electrode provided by an exemplary embodiment, Fig.21B is a cross-sectional view along the Fig.21A AA' direction in Fig. 21C is a cross-sectional view along the Fig.21A BB' direction in

[0067] Fig.22A is a top view after forming a second transistor and a second bit line provided by an exemplary embodiment, Fig. 22B is a cross-sectional view along the Fig.22A AA' direction in Fig. 22C is a cross-sectional view along the Fig.22A BB' direction in Detailed Embodiments

[0068] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Without conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other arbitrarily.

[0069] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should have the ordinary meaning as understood by those of ordinary skill in the art to which the present disclosure belongs.

[0070] The embodiments of the present disclosure do not necessarily limit the dimensions shown in the accompanying drawings. The shapes and sizes of the components in the drawings do not reflect the actual proportions. In addition, the accompanying drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values shown in the accompanying drawings.

[0071] The ordinal numbers such as "first", "second", "third", etc. in the present disclosure are set to avoid confusion of components and do not represent any order, quantity or importance.

[0072] In the present disclosure, for convenience, terms indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationship of the components with reference to the accompanying drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present disclosure. The positional relationship of the components is appropriately changed according to the directions describing the components. Therefore, it is not limited to the terms described in the disclosure and can be appropriately replaced according to the situation.

[0073] In the present disclosure, unless otherwise clearly defined and limited, the terms "mounted", "connected", "coupled" should be understood in a broad sense. For example, it can be a physical connection or a signal connection, a contact connection or an integral connection; it can be directly connected, or indirectly connected through an intermediate member, or the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure can be understood according to specific situations.

[0074] In the present disclosure, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, the channel region refers to the region where current mainly flows.

[0075] In the present disclosure, it may be that the first electrode is the drain electrode and the second electrode is the source electrode, or it may be that the first electrode is the source electrode and the second electrode is the drain electrode. In cases such as when using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" sometimes swap with each other. Therefore, in the present disclosure, the "source electrode" and "drain electrode" can swap with each other.

[0076] In the present disclosure, "connection" includes cases where components are connected together through an element having a certain electrical effect. The "element having a certain electrical effect" is not particularly limited as long as it can transfer electrical signals between the components to be connected. Examples of the "element having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0077] In the present disclosure, "parallel" means approximately parallel or almost parallel. For example, the state where the angle formed by two straight lines is 10° or less and -10° or more, and thus also includes the state where the angle is 5° or less and -5° or more. In addition, "perpendicular" means approximately perpendicular. For example, the state where the angle formed by two straight lines is 100° or less and 80° or more, and thus also includes the state where the angle is 95° or less and 85° or more.

[0078] The statement "A and B are of an integral structure" in the embodiments of the present disclosure may mean that there is no obvious boundary interface such as a fault or gap in the microscopic structure. Generally, when a connected film layer is patterned and formed on a single film layer, it is of an integral structure. For example, A and B are formed of the same material into a single film layer and simultaneously formed with a connected structure through the same patterning process.

[0079] In the embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0080] Figure 1A Top view of a semiconductor device provided for an exemplary embodiment Figure 1B is a cross-sectional view along Figure 1A the AA' direction in Figure 1Cis a cross-sectional view along the Figure 1A direction BB' in Figure 1A . As shown in Figure 1B , Figure 1C and

[0081] shown, an embodiment of the present disclosure provides a semiconductor device, including a plurality of memory cell arrays vertically stacked on a substrate 1, and the plurality of memory cell arrays may be distributed along a third direction Z. The third direction Z may be perpendicular to the substrate 1.

[0082] The memory cell array may include a plurality of first bit lines 30, a plurality of second bit lines 31, a plurality of first word lines 40, a plurality of second word lines 46, a plurality of control electrodes 45, and a plurality of memory cells. The plurality of memory cells of the memory cell array may be arrayed and distributed along a first direction x parallel to the substrate and a second direction y parallel to the substrate. The first direction x and the second direction y may intersect. In some embodiments, the first direction x and the second direction y may be perpendicular. The first bit lines 30 and the second bit lines 31 may be conductive lines extending along the second direction y, and the plurality of first bit lines 30 of the same memory cell array may be spaced from each other, and the plurality of second bit lines 31 of the same memory cell array may be spaced from each other. The plurality of first bit lines 30 may be distributed along the first direction x. The plurality of second bit lines 31 may be distributed along the first direction x. The first bit lines 30 and the second bit lines 31 may be spaced and distributed along the first direction x. The first bit lines 30 of different memory cell arrays may be stacked on the substrate 1, and the first bit lines 30 at the same position in different layers are spaced from each other. The second bit lines 31 of different memory cell arrays may be stacked on the substrate 1, and the second bit lines 31 at the same position in different layers are spaced from each other.

[0082] In some embodiments, the first bit line 30 is, for example, a read bit line, the second bit line 31 is, for example, a write bit line, the first word line 40 is, for example, a read word line, and the second word line 46 is, for example, a write word line.

[0083] The first word line 40 and the second word line 46 may extend along the third direction Z, and the memory cells at the same position stacked in the direction perpendicular to the substrate 1 share the first word line 40 and the second word line 46.

[0084] The memory cell may be a 2T0C memory cell, and the memory cell may include a first transistor and a second transistor. The first transistor and the second transistor of the same memory cell may be distributed along the first direction x.

[0085] The first transistor may include a first semiconductor layer 23, a first gate electrode 26, a first electrode 51, and a second electrode 52. The first electrode 51 may be a part of the first word line 40, and the first electrodes 51 of the first transistors at the same position in different layers may be part of the same first word line 40. The second electrode 52 may be connected to the first bit line 30. The second electrode 52 may be a part of the first bit line 30.

[0086] The second electrodes 52 of the first transistors of the memory cells in the same column of the same memory cell array may be connected to the same first bit line 30. That is, the second electrodes 52 of the first transistors in the same column distributed along the second direction y are connected to form a first bit line 30 extending along the second direction Y.

[0087] In some embodiments, the second transistor may include a second gate electrode 28, a second semiconductor layer 25, a third electrode 61, and a fourth electrode 62, and the second semiconductor layer 25 is respectively connected to the third electrode 61 and the fourth electrode 62. The third electrode 61 and the first gate electrode 26 may be connected to form an integrated structure, or the third electrode 61 and the first gate electrode 26 share the same electrode. The second gate electrodes 28 of the memory cells at the same position in different layers are connected to form a second word line 46.

[0088] The fourth electrode 62 may be connected to the second bit line 31. The fourth electrode 62 may be a part of the second bit line 31. The fourth electrodes 62 of the second transistors of the memory cells in the same column of the same memory cell array may be connected to the same second bit line 31. That is, the fourth electrodes 62 of the second transistors in the same column distributed along the second direction y are connected to form a second bit line 31 extending along the second direction y.

[0089] In some embodiments, the first transistor may be a read transistor, and the second transistor may be a write transistor.

[0090] In some embodiments, the control electrode 45 may extend in a direction perpendicular to the substrate 1 and may be a straight-line electrode. However, the embodiments of the present disclosure are not limited thereto, and the control electrode 45 may extend in a direction perpendicular to the substrate 1 as a whole, and the local topography is not limited.

[0091] Hereinafter, a semiconductor device including a plurality of vertically stacked memory cells at the same position will be described as an example.

[0092] As Figures 1A to 1CAs shown in the figure, an embodiment of the present disclosure provides a semiconductor device, which may include: a plurality of memory cells stacked in a direction perpendicular to the substrate, and a control electrode 45. Each layer of the memory cells includes: a first transistor and a second transistor; the second transistor and the first transistor of the same memory cell are sequentially distributed along a first direction x parallel to the substrate 1;

[0093] The first transistor includes a first gate electrode 26, a first semiconductor layer 23, and a first electrode 51; the first electrode 51 extends in a direction perpendicular to the substrate 1, and the first electrodes 51 of the first transistors at the same position in different layers are connected to form an integral structure; the first semiconductor layer 23 surrounds and connects the side wall of the first electrode 51; the first gate electrode 26 includes a first part surrounding the side wall of the first electrode 51 and a second part extending from the first part in a direction parallel to the substrate 1; the second part extends, for example, along the first direction x; the first part of the first gate electrode 26 is disposed on the side of the first semiconductor layer 23 facing away from the first electrode 51; the first part partially surrounds the first electrode 51, that is, the cross-section of the first part along a plane parallel to the substrate 1 is an open loop.

[0094] The second transistor includes a second gate electrode 28 and a second semiconductor layer 25. The second gate electrode 28 extends in a direction perpendicular to the substrate 1. The second gate electrodes 28 of the second transistors at the same position in different layers are connected to form an integral structure. The second semiconductor layer 25 surrounds the side wall of the second gate electrode 28, and the second semiconductor layer 25 is connected to the side wall of the first gate electrode 26 facing away from the first electrode 51;

[0095] The control electrode 45 penetrates through the different layers and extends in a direction perpendicular to the substrate 1. The control electrode 45 is distributed on the side wall of the first gate electrode 26 of the first transistor facing away from the first electrode 51, and is also distributed on the side wall of the second semiconductor layer 25 of the second transistor facing away from the second gate electrode 28. The control electrode 45 is arranged with the memory cells in a second direction y, and the first direction x and the second direction y intersect.

[0096] In the semiconductor device provided in this embodiment, a 2T0C structure with dual-gate control is realized by providing a control electrode, which improves the control ability. The control electrode is disposed on the side wall of the first gate electrode of the first transistor facing away from the first electrode, and on the side wall of the second semiconductor layer of the second transistor facing away from the second gate electrode, and is arranged with the memory cells in the second direction, that is, the control electrode is disposed in the interval region between the memory cells distributed in the second direction. Therefore, the control electrode can be provided without additionally increasing the device area, which can improve the device density and reduce the cost.

[0097] Among them, the first electrode 51 of the first transistors in different layers can be a part of the first word line 40. That is, before and after the formation of the first word line 40, there is no need to separately fabricate the first electrode 51. After the first word line 40 is fabricated, a part of the first word line 40 serves as the first electrode 51.

[0098] In some embodiments, the semiconductor device may further include: an insulating layer and a conductive layer that are alternately distributed in sequence from top to bottom along a direction perpendicular to the substrate; a first hole K1 that penetrates the insulating layer and the conductive layer;

[0099] In the first hole K1, a third gate insulating layer 13 surrounding the control electrode 45 and the control electrode 45 are sequentially distributed from outside to inside. The first bit line 30, the second bit line 31, the first gate electrode 26, the first semiconductor layer 32, and the second semiconductor layer 25 are disposed on the conductive layer;

[0100] In some embodiments, the aperture of the sub-hole of the first hole K1 in the conductive layer is the same as the aperture of the sub-hole of the first hole K1 in the insulating layer.

[0101] In some embodiments, the semiconductor device may further include: a second hole K2 that penetrates the insulating layer and the conductive layer, the second hole K2 communicates with the first hole K1, and a groove extending along the second direction y and communicating with the second hole K2 is provided between adjacent insulating layers, and the opening direction of the groove faces away from the second hole K2;

[0102] In the second hole K2, the first gate electrode 26, the first gate insulating layer 24, the first semiconductor layer 23, and the first electrode 51 are sequentially distributed from outside to inside, and the first gate electrode 26 and the first gate insulating layer 24 extend from the second hole K2 to the side wall of the groove. The side wall of the groove includes two adjacent insulating layers. That is, the first gate electrode 26 partially surrounds the first electrode 51 and extends from the communication part of the second hole K2 and the groove to the side wall of the groove. The first semiconductor layer 23 can be a fully surrounding type and fully surrounds the side wall of the first electrode 51. That is, the cross-section of the first semiconductor layer 23 along the direction parallel to the substrate 1 is a closed loop. Refer to Figure 1C , the first gate electrode 26 extends to the side wall of the groove.

[0103] In some embodiments, the first bit line 30 is disposed in the groove. Refer to Figure 1A , the long dashed line frame extending along the second direction y is the groove area.

[0104] In some embodiments, the aperture of the first sub-hole of the second hole K2 in the insulating layer is smaller than the aperture of the second sub-hole of the second hole K2 in the conductive layer. Refer to Figure 1A, the dotted line surrounding the second hole K2 is a schematic diagram of the second sub-hole of the second hole K2.

[0105] In some embodiments, the semiconductor device may further include: a third hole K3 penetrating the insulating layer and the conductive layer, the third hole K3 being connected to the first hole K1 and the second hole K2;

[0106] The second semiconductor layer 25 , the second gate insulating layer 27 and the second gate electrode 28 are sequentially distributed in the third hole K3 from outside to inside. The second gate insulating layer 27 surrounds the sidewall of the second gate electrode 28 to isolate the second gate electrode 28 from the semiconductor layer 25 .

[0107] In some embodiments, the aperture of the third sub-aperture of the third hole K3 located in the insulating layer is smaller than the aperture of the fourth sub-aperture of the third hole K3 located in the conductive layer. Figure 1A , the dotted line surrounding the third hole K3 is a schematic diagram of the fourth sub-hole of the third hole K3. The second hole K2 and the third hole K3 are distributed along the first direction x, the first hole K1 and the second hole K2 are distributed along the second direction y, and the first hole K1 and the third hole K3 are distributed along the second direction y.

[0108] In some embodiments, the size of the first hole K1 along the first direction x may be greater than the sum of the sizes of the second hole K2 and the third hole K3 along the first direction x, so as to facilitate the control electrode 45 to control the first transistor and the second transistor.

[0109] In some embodiments, the semiconductor device may include a plurality of control electrodes 45, and two control electrodes 45 are distributed on the sidewall of the second semiconductor layer 25 of the same memory cell away from the second gate electrode 28, and the two control electrodes 45 are spaced apart along the second direction y. That is, in this embodiment, one memory cell may be provided with two control electrodes, which are distributed on two opposite sides of the memory cell, but the embodiments of the present disclosure are not limited thereto, and the control electrode may be provided on only one side of the memory cell.

[0110] In some embodiments, the control electrodes 45 on both sides of the same memory cell may be electrically connected. The control electrodes 45 may be connected to the peripheral circuit of the memory cell array, or may be connected to the side of the memory cell array facing the substrate 1 (i.e., connected at the bottom of the memory cell array), or may be connected to the side of the memory cell array facing away from the substrate 1 (i.e., connected at the top of the memory cell array).

[0111] In some embodiments, only one of the control electrodes 45 may be provided between two adjacent memory cells along the second direction y. The control electrode 45 is insulated from the second semiconductor layers 25 of the two memory cells through different third gate insulating layers 13. The control electrode 45 can control two adjacent memory cells along the second direction y.

[0112] In some embodiments, the first gate electrodes 26 of the first transistors in the same column distributed along the second direction y in the same layer may be connected to form an integral structure. The first gate electrode 26 can extend into the groove, and the first gate electrodes 26 of the first transistors in the same column distributed along the second direction y in the same layer are connected through the portions extending into the groove.

[0113] In some embodiments, the first bit line 30 is connected to the first semiconductor layer 23 of the first transistors in the same column distributed along the second direction y in the same layer.

[0114] In some embodiments, the second bit line 31 is connected to the second semiconductor layer 25 of the second transistors in the same column distributed along the second direction y in the same layer.

[0115] In some embodiments, the first transistors adjacent along the first direction x may be connected to different first bit lines 30.

[0116] In some embodiments, the second transistors adjacent along the first direction x may be connected to different second bit lines 31.

[0117] In some embodiments, the second semiconductor layer 25 may be a fully surrounding type, surrounding the sidewalls of the second word line 46, that is, the cross-section of the second semiconductor layer 25 along the direction parallel to the substrate 1 is a closed loop.

[0118] In some embodiments, the second semiconductor layers 25 of the second transistors at the same position in different layers are arranged at intervals, for example, physically disconnected. The solution provided in this embodiment can eliminate the parasitic MOS between layers and reduce leakage.

[0119] FIG. 2A to FIG. 2C The semiconductor device structure shown is only an example, and the embodiments of the present disclosure are not limited thereto.

[0120] The technical solution of this embodiment will be further described below through the manufacturing process of the semiconductor device in this embodiment. The "lithography process" mentioned in this embodiment includes processes such as depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping, which are mature manufacturing processes in related technologies. The "lithography process" mentioned in this embodiment includes coating a film layer, mask exposure, and development, which are mature manufacturing processes in related technologies. Deposition can use known processes such as sputtering, evaporation, chemical vapor deposition, etc., coating can use known coating processes, and etching can use known methods, which will not be specifically limited here. In the description of this embodiment, it should be understood that a "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a lithography process or a lithography process during the entire manufacturing process, the "thin film" can also be called a "layer". If the "thin film" still requires a lithography process or a lithography process during the entire manufacturing process, it is called a "thin film" before the lithography process and a "layer" after the lithography process. The "layer" after the lithography process or the lithography process contains at least one "pattern".

[0121] In an exemplary embodiment, the manufacturing process of the semiconductor device may include:

[0122] 1) Depositing a first insulating thin film and a sacrificial layer thin film on the substrate 1 in sequence to form a stacked structure, the structure including a first insulating layer 9 and a sacrificial layer 10 arranged in sequence, as Figure 2A , Figure 2B and Figure 2C shown, where Figure 2A is a top view of the stacked structure provided by an exemplary embodiment, Figure 2B is a cross-sectional view along the AA' direction in Figure 2A , Figure 2C is a cross-sectional view along the BB' direction in Figure 2A .

[0123] The orthographic projections of the first insulating layer 9 and the sacrificial layer 10 in the direction parallel to the substrate 1 may overlap.

[0124] In some embodiments, the first insulating thin film may be a low-K dielectric layer, that is, a dielectric layer with a dielectric constant K < 3.9, including but not limited to silicon oxides, such as silicon dioxide (SiO2), etc.

[0125] In some embodiments, the sacrificial layer thin film may be an insulating material with a certain etching selectivity ratio with the first insulating thin film, such as silicon nitride (SiN), etc.

[0126] Figure 2B and Figure 2CThe stacked structure shown includes three first insulating layers 9 and two sacrificial layers 10 only as an example. In other embodiments, the stacked structure may include more or fewer first insulating layers 9 and sacrificial layers 10.

[0127] 2) Form a first hole K1, a second insulating layer 11, and a dummy layer 6;

[0128] Etch the stacked structure from the top layer to the bottom layer, and stop etching on the substrate 1 to form a plurality of first holes K1 penetrating the stacked structure; wherein, the plurality of first holes K1 may be arranged in an array in the first direction x and the second direction y. In a plane parallel to the substrate 1, the cross-section of the first hole K1 may extend in the first direction x. Between the first holes K1 adjacent in the second direction y is a transistor region, and a first transistor and a second transistor are formed in the transistor region subsequently. Between the first holes K1 adjacent in the first direction x is a bit line region, and a first bit line 30 and a second bit line 31 are formed in the bit line region subsequently.

[0129] Deposit a second insulating film to form a second insulating layer 11 covering the sidewalls and the bottom wall of the first hole K1;

[0130] Deposit a dummy layer film to form a dummy layer 6 filling the first hole K1; as Figure 3A , Figure 3B and Figure 3C shown, wherein, Figure 3A is a top view after forming the first hole K1, the second insulating layer 11, and the dummy layer 6 provided for an exemplary embodiment, Figure 3B is a cross-sectional view along the AA' direction in Figure 3A , Figure 3C is a cross-sectional view along the BB' direction in Figure 3A .

[0131] In some embodiments, the second insulating film may be an insulating material having a certain etching selectivity ratio with the sacrificial layer film, such as SiO2.

[0132] In some embodiments, the dummy layer film may be alumina (Al2O3), amorphous carbon (C), polysilicon (Poly), etc.

[0133] 3) Form a second hole K2 and a first trench T1;

[0134] Etch the stacked structure from the top layer to the bottom layer, and stop etching on the substrate 1 to form a second hole K2 penetrating the stacked structure in the transistor region and a first trench T1 penetrating the stacked structure in the bit line region; the first trench T1 extends in the second direction y, and the first trench T1 separates the storage cells adjacent in the first direction x, as Figure 4A , Figure 4B and Figure 4C shown, wherein, Figure 4A A top view after forming a second hole K2 and a first trench T1 provided for an exemplary embodiment Figure 4B For the cross-sectional view along Figure 4A the AA' direction in Figure 4C For the cross-sectional view along Figure 4A the BB' direction in

[0135] The second hole K2 includes a first sub-hole located in the first insulating layer 9 and a second sub-hole located in the sacrificial layer 10, and at this time, the apertures of the first sub-hole and the second sub-hole are the same; the first trench T1 includes a first sub-trench located in the first insulating layer 9 and a second sub-trench located in the sacrificial layer 10, and at this time, the width of the first sub-trench along the first direction x is the same as the width of the second sub-trench along the first direction x;

[0136] 4) Transversely etch the sacrificial layer 10;

[0137] Based on the second hole K2, transversely etch the sacrificial layer 10 along the first direction x and the second direction y (i.e., along the direction parallel to the substrate 1) to expand the aperture of the second sub-hole of the second hole K2 located in the sacrificial layer 10, and based on the first trench T1, transversely etch the sacrificial layer 10 along the first direction x to expand the width of the second sub-trench of the first trench T1 along the first direction x, and make the second hole K2 and the first trench T1 communicate, as shown in Figure 5A 、 Figure 5B and Figure 5C shown, where Figure 5A A top view after transversely etching the sacrificial layer 10 provided for an exemplary embodiment Figure 5B For the cross-sectional view along Figure 5A the AA' direction in Figure 5C For the cross-sectional view along Figure 5A the BB' direction in

[0138] At this time, the second hole K2 forms two types of holes with inconsistent sizes. Along the second direction y, the aperture of the first sub-hole of the second hole K2 located in the first insulating layer 9 is smaller than the aperture of the second sub-hole of the second hole K2 located in the sacrificial layer 10, that is, the orthographic projection of the first sub-hole of the second hole K2 located in the first insulating layer 9 on the substrate 1 falls within the orthographic projection of the second sub-hole of the second hole K2 located in the sacrificial layer 10 on the substrate 1. At this time, in addition to the first longitudinal hole K20 that penetrates the stacked structure along the direction perpendicular to the substrate 1, the second hole K2 further includes a first lateral groove K21 located in each sacrificial layer 10. The side walls of the first lateral groove K21 expose the adjacent second insulating layers 11 disposed opposite to each other along the second direction y. The first trench T1 forms two types of trenches with inconsistent sizes. The width of the first sub-trench of the first trench T1 located in the first insulating layer 9 along the first direction x is smaller than the width of the second sub-trench of the first trench T1 located in the sacrificial layer 10 along the first direction x. The orthographic projection of the first sub-trench of the first trench T1 located in the first insulating layer 9 on the substrate 1 falls within the orthographic projection of the second sub-trench of the first trench T1 located in the sacrificial layer 10 on the substrate 1, and the second hole K2 and the first trench T1 are connected. At this time, in addition to the first longitudinal trench T10 that penetrates the stacked structure along the direction perpendicular to the substrate 1, the first trench T1 further includes two lateral trenches located in each sacrificial layer 10: a first lateral trench T11 and a second lateral trench T12. Subsequently, two first bit lines 30 are respectively formed in the first lateral trench T11 and the second lateral trench T12. The first transistors in the same layer and the same column are connected to the same first bit line 30. Therefore, the first lateral trench T11 and the second lateral trench T12 extend along the second direction y to the region where the first transistors in the same layer and the same column are located. Figure 5A The region indicated by the dashed line in the figure is the region of lateral etching.

[0139] 5) Form the first gate electrode 26;

[0140] Deposit a first gate electrode film to form a first gate electrode 26 that covers the inner walls of the first trench T1 and the second hole K2 (the inner walls include the bottom wall and the side walls); as Fig. 6A , Figure 6B and Figure 6C shown, wherein, Fig. 6A is a top view after forming the first gate electrode 26 provided for an exemplary embodiment, Figure 6B is a cross-sectional view along the Fig. 6A AA' direction in Figure 6C is a cross-sectional view along the Fig. 6A BB' direction in

[0141] In some embodiments, the first gate electrode film may be one or more of the following different types of materials:

[0142] For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it can be a metal alloy containing these metals mentioned above.

[0143] Alternatively, it can be a conductive metal oxide, metal nitride, metal silicide, metal carbide, etc., such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), aluminum-doped zinc oxide (Aluminum doped ZincOxide, AZO) and other conductive metal oxide materials; for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN) and other conductive metal nitride materials.

[0144] Alternatively, it can be doped polysilicon, silicon, germanium, silicon germanium, etc. that are conductive after doping.

[0145] Subsequently, the second gate electrode film and the third conductive film are similar to the first gate electrode film and will not be elaborated further.

[0146] 6) Form the first barrier layer 8;

[0147] On the substrate 1 with the aforementioned structure formed, deposit a first barrier layer film to form the first barrier layer 8. The first barrier layer 8 covers the surface of the first gate electrode 26 (i.e., the surface exposed in the first trench T1 and the second hole K2), which is convenient for protecting the first gate electrode film to be retained when etching to remove part of the first gate electrode film. As shown in Fig. 7A 、 Figure 7B and Figure 7C shown, where Fig. 7A is a top view of the formed first barrier layer 8 provided by an exemplary embodiment, Figure 7B is a cross-sectional view along the AA' direction in Fig. 7A , and Figure 7C is a cross-sectional view along the BB' direction in Fig. 7A . The first barrier layer 8 may not completely fill the second hole K2 and the first trench T1.

[0148] In some embodiments, the first barrier layer film can be deposited by a high-temperature furnace tube process to obtain a first barrier layer film with high density. However, the embodiments of the present disclosure are not limited thereto, and other deposition processes can be used for deposition.

[0149] In some embodiments, the first barrier layer film includes but is not limited to alumina (Al2O3), amorphous carbon (C), polysilicon (Poly), titanium nitride (TiN), titanium carbonitride (TiCN), etc.

[0150] 7) Etch the first barrier layer 8;

[0151] Etch the first barrier layer 8 to remove the first barrier layer 8 within the first longitudinal hole K20 and the first longitudinal trench T10, and retain the first barrier layer 8 within the first lateral groove K21, the first lateral trench T11, and the second lateral trench T12. At this time, the first barrier layer 8 is distributed within the second sub-hole of the sacrificial layer 10 and within the second sub-trench of the sacrificial layer 10, as Fig. 8A , Figure 8B and Figure 8C shown, where Fig. 8A is a top view of the etched first barrier layer 8 provided for an exemplary embodiment, Figure 8B is a cross-sectional view along the Fig. 8A AA' direction in Figure 8C is a cross-sectional view along the Fig. 8A BB' direction in . At this time, the first gate electrode film in the first sub-hole and the first gate electrode film in the first sub-trench are exposed.

[0152] In some embodiments, the first barrier layer 8 can be etched by wet etching.

[0153] 8) Etch the first gate electrode 26;

[0154] Etch the first gate electrode 26 such that the first gate electrode film in the first sub-hole and the first gate electrode film in the first sub-trench are etched away, while the first gate electrode film in the second sub-hole and the first gate electrode film in the second sub-trench are protected by the first barrier layer 8 and thus retained, as Fig. 9A , Fig. 9B and Fig. 9C shown, where Fig. 9A is a top view of the etched first gate electrode 26 provided for an exemplary embodiment, Fig. 9B is a cross-sectional view along the Fig. 9A AA' direction in Fig. 9C is a cross-sectional view along the Fig. 9A BB' direction in . At this time, the first gate electrode 26 is only distributed on the inner walls of the second sub-hole and the second sub-trench, that is, on the inner walls of the first lateral groove K21, the first lateral trench T11, and the second lateral trench T12. The first gate electrodes 26 of the first transistors in different layers are disconnected. The first gate electrodes 26 of the first transistors in the same layer and the same column are connected together.

[0155] In some embodiments, the first gate electrode 26 can be etched by wet etching.

[0156] 9) Etch and remove the first barrier layer 8;

[0157] Etch and remove the first barrier layer 8, that is, etch and remove the first barrier layer 8 covering the surface of the first gate electrode 26, as Fig. 10A , Fig. 10B and Fig. 10C As shown, wherein, Fig. 10A is a top view of an exemplary embodiment after etching to remove the first barrier layer 8, Fig. 10B is a cross-sectional view along the Fig. 10A AA' direction in Fig. 10C is a cross-sectional view along the Fig. 10A BB' direction in

[0158] In some embodiments, the first barrier layer 8 can be removed by wet etching.

[0159] 10) Form a first gate insulating layer 24;

[0160] On the substrate 1 on which the foregoing structure is formed, deposit a first gate insulating thin film to form a first gate insulating layer 24. The first gate insulating layer 24 covers the second hole K2 and the inner walls of the first trench T1 where the first gate electrode 26 has been formed. The first gate insulating layer 24 isolates the first gate electrode 26 from the first semiconductor layer 23 to be formed subsequently, as Fig.11A , Fig. 11B and Fig. 11C shown, wherein, Fig.11A is a top view of an exemplary embodiment after forming the first gate insulating layer 24, Fig. 11B is a cross-sectional view along the Fig.11A AA' direction in Fig. 11C is a cross-sectional view along the Fig.11A BB' direction in

[0161] In some embodiments, the first gate insulating thin film may include one or more High-K dielectric materials, such as dielectric materials with a dielectric constant K≥3.9. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, for example, it may include at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2) and other high-K materials. The subsequent second gate insulating thin film and third gate insulating thin film are similar to the first gate insulating thin film and will not be elaborated here.

[0162] 11) Form a first semiconductor layer 23;

[0163] Deposit a first semiconductor thin film on the substrate 1 on which the foregoing structure is formed. The first semiconductor thin film covers the inner walls of the second hole K2 and the first trench T1 where the first gate electrode 26 and the first gate insulating layer 24 are formed; and the first semiconductor thin film extends along the inner walls of the second hole K2 and the first trench T1 and does not completely fill the second hole K2 and the first trench T1;

[0164] Etch away the first semiconductor thin film in the first sub-hole and the first semiconductor thin film in the first sub-groove to form the first semiconductor layer 23, as Fig. 12A , Fig. 12B and Fig. 12C shown, where Fig. 12A is a top view after forming the first semiconductor layer 23 provided for an exemplary embodiment, Fig. 12B is a cross-sectional view along the Fig. 12A AA' direction in Fig. 12C is a cross-sectional view along the Fig. 12A BB' direction in

[0165] In an exemplary embodiment of the present disclosure, the first semiconductor thin film may be a material such as silicon or polysilicon with a bandgap less than 2 eV, or it may be a wide-bandgap material, such as a metal oxide material with a bandgap greater than 2 eV.

[0166] For example, the material of the metal oxide semiconductor layer or the channel may include metal oxides of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may not exclude compounds containing other elements, such as elements N, Si, etc.; nor does it exclude other minor doping elements.

[0167] In some embodiments, the material of the metal oxide semiconductor layer or the channel may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO, IWO), titanium oxide (TiO), zinc oxide nitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), etc. materials, as long as the leakage current of the transistor can meet the requirements, and it can be specifically adjusted according to the actual situation.

[0168] These materials have a wide bandgap and low leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10 -15 A, thereby improving the operating performance of the dynamic memory.

[0169] The material of the above-mentioned metal oxide semiconductor layer or channel only emphasizes the element type of the material, and does not emphasize the atomic ratio in the material and the film quality of the material.

[0170] Subsequently, the material of the second semiconductor layer 25 is similar to that of the first semiconductor layer 23, and will not be described in detail.

[0171] 12) Form the first electrode 51;

[0172] Deposit a first conductive thin film on the substrate 1 having the above structure to form the first electrode 51. The first electrode 51 fills the second hole K2, covers the side wall and the bottom wall of the first trench T1, and does not completely fill the first trench T1, facilitating subsequent etching of the first conductive thin film in the first trench T1, as Fig.13A 、 Fig. 13B and Fig. 13C shown, where Fig.13A is a top view after forming the first electrode 51 provided for an exemplary embodiment, Fig. 13B is a cross-sectional view along the Fig.13A AA' direction in Fig. 13C is a cross-sectional view along the Fig.13A BB' direction in

[0173] In some embodiments, the first conductive thin film may be the following conductive materials:

[0174] For example, containing metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing these metals mentioned above;

[0175] Or, it may be a conductive metal oxide, metal nitride, metal silicide, metal carbide, etc., such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO) and other conductive metal oxide materials; for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN) and other conductive metal nitride materials;

[0176] Or, it may be doped polysilicon, silicon, germanium, silicon germanium, etc. that are conductive.

[0177] Subsequent other conductive thin films are similar and will not be described in detail.

[0178] 13) Form the second barrier layer 7;

[0179] Deposit a second barrier layer thin film on the substrate 1 forming the foregoing structure, pattern to form the second barrier layer 7, the second barrier layer 7 is provided with an opening, exposing the region where the first trench T1 is located, and the region outside the first trench T1 is covered with the second barrier layer 7, as Fig.14A , Fig. 14B and Fig. 14C shown, wherein, Fig.14A is a top view of the formed second barrier layer 7 provided for an exemplary embodiment, Fig. 14B is a cross-sectional view along the Fig.14A AA' direction in Fig. 14C is a cross-sectional view along the Fig.14A BB' direction in

[0180] In some embodiments, the second barrier layer thin film may be aluminum oxide (Al2O3), amorphous carbon (C), polysilicon (Poly), titanium nitride (TiN), titanium carbonitride (TiCN), etc.

[0181] 14) Etch and remove the first conductive thin film located in the first trench T1;

[0182] Etch and remove the first conductive thin film located in the first trench T1 (including the first longitudinal trench T10, the first transverse trench T11, and the second transverse trench T12) by wet etching. At this time, the first electrode 51 is only distributed in the second hole K2, and the first electrodes 51 of the first transistors at the same position in different layers are connected to form an integral structure, as Fig.15A , Fig. 15B and Fig. 15C shown, wherein, Fig.15A is a top view of the etched and removed first conductive thin film in the first trench T1 provided for an exemplary embodiment, Fig. 15B is a cross-sectional view along the Fig.15A AA' direction in Fig. 15C is a cross-sectional view along the Fig.15A BB' direction in

[0183] 15) Etch the first semiconductor layer 23;

[0184] Etch and remove the first semiconductor layer 23 located in the first transverse trench T11 and the second transverse trench T12 by wet etching, so that the first semiconductor layers 23 of the first transistors in the same layer and the same column are disconnected, as Fig.16A , Fig. 16B and Fig. 16C shown, wherein, Fig.16A is a top view of the etched first semiconductor layer 23 provided for an exemplary embodiment, Fig. 16B is a cross-sectional view along the Fig.16A AA' direction in Fig. 16C is a cross-sectional view along the Fig.16A BB' direction in the figure. It can be seen that at this time, the first semiconductor layer 23 in the first transverse groove T11 and the second transverse groove T12 is removed, and the first semiconductor layers 23 of the first transistors in the same layer and the same column are disconnected to avoid leakage.

[0185] 16) Form the first bit line 30;

[0186] Deposit a second conductive film on the substrate 1 having the foregoing structure to form the first bit line 30; the second conductive film fills the first transverse trench T11 and the second transverse trench T12, and does not completely fill the first longitudinal trench T10, that is, there is an opening in the second conductive film in the first longitudinal trench T10, which is convenient for etching the second conductive film in the first longitudinal trench T1 in the subsequent process through this opening, as Fig.17A , Fig. 17B and Fig. 17C shown, wherein Fig.17A is a top view after forming the first bit line 30 provided by an exemplary embodiment, Fig. 17B is a cross-sectional view along the Fig.17A AA' direction in the figure, Fig. 17C is a cross-sectional view along the Fig.17A BB' direction in the figure.

[0187] 17) Disconnect the first bit lines 30 of different layers;

[0188] Dry-etch the first bit line 30 from the top layer to the bottom layer, etch and remove the second conductive film located in the first longitudinal trench T10 to disconnect the first bit lines 30 of different layers, and form a plurality of first bit lines 30 distributed in different layers, so that the first bit lines 30 of different layers are disconnected, and the adjacent first bit lines 30 in the same layer can also be disconnected, as Fig.18A , Fig.18B and Fig.18C shown, wherein Fig.18A is a top view after disconnecting the first bit lines 30 of different layers provided by an exemplary embodiment, Fig.18B is a cross-sectional view along the Fig.18A AA' direction in the figure, Fig.18C is a cross-sectional view along the Fig.18A BB' direction in the figure. The two adjacent first bit lines 30 in the same layer are respectively located in the first transverse groove T11 and the second transverse groove T12.

[0189] 18) Form the third insulating layer 12;

[0190] Deposit a third insulating film on the substrate 1 having the above structure to form the third insulating layer 12, as Fig.19A , Fig.19B and Fig.19C shown, wherein Fig.19A A top view after forming the third insulating layer 12 provided for an exemplary embodiment Fig.19B For the along Fig.19A A cross-sectional view taken along the AA' direction in Fig.19C For the along Fig.19A A cross-sectional view taken along the BB' direction in. The third insulating layer 12 fills the first longitudinal trench T10. The first bit lines 30 at the same position in different layers are spaced apart by the first insulating layer 9, and the adjacent first bit lines 30 in the same layer are spaced apart by the third insulating layer 12.

[0191] In some embodiments, the third insulating thin film may be a low-K dielectric layer, including but not limited to silicon oxides such as SiO2 and the like.

[0192] 19) Etch and remove the second insulating layer 11 and the dummy layer 6;

[0193] Etch and remove the second insulating layer 11 and the dummy layer 6 to expose the first hole K1, and the sidewall of the first hole K1 exposes the first gate electrode 26, as shown in Fig. 20A , Fig. 20B and Fig. 20C shown, wherein Fig. 20A A top view after etching and removing the second insulating layer 11 and the dummy layer 6 provided for an exemplary embodiment Fig. 20B For the along Fig. 20A A cross-sectional view taken along the AA' direction in Fig. 20C For the along Fig. 20A A cross-sectional view taken along the BB' direction in.

[0194] 20) Form a third gate insulating layer 13 and a control electrode 45;

[0195] Deposit a third gate insulating thin film on the substrate 1 having the above structure to form a third gate insulating layer 13 covering the bottom wall and the sidewall of the first hole K1;

[0196] Deposit a third conductive thin film filling the first hole K1 to form a control electrode 45, and the control electrode 45 fills the first hole K1, as shown in Figure 21A , Figure 21B and Figure 21C shown, wherein Figure 21A A top view after forming the third gate insulating layer 13 and the control electrode 45 provided for an exemplary embodiment Figure 21B For the along Figure 21A A cross-sectional view taken along the AA' direction in Figure 21C For the along Figure 21A A cross-sectional view taken along the BB' direction in.

[0197] 21) Form a second transistor and a second bit line 31;

[0198] Etch the stacked structure from the top layer to the bottom layer, form a third hole K3 penetrating the stacked structure in the transistor region, and form a second trench T2 on the side of the second transistor region away from the first trench T1. The second trench T2 extends along the second direction y, and the second trench T2 separates adjacent memory cells. The first trench T1 and the second trench T2 are staggered along the second direction y. The third hole K3 is disposed on the side of the second hole K2 away from the first bit line 30. The third hole K3 includes a third sub-hole located in the first insulating layer 9 and a fourth sub-hole located in the sacrificial layer 10, and at this time, the apertures of the third sub-hole and the fourth sub-hole are the same. The second trench T2 includes a third sub-trench located in the first insulating layer 9 and a fourth sub-trench located in the sacrificial layer 10, and at this time, the width of the third sub-trench along the first direction x is the same as the width of the fourth sub-trench along the first direction x.

[0199] Laterally etch the sacrificial layer 10 along the first direction x and the second direction y based on the third hole K3 to enlarge the aperture of the fourth sub-hole of the third hole K3 located in the sacrificial layer 10, that is, the orthographic projection of the third sub-hole of the third hole K3 located in the first insulating layer 9 on the substrate 1 falls within the orthographic projection of the fourth sub-hole of the third hole K3 located in the sacrificial layer 10 on the substrate 1, and the side wall of the fourth sub-hole exposes the first gate electrode 26 and two third gate insulating layers 13 disposed oppositely along the second direction y. Lateral etch the sacrificial layer 10 along the first direction x based on the second trench T2 to enlarge the width of the fourth sub-trench of the second trench T2 located in the sacrificial layer 10 along the first direction x, so that the orthographic projection of the third sub-trench of the second trench T2 located in the first insulating layer 9 on the substrate falls within the orthographic projection of the fourth sub-trench located in the sacrificial layer 10 on the substrate, and the third hole K3 and the second trench T2 are communicated. At this time, the second trench T2 includes a second longitudinal trench extending along a direction perpendicular to the substrate 1 and two lateral trenches located in the sacrificial layer 10.

[0200] Form a second bit line 31 in the lateral trench of the second trench T2, form a fourth insulating layer 14 in the second longitudinal trench of the second trench T2, and deposit a second semiconductor thin film covering the inner wall of the third hole K3 in the third hole K3, etch and remove the second semiconductor thin film located in the third sub-hole to form a second semiconductor layer 25. Deposit a second gate insulating thin film and a second gate electrode thin film in the third hole K3 in sequence to form a second gate insulating layer 27 and a second gate electrode 28. The second gate electrode 28 fills the third hole K3, as Figure 22A 、 Figure 22B and Figure 22C shown, where Figure 22A is a top view after forming the second transistor and the second bit line 31 provided for an exemplary embodiment, Figure 22B is a cross-sectional view along the Figure 22A AA' direction inFigure 22C A sectional view along the Figure 22A direction of BB’ in. Among them, the second gate electrodes 28 of the second transistors at the same positions in different layers are connected to form an integral structure, which is the second word line 46. The second semiconductor layers 25 of the second transistors in different layers are disconnected to reduce leakage current. The second semiconductor layer 25 is connected to the first gate electrode 26. Figure 22A The dotted line in shows a top view schematic diagram of the fourth sub-hole of the third hole K3 in the sacrificial layer 10.

[0201] The embodiments of the present disclosure further provide an electronic device, including the semiconductor device of the foregoing embodiments, or the semiconductor device formed by the foregoing semiconductor device manufacturing method. The electronic device may be: a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, a mobile power supply, etc. The storage device may include the memory in a computer, etc., which is not limited herein.

[0202] Although the disclosed embodiments of the present invention are as above, the described content is only the embodiments adopted for facilitating the understanding of the present invention, and is not used to limit the present invention. Any person skilled in the art within the scope of the present invention can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed by the present invention. However, the scope of patent protection of the present invention shall still be subject to the scope defined by the appended claims.

Claims

1. A semiconductor device, characterized in that, include: Multiple layers of memory cells and control electrodes stacked in a direction perpendicular to the substrate, each layer of the memory cells comprising: a first transistor and a second transistor; The second transistor and the first transistor of the same memory cell are distributed along a first direction parallel to the substrate; The first transistor comprises a first gate electrode, a first semiconductor layer, and a first electrode; the first electrode extends in a direction perpendicular to the substrate, and the first electrodes of the first transistors at the same position in different layers are connected to form an integrated structure; the first semiconductor layer surrounds and connects the side wall of the first electrode; the first gate electrode comprises a first portion surrounding the side wall of the first electrode and a second portion extending from the first portion along the first direction; the first portion of the first gate electrode is arranged on a side of the first semiconductor layer away from the first electrode; The second transistor comprises a second gate electrode and a second semiconductor layer, the second gate electrode extends in a direction perpendicular to the substrate, the second gate electrodes of the second transistors at the same position in different layers are connected to form an integrated structure, the second semiconductor layer surrounds the side wall of the second gate electrode, and the second semiconductor layer is connected to the side wall of the first gate electrode facing away from the first electrode; The control electrode extends through the different layers in a direction perpendicular to the substrate. The control electrode is distributed on a side wall of a first gate electrode of the first transistor facing away from the first electrode, and on a side wall of a second semiconductor layer of the second transistor facing away from the second gate electrode. The control electrode and the storage unit are arranged in a second direction parallel to the substrate, and the first direction and the second direction intersect.

2. The semiconductor device according to claim 1, wherein The semiconductor device further includes: an insulating layer and a conductive layer alternately distributed from top to bottom in a direction perpendicular to the substrate; a first hole penetrating the insulating layer and the conductive layer; A third gate insulating layer surrounding the control electrode and the control electrode are sequentially distributed in the first hole from outside to inside.

3. The semiconductor device according to claim 2, wherein The semiconductor device further comprises: a second hole penetrating the insulating layer and the conductive layer, the second hole being connected to the first hole, a groove extending along the second direction and connected to the second hole being provided between adjacent insulating layers, and an opening direction of the groove being away from the second hole; The first gate electrode, the first gate insulating layer, the first semiconductor layer and the first electrode are sequentially distributed in the second hole from outside to inside, and the first gate electrode and the first gate insulating layer extend from the second hole to the sidewall of the groove.

4. The semiconductor device according to claim 3, characterized in that The aperture of a first sub-hole of the second hole located in the insulating layer is smaller than the aperture of a second sub-hole of the second hole located in the conductive layer.

5. The semiconductor device according to claim 3, characterized in that, The semiconductor device further comprises: a third hole penetrating through the insulating layer and the conductive layer, the third hole being connected with the first hole and the second hole; The second semiconductor layer, the second gate insulating layer and the second gate electrode are sequentially distributed in the third hole from outside to inside.

6. The semiconductor device according to claim 5, wherein The aperture of the third sub-hole of the third hole located in the insulating layer is smaller than the aperture of the fourth sub-hole of the third hole located in the conductive layer.

7. The semiconductor device according to claim 2, wherein The semiconductor device comprises a plurality of control electrodes. Two control electrodes are distributed on the side wall of the second semiconductor layer of the same storage unit away from the second gate electrode, and the two control electrodes are distributed at intervals along the second direction.

8. The semiconductor device according to claim 3, characterized in that, Each layer includes a plurality of storage units distributed in an array along the first direction and the second direction, and only one control electrode is arranged between two adjacent storage units along the second direction.

9. The semiconductor device according to claim 8, wherein, The first gate electrodes of the first transistors in the same layer and in the same column distributed along the second direction are connected to form an integrated structure.

10. The semiconductor device according to claim 8, wherein, The semiconductor device further comprises: a first bit line arranged in the groove, wherein the first bit line is connected to the first semiconductor layer of the first transistors in the same layer and in the same column distributed along the second direction.

11. The semiconductor device according to claim 10, wherein, The first transistors adjacent to each other along the first direction are connected to different first bit lines.

12. The semiconductor device according to claim 8, wherein, The semiconductor device further includes: a second bit line extending along the second direction, the second bit line being connected to a second semiconductor layer of second transistors in the same layer and in the same column distributed along the second direction.

13. The semiconductor device according to claim 12, wherein The second transistors adjacent in the first direction are connected to different second bit lines.

14. A method for manufacturing a semiconductor device, characterized in that, include: Providing a substrate, on which insulating thin films and sacrificial thin films are alternately deposited in sequence to form a stacked structure including insulating layers and sacrificial layers alternately arranged; The stack structure is patterned to form a plurality of first holes penetrating the stack structure and first trenches extending along a second direction, wherein adjacent first trenches and adjacent first holes along the second direction include first transistor regions and second transistor regions distributed along the first direction; A second hole is formed in the first transistor region and penetrates the stacked structure in a direction perpendicular to the substrate, and a sacrificial layer is laterally etched based on each of the second holes, so that the aperture of the second hole in the sacrificial layer is larger than the aperture of the insulating layer, and the second hole is connected with the first trench and the first hole; a first gate electrode of the first transistor, a first semiconductor layer and a first electrode extending in a direction perpendicular to the substrate are formed in the second hole, the first semiconductor layer surrounds the side wall of the first electrode, and the first gate electrode includes a first portion surrounding the side wall of the first electrode and a second portion extending from the first portion to the first trench; forming a third hole penetrating the stacked structure in a direction perpendicular to the substrate in the second transistor region, and laterally etching the sacrificial layer based on each of the third holes so that the third hole is connected with the first hole and the second hole, and forming a second gate electrode of the second transistor extending in a direction perpendicular to the substrate and a second semiconductor layer surrounding the sidewall of the second gate electrode in the third hole, and the second semiconductor layer is connected to the first gate electrode; A control electrode extending in a direction perpendicular to the substrate is formed in the first hole.

15. The manufacturing method of the semiconductor device according to claim 14, characterized in that, When the sacrificial layer is etched laterally based on each of the second holes, the sacrificial layer is also etched laterally based on the first trench, such that a positive projection of a first sub-trench of the insulating layer, where the first trench is located, onto the substrate falls within a positive projection of a second sub-trench of the sacrificial layer onto the substrate, and an aperture of a first sub-hole of the second hole located in the insulating layer is smaller than an aperture of a second sub-hole of the second hole located in the sacrificial layer; Forming a first gate electrode, a first semiconductor layer, and a first electrode extending in a direction perpendicular to the substrate within the second hole includes: Forming a first gate electrode thin film covering inner walls of the second hole and inner walls of the first trench, etching away the first gate electrode thin film located in the first sub-hole and the first sub-trench to form a first gate electrode covering inner walls of the second sub-hole and inner walls of the second trench; forming a first gate insulating layer covering inner walls of the second hole and the first trench; Depositing a first semiconductor thin film within the second hole and the first trench where the first gate electrode and the first gate insulating layer are formed, etching away the first semiconductor thin film within the first sub-hole and the first sub-trench to form a first semiconductor layer covering an inner wall of the second sub-hole, and the first semiconductor layer separating the second hole and the first trench; Forming a first electrode filling the second hole.

16. The method for manufacturing a semiconductor device according to claim 14, wherein: The method further includes: forming a second trench extending in a second direction on a side of the second transistor region away from the first trench; when the sacrificial layer is etched laterally based on each of the third holes, the sacrificial layer is also etched laterally based on the second trench, such that a positive projection of a third sub-trench of the insulating layer, where the second trench is located, onto the substrate falls within a positive projection of a fourth sub-trench of the sacrificial layer onto the substrate, an aperture of a third sub-hole of the third hole located in the insulating layer is smaller than an aperture of a fourth sub-hole of the third hole located in the sacrificial layer, and the second trench communicates with the third hole; forming a second bit line extending in the second direction within the fourth sub-trench; Forming a second gate electrode extending in a direction perpendicular to the substrate and a second semiconductor layer surrounding sidewalls of the second gate electrode of the second transistor within the third hole includes: Forming and depositing a second semiconductor thin film covering an inner wall of the third hole within the third hole, etching away the second semiconductor thin film located in the third sub-hole to form a second semiconductor layer covering an inner wall of the fourth sub-hole; Sequentially forming a second gate insulating layer covering an inner wall of the third hole and a second gate electrode filling the third hole within the third hole where the second semiconductor layer is formed.

17. An electronic device, characterized in that, Including a semiconductor device according to any one of claims 1 to 13, or a semiconductor device formed by the method for manufacturing a semiconductor device according to any one of claims 14 to 16.

Images