Low-lattice mismatch MISHEMT interface buffer layer, preparation method thereof and MISHEMT device comprising low-lattice mismatch MISHEMT interface buffer layer

Abstract

The invention discloses a low lattice mismatch MISHEMT interface buffer layer, a preparation method thereof and an MISHEMT device comprising the same, and relates to the technical field of semiconductors. The interface buffer layer is arranged below the gate dielectric layer, and the interface buffer layer comprises a first AlGaN layer; a second AlGaN layer, wherein the second AlGaN layer is deposited on the upper surface of the first AlGaN layer; the third AlGaN layer is deposited on the upper surface of the second AlGaN layer; an AlN layer, wherein the AlN layer is deposited between the third AlGaN layer and the gate dielectric layer; the content of Al in the first AlGaN layer, the content of Al in the second AlGaN layer and the content of Al in the third AlGaN layer are sequentially increased. The lattice mismatch degree between adjacent materials in the interface buffer layer provided by the invention is greatly reduced, the overall lattice mismatch degree is far less than 2.4%, and the deep energy level defect caused by abrupt change of energy level arrangement can be effectively reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and more specifically, to a low lattice mismatch MISHEMT interface buffer layer, a preparation method thereof, and a MISHEMT device containing the same. Background Art

[0002] As a member of the third-generation semiconductor material system, gallium nitride (GaN) has unique advantages such as an adjustable wide bandgap, a high breakdown electric field, and a high saturation velocity; at the same time, a high electron mobility transistor (HEMT) can effectively utilize the characteristics of GaN materials to realize high-performance high-frequency power devices, making GaN-based HEMTs a research hotspot.

[0003] According to the different gate contact structures, GaN-based HEMT devices can be divided into two categories: one is the traditional GaN-based HEMT device with a Schottky gate contact; the other is the GaN-based insulated gate HEMT device, which adds an insulating material between the gate electrode and the nitride semiconductor material on the basis of the traditional HEMT device structure to form a metal-insulator-semiconductor high electron mobility transistor (MISHEMT).

[0004] Existing conventional MISHEMT devices such as Figure 1 and Figure 2 shown, Figure 1 In the structure shown, there is no interface buffer layer structure, and a gate dielectric layer is directly provided between the nitride semiconductor (p-GaN) and the gate electrode (gate). However, this structure has the following defects: since the gate dielectric layer is usually an amorphous structure, the interface defect density at the contact surface between the single-crystal p-GaN and the gate dielectric layer is relatively high, which will in turn affect the electrical properties of the device.

[0005] Therefore, how to optimize the interface defects at the contact surface between p-GaN and the gate dielectric layer to improve the electrical properties of GaN HEMT devices is the problem to be solved. Summary of the Invention

[0006] In view of this, one of the purposes of the present invention is to provide a low lattice mismatch MISHEMT interface buffer layer to solve the problems in the prior art.

[0007] To achieve the above object, the technical solution of the present invention is as follows: A low lattice mismatch MISHEMT interface buffer layer, the interface buffer layer is provided under the gate dielectric layer, and the interface buffer layer includes: A first AlGaN layer; A second AlGaN layer, the second AlGaN layer is deposited on the upper surface of the first AlGaN layer; A third AlGaN layer, the third AlGaN layer being deposited on the upper surface of the second AlGaN layer; An AlN layer, the AlN layer being deposited between the third AlGaN layer and the gate dielectric layer; The content of Al in the first AlGaN layer, the second AlGaN layer, and the third AlGaN layer increases in sequence.

[0008] In the present invention, for a MISHEMT device with a p-GaN layer provided on the top, the interface buffer layer is provided between the p-GaN layer and the gate dielectric layer; for a depletion-type MISHEMT device without a p-GaN layer provided on the top, the interface buffer layer can be directly provided between the AlGaN barrier layer and the gate dielectric layer. Whether it is a p-GaN layer or an AlGaN barrier layer, GaN is included in its composition.

[0009] By providing an AlN layer below the gate dielectric layer, the conduction band difference between AlN and GaN is as high as 1.8 eV. Using AlN as the interface buffer layer of a GaNHEMT can effectively reduce the leakage current. However, due to the relatively high lattice mismatch between AlN and GaN, exceeding 2.4%, it will directly affect the electron mobility; at the same time, the thermal expansion coefficients of AlN and GaN are different, and subsequent annealing may generate stress at the interface, resulting in poor contact quality.

[0010] Therefore, the present invention further provides three-layer AlGaN buffer layers at the bottom of the AlN, and the content of Al in the three-layer AlGaN increases from bottom to top, effectively solving the lattice mismatch problem between AlN and GaN; and it can also solve the problem of bandgap mutation between AlN and GaN.

[0011] Further, the first AlGaN layer is deposited on the upper surface of the p-GaN layer; that is, it is preferably applicable to a MISHEMT device with a p-GaN layer provided on the top; The content of Al in the first AlGaN layer is 5% - 35%; the content of Al in the second AlGaN layer is 25% - 65%; the content of Al in the third AlGaN layer is 55% - 95%.

[0012] Among them, p-GaN, that is, p-type gallium nitride, is a material formed by doping a p-type dopant in gallium nitride (GaN); the commonly used p-type dopant is Mg (magnesium). In addition, C, Be, and Ca dopants with relatively small ionization energies can also achieve p-type doping effects under different conditions, and specific limitations are not made here.

[0013] Optionally, the number of AlGaN layers in the interface buffer layer can also be set to only two layers, or four layers or more to achieve the lowest interface defects.

[0014] Further, the atomic ratio of Al to Ga in the first AlGaN layer is 3:7; the atomic ratio of Al to Ga in the second AlGaN layer is 6:4; the atomic ratio of Al to Ga in the third AlGaN layer is 9:1.

[0015] Optionally, the atomic ratio of Al to Ga in each AlGaN layer can also be adjusted to achieve the lowest interface defects.

[0016] Further, the thickness of the first AlGaN layer is 0.5 - 1.5 nm; the thickness of the second AlGaN layer is 0.5 - 1.5 nm; the thickness of the third AlGaN layer is 1 - 2 nm.

[0017] The second object of the present invention is to provide a method for preparing the above-mentioned low lattice mismatch MISHEMT interface buffer layer, including the following steps: 1) Deposit and form the first AlGaN layer on the p-GaN layer; 2) Perform the first annealing treatment; specifically, an annealing treatment can be performed once after each super cycle (cycle) during the deposition of the first AlGaN layer, or an annealing treatment can be performed after the overall deposition of the first AlGaN layer is completed; 3) Deposit the second AlGaN layer on the first AlGaN layer; 4) Perform the second annealing treatment; specifically, an annealing treatment can be performed once after each super cycle (cycle) during the deposition of the second AlGaN layer, or an annealing treatment can be performed after the overall deposition of the second AlGaN layer is completed; 5) Deposit and form the third AlGaN layer on the second AlGaN layer; 6) Perform the third annealing treatment; similarly, an annealing treatment can be performed once after each super cycle (cycle) during the deposition of the third AlGaN layer, or an annealing treatment can be performed after the overall deposition of the third AlGaN layer is completed; 7) Deposit and form the AlN layer on the third AlGaN layer; 8) Perform the fourth annealing treatment; 9) Deposit and form the gate dielectric layer on the AlN layer; 10) Perform the fifth annealing treatment to obtain the product.

[0018] Further, in step 1), specifically, the first AlGaN layer is prepared by ALD deposition. When using ALD to deposit the first AlGaN layer, each super cycle includes sequentially performing 2 - 5 GaN cycles, 1 - 4 AlN cycles, and 2 - 4 GaN cycles until the first AlGaN layer with the required thickness is deposited; In step 3), specifically, the second AlGaN layer is prepared by ALD deposition. When depositing the second AlGaN layer by ALD, each supercycle includes sequentially performing 1 - 3 GaN cycles, 4 - 7 AlN cycles, and 1 - 3 GaN cycles until the second AlGaN layer with the desired thickness is deposited; In step 5), specifically, the third AlGaN layer is prepared by ALD deposition. When depositing the third AlGaN layer by ALD, each supercycle includes sequentially performing 1 - 4 GaN cycles and 6 - 9 AlN cycles until the third AlGaN layer with the desired thickness is obtained Further, in step 1), specifically, the first AlGaN layer is prepared by ALD deposition. When depositing the first AlGaN layer by ALD, each supercycle includes sequentially performing 4 GaN cycles, 3 AlN cycles, and 3 GaN cycles until the first AlGaN layer with the desired thickness is deposited; In step 3), specifically, the second AlGaN layer is prepared by ALD deposition. When depositing the second AlGaN layer by ALD, each supercycle includes sequentially performing 2 GaN cycles, 6 AlN cycles, and 2 GaN cycles until the second AlGaN layer with the desired thickness is deposited; In step 5), specifically, the third AlGaN layer is prepared by ALD deposition. When depositing the third AlGaN layer by ALD, each supercycle includes sequentially performing 1 GaN cycle and 9 AlN cycles until the third AlGaN layer with the desired thickness is obtained.

[0019] Optionally, each cycle in each layer of AlGaN can be flexibly changed. For example, when depositing the first AlGaN layer, each supercycle includes sequentially 3 GaN + 3 AlN + 4 GaN; or 2 GaN + 3 AlN + 5 GaN; until the first AlGaN layer with the desired thickness is deposited; or alternating, etc. It can be understood that for depositing the second AlGaN layer, each cycle can also be adjusted to achieve the lowest interface defects; as long as it is ensured that the beginning and end of each cycle in the first AlGaN layer and the second AlGaN layer are GaN layers.

[0020] Further, the first annealing treatment, the second annealing treatment, and the third annealing treatment are specifically in - situ annealing with nitrogen at the original temperature in the ALD chamber for 1 - 10 minutes, or treatment with nitrogen plasma for 5 - 600 seconds, or both.

[0021] In step 8), the fourth annealing treatment can be to take out the sample and place it in an external annealing device for high - temperature annealing; the specific annealing temperature is 400 - 800 °C, the annealing environment is nitrogen, and the annealing time is 1 - 3 hours.

[0022] In step 10), the fifth annealing treatment is a low-temperature annealing treatment, with a specific annealing temperature of ≤ 300 °C, an annealing environment of air or vacuum, and an annealing time of ≤ 1 hour.

[0023] Through the above deposition method, the beginning and end of each cycle in the first AlGaN layer and the second AlGaN layer are GaN layers, which is also the key to improving the contact quality and lattice quality of each layer of the interface buffer layer.

[0024] Moreover, the three AlGaN layers, the AlN layer, and the gate dielectric layer can all be prepared by ALD, which simplifies the preparation method and is conducive to reducing the production cost of the device and improving the production efficiency.

[0025] The preparation method provided by the present invention can set different annealing treatment processes after the three AlGaN layers (the first AlGaN layer, the second AlGaN layer, and the third AlGaN layer) and the AlN layer. The annealing optimization process is more flexible, and the overall quality of the interface buffer layer is improved more significantly.

[0026] By performing multiple annealings on the interface buffer layer, the material parameters such as the element diffusion degree and lattice structure in each layer can be effectively regulated.

[0027] A third object of the present invention is to provide a MISHEMT device including the low lattice mismatch MISHEMT interface buffer layer described in any one of the above.

[0028] Further, the device includes an epitaxial substrate layer, an epitaxial buffer layer, a GaN channel layer, an AlGaN barrier layer, which are sequentially arranged from bottom to top, and a source electrode, a drain electrode, and a p-GaN layer disposed on the AlGaN barrier layer. The source electrode and the drain electrode are respectively located on the left and right sides of the p-GaN layer. The interface buffer layer is disposed on the p-GaN layer, a gate dielectric layer is disposed on the upper surface of the interface buffer layer, and a gate electrode is disposed on the gate dielectric layer.

[0029] Further, the material of the epitaxial substrate is one of a silicon wafer, sapphire, GaN, and SiC; the gate dielectric layer is obtained by laminating one or more of Ta2O5, Al2O3, HfO2, and SiN.

[0030] Further, the epitaxial buffer layer, the GaN channel layer, the AlGaN barrier layer, and the p-GaN layer can be prepared by epitaxial methods such as metal organic chemical vapor deposition (MOCVD) and molecular beam epitaxy (MBE), and the present invention does not make specific limitations.

[0031] Further, at least one method among atomic layer deposition (ALD), magnetron sputtering, electron beam evaporation, and thermal evaporation is selected for the preparation of the gate electrode, the source electrode, and the drain electrode. At the same time, different preparation methods can be used between different electrodes.

[0032] Further, the source electrode and the drain electrode can be a single material or a laminated structure of multiple materials selected from metals or semiconductors with good conductivity, and it is required to easily form a good ohmic contact with AlGaN.

[0033] Further, the gate electrode can be a single material or a laminated structure of multiple materials selected from metals or semiconductors with good conductivity, and it is required to easily form a Schottky contact with the gate dielectric layer.

[0034] In the present invention, the thickness of the epitaxial substrate layer is 800 um to 1200 um; the thickness of the epitaxial buffer layer is 4000 nm to 6000 nm; the thickness of the GaN channel layer is 100 nm to 300 nm; the thickness of the AlGaN barrier layer is 5 nm to 50 nm; the thickness of the p-GaN layer is 50 nm to 300 nm; the thickness of the AlN layer is 1 nm to 10 nm.

[0035] Compared with the prior art, the present invention has the following advantages: (1) The lattice mismatch degree between adjacent materials of the p-GaN layer, the first AlGaN layer, the second AlGaN layer, the third AlGaN layer, and the AlN layer is greatly reduced, and the overall lattice mismatch degree is much less than 2.4%.

[0036] (2) The band gaps between the p-GaN layer, the first AlGaN layer, the second AlGaN layer, the third AlGaN layer, and the AlN layer present a stepped gradual change structure, effectively reducing the deep-level defects caused by the sudden change of the energy level arrangement.

[0037] (3) After the growth of the first AlGaN layer, the second AlGaN layer, the third AlGaN layer, and the AlN layer, the annealing method, annealing temperature, annealing atmosphere, and annealing time are respectively adjusted. The annealing conditions are more flexible and the interface modification is better.

[0038] (4) GaN is at the head and tail of each cycle in the first AlGaN layer and the second AlGaN layer, avoiding the generation of defects between cycles during annealing. Description of the Drawings

[0039] Figure 1 is a schematic structural diagram of a conventional MISHEMT device in the prior art; wherein, S represents the source electrode, D represents the drain electrode; and S represents the gate electrode.

[0040] Figure 2 is Figure 1 the enlarged structural diagram at position A in

[0041] Figure 3 is a schematic structural diagram with an AlN layer provided only between the p-GaN layer and the gate dielectric layer of the MISHEMT device.

[0042] Figure 4 is Figure 3 the enlarged schematic structural view of location A in

[0043] Figure 5 the schematic structural view of the present invention with an AlN layer and multiple AlGaN layers disposed between the p-GaN layer and the gate dielectric layer.

[0044] Figure 6 is Figure 5 the enlarged schematic structural view of location A in Specific Embodiments

[0045] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without departing from the spirit of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed below.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this invention belongs. The terms used in the specification of the present invention herein are for the purpose of describing specific embodiments only and are not intended to limit the present invention.

[0047] Unless otherwise specifically stated, the materials and reagents used in the present invention can be obtained from commercial products in this field.

[0048] Example 1 A MISHEMT device with multiple AlGaN layers in an interface buffer layer, the structure is as shown in Figure 5 and Figure 6 , and the preparation method includes: S1. Deposit an epitaxial buffer layer, a GaN channel layer, and an AlGaN barrier layer on the epitaxial substrate layer in sequence; then deposit a source electrode at one end of the AlGaN barrier layer, a drain electrode at the other end, and a p-GaN layer in the middle; wherein, the thickness of the epitaxial substrate layer is about 1000 um; the thickness of the epitaxial buffer layer is about 5000 nm; the thickness of the GaN channel layer is 200 nm; the thickness of the AlGaN barrier layer is 20 nm; the thickness of the p-GaN layer is 100 nm; S2. Deposit an interface buffer layer, the interface buffer layer covers the entire p-GaN layer, and at the same time, the upper surfaces of the AlGaN barrier layers between the source electrode and the p-GaN layer, between the drain electrode and the p-GaN layer, and on the source electrode and the drain electrode are all deposited and covered with the interface buffer layer; in addition, the interface buffer layer is deposited and covered along the outer ends of the source electrode and the drain electrode respectively down to the epitaxial ends of the epitaxial buffer layer; of course, voids for connecting to an external circuit are left on the source electrode and the drain electrode; Specifically, the deposition process of the interface buffer layer includes: S21. Prepare the first AlGaN layer (AlGaN-1) on the p-GaN layer by ALD, where the molar content of Al in the film layer is 30%. Specifically, during deposition, each cycle includes 4 GaN + 3 AlN + 3 GaN; until a first AlGaN layer with a thickness of about 1 nm is deposited. When depositing the first AlGaN layer, perform the first annealing treatment. During the first annealing, it can be in-situ and at the original temperature in the ALD chamber with nitrogen annealing for 5 minutes after each cycle. S22. Prepare the second AlGaN layer (AlGaN-2) on the first AlGaN layer by ALD, where the molar content of Al in the film layer is 60%. Specifically, during deposition, each cycle includes 2 GaN + 6 AlN + 2 GaN; until a second AlGaN layer with a thickness of about 1 nm is deposited. When depositing the second AlGaN layer, perform the second annealing treatment. During the second annealing, it can be treated with nitrogen plasma for 100 s after each cycle. S23. Prepare the third AlGaN layer (AlGaN-3) on the second AlGaN layer by ALD, where the molar content of Al in the film layer is 90%. Specifically, during deposition, each cycle includes 1 GaN + 9 AlN; until a third AlGaN layer with a thickness of about 1.5 nm is deposited. When depositing the third AlGaN layer, perform the third annealing treatment. During the third annealing, it can be treated with nitrogen plasma for 100 s after some cycles, and in-situ and at the original temperature in the ALD chamber with nitrogen annealing for 5 minutes after some cycles. S24. Deposit an AlN layer on the third AlGaN layer by an ALD device to obtain an AlN layer with a thickness of 5 nm. S25. Perform the fourth annealing on the interface buffer layer; the fourth annealing can be to take out the sample and place it in an external annealing device for high-temperature annealing; the annealing temperature is 700 °C, the annealing environment is nitrogen, and the annealing time is 2 hours. S26. Prepare a gate dielectric layer on the AlN layer by ALD. S27. Perform low-temperature annealing treatment; the specific temperature is 200 °C, the annealing environment is vacuum, and the annealing time is 40 minutes. S3. Prepare a gate electrode on the gate dielectric layer.

[0049] Thus, a MISHEMT device containing multiple AlGaN layers is obtained.

[0050] In this embodiment, the lattice mismatch degrees between adjacent materials of the p-GaN layer, AlGaN-1, AlGaN-2, AlGaN-3, and AlN layers are all less than 0.5%, and the overall lattice mismatch degree is much less than 2.4%.

[0051] Comparative Example 1 The difference between this embodiment and Embodiment 1 is only that the first AlGaN layer, the second AlGaN layer, and the third AlGaN layer are not included in the interface buffer layer; the prepared MISHEMT device is as Figure 3 and Figure 4 shown.

[0052] In this embodiment, the lattice mismatch degree between p-GaN and AlN exceeds 2.4%, specifically 2.7%.

[0053] Comparative Example 2 The difference between this embodiment and Embodiment 1 is only that when preparing the interface buffer layer, in step S21, when preparing the first AlGaN layer, each cycle includes 7 GaN + 3 AlN; in step S22, when preparing the second AlGaN layer, each cycle includes 4 GaN + 6 AlN.

[0054] The remaining steps are the same.

[0055] In this embodiment, the lattice mismatch degrees between adjacent materials of the p-GaN layer, AlGaN-1, AlGaN-2, AlGaN-3, and AlN layers are all greater than 2.2%, and the overall lattice mismatch degree is 2.5%.

[0056] Comparative Example 3 The difference between this embodiment and Embodiment 1 is only that when preparing the interface buffer layer, in step S21, when preparing the first AlGaN layer, each cycle includes 1 GaN + 9 AlN; in step S22, when preparing the second AlGaN layer, each cycle includes 4 GaN + 6 AlN; in step S23, when preparing the third AlGaN layer, each cycle includes 4 GaN + 3 AlN + 3 GaN.

[0057] The remaining steps are the same.

[0058] In this embodiment, the lattice mismatch degrees between adjacent materials of the p-GaN layer, AlGaN-1, AlGaN-2, AlGaN-3, and AlN layers are all greater than 2.2%, and the overall lattice mismatch degree is 2.4%.

[0059] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0060] The above-described embodiments merely represent several implementation manners of the present invention. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention patent shall be subject to the appended claims.

Claims

1. A low lattice mismatch MISHEMT interface buffer layer, characterized in that, The interface buffer layer is disposed under the gate dielectric layer, and the interface buffer layer includes: A first AlGaN layer; A second AlGaN layer deposited on the upper surface of the first AlGaN layer; A third AlGaN layer deposited on the upper surface of the second AlGaN layer; An AlN layer deposited between the third AlGaN layer and the gate dielectric layer; The content of Al in the first AlGaN layer, the second AlGaN layer, and the third AlGaN layer increases in sequence.

2. The low lattice mismatch MISHEMT interface buffer layer according to claim 1, wherein The first AlGaN layer is deposited on the upper surface of the p-GaN layer; The content of Al in the first AlGaN layer is 5% - 35%; the content of Al in the second AlGaN layer is 25% - 65%; the content of Al in the third AlGaN layer is 55% - 95%.

3. The low lattice mismatch MISHEMT interface buffer layer according to claim 1, characterized in that, The atomic ratio of Al to Ga in the first AlGaN layer is 3:7; the atomic ratio of Al to Ga in the second AlGaN layer is 6:4; the atomic ratio of Al to Ga in the third AlGaN layer is 9:

1.

4. The low lattice mismatch MISHEMT interface buffer layer according to claim 1, characterized in that, The thickness of the first AlGaN layer is 0.5 - 1.5 nm; the thickness of the second AlGaN layer is 0.5 - 1.5 nm; the thickness of the third AlGaN layer is 1 - 2 nm.

5. The preparation method of the low lattice mismatch MISHEMT interface buffer layer according to any one of claims 1-4, characterized in that, Including the following steps: 1) Deposit and form a first AlGaN layer on the p-GaN layer; 2) Conduct a first annealing treatment; 3) Deposit a second AlGaN layer on the first AlGaN layer; 4) Conduct a second annealing treatment; 5) Deposit and form a third AlGaN layer on the second AlGaN layer; 6) Conduct a third annealing treatment; 7) Deposit and form an AlN layer on the third AlGaN layer; 8) Conduct a fourth annealing treatment; 9) Deposit and form a gate dielectric layer on the AlN layer; 10) Conduct a fifth annealing treatment to obtain the product.

6. The preparation method according to claim 5, wherein In step 1), specifically, the first AlGaN layer is prepared by ALD deposition. When using ALD to deposit the first AlGaN layer, each super cycle includes sequentially performing 2 - 5 GaN cycles, 1 - 4 AlN cycles, and 2 - 4 GaN cycles until the first AlGaN layer with the required thickness is deposited; In step 3), specifically, the second AlGaN layer is prepared by ALD deposition. When using ALD to deposit the second AlGaN layer, each super cycle includes sequentially performing 1 - 3 GaN cycles, 4 - 7 AlN cycles, and 1 - 3 GaN cycles until the second AlGaN layer with the required thickness is deposited; In step 5), specifically, the third AlGaN layer is prepared by ALD deposition. When using ALD to deposit the third AlGaN layer, each super cycle includes sequentially performing 1 - 4 GaN cycles and 6 - 9 AlN cycles until the third AlGaN layer with the required thickness is obtained.

7. The preparation method according to claim 5, wherein The first annealing treatment, the second annealing treatment, and the third annealing treatment are specifically in-situ annealing in nitrogen at the original temperature in the ALD chamber for 1 - 10 minutes, or treating with nitrogen plasma for 5 - 600 seconds, or both.

8. A MISHEMT device comprising the low lattice mismatch MISHEMT interface buffer layer according to any one of claims 1 - 4.

9. The device according to claim 8, characterized in that, The device includes an epitaxial substrate layer, an epitaxial buffer layer, a GaN channel layer, an AlGaN barrier layer, which are sequentially arranged from bottom to top, and a source electrode, a drain electrode, and a p-GaN layer disposed on the AlGaN barrier layer. The source electrode and the drain electrode are respectively located on the left and right sides of the p-GaN layer. The interface buffer layer is disposed on the p-GaN layer, a gate dielectric layer is disposed on the upper surface of the interface buffer layer, and a gate electrode is disposed on the gate dielectric layer.

10. The device according to claim 9, characterized in that, The material of the epitaxial substrate is one of silicon wafer, sapphire, GaN, and SiC; the gate dielectric layer is obtained by laminating one or more of Ta2O5, Al2O3, HfO2, and SiN.

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